[people/ms/u-boot.git] / drivers / i2c / adi_i2c.c

/*
 * i2c.c - driver for ADI TWI/I2C
 *
 * Copyright (c) 2006-2014 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.txt for instructions.
 */

#include <common.h>
#include <console.h>
#include <i2c.h>

#include <asm/clock.h>
#include <asm/twi.h>
#include <asm/io.h>

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);

/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
struct twi_regs {
	ureg(clkdiv);
	ureg(control);
	ureg(slave_ctl);
	ureg(slave_stat);
	ureg(slave_addr);
	ureg(master_ctl);
	ureg(master_stat);
	ureg(master_addr);
	ureg(int_stat);
	ureg(int_mask);
	ureg(fifo_ctl);
	ureg(fifo_stat);
	char __pad[0x50];
	ureg(xmt_data8);
	ureg(xmt_data16);
	ureg(rcv_data8);
	ureg(rcv_data16);
};
#undef ureg

#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
# ifdef CONFIG_SYS_MAX_I2C_BUS
# undef CONFIG_SYS_MAX_I2C_BUS
# endif
#define CONFIG_SYS_MAX_I2C_BUS 1
#endif

/*
 * The way speed is changed into duty often results in integer truncation
 * with 50% duty, so we'll force rounding up to the next duty by adding 1
 * to the max.  In practice this will get us a speed of something like
 * 385 KHz.  The other limit is easy to handle as it is only 8 bits.
 */
#define I2C_SPEED_MAX             400000
#define I2C_SPEED_TO_DUTY(speed)  (5000000 / (speed))
#define I2C_DUTY_MAX              (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
#define I2C_DUTY_MIN              0xff	/* 8 bit limited */
#define SYS_I2C_DUTY              I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
/* Note: duty is inverse of speed, so the comparisons below are correct */
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
# error "The I2C hardware can only operate 20KHz - 400KHz"
#endif

/* All transfers are described by this data structure */
struct adi_i2c_msg {
	u8 flags;
#define I2C_M_COMBO		0x4
#define I2C_M_STOP		0x2
#define I2C_M_READ		0x1
	int len;		/* msg length */
	u8 *buf;		/* pointer to msg data */
	int alen;		/* addr length */
	u8 *abuf;		/* addr buffer */
};

/* Allow msec timeout per ~byte transfer */
#define I2C_TIMEOUT 10

/**
 * wait_for_completion - manage the actual i2c transfer
 *	@msg: the i2c msg
 */
static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
{
	u16 int_stat, ctl;
	ulong timebase = get_timer(0);

	do {
		int_stat = readw(&twi->int_stat);

		if (int_stat & XMTSERV) {
			writew(XMTSERV, &twi->int_stat);
			if (msg->alen) {
				writew(*(msg->abuf++), &twi->xmt_data8);
				--msg->alen;
			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
				writew(*(msg->buf++), &twi->xmt_data8);
				--msg->len;
			} else {
				ctl = readw(&twi->master_ctl);
				if (msg->flags & I2C_M_COMBO)
					writew(ctl | RSTART | MDIR,
							&twi->master_ctl);
				else
					writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & RCVSERV) {
			writew(RCVSERV, &twi->int_stat);
			if (msg->len) {
				*(msg->buf++) = readw(&twi->rcv_data8);
				--msg->len;
			} else if (msg->flags & I2C_M_STOP) {
				ctl = readw(&twi->master_ctl);
				writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & MERR) {
			writew(MERR, &twi->int_stat);
			return msg->len;
		}
		if (int_stat & MCOMP) {
			writew(MCOMP, &twi->int_stat);
			if (msg->flags & I2C_M_COMBO && msg->len) {
				ctl = readw(&twi->master_ctl);
				ctl = (ctl & ~RSTART) |
					(min(msg->len, 0xff) << 6) | MEN | MDIR;
				writew(ctl, &twi->master_ctl);
			} else
				break;
		}

		/* If we were able to do something, reset timeout */
		if (int_stat)
			timebase = get_timer(0);

	} while (get_timer(timebase) < I2C_TIMEOUT);

	return msg->len;
}

static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
			int alen, uint8_t *buffer, int len, uint8_t flags)
{
	struct twi_regs *twi = i2c_get_base(adap);
	int ret;
	u16 ctl;
	uchar addr_buffer[] = {
		(addr >>  0),
		(addr >>  8),
		(addr >> 16),
	};
	struct adi_i2c_msg msg = {
		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
		.buf   = buffer,
		.len   = len,
		.abuf  = addr_buffer,
		.alen  = alen,
	};

	/* wait for things to settle */
	while (readw(&twi->master_stat) & BUSBUSY)
		if (ctrlc())
			return 1;

	/* Set Transmit device address */
	writew(chip, &twi->master_addr);

	/* Clear the FIFO before starting things */
	writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
	writew(0, &twi->fifo_ctl);

	/* prime the pump */
	if (msg.alen) {
		len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
		writew(*(msg.abuf++), &twi->xmt_data8);
		--msg.alen;
	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
		writew(*(msg.buf++), &twi->xmt_data8);
		--msg.len;
	}

	/* clear int stat */
	writew(-1, &twi->master_stat);
	writew(-1, &twi->int_stat);
	writew(0, &twi->int_mask);

	/* Master enable */
	ctl = readw(&twi->master_ctl);
	ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
		((msg.flags & I2C_M_READ) ? MDIR : 0);
	writew(ctl, &twi->master_ctl);

	/* process the rest */
	ret = wait_for_completion(twi, &msg);

	if (ret) {
		ctl = readw(&twi->master_ctl) & ~MEN;
		writew(ctl, &twi->master_ctl);
		ctl = readw(&twi->control) & ~TWI_ENA;
		writew(ctl, &twi->control);
		ctl = readw(&twi->control) | TWI_ENA;
		writew(ctl, &twi->control);
	}

	return ret;
}

static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);

	/* Set TWI interface clock */
	if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
		return -1;
	clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
	writew(clkdiv, &twi->clkdiv);

	/* Don't turn it on */
	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);

	return 0;
}

static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;

	/* Set TWI internal clock as 10MHz */
	writew(prescale, &twi->control);

	/* Set TWI interface clock as specified */
	i2c_set_bus_speed(speed);

	/* Enable it */
	writew(TWI_ENA | prescale, &twi->control);
}

static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer,
			len, alen ? I2C_M_COMBO : I2C_M_READ);
}

static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
}

static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	u8 byte;
	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
}

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_MAX_I2C_BUS > 2
	case 2:
		return (struct twi_regs *)TWI2_CLKDIV;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
	case 1:
		return (struct twi_regs *)TWI1_CLKDIV;
#endif
	case 0:
		return (struct twi_regs *)TWI0_CLKDIV;

	default:
		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	}

	return NULL;
}

U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 0)

#if CONFIG_SYS_MAX_I2C_BUS > 1
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 1)
#endif

#if CONFIG_SYS_MAX_I2C_BUS > 2
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 2)
#endif
Commit	Line	Data
be853bf8	1	/*
fea9b69a	2	* i2c.c - driver for ADI TWI/I2C
be853bf8	3	*
fea9b69a	4	* Copyright (c) 2006-2014 Analog Devices Inc.
be853bf8 MF	5	*
be853bf8 MF	6	* Licensed under the GPL-2 or later.
28527096 SG	7	*
	8	* NOTE: This driver should be converted to driver model before June 2017.
	9	* Please see doc/driver-model/i2c-howto.txt for instructions.
be853bf8 MF	10	*/
	11
	12	#include <common.h>
24b852a7	13	#include <console.h>
be853bf8 MF	14	#include <i2c.h>
be853bf8 MF	15
d6a320d5	16	#include <asm/clock.h>
fea9b69a	17	#include <asm/twi.h>
a6be70f7	18	#include <asm/io.h>
be853bf8	19
c469703b SJ	20	static struct twi_regs i2c_get_base(struct i2c_adapter adap);
c469703b SJ	21
b5cebb4f MF	22	/* Every register is 32bit aligned, but only 16bits in size */
	23	#define ureg(name) u16 name; u16 __pad_##name;
	24	struct twi_regs {
	25	ureg(clkdiv);
	26	ureg(control);
	27	ureg(slave_ctl);
	28	ureg(slave_stat);
	29	ureg(slave_addr);
	30	ureg(master_ctl);
	31	ureg(master_stat);
	32	ureg(master_addr);
	33	ureg(int_stat);
	34	ureg(int_mask);
	35	ureg(fifo_ctl);
	36	ureg(fifo_stat);
	37	char __pad[0x50];
	38	ureg(xmt_data8);
	39	ureg(xmt_data16);
	40	ureg(rcv_data8);
	41	ureg(rcv_data16);
	42	};
	43	#undef ureg
	44
b5cebb4f MF	45	#ifdef TWI_CLKDIV
b5cebb4f MF	46	#define TWI0_CLKDIV TWI_CLKDIV
c469703b SJ	47	# ifdef CONFIG_SYS_MAX_I2C_BUS
	48	# undef CONFIG_SYS_MAX_I2C_BUS
	49	# endif
	50	#define CONFIG_SYS_MAX_I2C_BUS 1
be853bf8	51	#endif
08a1c625 MF	52
	53	/*
	54	* The way speed is changed into duty often results in integer truncation
	55	* with 50% duty, so we'll force rounding up to the next duty by adding 1
	56	* to the max. In practice this will get us a speed of something like
	57	* 385 KHz. The other limit is easy to handle as it is only 8 bits.
	58	*/
	59	#define I2C_SPEED_MAX 400000
	60	#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
	61	#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
	62	#define I2C_DUTY_MIN 0xff /* 8 bit limited */
	63	#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
	64	/* Note: duty is inverse of speed, so the comparisons below are correct */
	65	#if SYS_I2C_DUTY < I2C_DUTY_MAX \|\| SYS_I2C_DUTY > I2C_DUTY_MIN
c469703b	66	# error "The I2C hardware can only operate 20KHz - 400KHz"
be853bf8 MF	67	#endif
	68
	69	/* All transfers are described by this data structure */
fffff726	70	struct adi_i2c_msg {
be853bf8 MF	71	u8 flags;
	72	#define I2C_M_COMBO 0x4
	73	#define I2C_M_STOP 0x2
	74	#define I2C_M_READ 0x1
	75	int len; /* msg length */
	76	u8 buf; / pointer to msg data */
	77	int alen; /* addr length */
	78	u8 abuf; / addr buffer */
	79	};
	80
3814ea4f MF	81	/* Allow msec timeout per ~byte transfer */
	82	#define I2C_TIMEOUT 10
	83
be853bf8 MF	84	/**
	85	* wait_for_completion - manage the actual i2c transfer
	86	* @msg: the i2c msg
	87	*/
fffff726	88	static int wait_for_completion(struct twi_regs twi, struct adi_i2c_msg msg)
be853bf8	89	{
a6be70f7	90	u16 int_stat, ctl;
3814ea4f	91	ulong timebase = get_timer(0);
be853bf8	92
3814ea4f	93	do {
a6be70f7	94	int_stat = readw(&twi->int_stat);
be853bf8 MF	95
be853bf8 MF	96	if (int_stat & XMTSERV) {
a6be70f7	97	writew(XMTSERV, &twi->int_stat);
be853bf8	98	if (msg->alen) {
a6be70f7	99	writew(*(msg->abuf++), &twi->xmt_data8);
be853bf8 MF	100	--msg->alen;
be853bf8 MF	101	} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
a6be70f7	102	writew(*(msg->buf++), &twi->xmt_data8);
be853bf8 MF	103	--msg->len;
be853bf8 MF	104	} else {
a6be70f7 SJ	105	ctl = readw(&twi->master_ctl);
	106	if (msg->flags & I2C_M_COMBO)
	107	writew(ctl \| RSTART \| MDIR,
	108	&twi->master_ctl);
	109	else
	110	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	111	}
	112	}
	113	if (int_stat & RCVSERV) {
a6be70f7	114	writew(RCVSERV, &twi->int_stat);
be853bf8	115	if (msg->len) {
a6be70f7	116	*(msg->buf++) = readw(&twi->rcv_data8);
be853bf8 MF	117	--msg->len;
be853bf8 MF	118	} else if (msg->flags & I2C_M_STOP) {
a6be70f7 SJ	119	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	120	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	121	}
	122	}
	123	if (int_stat & MERR) {
a6be70f7	124	writew(MERR, &twi->int_stat);
3814ea4f	125	return msg->len;
be853bf8 MF	126	}
be853bf8 MF	127	if (int_stat & MCOMP) {
a6be70f7	128	writew(MCOMP, &twi->int_stat);
be853bf8	129	if (msg->flags & I2C_M_COMBO && msg->len) {
a6be70f7 SJ	130	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	131	ctl = (ctl & ~RSTART) \|
b5cebb4f	132	(min(msg->len, 0xff) << 6) \| MEN \| MDIR;
a6be70f7	133	writew(ctl, &twi->master_ctl);
be853bf8 MF	134	} else
	135	break;
	136	}
3814ea4f MF	137
	138	/* If we were able to do something, reset timeout */
	139	if (int_stat)
	140	timebase = get_timer(0);
	141
	142	} while (get_timer(timebase) < I2C_TIMEOUT);
be853bf8 MF	143
	144	return msg->len;
	145	}
	146
c469703b SJ	147	static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
c469703b SJ	148	int alen, uint8_t *buffer, int len, uint8_t flags)
be853bf8	149	{
c469703b	150	struct twi_regs *twi = i2c_get_base(adap);
a6be70f7 SJ	151	int ret;
a6be70f7 SJ	152	u16 ctl;
be853bf8 MF	153	uchar addr_buffer[] = {
	154	(addr >> 0),
	155	(addr >> 8),
	156	(addr >> 16),
	157	};
fffff726	158	struct adi_i2c_msg msg = {
be853bf8 MF	159	.flags = flags \| (len >= 0xff ? I2C_M_STOP : 0),
	160	.buf = buffer,
	161	.len = len,
	162	.abuf = addr_buffer,
	163	.alen = alen,
	164	};
be853bf8	165
be853bf8	166	/* wait for things to settle */
a6be70f7	167	while (readw(&twi->master_stat) & BUSBUSY)
be853bf8 MF	168	if (ctrlc())
	169	return 1;
	170
	171	/* Set Transmit device address */
a6be70f7	172	writew(chip, &twi->master_addr);
be853bf8 MF	173
be853bf8 MF	174	/* Clear the FIFO before starting things */
a6be70f7 SJ	175	writew(XMTFLUSH \| RCVFLUSH, &twi->fifo_ctl);
a6be70f7 SJ	176	writew(0, &twi->fifo_ctl);
be853bf8 MF	177
	178	/* prime the pump */
	179	if (msg.alen) {
98ab14e8	180	len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
a6be70f7	181	writew(*(msg.abuf++), &twi->xmt_data8);
be853bf8 MF	182	--msg.alen;
be853bf8 MF	183	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
a6be70f7	184	writew(*(msg.buf++), &twi->xmt_data8);
be853bf8 MF	185	--msg.len;
	186	}
	187
	188	/* clear int stat */
a6be70f7 SJ	189	writew(-1, &twi->master_stat);
	190	writew(-1, &twi->int_stat);
	191	writew(0, &twi->int_mask);
be853bf8 MF	192
be853bf8 MF	193	/* Master enable */
a6be70f7 SJ	194	ctl = readw(&twi->master_ctl);
	195	ctl = (ctl & FAST) \| (min(len, 0xff) << 6) \| MEN \|
	196	((msg.flags & I2C_M_READ) ? MDIR : 0);
	197	writew(ctl, &twi->master_ctl);
be853bf8 MF	198
be853bf8 MF	199	/* process the rest */
c469703b	200	ret = wait_for_completion(twi, &msg);
be853bf8 MF	201
be853bf8 MF	202	if (ret) {
a6be70f7 SJ	203	ctl = readw(&twi->master_ctl) & ~MEN;
	204	writew(ctl, &twi->master_ctl);
	205	ctl = readw(&twi->control) & ~TWI_ENA;
	206	writew(ctl, &twi->control);
	207	ctl = readw(&twi->control) \| TWI_ENA;
	208	writew(ctl, &twi->control);
be853bf8 MF	209	}
	210
	211	return ret;
	212	}
	213
c469703b	214	static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
08a1c625	215	{
c469703b	216	struct twi_regs *twi = i2c_get_base(adap);
08a1c625 MF	217	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
	218
	219	/* Set TWI interface clock */
	220	if (clkdiv < I2C_DUTY_MAX \|\| clkdiv > I2C_DUTY_MIN)
	221	return -1;
a6be70f7 SJ	222	clkdiv = (clkdiv << 8) \| (clkdiv & 0xff);
a6be70f7 SJ	223	writew(clkdiv, &twi->clkdiv);
08a1c625 MF	224
08a1c625 MF	225	/* Don't turn it on */
a6be70f7	226	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
08a1c625 MF	227
	228	return 0;
	229	}
	230
c469703b	231	static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
be853bf8	232	{
c469703b SJ	233	struct twi_regs *twi = i2c_get_base(adap);
c469703b SJ	234	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
be853bf8 MF	235
be853bf8 MF	236	/* Set TWI internal clock as 10MHz */
a6be70f7	237	writew(prescale, &twi->control);
be853bf8 MF	238
be853bf8 MF	239	/* Set TWI interface clock as specified */
08a1c625	240	i2c_set_bus_speed(speed);
be853bf8	241
08a1c625	242	/* Enable it */
a6be70f7	243	writew(TWI_ENA \| prescale, &twi->control);
be853bf8 MF	244	}
be853bf8 MF	245
c469703b SJ	246	static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	247	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	248	{
c469703b SJ	249	return i2c_transfer(adap, chip, addr, alen, buffer,
c469703b SJ	250	len, alen ? I2C_M_COMBO : I2C_M_READ);
be853bf8 MF	251	}
be853bf8 MF	252
c469703b SJ	253	static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	254	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	255	{
c469703b	256	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
be853bf8 MF	257	}
be853bf8 MF	258
c469703b	259	static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
be853bf8	260	{
c469703b SJ	261	u8 byte;
c469703b SJ	262	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
be853bf8	263	}
b5cebb4f	264
c469703b	265	static struct twi_regs i2c_get_base(struct i2c_adapter adap)
b5cebb4f	266	{
c469703b SJ	267	switch (adap->hwadapnr) {
	268	#if CONFIG_SYS_MAX_I2C_BUS > 2
	269	case 2:
	270	return (struct twi_regs *)TWI2_CLKDIV;
b5cebb4f MF	271	#endif
b5cebb4f MF	272	#if CONFIG_SYS_MAX_I2C_BUS > 1
a6be70f7	273	case 1:
c469703b	274	return (struct twi_regs *)TWI1_CLKDIV;
b5cebb4f	275	#endif
c469703b SJ	276	case 0:
	277	return (struct twi_regs *)TWI0_CLKDIV;
	278
	279	default:
	280	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
b5cebb4f	281	}
c469703b SJ	282
c469703b SJ	283	return NULL;
b5cebb4f MF	284	}
b5cebb4f MF	285
c469703b SJ	286	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
	287	adi_i2c_read, adi_i2c_write,
	288	adi_i2c_setspeed,
	289	CONFIG_SYS_I2C_SPEED,
	290	0,
	291	0)
	292
b5cebb4f	293	#if CONFIG_SYS_MAX_I2C_BUS > 1
c469703b SJ	294	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
	295	adi_i2c_read, adi_i2c_write,
	296	adi_i2c_setspeed,
	297	CONFIG_SYS_I2C_SPEED,
	298	0,
	299	1)
b5cebb4f	300	#endif
c469703b	301
b5cebb4f	302	#if CONFIG_SYS_MAX_I2C_BUS > 2
c469703b SJ	303	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
	304	adi_i2c_read, adi_i2c_write,
	305	adi_i2c_setspeed,
	306	CONFIG_SYS_I2C_SPEED,
	307	0,
	308	2)
b5cebb4f	309	#endif