[people/ms/u-boot.git] / drivers / i2c / adi_i2c.c

/*
 * i2c.c - driver for ADI TWI/I2C
 *
 * Copyright (c) 2006-2014 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <console.h>
#include <i2c.h>

#include <asm/clock.h>
#include <asm/twi.h>
#include <asm/io.h>

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);

/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
struct twi_regs {
	ureg(clkdiv);
	ureg(control);
	ureg(slave_ctl);
	ureg(slave_stat);
	ureg(slave_addr);
	ureg(master_ctl);
	ureg(master_stat);
	ureg(master_addr);
	ureg(int_stat);
	ureg(int_mask);
	ureg(fifo_ctl);
	ureg(fifo_stat);
	char __pad[0x50];
	ureg(xmt_data8);
	ureg(xmt_data16);
	ureg(rcv_data8);
	ureg(rcv_data16);
};
#undef ureg

#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
# ifdef CONFIG_SYS_MAX_I2C_BUS
# undef CONFIG_SYS_MAX_I2C_BUS
# endif
#define CONFIG_SYS_MAX_I2C_BUS 1
#endif

/*
 * The way speed is changed into duty often results in integer truncation
 * with 50% duty, so we'll force rounding up to the next duty by adding 1
 * to the max.  In practice this will get us a speed of something like
 * 385 KHz.  The other limit is easy to handle as it is only 8 bits.
 */
#define I2C_SPEED_MAX             400000
#define I2C_SPEED_TO_DUTY(speed)  (5000000 / (speed))
#define I2C_DUTY_MAX              (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
#define I2C_DUTY_MIN              0xff	/* 8 bit limited */
#define SYS_I2C_DUTY              I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
/* Note: duty is inverse of speed, so the comparisons below are correct */
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
# error "The I2C hardware can only operate 20KHz - 400KHz"
#endif

/* All transfers are described by this data structure */
struct adi_i2c_msg {
	u8 flags;
#define I2C_M_COMBO		0x4
#define I2C_M_STOP		0x2
#define I2C_M_READ		0x1
	int len;		/* msg length */
	u8 *buf;		/* pointer to msg data */
	int alen;		/* addr length */
	u8 *abuf;		/* addr buffer */
};

/* Allow msec timeout per ~byte transfer */
#define I2C_TIMEOUT 10

/**
 * wait_for_completion - manage the actual i2c transfer
 *	@msg: the i2c msg
 */
static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
{
	u16 int_stat, ctl;
	ulong timebase = get_timer(0);

	do {
		int_stat = readw(&twi->int_stat);

		if (int_stat & XMTSERV) {
			writew(XMTSERV, &twi->int_stat);
			if (msg->alen) {
				writew(*(msg->abuf++), &twi->xmt_data8);
				--msg->alen;
			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
				writew(*(msg->buf++), &twi->xmt_data8);
				--msg->len;
			} else {
				ctl = readw(&twi->master_ctl);
				if (msg->flags & I2C_M_COMBO)
					writew(ctl | RSTART | MDIR,
							&twi->master_ctl);
				else
					writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & RCVSERV) {
			writew(RCVSERV, &twi->int_stat);
			if (msg->len) {
				*(msg->buf++) = readw(&twi->rcv_data8);
				--msg->len;
			} else if (msg->flags & I2C_M_STOP) {
				ctl = readw(&twi->master_ctl);
				writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & MERR) {
			writew(MERR, &twi->int_stat);
			return msg->len;
		}
		if (int_stat & MCOMP) {
			writew(MCOMP, &twi->int_stat);
			if (msg->flags & I2C_M_COMBO && msg->len) {
				ctl = readw(&twi->master_ctl);
				ctl = (ctl & ~RSTART) |
					(min(msg->len, 0xff) << 6) | MEN | MDIR;
				writew(ctl, &twi->master_ctl);
			} else
				break;
		}

		/* If we were able to do something, reset timeout */
		if (int_stat)
			timebase = get_timer(0);

	} while (get_timer(timebase) < I2C_TIMEOUT);

	return msg->len;
}

static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
			int alen, uint8_t *buffer, int len, uint8_t flags)
{
	struct twi_regs *twi = i2c_get_base(adap);
	int ret;
	u16 ctl;
	uchar addr_buffer[] = {
		(addr >>  0),
		(addr >>  8),
		(addr >> 16),
	};
	struct adi_i2c_msg msg = {
		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
		.buf   = buffer,
		.len   = len,
		.abuf  = addr_buffer,
		.alen  = alen,
	};

	/* wait for things to settle */
	while (readw(&twi->master_stat) & BUSBUSY)
		if (ctrlc())
			return 1;

	/* Set Transmit device address */
	writew(chip, &twi->master_addr);

	/* Clear the FIFO before starting things */
	writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
	writew(0, &twi->fifo_ctl);

	/* prime the pump */
	if (msg.alen) {
		len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
		writew(*(msg.abuf++), &twi->xmt_data8);
		--msg.alen;
	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
		writew(*(msg.buf++), &twi->xmt_data8);
		--msg.len;
	}

	/* clear int stat */
	writew(-1, &twi->master_stat);
	writew(-1, &twi->int_stat);
	writew(0, &twi->int_mask);

	/* Master enable */
	ctl = readw(&twi->master_ctl);
	ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
		((msg.flags & I2C_M_READ) ? MDIR : 0);
	writew(ctl, &twi->master_ctl);

	/* process the rest */
	ret = wait_for_completion(twi, &msg);

	if (ret) {
		ctl = readw(&twi->master_ctl) & ~MEN;
		writew(ctl, &twi->master_ctl);
		ctl = readw(&twi->control) & ~TWI_ENA;
		writew(ctl, &twi->control);
		ctl = readw(&twi->control) | TWI_ENA;
		writew(ctl, &twi->control);
	}

	return ret;
}

static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);

	/* Set TWI interface clock */
	if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
		return -1;
	clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
	writew(clkdiv, &twi->clkdiv);

	/* Don't turn it on */
	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);

	return 0;
}

static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;

	/* Set TWI internal clock as 10MHz */
	writew(prescale, &twi->control);

	/* Set TWI interface clock as specified */
	i2c_set_bus_speed(speed);

	/* Enable it */
	writew(TWI_ENA | prescale, &twi->control);
}

static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer,
			len, alen ? I2C_M_COMBO : I2C_M_READ);
}

static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
}

static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	u8 byte;
	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
}

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_MAX_I2C_BUS > 2
	case 2:
		return (struct twi_regs *)TWI2_CLKDIV;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
	case 1:
		return (struct twi_regs *)TWI1_CLKDIV;
#endif
	case 0:
		return (struct twi_regs *)TWI0_CLKDIV;

	default:
		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	}

	return NULL;
}

U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 0)

#if CONFIG_SYS_MAX_I2C_BUS > 1
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 1)
#endif

#if CONFIG_SYS_MAX_I2C_BUS > 2
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 2)
#endif
Commit	Line	Data
be853bf8	1	/*
fea9b69a	2	* i2c.c - driver for ADI TWI/I2C
be853bf8	3	*
fea9b69a	4	* Copyright (c) 2006-2014 Analog Devices Inc.
be853bf8 MF	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
24b852a7	10	#include <console.h>
be853bf8 MF	11	#include <i2c.h>
be853bf8 MF	12
d6a320d5	13	#include <asm/clock.h>
fea9b69a	14	#include <asm/twi.h>
a6be70f7	15	#include <asm/io.h>
be853bf8	16
c469703b SJ	17	static struct twi_regs i2c_get_base(struct i2c_adapter adap);
c469703b SJ	18
b5cebb4f MF	19	/* Every register is 32bit aligned, but only 16bits in size */
	20	#define ureg(name) u16 name; u16 __pad_##name;
	21	struct twi_regs {
	22	ureg(clkdiv);
	23	ureg(control);
	24	ureg(slave_ctl);
	25	ureg(slave_stat);
	26	ureg(slave_addr);
	27	ureg(master_ctl);
	28	ureg(master_stat);
	29	ureg(master_addr);
	30	ureg(int_stat);
	31	ureg(int_mask);
	32	ureg(fifo_ctl);
	33	ureg(fifo_stat);
	34	char __pad[0x50];
	35	ureg(xmt_data8);
	36	ureg(xmt_data16);
	37	ureg(rcv_data8);
	38	ureg(rcv_data16);
	39	};
	40	#undef ureg
	41
b5cebb4f MF	42	#ifdef TWI_CLKDIV
b5cebb4f MF	43	#define TWI0_CLKDIV TWI_CLKDIV
c469703b SJ	44	# ifdef CONFIG_SYS_MAX_I2C_BUS
	45	# undef CONFIG_SYS_MAX_I2C_BUS
	46	# endif
	47	#define CONFIG_SYS_MAX_I2C_BUS 1
be853bf8	48	#endif
08a1c625 MF	49
	50	/*
	51	* The way speed is changed into duty often results in integer truncation
	52	* with 50% duty, so we'll force rounding up to the next duty by adding 1
	53	* to the max. In practice this will get us a speed of something like
	54	* 385 KHz. The other limit is easy to handle as it is only 8 bits.
	55	*/
	56	#define I2C_SPEED_MAX 400000
	57	#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
	58	#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
	59	#define I2C_DUTY_MIN 0xff /* 8 bit limited */
	60	#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
	61	/* Note: duty is inverse of speed, so the comparisons below are correct */
	62	#if SYS_I2C_DUTY < I2C_DUTY_MAX \|\| SYS_I2C_DUTY > I2C_DUTY_MIN
c469703b	63	# error "The I2C hardware can only operate 20KHz - 400KHz"
be853bf8 MF	64	#endif
	65
	66	/* All transfers are described by this data structure */
fffff726	67	struct adi_i2c_msg {
be853bf8 MF	68	u8 flags;
	69	#define I2C_M_COMBO 0x4
	70	#define I2C_M_STOP 0x2
	71	#define I2C_M_READ 0x1
	72	int len; /* msg length */
	73	u8 buf; / pointer to msg data */
	74	int alen; /* addr length */
	75	u8 abuf; / addr buffer */
	76	};
	77
3814ea4f MF	78	/* Allow msec timeout per ~byte transfer */
	79	#define I2C_TIMEOUT 10
	80
be853bf8 MF	81	/**
	82	* wait_for_completion - manage the actual i2c transfer
	83	* @msg: the i2c msg
	84	*/
fffff726	85	static int wait_for_completion(struct twi_regs twi, struct adi_i2c_msg msg)
be853bf8	86	{
a6be70f7	87	u16 int_stat, ctl;
3814ea4f	88	ulong timebase = get_timer(0);
be853bf8	89
3814ea4f	90	do {
a6be70f7	91	int_stat = readw(&twi->int_stat);
be853bf8 MF	92
be853bf8 MF	93	if (int_stat & XMTSERV) {
a6be70f7	94	writew(XMTSERV, &twi->int_stat);
be853bf8	95	if (msg->alen) {
a6be70f7	96	writew(*(msg->abuf++), &twi->xmt_data8);
be853bf8 MF	97	--msg->alen;
be853bf8 MF	98	} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
a6be70f7	99	writew(*(msg->buf++), &twi->xmt_data8);
be853bf8 MF	100	--msg->len;
be853bf8 MF	101	} else {
a6be70f7 SJ	102	ctl = readw(&twi->master_ctl);
	103	if (msg->flags & I2C_M_COMBO)
	104	writew(ctl \| RSTART \| MDIR,
	105	&twi->master_ctl);
	106	else
	107	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	108	}
	109	}
	110	if (int_stat & RCVSERV) {
a6be70f7	111	writew(RCVSERV, &twi->int_stat);
be853bf8	112	if (msg->len) {
a6be70f7	113	*(msg->buf++) = readw(&twi->rcv_data8);
be853bf8 MF	114	--msg->len;
be853bf8 MF	115	} else if (msg->flags & I2C_M_STOP) {
a6be70f7 SJ	116	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	117	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	118	}
	119	}
	120	if (int_stat & MERR) {
a6be70f7	121	writew(MERR, &twi->int_stat);
3814ea4f	122	return msg->len;
be853bf8 MF	123	}
be853bf8 MF	124	if (int_stat & MCOMP) {
a6be70f7	125	writew(MCOMP, &twi->int_stat);
be853bf8	126	if (msg->flags & I2C_M_COMBO && msg->len) {
a6be70f7 SJ	127	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	128	ctl = (ctl & ~RSTART) \|
b5cebb4f	129	(min(msg->len, 0xff) << 6) \| MEN \| MDIR;
a6be70f7	130	writew(ctl, &twi->master_ctl);
be853bf8 MF	131	} else
	132	break;
	133	}
3814ea4f MF	134
	135	/* If we were able to do something, reset timeout */
	136	if (int_stat)
	137	timebase = get_timer(0);
	138
	139	} while (get_timer(timebase) < I2C_TIMEOUT);
be853bf8 MF	140
	141	return msg->len;
	142	}
	143
c469703b SJ	144	static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
c469703b SJ	145	int alen, uint8_t *buffer, int len, uint8_t flags)
be853bf8	146	{
c469703b	147	struct twi_regs *twi = i2c_get_base(adap);
a6be70f7 SJ	148	int ret;
a6be70f7 SJ	149	u16 ctl;
be853bf8 MF	150	uchar addr_buffer[] = {
	151	(addr >> 0),
	152	(addr >> 8),
	153	(addr >> 16),
	154	};
fffff726	155	struct adi_i2c_msg msg = {
be853bf8 MF	156	.flags = flags \| (len >= 0xff ? I2C_M_STOP : 0),
	157	.buf = buffer,
	158	.len = len,
	159	.abuf = addr_buffer,
	160	.alen = alen,
	161	};
be853bf8	162
be853bf8	163	/* wait for things to settle */
a6be70f7	164	while (readw(&twi->master_stat) & BUSBUSY)
be853bf8 MF	165	if (ctrlc())
	166	return 1;
	167
	168	/* Set Transmit device address */
a6be70f7	169	writew(chip, &twi->master_addr);
be853bf8 MF	170
be853bf8 MF	171	/* Clear the FIFO before starting things */
a6be70f7 SJ	172	writew(XMTFLUSH \| RCVFLUSH, &twi->fifo_ctl);
a6be70f7 SJ	173	writew(0, &twi->fifo_ctl);
be853bf8 MF	174
	175	/* prime the pump */
	176	if (msg.alen) {
98ab14e8	177	len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
a6be70f7	178	writew(*(msg.abuf++), &twi->xmt_data8);
be853bf8 MF	179	--msg.alen;
be853bf8 MF	180	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
a6be70f7	181	writew(*(msg.buf++), &twi->xmt_data8);
be853bf8 MF	182	--msg.len;
	183	}
	184
	185	/* clear int stat */
a6be70f7 SJ	186	writew(-1, &twi->master_stat);
	187	writew(-1, &twi->int_stat);
	188	writew(0, &twi->int_mask);
be853bf8 MF	189
be853bf8 MF	190	/* Master enable */
a6be70f7 SJ	191	ctl = readw(&twi->master_ctl);
	192	ctl = (ctl & FAST) \| (min(len, 0xff) << 6) \| MEN \|
	193	((msg.flags & I2C_M_READ) ? MDIR : 0);
	194	writew(ctl, &twi->master_ctl);
be853bf8 MF	195
be853bf8 MF	196	/* process the rest */
c469703b	197	ret = wait_for_completion(twi, &msg);
be853bf8 MF	198
be853bf8 MF	199	if (ret) {
a6be70f7 SJ	200	ctl = readw(&twi->master_ctl) & ~MEN;
	201	writew(ctl, &twi->master_ctl);
	202	ctl = readw(&twi->control) & ~TWI_ENA;
	203	writew(ctl, &twi->control);
	204	ctl = readw(&twi->control) \| TWI_ENA;
	205	writew(ctl, &twi->control);
be853bf8 MF	206	}
	207
	208	return ret;
	209	}
	210
c469703b	211	static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
08a1c625	212	{
c469703b	213	struct twi_regs *twi = i2c_get_base(adap);
08a1c625 MF	214	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
	215
	216	/* Set TWI interface clock */
	217	if (clkdiv < I2C_DUTY_MAX \|\| clkdiv > I2C_DUTY_MIN)
	218	return -1;
a6be70f7 SJ	219	clkdiv = (clkdiv << 8) \| (clkdiv & 0xff);
a6be70f7 SJ	220	writew(clkdiv, &twi->clkdiv);
08a1c625 MF	221
08a1c625 MF	222	/* Don't turn it on */
a6be70f7	223	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
08a1c625 MF	224
	225	return 0;
	226	}
	227
c469703b	228	static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
be853bf8	229	{
c469703b SJ	230	struct twi_regs *twi = i2c_get_base(adap);
c469703b SJ	231	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
be853bf8 MF	232
be853bf8 MF	233	/* Set TWI internal clock as 10MHz */
a6be70f7	234	writew(prescale, &twi->control);
be853bf8 MF	235
be853bf8 MF	236	/* Set TWI interface clock as specified */
08a1c625	237	i2c_set_bus_speed(speed);
be853bf8	238
08a1c625	239	/* Enable it */
a6be70f7	240	writew(TWI_ENA \| prescale, &twi->control);
be853bf8 MF	241	}
be853bf8 MF	242
c469703b SJ	243	static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	244	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	245	{
c469703b SJ	246	return i2c_transfer(adap, chip, addr, alen, buffer,
c469703b SJ	247	len, alen ? I2C_M_COMBO : I2C_M_READ);
be853bf8 MF	248	}
be853bf8 MF	249
c469703b SJ	250	static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	251	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	252	{
c469703b	253	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
be853bf8 MF	254	}
be853bf8 MF	255
c469703b	256	static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
be853bf8	257	{
c469703b SJ	258	u8 byte;
c469703b SJ	259	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
be853bf8	260	}
b5cebb4f	261
c469703b	262	static struct twi_regs i2c_get_base(struct i2c_adapter adap)
b5cebb4f	263	{
c469703b SJ	264	switch (adap->hwadapnr) {
	265	#if CONFIG_SYS_MAX_I2C_BUS > 2
	266	case 2:
	267	return (struct twi_regs *)TWI2_CLKDIV;
b5cebb4f MF	268	#endif
b5cebb4f MF	269	#if CONFIG_SYS_MAX_I2C_BUS > 1
a6be70f7	270	case 1:
c469703b	271	return (struct twi_regs *)TWI1_CLKDIV;
b5cebb4f	272	#endif
c469703b SJ	273	case 0:
	274	return (struct twi_regs *)TWI0_CLKDIV;
	275
	276	default:
	277	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
b5cebb4f	278	}
c469703b SJ	279
c469703b SJ	280	return NULL;
b5cebb4f MF	281	}
b5cebb4f MF	282
c469703b SJ	283	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
	284	adi_i2c_read, adi_i2c_write,
	285	adi_i2c_setspeed,
	286	CONFIG_SYS_I2C_SPEED,
	287	0,
	288	0)
	289
b5cebb4f	290	#if CONFIG_SYS_MAX_I2C_BUS > 1
c469703b SJ	291	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
	292	adi_i2c_read, adi_i2c_write,
	293	adi_i2c_setspeed,
	294	CONFIG_SYS_I2C_SPEED,
	295	0,
	296	1)
b5cebb4f	297	#endif
c469703b	298
b5cebb4f	299	#if CONFIG_SYS_MAX_I2C_BUS > 2
c469703b SJ	300	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
	301	adi_i2c_read, adi_i2c_write,
	302	adi_i2c_setspeed,
	303	CONFIG_SYS_I2C_SPEED,
	304	0,
	305	2)
b5cebb4f	306	#endif