[people/ms/u-boot.git] / drivers / i2c / adi_i2c.c

/*
 * i2c.c - driver for ADI TWI/I2C
 *
 * Copyright (c) 2006-2014 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <i2c.h>

#include <asm/clock.h>
#include <asm/twi.h>
#include <asm/io.h>

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);

/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
struct twi_regs {
	ureg(clkdiv);
	ureg(control);
	ureg(slave_ctl);
	ureg(slave_stat);
	ureg(slave_addr);
	ureg(master_ctl);
	ureg(master_stat);
	ureg(master_addr);
	ureg(int_stat);
	ureg(int_mask);
	ureg(fifo_ctl);
	ureg(fifo_stat);
	char __pad[0x50];
	ureg(xmt_data8);
	ureg(xmt_data16);
	ureg(rcv_data8);
	ureg(rcv_data16);
};
#undef ureg

#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
# ifdef CONFIG_SYS_MAX_I2C_BUS
# undef CONFIG_SYS_MAX_I2C_BUS
# endif
#define CONFIG_SYS_MAX_I2C_BUS 1
#endif

/*
 * The way speed is changed into duty often results in integer truncation
 * with 50% duty, so we'll force rounding up to the next duty by adding 1
 * to the max.  In practice this will get us a speed of something like
 * 385 KHz.  The other limit is easy to handle as it is only 8 bits.
 */
#define I2C_SPEED_MAX             400000
#define I2C_SPEED_TO_DUTY(speed)  (5000000 / (speed))
#define I2C_DUTY_MAX              (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
#define I2C_DUTY_MIN              0xff	/* 8 bit limited */
#define SYS_I2C_DUTY              I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
/* Note: duty is inverse of speed, so the comparisons below are correct */
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
# error "The I2C hardware can only operate 20KHz - 400KHz"
#endif

/* All transfers are described by this data structure */
struct i2c_msg {
	u8 flags;
#define I2C_M_COMBO		0x4
#define I2C_M_STOP		0x2
#define I2C_M_READ		0x1
	int len;		/* msg length */
	u8 *buf;		/* pointer to msg data */
	int alen;		/* addr length */
	u8 *abuf;		/* addr buffer */
};

/* Allow msec timeout per ~byte transfer */
#define I2C_TIMEOUT 10

/**
 * wait_for_completion - manage the actual i2c transfer
 *	@msg: the i2c msg
 */
static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
{
	u16 int_stat, ctl;
	ulong timebase = get_timer(0);

	do {
		int_stat = readw(&twi->int_stat);

		if (int_stat & XMTSERV) {
			writew(XMTSERV, &twi->int_stat);
			if (msg->alen) {
				writew(*(msg->abuf++), &twi->xmt_data8);
				--msg->alen;
			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
				writew(*(msg->buf++), &twi->xmt_data8);
				--msg->len;
			} else {
				ctl = readw(&twi->master_ctl);
				if (msg->flags & I2C_M_COMBO)
					writew(ctl | RSTART | MDIR,
							&twi->master_ctl);
				else
					writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & RCVSERV) {
			writew(RCVSERV, &twi->int_stat);
			if (msg->len) {
				*(msg->buf++) = readw(&twi->rcv_data8);
				--msg->len;
			} else if (msg->flags & I2C_M_STOP) {
				ctl = readw(&twi->master_ctl);
				writew(ctl | STOP, &twi->master_ctl);
			}
		}
		if (int_stat & MERR) {
			writew(MERR, &twi->int_stat);
			return msg->len;
		}
		if (int_stat & MCOMP) {
			writew(MCOMP, &twi->int_stat);
			if (msg->flags & I2C_M_COMBO && msg->len) {
				ctl = readw(&twi->master_ctl);
				ctl = (ctl & ~RSTART) |
					(min(msg->len, 0xff) << 6) | MEN | MDIR;
				writew(ctl, &twi->master_ctl);
			} else
				break;
		}

		/* If we were able to do something, reset timeout */
		if (int_stat)
			timebase = get_timer(0);

	} while (get_timer(timebase) < I2C_TIMEOUT);

	return msg->len;
}

static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
			int alen, uint8_t *buffer, int len, uint8_t flags)
{
	struct twi_regs *twi = i2c_get_base(adap);
	int ret;
	u16 ctl;
	uchar addr_buffer[] = {
		(addr >>  0),
		(addr >>  8),
		(addr >> 16),
	};
	struct i2c_msg msg = {
		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
		.buf   = buffer,
		.len   = len,
		.abuf  = addr_buffer,
		.alen  = alen,
	};

	/* wait for things to settle */
	while (readw(&twi->master_stat) & BUSBUSY)
		if (ctrlc())
			return 1;

	/* Set Transmit device address */
	writew(chip, &twi->master_addr);

	/* Clear the FIFO before starting things */
	writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
	writew(0, &twi->fifo_ctl);

	/* prime the pump */
	if (msg.alen) {
		len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
		writew(*(msg.abuf++), &twi->xmt_data8);
		--msg.alen;
	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
		writew(*(msg.buf++), &twi->xmt_data8);
		--msg.len;
	}

	/* clear int stat */
	writew(-1, &twi->master_stat);
	writew(-1, &twi->int_stat);
	writew(0, &twi->int_mask);

	/* Master enable */
	ctl = readw(&twi->master_ctl);
	ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
		((msg.flags & I2C_M_READ) ? MDIR : 0);
	writew(ctl, &twi->master_ctl);

	/* process the rest */
	ret = wait_for_completion(twi, &msg);

	if (ret) {
		ctl = readw(&twi->master_ctl) & ~MEN;
		writew(ctl, &twi->master_ctl);
		ctl = readw(&twi->control) & ~TWI_ENA;
		writew(ctl, &twi->control);
		ctl = readw(&twi->control) | TWI_ENA;
		writew(ctl, &twi->control);
	}

	return ret;
}

static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);

	/* Set TWI interface clock */
	if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
		return -1;
	clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
	writew(clkdiv, &twi->clkdiv);

	/* Don't turn it on */
	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);

	return 0;
}

static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	struct twi_regs *twi = i2c_get_base(adap);
	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;

	/* Set TWI internal clock as 10MHz */
	writew(prescale, &twi->control);

	/* Set TWI interface clock as specified */
	i2c_set_bus_speed(speed);

	/* Enable it */
	writew(TWI_ENA | prescale, &twi->control);
}

static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer,
			len, alen ? I2C_M_COMBO : I2C_M_READ);
}

static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
			uint addr, int alen, uint8_t *buffer, int len)
{
	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
}

static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	u8 byte;
	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
}

static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_MAX_I2C_BUS > 2
	case 2:
		return (struct twi_regs *)TWI2_CLKDIV;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
	case 1:
		return (struct twi_regs *)TWI1_CLKDIV;
#endif
	case 0:
		return (struct twi_regs *)TWI0_CLKDIV;

	default:
		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	}

	return NULL;
}

U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 0)

#if CONFIG_SYS_MAX_I2C_BUS > 1
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 1)
#endif

#if CONFIG_SYS_MAX_I2C_BUS > 2
U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
			 adi_i2c_read, adi_i2c_write,
			 adi_i2c_setspeed,
			 CONFIG_SYS_I2C_SPEED,
			 0,
			 2)
#endif
Commit	Line	Data
be853bf8	1	/*
fea9b69a	2	* i2c.c - driver for ADI TWI/I2C
be853bf8	3	*
fea9b69a	4	* Copyright (c) 2006-2014 Analog Devices Inc.
be853bf8 MF	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
	10	#include <i2c.h>
	11
d6a320d5	12	#include <asm/clock.h>
fea9b69a	13	#include <asm/twi.h>
a6be70f7	14	#include <asm/io.h>
be853bf8	15
c469703b SJ	16	static struct twi_regs i2c_get_base(struct i2c_adapter adap);
c469703b SJ	17
b5cebb4f MF	18	/* Every register is 32bit aligned, but only 16bits in size */
	19	#define ureg(name) u16 name; u16 __pad_##name;
	20	struct twi_regs {
	21	ureg(clkdiv);
	22	ureg(control);
	23	ureg(slave_ctl);
	24	ureg(slave_stat);
	25	ureg(slave_addr);
	26	ureg(master_ctl);
	27	ureg(master_stat);
	28	ureg(master_addr);
	29	ureg(int_stat);
	30	ureg(int_mask);
	31	ureg(fifo_ctl);
	32	ureg(fifo_stat);
	33	char __pad[0x50];
	34	ureg(xmt_data8);
	35	ureg(xmt_data16);
	36	ureg(rcv_data8);
	37	ureg(rcv_data16);
	38	};
	39	#undef ureg
	40
b5cebb4f MF	41	#ifdef TWI_CLKDIV
b5cebb4f MF	42	#define TWI0_CLKDIV TWI_CLKDIV
c469703b SJ	43	# ifdef CONFIG_SYS_MAX_I2C_BUS
	44	# undef CONFIG_SYS_MAX_I2C_BUS
	45	# endif
	46	#define CONFIG_SYS_MAX_I2C_BUS 1
be853bf8	47	#endif
08a1c625 MF	48
	49	/*
	50	* The way speed is changed into duty often results in integer truncation
	51	* with 50% duty, so we'll force rounding up to the next duty by adding 1
	52	* to the max. In practice this will get us a speed of something like
	53	* 385 KHz. The other limit is easy to handle as it is only 8 bits.
	54	*/
	55	#define I2C_SPEED_MAX 400000
	56	#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
	57	#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
	58	#define I2C_DUTY_MIN 0xff /* 8 bit limited */
	59	#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
	60	/* Note: duty is inverse of speed, so the comparisons below are correct */
	61	#if SYS_I2C_DUTY < I2C_DUTY_MAX \|\| SYS_I2C_DUTY > I2C_DUTY_MIN
c469703b	62	# error "The I2C hardware can only operate 20KHz - 400KHz"
be853bf8 MF	63	#endif
	64
	65	/* All transfers are described by this data structure */
	66	struct i2c_msg {
	67	u8 flags;
	68	#define I2C_M_COMBO 0x4
	69	#define I2C_M_STOP 0x2
	70	#define I2C_M_READ 0x1
	71	int len; /* msg length */
	72	u8 buf; / pointer to msg data */
	73	int alen; /* addr length */
	74	u8 abuf; / addr buffer */
	75	};
	76
3814ea4f MF	77	/* Allow msec timeout per ~byte transfer */
	78	#define I2C_TIMEOUT 10
	79
be853bf8 MF	80	/**
	81	* wait_for_completion - manage the actual i2c transfer
	82	* @msg: the i2c msg
	83	*/
c469703b	84	static int wait_for_completion(struct twi_regs twi, struct i2c_msg msg)
be853bf8	85	{
a6be70f7	86	u16 int_stat, ctl;
3814ea4f	87	ulong timebase = get_timer(0);
be853bf8	88
3814ea4f	89	do {
a6be70f7	90	int_stat = readw(&twi->int_stat);
be853bf8 MF	91
be853bf8 MF	92	if (int_stat & XMTSERV) {
a6be70f7	93	writew(XMTSERV, &twi->int_stat);
be853bf8	94	if (msg->alen) {
a6be70f7	95	writew(*(msg->abuf++), &twi->xmt_data8);
be853bf8 MF	96	--msg->alen;
be853bf8 MF	97	} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
a6be70f7	98	writew(*(msg->buf++), &twi->xmt_data8);
be853bf8 MF	99	--msg->len;
be853bf8 MF	100	} else {
a6be70f7 SJ	101	ctl = readw(&twi->master_ctl);
	102	if (msg->flags & I2C_M_COMBO)
	103	writew(ctl \| RSTART \| MDIR,
	104	&twi->master_ctl);
	105	else
	106	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	107	}
	108	}
	109	if (int_stat & RCVSERV) {
a6be70f7	110	writew(RCVSERV, &twi->int_stat);
be853bf8	111	if (msg->len) {
a6be70f7	112	*(msg->buf++) = readw(&twi->rcv_data8);
be853bf8 MF	113	--msg->len;
be853bf8 MF	114	} else if (msg->flags & I2C_M_STOP) {
a6be70f7 SJ	115	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	116	writew(ctl \| STOP, &twi->master_ctl);
be853bf8 MF	117	}
	118	}
	119	if (int_stat & MERR) {
a6be70f7	120	writew(MERR, &twi->int_stat);
3814ea4f	121	return msg->len;
be853bf8 MF	122	}
be853bf8 MF	123	if (int_stat & MCOMP) {
a6be70f7	124	writew(MCOMP, &twi->int_stat);
be853bf8	125	if (msg->flags & I2C_M_COMBO && msg->len) {
a6be70f7 SJ	126	ctl = readw(&twi->master_ctl);
a6be70f7 SJ	127	ctl = (ctl & ~RSTART) \|
b5cebb4f	128	(min(msg->len, 0xff) << 6) \| MEN \| MDIR;
a6be70f7	129	writew(ctl, &twi->master_ctl);
be853bf8 MF	130	} else
	131	break;
	132	}
3814ea4f MF	133
	134	/* If we were able to do something, reset timeout */
	135	if (int_stat)
	136	timebase = get_timer(0);
	137
	138	} while (get_timer(timebase) < I2C_TIMEOUT);
be853bf8 MF	139
	140	return msg->len;
	141	}
	142
c469703b SJ	143	static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
c469703b SJ	144	int alen, uint8_t *buffer, int len, uint8_t flags)
be853bf8	145	{
c469703b	146	struct twi_regs *twi = i2c_get_base(adap);
a6be70f7 SJ	147	int ret;
a6be70f7 SJ	148	u16 ctl;
be853bf8 MF	149	uchar addr_buffer[] = {
	150	(addr >> 0),
	151	(addr >> 8),
	152	(addr >> 16),
	153	};
	154	struct i2c_msg msg = {
	155	.flags = flags \| (len >= 0xff ? I2C_M_STOP : 0),
	156	.buf = buffer,
	157	.len = len,
	158	.abuf = addr_buffer,
	159	.alen = alen,
	160	};
be853bf8	161
be853bf8	162	/* wait for things to settle */
a6be70f7	163	while (readw(&twi->master_stat) & BUSBUSY)
be853bf8 MF	164	if (ctrlc())
	165	return 1;
	166
	167	/* Set Transmit device address */
a6be70f7	168	writew(chip, &twi->master_addr);
be853bf8 MF	169
be853bf8 MF	170	/* Clear the FIFO before starting things */
a6be70f7 SJ	171	writew(XMTFLUSH \| RCVFLUSH, &twi->fifo_ctl);
a6be70f7 SJ	172	writew(0, &twi->fifo_ctl);
be853bf8 MF	173
	174	/* prime the pump */
	175	if (msg.alen) {
98ab14e8	176	len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
a6be70f7	177	writew(*(msg.abuf++), &twi->xmt_data8);
be853bf8 MF	178	--msg.alen;
be853bf8 MF	179	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
a6be70f7	180	writew(*(msg.buf++), &twi->xmt_data8);
be853bf8 MF	181	--msg.len;
	182	}
	183
	184	/* clear int stat */
a6be70f7 SJ	185	writew(-1, &twi->master_stat);
	186	writew(-1, &twi->int_stat);
	187	writew(0, &twi->int_mask);
be853bf8 MF	188
be853bf8 MF	189	/* Master enable */
a6be70f7 SJ	190	ctl = readw(&twi->master_ctl);
	191	ctl = (ctl & FAST) \| (min(len, 0xff) << 6) \| MEN \|
	192	((msg.flags & I2C_M_READ) ? MDIR : 0);
	193	writew(ctl, &twi->master_ctl);
be853bf8 MF	194
be853bf8 MF	195	/* process the rest */
c469703b	196	ret = wait_for_completion(twi, &msg);
be853bf8 MF	197
be853bf8 MF	198	if (ret) {
a6be70f7 SJ	199	ctl = readw(&twi->master_ctl) & ~MEN;
	200	writew(ctl, &twi->master_ctl);
	201	ctl = readw(&twi->control) & ~TWI_ENA;
	202	writew(ctl, &twi->control);
	203	ctl = readw(&twi->control) \| TWI_ENA;
	204	writew(ctl, &twi->control);
be853bf8 MF	205	}
	206
	207	return ret;
	208	}
	209
c469703b	210	static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
08a1c625	211	{
c469703b	212	struct twi_regs *twi = i2c_get_base(adap);
08a1c625 MF	213	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
	214
	215	/* Set TWI interface clock */
	216	if (clkdiv < I2C_DUTY_MAX \|\| clkdiv > I2C_DUTY_MIN)
	217	return -1;
a6be70f7 SJ	218	clkdiv = (clkdiv << 8) \| (clkdiv & 0xff);
a6be70f7 SJ	219	writew(clkdiv, &twi->clkdiv);
08a1c625 MF	220
08a1c625 MF	221	/* Don't turn it on */
a6be70f7	222	writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
08a1c625 MF	223
	224	return 0;
	225	}
	226
c469703b	227	static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
be853bf8	228	{
c469703b SJ	229	struct twi_regs *twi = i2c_get_base(adap);
c469703b SJ	230	u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
be853bf8 MF	231
be853bf8 MF	232	/* Set TWI internal clock as 10MHz */
a6be70f7	233	writew(prescale, &twi->control);
be853bf8 MF	234
be853bf8 MF	235	/* Set TWI interface clock as specified */
08a1c625	236	i2c_set_bus_speed(speed);
be853bf8	237
08a1c625	238	/* Enable it */
a6be70f7	239	writew(TWI_ENA \| prescale, &twi->control);
be853bf8 MF	240	}
be853bf8 MF	241
c469703b SJ	242	static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	243	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	244	{
c469703b SJ	245	return i2c_transfer(adap, chip, addr, alen, buffer,
c469703b SJ	246	len, alen ? I2C_M_COMBO : I2C_M_READ);
be853bf8 MF	247	}
be853bf8 MF	248
c469703b SJ	249	static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
c469703b SJ	250	uint addr, int alen, uint8_t *buffer, int len)
be853bf8	251	{
c469703b	252	return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
be853bf8 MF	253	}
be853bf8 MF	254
c469703b	255	static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
be853bf8	256	{
c469703b SJ	257	u8 byte;
c469703b SJ	258	return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
be853bf8	259	}
b5cebb4f	260
c469703b	261	static struct twi_regs i2c_get_base(struct i2c_adapter adap)
b5cebb4f	262	{
c469703b SJ	263	switch (adap->hwadapnr) {
	264	#if CONFIG_SYS_MAX_I2C_BUS > 2
	265	case 2:
	266	return (struct twi_regs *)TWI2_CLKDIV;
b5cebb4f MF	267	#endif
b5cebb4f MF	268	#if CONFIG_SYS_MAX_I2C_BUS > 1
a6be70f7	269	case 1:
c469703b	270	return (struct twi_regs *)TWI1_CLKDIV;
b5cebb4f	271	#endif
c469703b SJ	272	case 0:
	273	return (struct twi_regs *)TWI0_CLKDIV;
	274
	275	default:
	276	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
b5cebb4f	277	}
c469703b SJ	278
c469703b SJ	279	return NULL;
b5cebb4f MF	280	}
b5cebb4f MF	281
c469703b SJ	282	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
	283	adi_i2c_read, adi_i2c_write,
	284	adi_i2c_setspeed,
	285	CONFIG_SYS_I2C_SPEED,
	286	0,
	287	0)
	288
b5cebb4f	289	#if CONFIG_SYS_MAX_I2C_BUS > 1
c469703b SJ	290	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
	291	adi_i2c_read, adi_i2c_write,
	292	adi_i2c_setspeed,
	293	CONFIG_SYS_I2C_SPEED,
	294	0,
	295	1)
b5cebb4f	296	#endif
c469703b	297
b5cebb4f	298	#if CONFIG_SYS_MAX_I2C_BUS > 2
c469703b SJ	299	U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
	300	adi_i2c_read, adi_i2c_write,
	301	adi_i2c_setspeed,
	302	CONFIG_SYS_I2C_SPEED,
	303	0,
	304	2)
b5cebb4f	305	#endif