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4dc038f3 | 1 | /* |
2 | * Copyright (C) 2012-2020 ASPEED Technology Inc. | |
3 | * Copyright 2016 IBM Corporation | |
4 | * Copyright 2017 Google, Inc. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | #ifndef __AST_I2C_H_ | |
9 | #define __AST_I2C_H_ | |
10 | ||
11 | struct ast_i2c_regs { | |
12 | u32 fcr; | |
13 | u32 cactcr1; | |
14 | u32 cactcr2; | |
15 | u32 icr; | |
16 | u32 isr; | |
17 | u32 csr; | |
18 | u32 sdar; | |
19 | u32 pbcr; | |
20 | u32 trbbr; | |
21 | #ifdef CONFIG_ASPEED_AST2500 | |
22 | u32 dma_mbar; | |
23 | u32 dma_tlr; | |
24 | #endif | |
25 | }; | |
26 | ||
27 | /* Device Register Definition */ | |
28 | /* 0x00 : I2CD Function Control Register */ | |
29 | #define I2CD_BUFF_SEL_MASK (0x7 << 20) | |
30 | #define I2CD_BUFF_SEL(x) (x << 20) | |
31 | #define I2CD_M_SDA_LOCK_EN (0x1 << 16) | |
32 | #define I2CD_MULTI_MASTER_DIS (0x1 << 15) | |
33 | #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) | |
34 | #define I2CD_MSB_STS (0x1 << 9) | |
35 | #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) | |
36 | #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) | |
37 | #define I2CD_M_HIGH_SPEED_EN (0x1 << 6) | |
38 | #define I2CD_DEF_ADDR_EN (0x1 << 5) | |
39 | #define I2CD_DEF_ALERT_EN (0x1 << 4) | |
40 | #define I2CD_DEF_ARP_EN (0x1 << 3) | |
41 | #define I2CD_DEF_GCALL_EN (0x1 << 2) | |
42 | #define I2CD_SLAVE_EN (0x1 << 1) | |
43 | #define I2CD_MASTER_EN (0x1) | |
44 | ||
45 | /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ | |
46 | /* Base register value. These bits are always set by the driver. */ | |
47 | #define I2CD_CACTC_BASE 0xfff00300 | |
48 | #define I2CD_TCKHIGH_SHIFT 16 | |
49 | #define I2CD_TCKLOW_SHIFT 12 | |
50 | #define I2CD_THDDAT_SHIFT 10 | |
51 | #define I2CD_TO_DIV_SHIFT 8 | |
52 | #define I2CD_BASE_DIV_SHIFT 0 | |
53 | ||
54 | /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ | |
55 | #define I2CD_tTIMEOUT 1 | |
56 | #define I2CD_NO_TIMEOUT_CTRL 0 | |
57 | ||
58 | /* 0x0c : I2CD Interrupt Control Register & | |
59 | * 0x10 : I2CD Interrupt Status Register | |
60 | * | |
61 | * These share bit definitions, so use the same values for the enable & | |
62 | * status bits. | |
63 | */ | |
64 | #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) | |
65 | #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) | |
66 | #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) | |
67 | #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) | |
68 | #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) | |
69 | #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) | |
70 | #define I2CD_INTR_GCALL_ADDR (0x1 << 8) | |
71 | #define I2CD_INTR_SLAVE_MATCH (0x1 << 7) | |
72 | #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) | |
73 | #define I2CD_INTR_ABNORMAL (0x1 << 5) | |
74 | #define I2CD_INTR_NORMAL_STOP (0x1 << 4) | |
75 | #define I2CD_INTR_ARBIT_LOSS (0x1 << 3) | |
76 | #define I2CD_INTR_RX_DONE (0x1 << 2) | |
77 | #define I2CD_INTR_TX_NAK (0x1 << 1) | |
78 | #define I2CD_INTR_TX_ACK (0x1 << 0) | |
79 | ||
80 | /* 0x14 : I2CD Command/Status Register */ | |
81 | #define I2CD_SDA_OE (0x1 << 28) | |
82 | #define I2CD_SDA_O (0x1 << 27) | |
83 | #define I2CD_SCL_OE (0x1 << 26) | |
84 | #define I2CD_SCL_O (0x1 << 25) | |
85 | #define I2CD_TX_TIMING (0x1 << 24) | |
86 | #define I2CD_TX_STATUS (0x1 << 23) | |
87 | ||
88 | /* Tx State Machine */ | |
89 | #define I2CD_IDLE 0x0 | |
90 | #define I2CD_MACTIVE 0x8 | |
91 | #define I2CD_MSTART 0x9 | |
92 | #define I2CD_MSTARTR 0xa | |
93 | #define I2CD_MSTOP 0xb | |
94 | #define I2CD_MTXD 0xc | |
95 | #define I2CD_MRXACK 0xd | |
96 | #define I2CD_MRXD 0xe | |
97 | #define I2CD_MTXACK 0xf | |
98 | #define I2CD_SWAIT 0x1 | |
99 | #define I2CD_SRXD 0x4 | |
100 | #define I2CD_STXACK 0x5 | |
101 | #define I2CD_STXD 0x6 | |
102 | #define I2CD_SRXACK 0x7 | |
103 | #define I2CD_RECOVER 0x3 | |
104 | ||
105 | #define I2CD_SCL_LINE_STS (0x1 << 18) | |
106 | #define I2CD_SDA_LINE_STS (0x1 << 17) | |
107 | #define I2CD_BUS_BUSY_STS (0x1 << 16) | |
108 | #define I2CD_SDA_OE_OUT_DIR (0x1 << 15) | |
109 | #define I2CD_SDA_O_OUT_DIR (0x1 << 14) | |
110 | #define I2CD_SCL_OE_OUT_DIR (0x1 << 13) | |
111 | #define I2CD_SCL_O_OUT_DIR (0x1 << 12) | |
112 | #define I2CD_BUS_RECOVER_CMD (0x1 << 11) | |
113 | #define I2CD_S_ALT_EN (0x1 << 10) | |
114 | #define I2CD_RX_DMA_ENABLE (0x1 << 9) | |
115 | #define I2CD_TX_DMA_ENABLE (0x1 << 8) | |
116 | ||
117 | /* Command Bit */ | |
118 | #define I2CD_RX_BUFF_ENABLE (0x1 << 7) | |
119 | #define I2CD_TX_BUFF_ENABLE (0x1 << 6) | |
120 | #define I2CD_M_STOP_CMD (0x1 << 5) | |
121 | #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) | |
122 | #define I2CD_M_RX_CMD (0x1 << 3) | |
123 | #define I2CD_S_TX_CMD (0x1 << 2) | |
124 | #define I2CD_M_TX_CMD (0x1 << 1) | |
125 | #define I2CD_M_START_CMD 0x1 | |
126 | ||
127 | #define I2CD_RX_DATA_SHIFT 8 | |
128 | #define I2CD_RX_DATA_MASK (0xff << I2CD_RX_DATA_SHIFT) | |
129 | ||
130 | #define I2C_HIGHSPEED_RATE 400000 | |
131 | ||
132 | #endif /* __AST_I2C_H_ */ |