[people/ms/u-boot.git] / drivers / i2c / bfin-twi_i2c.c

/*
 * i2c.c - driver for Blackfin on-chip TWI/I2C
 *
 * Copyright (c) 2006-2010 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <i2c.h>

#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/mach-common/bits/twi.h>

/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
struct twi_regs {
	ureg(clkdiv);
	ureg(control);
	ureg(slave_ctl);
	ureg(slave_stat);
	ureg(slave_addr);
	ureg(master_ctl);
	ureg(master_stat);
	ureg(master_addr);
	ureg(int_stat);
	ureg(int_mask);
	ureg(fifo_ctl);
	ureg(fifo_stat);
	char __pad[0x50];
	ureg(xmt_data8);
	ureg(xmt_data16);
	ureg(rcv_data8);
	ureg(rcv_data16);
};
#undef ureg

/* U-Boot I2C framework allows only one active device at a time.  */
#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
#endif
static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;

#ifdef DEBUG
# define dmemset(s, c, n) memset(s, c, n)
#else
# define dmemset(s, c, n)
#endif
#define debugi(fmt, args...) \
	debug( \
		"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
		twi->master_stat, twi->fifo_stat, twi->int_stat, \
		__func__, __LINE__, ## args)

#ifdef CONFIG_TWICLK_KHZ
# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
#endif

/*
 * The way speed is changed into duty often results in integer truncation
 * with 50% duty, so we'll force rounding up to the next duty by adding 1
 * to the max.  In practice this will get us a speed of something like
 * 385 KHz.  The other limit is easy to handle as it is only 8 bits.
 */
#define I2C_SPEED_MAX             400000
#define I2C_SPEED_TO_DUTY(speed)  (5000000 / (speed))
#define I2C_DUTY_MAX              (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
#define I2C_DUTY_MIN              0xff	/* 8 bit limited */
#define SYS_I2C_DUTY              I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
/* Note: duty is inverse of speed, so the comparisons below are correct */
#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
#endif

/* All transfers are described by this data structure */
struct i2c_msg {
	u8 flags;
#define I2C_M_COMBO		0x4
#define I2C_M_STOP		0x2
#define I2C_M_READ		0x1
	int len;		/* msg length */
	u8 *buf;		/* pointer to msg data */
	int alen;		/* addr length */
	u8 *abuf;		/* addr buffer */
};

/* Allow msec timeout per ~byte transfer */
#define I2C_TIMEOUT 10

/**
 * wait_for_completion - manage the actual i2c transfer
 *	@msg: the i2c msg
 */
static int wait_for_completion(struct i2c_msg *msg)
{
	uint16_t int_stat;
	ulong timebase = get_timer(0);

	do {
		int_stat = twi->int_stat;

		if (int_stat & XMTSERV) {
			debugi("processing XMTSERV");
			twi->int_stat = XMTSERV;
			SSYNC();
			if (msg->alen) {
				twi->xmt_data8 = *(msg->abuf++);
				--msg->alen;
			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
				twi->xmt_data8 = *(msg->buf++);
				--msg->len;
			} else {
				twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP;
				SSYNC();
			}
		}
		if (int_stat & RCVSERV) {
			debugi("processing RCVSERV");
			twi->int_stat = RCVSERV;
			SSYNC();
			if (msg->len) {
				*(msg->buf++) = twi->rcv_data8;
				--msg->len;
			} else if (msg->flags & I2C_M_STOP) {
				twi->master_ctl |= STOP;
				SSYNC();
			}
		}
		if (int_stat & MERR) {
			debugi("processing MERR");
			twi->int_stat = MERR;
			SSYNC();
			return msg->len;
		}
		if (int_stat & MCOMP) {
			debugi("processing MCOMP");
			twi->int_stat = MCOMP;
			SSYNC();
			if (msg->flags & I2C_M_COMBO && msg->len) {
				twi->master_ctl = (twi->master_ctl & ~RSTART) |
					(min(msg->len, 0xff) << 6) | MEN | MDIR;
				SSYNC();
			} else
				break;
		}

		/* If we were able to do something, reset timeout */
		if (int_stat)
			timebase = get_timer(0);

	} while (get_timer(timebase) < I2C_TIMEOUT);

	return msg->len;
}

/**
 * i2c_transfer - setup an i2c transfer
 *	@return: 0 if things worked, non-0 if things failed
 *
 *	Here we just get the i2c stuff all prepped and ready, and then tail off
 *	into wait_for_completion() for all the bits to go.
 */
static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
{
	uchar addr_buffer[] = {
		(addr >>  0),
		(addr >>  8),
		(addr >> 16),
	};
	struct i2c_msg msg = {
		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
		.buf   = buffer,
		.len   = len,
		.abuf  = addr_buffer,
		.alen  = alen,
	};
	int ret;

	dmemset(buffer, 0xff, len);
	debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
		chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));

	/* wait for things to settle */
	while (twi->master_stat & BUSBUSY)
		if (ctrlc())
			return 1;

	/* Set Transmit device address */
	twi->master_addr = chip;

	/* Clear the FIFO before starting things */
	twi->fifo_ctl = XMTFLUSH | RCVFLUSH;
	SSYNC();
	twi->fifo_ctl = 0;
	SSYNC();

	/* prime the pump */
	if (msg.alen) {
		len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
		debugi("first byte=0x%02x", *msg.abuf);
		twi->xmt_data8 = *(msg.abuf++);
		--msg.alen;
	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
		debugi("first byte=0x%02x", *msg.buf);
		twi->xmt_data8 = *(msg.buf++);
		--msg.len;
	}

	/* clear int stat */
	twi->master_stat = -1;
	twi->int_stat = -1;
	twi->int_mask = 0;
	SSYNC();

	/* Master enable */
	twi->master_ctl =
			(twi->master_ctl & FAST) |
			(min(len, 0xff) << 6) | MEN |
			((msg.flags & I2C_M_READ) ? MDIR : 0);
	SSYNC();
	debugi("CTL=0x%04x", twi->master_ctl);

	/* process the rest */
	ret = wait_for_completion(&msg);
	debugi("ret=%d", ret);

	if (ret) {
		twi->master_ctl &= ~MEN;
		twi->control &= ~TWI_ENA;
		SSYNC();
		twi->control |= TWI_ENA;
		SSYNC();
	}

	return ret;
}

/**
 * i2c_set_bus_speed - set i2c bus speed
 *	@speed: bus speed (in HZ)
 */
int i2c_set_bus_speed(unsigned int speed)
{
	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);

	/* Set TWI interface clock */
	if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
		return -1;
	twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff);

	/* Don't turn it on */
	twi->master_ctl = (speed > 100000 ? FAST : 0);

	return 0;
}

/**
 * i2c_get_bus_speed - get i2c bus speed
 *	@speed: bus speed (in HZ)
 */
unsigned int i2c_get_bus_speed(void)
{
	/* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
	return 5000000 / (twi->clkdiv & 0xff);
}

/**
 * i2c_init - initialize the i2c bus
 *	@speed: bus speed (in HZ)
 *	@slaveaddr: address of device in slave mode (0 - not slave)
 *
 *	Slave mode isn't actually implemented.  It'll stay that way until
 *	we get a real request for it.
 */
void i2c_init(int speed, int slaveaddr)
{
	uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;

	/* Set TWI internal clock as 10MHz */
	twi->control = prescale;

	/* Set TWI interface clock as specified */
	i2c_set_bus_speed(speed);

	/* Enable it */
	twi->control = TWI_ENA | prescale;
	SSYNC();

	debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);

#if CONFIG_SYS_I2C_SLAVE
# error I2C slave support not tested/supported
	/* If they want us as a slave, do it */
	if (slaveaddr) {
		twi->slave_addr = slaveaddr;
		twi->slave_ctl = SEN;
	}
#endif
}

/**
 * i2c_probe - test if a chip exists at a given i2c address
 *	@chip: i2c chip addr to search for
 *	@return: 0 if found, non-0 if not found
 */
int i2c_probe(uchar chip)
{
	u8 byte;
	return i2c_read(chip, 0, 0, &byte, 1);
}

/**
 * i2c_read - read data from an i2c device
 *	@chip: i2c chip addr
 *	@addr: memory (register) address in the chip
 *	@alen: byte size of address
 *	@buffer: buffer to store data read from chip
 *	@len: how many bytes to read
 *	@return: 0 on success, non-0 on failure
 */
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
}

/**
 * i2c_write - write data to an i2c device
 *	@chip: i2c chip addr
 *	@addr: memory (register) address in the chip
 *	@alen: byte size of address
 *	@buffer: buffer holding data to write to chip
 *	@len: how many bytes to write
 *	@return: 0 on success, non-0 on failure
 */
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	return i2c_transfer(chip, addr, alen, buffer, len, 0);
}

/**
 * i2c_set_bus_num - change active I2C bus
 *	@bus: bus index, zero based
 *	@returns: 0 on success, non-0 on failure
 */
int i2c_set_bus_num(unsigned int bus)
{
	switch (bus) {
#if CONFIG_SYS_MAX_I2C_BUS > 0
		case 0: twi = (void *)TWI0_CLKDIV; return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
		case 1: twi = (void *)TWI1_CLKDIV; return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 2
		case 2: twi = (void *)TWI2_CLKDIV; return 0;
#endif
		default: return -1;
	}
}

/**
 * i2c_get_bus_num - returns index of active I2C bus
 */
unsigned int i2c_get_bus_num(void)
{
	switch ((unsigned long)twi) {
#if CONFIG_SYS_MAX_I2C_BUS > 0
		case TWI0_CLKDIV: return 0;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 1
		case TWI1_CLKDIV: return 1;
#endif
#if CONFIG_SYS_MAX_I2C_BUS > 2
		case TWI2_CLKDIV: return 2;
#endif
		default: return -1;
	}
}
Commit	Line	Data
be853bf8 MF	1	/*
	2	* i2c.c - driver for Blackfin on-chip TWI/I2C
	3	*
b5cebb4f	4	* Copyright (c) 2006-2010 Analog Devices Inc.
be853bf8 MF	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
	10	#include <i2c.h>
	11
	12	#include <asm/blackfin.h>
d6a320d5	13	#include <asm/clock.h>
be853bf8 MF	14	#include <asm/mach-common/bits/twi.h>
be853bf8 MF	15
b5cebb4f MF	16	/* Every register is 32bit aligned, but only 16bits in size */
	17	#define ureg(name) u16 name; u16 __pad_##name;
	18	struct twi_regs {
	19	ureg(clkdiv);
	20	ureg(control);
	21	ureg(slave_ctl);
	22	ureg(slave_stat);
	23	ureg(slave_addr);
	24	ureg(master_ctl);
	25	ureg(master_stat);
	26	ureg(master_addr);
	27	ureg(int_stat);
	28	ureg(int_mask);
	29	ureg(fifo_ctl);
	30	ureg(fifo_stat);
	31	char __pad[0x50];
	32	ureg(xmt_data8);
	33	ureg(xmt_data16);
	34	ureg(rcv_data8);
	35	ureg(rcv_data16);
	36	};
	37	#undef ureg
	38
	39	/* U-Boot I2C framework allows only one active device at a time. */
	40	#ifdef TWI_CLKDIV
	41	#define TWI0_CLKDIV TWI_CLKDIV
	42	#endif
	43	static volatile struct twi_regs twi = (void )TWI0_CLKDIV;
	44
be853bf8 MF	45	#ifdef DEBUG
	46	# define dmemset(s, c, n) memset(s, c, n)
	47	#else
	48	# define dmemset(s, c, n)
	49	#endif
	50	#define debugi(fmt, args...) \
	51	debug( \
b5cebb4f MF	52	"MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
b5cebb4f MF	53	twi->master_stat, twi->fifo_stat, twi->int_stat, \
be853bf8 MF	54	__func__, __LINE__, ## args)
be853bf8 MF	55
be853bf8 MF	56	#ifdef CONFIG_TWICLK_KHZ
	57	# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
	58	#endif
08a1c625 MF	59
	60	/*
	61	* The way speed is changed into duty often results in integer truncation
	62	* with 50% duty, so we'll force rounding up to the next duty by adding 1
	63	* to the max. In practice this will get us a speed of something like
	64	* 385 KHz. The other limit is easy to handle as it is only 8 bits.
	65	*/
	66	#define I2C_SPEED_MAX 400000
	67	#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
	68	#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
	69	#define I2C_DUTY_MIN 0xff /* 8 bit limited */
	70	#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
	71	/* Note: duty is inverse of speed, so the comparisons below are correct */
	72	#if SYS_I2C_DUTY < I2C_DUTY_MAX \|\| SYS_I2C_DUTY > I2C_DUTY_MIN
	73	# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
be853bf8 MF	74	#endif
	75
	76	/* All transfers are described by this data structure */
	77	struct i2c_msg {
	78	u8 flags;
	79	#define I2C_M_COMBO 0x4
	80	#define I2C_M_STOP 0x2
	81	#define I2C_M_READ 0x1
	82	int len; /* msg length */
	83	u8 buf; / pointer to msg data */
	84	int alen; /* addr length */
	85	u8 abuf; / addr buffer */
	86	};
	87
3814ea4f MF	88	/* Allow msec timeout per ~byte transfer */
	89	#define I2C_TIMEOUT 10
	90
be853bf8 MF	91	/**
	92	* wait_for_completion - manage the actual i2c transfer
	93	* @msg: the i2c msg
	94	*/
	95	static int wait_for_completion(struct i2c_msg *msg)
	96	{
	97	uint16_t int_stat;
3814ea4f	98	ulong timebase = get_timer(0);
be853bf8	99
3814ea4f	100	do {
b5cebb4f	101	int_stat = twi->int_stat;
be853bf8 MF	102
	103	if (int_stat & XMTSERV) {
	104	debugi("processing XMTSERV");
b5cebb4f	105	twi->int_stat = XMTSERV;
be853bf8 MF	106	SSYNC();
be853bf8 MF	107	if (msg->alen) {
b5cebb4f	108	twi->xmt_data8 = *(msg->abuf++);
be853bf8 MF	109	--msg->alen;
be853bf8 MF	110	} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
b5cebb4f	111	twi->xmt_data8 = *(msg->buf++);
be853bf8 MF	112	--msg->len;
be853bf8 MF	113	} else {
b5cebb4f	114	twi->master_ctl \|= (msg->flags & I2C_M_COMBO) ? RSTART \| MDIR : STOP;
be853bf8 MF	115	SSYNC();
	116	}
	117	}
	118	if (int_stat & RCVSERV) {
	119	debugi("processing RCVSERV");
b5cebb4f	120	twi->int_stat = RCVSERV;
be853bf8 MF	121	SSYNC();
be853bf8 MF	122	if (msg->len) {
b5cebb4f	123	*(msg->buf++) = twi->rcv_data8;
be853bf8 MF	124	--msg->len;
be853bf8 MF	125	} else if (msg->flags & I2C_M_STOP) {
b5cebb4f	126	twi->master_ctl \|= STOP;
be853bf8 MF	127	SSYNC();
	128	}
	129	}
	130	if (int_stat & MERR) {
	131	debugi("processing MERR");
b5cebb4f	132	twi->int_stat = MERR;
be853bf8	133	SSYNC();
3814ea4f	134	return msg->len;
be853bf8 MF	135	}
	136	if (int_stat & MCOMP) {
	137	debugi("processing MCOMP");
b5cebb4f	138	twi->int_stat = MCOMP;
be853bf8 MF	139	SSYNC();
be853bf8 MF	140	if (msg->flags & I2C_M_COMBO && msg->len) {
b5cebb4f MF	141	twi->master_ctl = (twi->master_ctl & ~RSTART) \|
b5cebb4f MF	142	(min(msg->len, 0xff) << 6) \| MEN \| MDIR;
be853bf8 MF	143	SSYNC();
	144	} else
	145	break;
	146	}
3814ea4f MF	147
	148	/* If we were able to do something, reset timeout */
	149	if (int_stat)
	150	timebase = get_timer(0);
	151
	152	} while (get_timer(timebase) < I2C_TIMEOUT);
be853bf8 MF	153
	154	return msg->len;
	155	}
	156
	157	/**
	158	* i2c_transfer - setup an i2c transfer
	159	* @return: 0 if things worked, non-0 if things failed
	160	*
	161	* Here we just get the i2c stuff all prepped and ready, and then tail off
	162	* into wait_for_completion() for all the bits to go.
	163	*/
	164	static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
	165	{
	166	uchar addr_buffer[] = {
	167	(addr >> 0),
	168	(addr >> 8),
	169	(addr >> 16),
	170	};
	171	struct i2c_msg msg = {
	172	.flags = flags \| (len >= 0xff ? I2C_M_STOP : 0),
	173	.buf = buffer,
	174	.len = len,
	175	.abuf = addr_buffer,
	176	.alen = alen,
	177	};
	178	int ret;
	179
	180	dmemset(buffer, 0xff, len);
	181	debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
	182	chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
	183
	184	/* wait for things to settle */
b5cebb4f	185	while (twi->master_stat & BUSBUSY)
be853bf8 MF	186	if (ctrlc())
	187	return 1;
	188
	189	/* Set Transmit device address */
b5cebb4f	190	twi->master_addr = chip;
be853bf8 MF	191
be853bf8 MF	192	/* Clear the FIFO before starting things */
b5cebb4f	193	twi->fifo_ctl = XMTFLUSH \| RCVFLUSH;
be853bf8	194	SSYNC();
b5cebb4f	195	twi->fifo_ctl = 0;
be853bf8 MF	196	SSYNC();
	197
	198	/* prime the pump */
	199	if (msg.alen) {
98ab14e8	200	len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
be853bf8	201	debugi("first byte=0x%02x", *msg.abuf);
b5cebb4f	202	twi->xmt_data8 = *(msg.abuf++);
be853bf8 MF	203	--msg.alen;
	204	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
	205	debugi("first byte=0x%02x", *msg.buf);
b5cebb4f	206	twi->xmt_data8 = *(msg.buf++);
be853bf8 MF	207	--msg.len;
	208	}
	209
	210	/* clear int stat */
b5cebb4f MF	211	twi->master_stat = -1;
	212	twi->int_stat = -1;
	213	twi->int_mask = 0;
be853bf8 MF	214	SSYNC();
	215
	216	/* Master enable */
b5cebb4f MF	217	twi->master_ctl =
b5cebb4f MF	218	(twi->master_ctl & FAST) \|
be853bf8	219	(min(len, 0xff) << 6) \| MEN \|
b5cebb4f	220	((msg.flags & I2C_M_READ) ? MDIR : 0);
be853bf8	221	SSYNC();
b5cebb4f	222	debugi("CTL=0x%04x", twi->master_ctl);
be853bf8 MF	223
	224	/* process the rest */
	225	ret = wait_for_completion(&msg);
	226	debugi("ret=%d", ret);
	227
	228	if (ret) {
b5cebb4f MF	229	twi->master_ctl &= ~MEN;
b5cebb4f MF	230	twi->control &= ~TWI_ENA;
be853bf8	231	SSYNC();
b5cebb4f	232	twi->control \|= TWI_ENA;
be853bf8 MF	233	SSYNC();
	234	}
	235
	236	return ret;
	237	}
	238
08a1c625 MF	239	/**
	240	* i2c_set_bus_speed - set i2c bus speed
	241	* @speed: bus speed (in HZ)
	242	*/
	243	int i2c_set_bus_speed(unsigned int speed)
	244	{
	245	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
	246
	247	/* Set TWI interface clock */
	248	if (clkdiv < I2C_DUTY_MAX \|\| clkdiv > I2C_DUTY_MIN)
	249	return -1;
b5cebb4f	250	twi->clkdiv = (clkdiv << 8) \| (clkdiv & 0xff);
08a1c625 MF	251
08a1c625 MF	252	/* Don't turn it on */
b5cebb4f	253	twi->master_ctl = (speed > 100000 ? FAST : 0);
08a1c625 MF	254
	255	return 0;
	256	}
	257
	258	/**
	259	* i2c_get_bus_speed - get i2c bus speed
	260	* @speed: bus speed (in HZ)
	261	*/
	262	unsigned int i2c_get_bus_speed(void)
	263	{
	264	/* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
b5cebb4f	265	return 5000000 / (twi->clkdiv & 0xff);
08a1c625 MF	266	}
	267
	268	/**
be853bf8 MF	269	* i2c_init - initialize the i2c bus
	270	* @speed: bus speed (in HZ)
	271	* @slaveaddr: address of device in slave mode (0 - not slave)
	272	*
	273	* Slave mode isn't actually implemented. It'll stay that way until
	274	* we get a real request for it.
	275	*/
	276	void i2c_init(int speed, int slaveaddr)
	277	{
d6a320d5	278	uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
be853bf8 MF	279
be853bf8 MF	280	/* Set TWI internal clock as 10MHz */
b5cebb4f	281	twi->control = prescale;
be853bf8 MF	282
be853bf8 MF	283	/* Set TWI interface clock as specified */
08a1c625	284	i2c_set_bus_speed(speed);
be853bf8	285
08a1c625	286	/* Enable it */
b5cebb4f	287	twi->control = TWI_ENA \| prescale;
be853bf8 MF	288	SSYNC();
be853bf8 MF	289
b5cebb4f	290	debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);
be853bf8 MF	291
	292	#if CONFIG_SYS_I2C_SLAVE
	293	# error I2C slave support not tested/supported
	294	/* If they want us as a slave, do it */
	295	if (slaveaddr) {
b5cebb4f MF	296	twi->slave_addr = slaveaddr;
b5cebb4f MF	297	twi->slave_ctl = SEN;
be853bf8 MF	298	}
	299	#endif
	300	}
	301
	302	/**
	303	* i2c_probe - test if a chip exists at a given i2c address
	304	* @chip: i2c chip addr to search for
	305	* @return: 0 if found, non-0 if not found
	306	*/
	307	int i2c_probe(uchar chip)
	308	{
	309	u8 byte;
	310	return i2c_read(chip, 0, 0, &byte, 1);
	311	}
	312
	313	/**
	314	* i2c_read - read data from an i2c device
	315	* @chip: i2c chip addr
	316	* @addr: memory (register) address in the chip
	317	* @alen: byte size of address
	318	* @buffer: buffer to store data read from chip
	319	* @len: how many bytes to read
	320	* @return: 0 on success, non-0 on failure
	321	*/
	322	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
	323	{
	324	return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
	325	}
	326
	327	/**
	328	* i2c_write - write data to an i2c device
	329	* @chip: i2c chip addr
	330	* @addr: memory (register) address in the chip
	331	* @alen: byte size of address
98ab14e8	332	* @buffer: buffer holding data to write to chip
be853bf8 MF	333	* @len: how many bytes to write
	334	* @return: 0 on success, non-0 on failure
	335	*/
	336	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
	337	{
	338	return i2c_transfer(chip, addr, alen, buffer, len, 0);
	339	}
b5cebb4f MF	340
	341	/**
	342	* i2c_set_bus_num - change active I2C bus
	343	* @bus: bus index, zero based
	344	* @returns: 0 on success, non-0 on failure
	345	*/
	346	int i2c_set_bus_num(unsigned int bus)
	347	{
	348	switch (bus) {
	349	#if CONFIG_SYS_MAX_I2C_BUS > 0
	350	case 0: twi = (void *)TWI0_CLKDIV; return 0;
	351	#endif
	352	#if CONFIG_SYS_MAX_I2C_BUS > 1
	353	case 1: twi = (void *)TWI1_CLKDIV; return 0;
	354	#endif
	355	#if CONFIG_SYS_MAX_I2C_BUS > 2
	356	case 2: twi = (void *)TWI2_CLKDIV; return 0;
	357	#endif
	358	default: return -1;
	359	}
	360	}
	361
	362	/**
	363	* i2c_get_bus_num - returns index of active I2C bus
	364	*/
	365	unsigned int i2c_get_bus_num(void)
	366	{
	367	switch ((unsigned long)twi) {
	368	#if CONFIG_SYS_MAX_I2C_BUS > 0
	369	case TWI0_CLKDIV: return 0;
	370	#endif
	371	#if CONFIG_SYS_MAX_I2C_BUS > 1
	372	case TWI1_CLKDIV: return 1;
	373	#endif
	374	#if CONFIG_SYS_MAX_I2C_BUS > 2
	375	case TWI2_CLKDIV: return 2;
	376	#endif
	377	default: return -1;
	378	}
	379	}