[thirdparty/kernel/stable.git] / drivers / i2c / busses / i2c-au1550.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
 *
 * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
 *
 * The documentation describes this as an SMBus controller, but it doesn't
 * understand any of the SMBus protocol in hardware.  It's really an I2C
 * controller that could emulate most of the SMBus in software.
 *
 * This is just a skeleton adapter to use with the Au1550 PSC
 * algorithm.  It was developed for the Pb1550, but will work with
 * any Au1550 board that has a similar PSC configuration.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/slab.h>

#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>

#define PSC_SEL		0x00
#define PSC_CTRL	0x04
#define PSC_SMBCFG	0x08
#define PSC_SMBMSK	0x0C
#define PSC_SMBPCR	0x10
#define PSC_SMBSTAT	0x14
#define PSC_SMBEVNT	0x18
#define PSC_SMBTXRX	0x1C
#define PSC_SMBTMR	0x20

struct i2c_au1550_data {
	void __iomem *psc_base;
	int	xfer_timeout;
	struct i2c_adapter adap;
};

static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
{
	__raw_writel(v, a->psc_base + r);
	wmb();
}

static inline unsigned long RD(struct i2c_au1550_data *a, int r)
{
	return __raw_readl(a->psc_base + r);
}

static int wait_xfer_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Tx Buffer Empty */
	for (i = 0; i < adap->xfer_timeout; i++) {
		if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
			return 0;

		udelay(1);
	}

	return -ETIMEDOUT;
}

static int wait_ack(struct i2c_au1550_data *adap)
{
	unsigned long stat;

	if (wait_xfer_done(adap))
		return -ETIMEDOUT;

	stat = RD(adap, PSC_SMBEVNT);
	if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
		return -ETIMEDOUT;

	return 0;
}

static int wait_master_done(struct i2c_au1550_data *adap)
{
	int i;

	/* Wait for Master Done. */
	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
		if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
			return 0;
		udelay(1);
	}

	return -ETIMEDOUT;
}

static int
do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
{
	unsigned long stat;

	/* Reset the FIFOs, clear events. */
	stat = RD(adap, PSC_SMBSTAT);
	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);

	if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
		WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
		while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
			cpu_relax();
		udelay(50);
	}

	/* Write out the i2c chip address and specify operation */
	addr <<= 1;
	if (rd)
		addr |= 1;

	/* zero-byte xfers stop immediately */
	if (q)
		addr |= PSC_SMBTXRX_STP;

	/* Put byte into fifo, start up master. */
	WR(adap, PSC_SMBTXRX, addr);
	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
	if (wait_ack(adap))
		return -EIO;
	return (q) ? wait_master_done(adap) : 0;
}

static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
{
	int j;

	if (wait_xfer_done(adap))
		return -EIO;

	j =  adap->xfer_timeout * 100;
	do {
		j--;
		if (j <= 0)
			return -EIO;

		if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
			j = 0;
		else
			udelay(1);
	} while (j > 0);

	*out = RD(adap, PSC_SMBTXRX);

	return 0;
}

static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
		    unsigned int len)
{
	int i;

	if (len == 0)
		return 0;

	/* A read is performed by stuffing the transmit fifo with
	 * zero bytes for timing, waiting for bytes to appear in the
	 * receive fifo, then reading the bytes.
	 */
	i = 0;
	while (i < (len - 1)) {
		WR(adap, PSC_SMBTXRX, 0);
		if (wait_for_rx_byte(adap, &buf[i]))
			return -EIO;

		i++;
	}

	/* The last byte has to indicate transfer done. */
	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
	if (wait_master_done(adap))
		return -EIO;

	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
	return 0;
}

static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
		     unsigned int len)
{
	int i;
	unsigned long data;

	if (len == 0)
		return 0;

	i = 0;
	while (i < (len-1)) {
		data = buf[i];
		WR(adap, PSC_SMBTXRX, data);
		if (wait_ack(adap))
			return -EIO;
		i++;
	}

	/* The last byte has to indicate transfer done. */
	data = buf[i];
	data |= PSC_SMBTXRX_STP;
	WR(adap, PSC_SMBTXRX, data);
	if (wait_master_done(adap))
		return -EIO;
	return 0;
}

static int
au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
{
	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	struct i2c_msg *p;
	int i, err = 0;

	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);

	for (i = 0; !err && i < num; i++) {
		p = &msgs[i];
		err = do_address(adap, p->addr, p->flags & I2C_M_RD,
				 (p->len == 0));
		if (err || !p->len)
			continue;
		if (p->flags & I2C_M_RD)
			err = i2c_read(adap, p->buf, p->len);
		else
			err = i2c_write(adap, p->buf, p->len);
	}

	/* Return the number of messages processed, or the error code.
	*/
	if (err == 0)
		err = num;

	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);

	return err;
}

static u32 au1550_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm au1550_algo = {
	.master_xfer	= au1550_xfer,
	.functionality	= au1550_func,
};

static void i2c_au1550_setup(struct i2c_au1550_data *priv)
{
	unsigned long cfg;

	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
	WR(priv, PSC_SMBCFG, cfg);

	/* Divide by 8 to get a 6.25 MHz clock.  The later protocol
	 * timings are based on this clock.
	 */
	cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	WR(priv, PSC_SMBCFG, cfg);
	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);

	/* Set the protocol timer values.  See Table 71 in the
	 * Au1550 Data Book for standard timing values.
	 */
	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \
		PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \
		PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \
		PSC_SMBTMR_SET_CH(20));

	cfg |= PSC_SMBCFG_DE_ENABLE;
	WR(priv, PSC_SMBCFG, cfg);
	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
		cpu_relax();

	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
}

static void i2c_au1550_disable(struct i2c_au1550_data *priv)
{
	WR(priv, PSC_SMBCFG, 0);
	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
}

/*
 * registering functions to load algorithms at runtime
 * Prior to calling us, the 50MHz clock frequency and routing
 * must have been set up for the PSC indicated by the adapter.
 */
static int
i2c_au1550_probe(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv;
	struct resource *r;
	int ret;

	priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
			    GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->psc_base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(priv->psc_base))
		return PTR_ERR(priv->psc_base);

	priv->xfer_timeout = 200;

	priv->adap.nr = pdev->id;
	priv->adap.algo = &au1550_algo;
	priv->adap.algo_data = priv;
	priv->adap.dev.parent = &pdev->dev;
	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));

	/* Now, set up the PSC for SMBus PIO mode. */
	i2c_au1550_setup(priv);

	ret = i2c_add_numbered_adapter(&priv->adap);
	if (ret) {
		i2c_au1550_disable(priv);
		return ret;
	}

	platform_set_drvdata(pdev, priv);
	return 0;
}

static int i2c_au1550_remove(struct platform_device *pdev)
{
	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);

	i2c_del_adapter(&priv->adap);
	i2c_au1550_disable(priv);
	return 0;
}

#ifdef CONFIG_PM
static int i2c_au1550_suspend(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_disable(priv);

	return 0;
}

static int i2c_au1550_resume(struct device *dev)
{
	struct i2c_au1550_data *priv = dev_get_drvdata(dev);

	i2c_au1550_setup(priv);

	return 0;
}

static const struct dev_pm_ops i2c_au1550_pmops = {
	.suspend	= i2c_au1550_suspend,
	.resume		= i2c_au1550_resume,
};

#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)

#else
#define AU1XPSC_SMBUS_PMOPS NULL
#endif

static struct platform_driver au1xpsc_smbus_driver = {
	.driver = {
		.name	= "au1xpsc_smbus",
		.pm	= AU1XPSC_SMBUS_PMOPS,
	},
	.probe		= i2c_au1550_probe,
	.remove		= i2c_au1550_remove,
};

module_platform_driver(au1xpsc_smbus_driver);

MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:au1xpsc_smbus");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
	4	* Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
	5	*
	6	* 2.6 port by Matt Porter <mporter@kernel.crashing.org>
	7	*
	8	* The documentation describes this as an SMBus controller, but it doesn't
	9	* understand any of the SMBus protocol in hardware. It's really an I2C
	10	* controller that could emulate most of the SMBus in software.
	11	*
	12	* This is just a skeleton adapter to use with the Au1550 PSC
	13	* algorithm. It was developed for the Pb1550, but will work with
	14	* any Au1550 board that has a similar PSC configuration.
1da177e4 LT	15	*/
1da177e4 LT	16
1da177e4 LT	17	#include <linux/delay.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
8b798c4d	20	#include <linux/platform_device.h>
1da177e4 LT	21	#include <linux/errno.h>
1da177e4 LT	22	#include <linux/i2c.h>
8b798c4d	23	#include <linux/slab.h>
1da177e4	24
50d5676e	25	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	26	#include <asm/mach-au1x00/au1xxx_psc.h>
1da177e4 LT	27
c5de6467 ML	28	#define PSC_SEL 0x00
	29	#define PSC_CTRL 0x04
	30	#define PSC_SMBCFG 0x08
	31	#define PSC_SMBMSK 0x0C
	32	#define PSC_SMBPCR 0x10
	33	#define PSC_SMBSTAT 0x14
	34	#define PSC_SMBEVNT 0x18
	35	#define PSC_SMBTXRX 0x1C
	36	#define PSC_SMBTMR 0x20
	37
8b798c4d	38	struct i2c_au1550_data {
c5de6467	39	void __iomem *psc_base;
8b798c4d	40	int xfer_timeout;
8b798c4d	41	struct i2c_adapter adap;
8b798c4d	42	};
1da177e4	43
c5de6467	44	static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
1da177e4	45	{
c5de6467 ML	46	__raw_writel(v, a->psc_base + r);
	47	wmb();
	48	}
1da177e4	49
c5de6467 ML	50	static inline unsigned long RD(struct i2c_au1550_data *a, int r)
	51	{
	52	return __raw_readl(a->psc_base + r);
	53	}
1da177e4	54
c5de6467 ML	55	static int wait_xfer_done(struct i2c_au1550_data *adap)
	56	{
	57	int i;
	58
	59	/* Wait for Tx Buffer Empty */
1da177e4	60	for (i = 0; i < adap->xfer_timeout; i++) {
c5de6467	61	if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
1da177e4	62	return 0;
a202707e	63
1da177e4 LT	64	udelay(1);
	65	}
	66
	67	return -ETIMEDOUT;
	68	}
	69
c5de6467	70	static int wait_ack(struct i2c_au1550_data *adap)
1da177e4	71	{
c5de6467	72	unsigned long stat;
1da177e4 LT	73
	74	if (wait_xfer_done(adap))
	75	return -ETIMEDOUT;
	76
c5de6467	77	stat = RD(adap, PSC_SMBEVNT);
1da177e4 LT	78	if ((stat & (PSC_SMBEVNT_DN \| PSC_SMBEVNT_AN \| PSC_SMBEVNT_AL)) != 0)
	79	return -ETIMEDOUT;
	80
	81	return 0;
	82	}
	83
c5de6467	84	static int wait_master_done(struct i2c_au1550_data *adap)
1da177e4	85	{
c5de6467	86	int i;
1da177e4	87
c5de6467	88	/* Wait for Master Done. */
84785f12	89	for (i = 0; i < 2 * adap->xfer_timeout; i++) {
c5de6467	90	if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
1da177e4 LT	91	return 0;
	92	udelay(1);
	93	}
	94
	95	return -ETIMEDOUT;
	96	}
	97
	98	static int
91f27958	99	do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
1da177e4	100	{
c5de6467	101	unsigned long stat;
1da177e4	102
c5de6467 ML	103	/* Reset the FIFOs, clear events. */
	104	stat = RD(adap, PSC_SMBSTAT);
	105	WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
8859942e DP	106
8859942e DP	107	if (!(stat & PSC_SMBSTAT_TE) \|\| !(stat & PSC_SMBSTAT_RE)) {
c5de6467 ML	108	WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
	109	while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
	110	cpu_relax();
8859942e DP	111	udelay(50);
8859942e DP	112	}
1da177e4	113
c5de6467	114	/* Write out the i2c chip address and specify operation */
1da177e4 LT	115	addr <<= 1;
	116	if (rd)
	117	addr \|= 1;
	118
91f27958 ML	119	/* zero-byte xfers stop immediately */
	120	if (q)
	121	addr \|= PSC_SMBTXRX_STP;
	122
c5de6467 ML	123	/* Put byte into fifo, start up master. */
	124	WR(adap, PSC_SMBTXRX, addr);
	125	WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
1da177e4 LT	126	if (wait_ack(adap))
1da177e4 LT	127	return -EIO;
91f27958	128	return (q) ? wait_master_done(adap) : 0;
1da177e4 LT	129	}
1da177e4 LT	130
c5de6467	131	static int wait_for_rx_byte(struct i2c_au1550_data adap, unsigned char out)
1da177e4	132	{
c5de6467	133	int j;
1da177e4 LT	134
	135	if (wait_xfer_done(adap))
	136	return -EIO;
	137
1da177e4 LT	138	j = adap->xfer_timeout * 100;
	139	do {
	140	j--;
	141	if (j <= 0)
	142	return -EIO;
	143
c5de6467	144	if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
1da177e4 LT	145	j = 0;
	146	else
	147	udelay(1);
	148	} while (j > 0);
c5de6467 ML	149
c5de6467 ML	150	*out = RD(adap, PSC_SMBTXRX);
1da177e4 LT	151
	152	return 0;
	153	}
	154
c5de6467	155	static int i2c_read(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	156	unsigned int len)
1da177e4 LT	157	{
c5de6467	158	int i;
1da177e4 LT	159
	160	if (len == 0)
	161	return 0;
	162
	163	/* A read is performed by stuffing the transmit fifo with
	164	* zero bytes for timing, waiting for bytes to appear in the
	165	* receive fifo, then reading the bytes.
	166	*/
1da177e4	167	i = 0;
c5de6467 ML	168	while (i < (len - 1)) {
	169	WR(adap, PSC_SMBTXRX, 0);
	170	if (wait_for_rx_byte(adap, &buf[i]))
1da177e4 LT	171	return -EIO;
1da177e4 LT	172
1da177e4 LT	173	i++;
	174	}
	175
c5de6467 ML	176	/* The last byte has to indicate transfer done. */
c5de6467 ML	177	WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
1da177e4 LT	178	if (wait_master_done(adap))
	179	return -EIO;
	180
c5de6467	181	buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
1da177e4 LT	182	return 0;
	183	}
	184
c5de6467	185	static int i2c_write(struct i2c_au1550_data adap, unsigned char buf,
1da177e4 LT	186	unsigned int len)
1da177e4 LT	187	{
c5de6467 ML	188	int i;
c5de6467 ML	189	unsigned long data;
1da177e4 LT	190
	191	if (len == 0)
	192	return 0;
	193
1da177e4 LT	194	i = 0;
	195	while (i < (len-1)) {
	196	data = buf[i];
c5de6467	197	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	198	if (wait_ack(adap))
	199	return -EIO;
	200	i++;
	201	}
	202
c5de6467	203	/* The last byte has to indicate transfer done. */
1da177e4 LT	204	data = buf[i];
1da177e4 LT	205	data \|= PSC_SMBTXRX_STP;
c5de6467	206	WR(adap, PSC_SMBTXRX, data);
1da177e4 LT	207	if (wait_master_done(adap))
	208	return -EIO;
	209	return 0;
	210	}
	211
	212	static int
	213	au1550_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs, int num)
	214	{
	215	struct i2c_au1550_data *adap = i2c_adap->algo_data;
	216	struct i2c_msg *p;
	217	int i, err = 0;
	218
c5de6467	219	WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
f09f71b2	220
1da177e4 LT	221	for (i = 0; !err && i < num; i++) {
1da177e4 LT	222	p = &msgs[i];
91f27958 ML	223	err = do_address(adap, p->addr, p->flags & I2C_M_RD,
91f27958 ML	224	(p->len == 0));
1da177e4 LT	225	if (err \|\| !p->len)
	226	continue;
	227	if (p->flags & I2C_M_RD)
	228	err = i2c_read(adap, p->buf, p->len);
	229	else
	230	err = i2c_write(adap, p->buf, p->len);
	231	}
	232
	233	/* Return the number of messages processed, or the error code.
	234	*/
	235	if (err == 0)
	236	err = num;
f09f71b2	237
c5de6467	238	WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2	239
1da177e4 LT	240	return err;
	241	}
	242
c5de6467	243	static u32 au1550_func(struct i2c_adapter *adap)
1da177e4	244	{
6ed07134	245	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
1da177e4 LT	246	}
1da177e4 LT	247
8f9082c5	248	static const struct i2c_algorithm au1550_algo = {
1da177e4 LT	249	.master_xfer = au1550_xfer,
	250	.functionality = au1550_func,
	251	};
	252
f09f71b2 ML	253	static void i2c_au1550_setup(struct i2c_au1550_data *priv)
f09f71b2 ML	254	{
c5de6467	255	unsigned long cfg;
f09f71b2	256
c5de6467 ML	257	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
	258	WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
	259	WR(priv, PSC_SMBCFG, 0);
	260	WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
	261	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	262	cpu_relax();
	263
	264	cfg = PSC_SMBCFG_RT_FIFO8 \| PSC_SMBCFG_TT_FIFO8 \| PSC_SMBCFG_DD_DISABLE;
	265	WR(priv, PSC_SMBCFG, cfg);
f09f71b2 ML	266
	267	/* Divide by 8 to get a 6.25 MHz clock. The later protocol
	268	* timings are based on this clock.
	269	*/
c5de6467 ML	270	cfg \|= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
	271	WR(priv, PSC_SMBCFG, cfg);
	272	WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
f09f71b2 ML	273
	274	/* Set the protocol timer values. See Table 71 in the
	275	* Au1550 Data Book for standard timing values.
	276	*/
8a5e3d47 ML	277	WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) \| PSC_SMBTMR_SET_PS(20) \| \
	278	PSC_SMBTMR_SET_PU(20) \| PSC_SMBTMR_SET_SH(20) \| \
	279	PSC_SMBTMR_SET_SU(20) \| PSC_SMBTMR_SET_CL(20) \| \
	280	PSC_SMBTMR_SET_CH(20));
f09f71b2	281
c5de6467 ML	282	cfg \|= PSC_SMBCFG_DE_ENABLE;
	283	WR(priv, PSC_SMBCFG, cfg);
	284	while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
	285	cpu_relax();
f09f71b2	286
c5de6467	287	WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
f09f71b2 ML	288	}
	289
	290	static void i2c_au1550_disable(struct i2c_au1550_data *priv)
	291	{
c5de6467 ML	292	WR(priv, PSC_SMBCFG, 0);
c5de6467 ML	293	WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
f09f71b2 ML	294	}
f09f71b2 ML	295
1da177e4 LT	296	/*
	297	* registering functions to load algorithms at runtime
	298	* Prior to calling us, the 50MHz clock frequency and routing
	299	* must have been set up for the PSC indicated by the adapter.
	300	*/
0b255e92	301	static int
8b798c4d	302	i2c_au1550_probe(struct platform_device *pdev)
1da177e4	303	{
8b798c4d	304	struct i2c_au1550_data *priv;
8b798c4d	305	struct resource *r;
8b798c4d ML	306	int ret;
8b798c4d ML	307
174f2366 AL	308	priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
	309	GFP_KERNEL);
	310	if (!priv)
	311	return -ENOMEM;
1da177e4	312
174f2366 AL	313	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	314	priv->psc_base = devm_ioremap_resource(&pdev->dev, r);
	315	if (IS_ERR(priv->psc_base))
	316	return PTR_ERR(priv->psc_base);
8b798c4d	317
8b798c4d	318	priv->xfer_timeout = 200;
8b798c4d	319
8b798c4d ML	320	priv->adap.nr = pdev->id;
	321	priv->adap.algo = &au1550_algo;
	322	priv->adap.algo_data = priv;
	323	priv->adap.dev.parent = &pdev->dev;
	324	strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
1da177e4	325
c5de6467	326	/* Now, set up the PSC for SMBus PIO mode. */
f09f71b2	327	i2c_au1550_setup(priv);
1da177e4	328
8b798c4d	329	ret = i2c_add_numbered_adapter(&priv->adap);
174f2366 AL	330	if (ret) {
	331	i2c_au1550_disable(priv);
	332	return ret;
8b798c4d ML	333	}
8b798c4d ML	334
174f2366 AL	335	platform_set_drvdata(pdev, priv);
174f2366 AL	336	return 0;
8b798c4d	337	}
1da177e4	338
0b255e92	339	static int i2c_au1550_remove(struct platform_device *pdev)
1da177e4	340	{
8b798c4d	341	struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
8b798c4d	342
8b798c4d	343	i2c_del_adapter(&priv->adap);
f09f71b2	344	i2c_au1550_disable(priv);
8b798c4d	345	return 0;
1da177e4 LT	346	}
1da177e4 LT	347
f09f71b2	348	#ifdef CONFIG_PM
46f344e2	349	static int i2c_au1550_suspend(struct device *dev)
1da177e4	350	{
46f344e2	351	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	352
f09f71b2 ML	353	i2c_au1550_disable(priv);
f09f71b2 ML	354
1da177e4 LT	355	return 0;
	356	}
	357
46f344e2	358	static int i2c_au1550_resume(struct device *dev)
1da177e4	359	{
46f344e2	360	struct i2c_au1550_data *priv = dev_get_drvdata(dev);
8b798c4d	361
f09f71b2 ML	362	i2c_au1550_setup(priv);
f09f71b2 ML	363
1da177e4 LT	364	return 0;
1da177e4 LT	365	}
46f344e2 ML	366
	367	static const struct dev_pm_ops i2c_au1550_pmops = {
	368	.suspend = i2c_au1550_suspend,
	369	.resume = i2c_au1550_resume,
	370	};
	371
	372	#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
	373
f09f71b2	374	#else
46f344e2	375	#define AU1XPSC_SMBUS_PMOPS NULL
f09f71b2	376	#endif
1da177e4	377
8b798c4d ML	378	static struct platform_driver au1xpsc_smbus_driver = {
	379	.driver = {
	380	.name = "au1xpsc_smbus",
46f344e2	381	.pm = AU1XPSC_SMBUS_PMOPS,
8b798c4d ML	382	},
8b798c4d ML	383	.probe = i2c_au1550_probe,
0b255e92	384	.remove = i2c_au1550_remove,
1da177e4 LT	385	};
1da177e4 LT	386
a3664b51	387	module_platform_driver(au1xpsc_smbus_driver);
1da177e4 LT	388
	389	MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
	390	MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
	391	MODULE_LICENSE("GPL");
add8eda7	392	MODULE_ALIAS("platform:au1xpsc_smbus");