[thirdparty/linux.git] / drivers / i2c / busses / i2c-iop3xx.c

/* ------------------------------------------------------------------------- */
/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x       */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
 *                    <Peter dot Milne at D hyphen TACQ dot com>
 *
 * With acknowledgements to i2c-algo-ibm_ocp.c by
 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
 *
 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
 *
 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
 *
 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
 *
 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
 *
 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
 * - Make it work with IXP46x chips
 * - Cleanup function names, coding style, etc
 *
 * - writing to slave address causes latchup on iop331.
 *	fix: driver refuses to address self.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.
 */

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include "i2c-iop3xx.h"

/* global unit counter */
static int i2c_id;

static inline unsigned char
iic_cook_addr(struct i2c_msg *msg)
{
	unsigned char addr;

	addr = i2c_8bit_addr_from_msg(msg);

	return addr;
}

static void
iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	/* Follows devman 9.3 */
	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void
iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;

	/*
	 * Every time unit enable is asserted, GPOD needs to be cleared
	 * on IOP3XX to avoid data corruption on the bus.
	 */
#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
	if (iop3xx_adap->id == 0) {
		gpio_set_value(7, 0);
		gpio_set_value(6, 0);
	} else {
		gpio_set_value(5, 0);
		gpio_set_value(4, 0);
	}
#endif
	/* NB SR bits not same position as CR IE bits :-( */
	iop3xx_adap->SR_enabled =
		IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;

	cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

static void
iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);

	cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
		IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}

/*
 * NB: the handler has to clear the source of the interrupt!
 * Then it passes the SR flags of interest to BH via adap data
 */
static irqreturn_t
iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);

	if ((sr &= iop3xx_adap->SR_enabled)) {
		__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
		iop3xx_adap->SR_received |= sr;
		wake_up_interruptible(&iop3xx_adap->waitq);
	}
	return IRQ_HANDLED;
}

/* check all error conditions, clear them , report most important */
static int
iop3xx_i2c_error(u32 sr)
{
	int rc = 0;

	if ((sr & IOP3XX_ISR_BERRD)) {
		if ( !rc ) rc = -I2C_ERR_BERR;
	}
	if ((sr & IOP3XX_ISR_ALD)) {
		if ( !rc ) rc = -I2C_ERR_ALD;
	}
	return rc;
}

static inline u32
iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
	unsigned long flags;
	u32 sr;

	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	sr = iop3xx_adap->SR_received;
	iop3xx_adap->SR_received = 0;
	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);

	return sr;
}

/*
 * sleep until interrupted, then recover and analyse the SR
 * saved by handler
 */
typedef int (* compare_func)(unsigned test, unsigned mask);
/* returns 1 on correct comparison */

static int
iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
			  unsigned flags, unsigned* status,
			  compare_func compare)
{
	unsigned sr = 0;
	int interrupted;
	int done;
	int rc = 0;

	do {
		interrupted = wait_event_interruptible_timeout (
			iop3xx_adap->waitq,
			(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
			1 * HZ
			);
		if ((rc = iop3xx_i2c_error(sr)) < 0) {
			*status = sr;
			return rc;
		} else if (!interrupted) {
			*status = sr;
			return -ETIMEDOUT;
		}
	} while(!done);

	*status = sr;

	return 0;
}

/*
 * Concrete compare_funcs
 */
static int
all_bits_clear(unsigned test, unsigned mask)
{
	return (test & mask) == 0;
}

static int
any_bits_set(unsigned test, unsigned mask)
{
	return (test & mask) != 0;
}

static int
iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap,
	        IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status, any_bits_set);
}

static int
iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap,
		IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
		status,	any_bits_set);
}

static int
iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
	return iop3xx_i2c_wait_event(
		iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
}

static int
iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
				struct i2c_msg* msg)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc;

	/* avoid writing to my slave address (hangs on 80331),
	 * forbidden in Intel developer manual
	 */
	if (msg->addr == MYSAR) {
		return -EBUSY;
	}

	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);

	cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;

	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int
iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	cr &= ~IOP3XX_ICR_MSTART;
	if (stop) {
		cr |= IOP3XX_ICR_MSTOP;
	} else {
		cr &= ~IOP3XX_ICR_MSTOP;
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);

	return rc;
}

static int
iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
				int stop)
{
	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	int status;
	int rc = 0;

	cr &= ~IOP3XX_ICR_MSTART;

	if (stop) {
		cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
	} else {
		cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
	}
	cr |= IOP3XX_ICR_TBYTE;
	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);

	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);

	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);

	return rc;
}

static int
iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	return rc;
}

static int
iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int ii;
	int rc = 0;

	for (ii = 0; rc == 0 && ii != count; ++ii)
		rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);

	return rc;
}

/*
 * Description:  This function implements combined transactions.  Combined
 * transactions consist of combinations of reading and writing blocks of data.
 * FROM THE SAME ADDRESS
 * Each transfer (i.e. a read or a write) is separated by a repeated start
 * condition.
 */
static int
iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int rc;

	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	if (rc < 0) {
		return rc;
	}

	if ((pmsg->flags&I2C_M_RD)) {
		return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	} else {
		return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	}
}

/*
 * master_xfer() - main read/write entry
 */
static int
iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
				int num)
{
	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	int im = 0;
	int ret = 0;
	int status;

	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	iop3xx_i2c_reset(iop3xx_adap);
	iop3xx_i2c_enable(iop3xx_adap);

	for (im = 0; ret == 0 && im != num; im++) {
		ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	}

	iop3xx_i2c_transaction_cleanup(iop3xx_adap);

	if(ret)
		return ret;

	return im;
}

static u32
iop3xx_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm iop3xx_i2c_algo = {
	.master_xfer	= iop3xx_i2c_master_xfer,
	.functionality	= iop3xx_i2c_func,
};

static int
iop3xx_i2c_remove(struct platform_device *pdev)
{
	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
	struct i2c_algo_iop3xx_data *adapter_data =
		(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);

	/*
	 * Disable the actual HW unit
	 */
	cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
		IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);

	iounmap(adapter_data->ioaddr);
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	kfree(adapter_data);
	kfree(padapter);

	return 0;
}

static int
iop3xx_i2c_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret, irq;
	struct i2c_adapter *new_adapter;
	struct i2c_algo_iop3xx_data *adapter_data;

	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
	if (!new_adapter) {
		ret = -ENOMEM;
		goto out;
	}

	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
	if (!adapter_data) {
		ret = -ENOMEM;
		goto free_adapter;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto free_both;
	}

	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
		ret = -EBUSY;
		goto free_both;
	}

	/* set the adapter enumeration # */
	adapter_data->id = i2c_id++;

	adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
	if (!adapter_data->ioaddr) {
		ret = -ENOMEM;
		goto release_region;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = -ENXIO;
		goto unmap;
	}
	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
				pdev->name, adapter_data);

	if (ret) {
		ret = -EIO;
		goto unmap;
	}

	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
	new_adapter->owner = THIS_MODULE;
	new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
	new_adapter->dev.parent = &pdev->dev;
	new_adapter->dev.of_node = pdev->dev.of_node;
	new_adapter->nr = pdev->id;

	/*
	 * Default values...should these come in from board code?
	 */
	new_adapter->timeout = HZ;
	new_adapter->algo = &iop3xx_i2c_algo;

	init_waitqueue_head(&adapter_data->waitq);
	spin_lock_init(&adapter_data->lock);

	iop3xx_i2c_reset(adapter_data);
	iop3xx_i2c_enable(adapter_data);

	platform_set_drvdata(pdev, new_adapter);
	new_adapter->algo_data = adapter_data;

	i2c_add_numbered_adapter(new_adapter);

	return 0;

unmap:
	iounmap(adapter_data->ioaddr);

release_region:
	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);

free_both:
	kfree(adapter_data);

free_adapter:
	kfree(new_adapter);

out:
	return ret;
}

static const struct of_device_id i2c_iop3xx_match[] = {
	{ .compatible = "intel,iop3xx-i2c", },
	{ .compatible = "intel,ixp4xx-i2c", },
	{},
};
MODULE_DEVICE_TABLE(of, i2c_iop3xx_match);

static struct platform_driver iop3xx_i2c_driver = {
	.probe		= iop3xx_i2c_probe,
	.remove		= iop3xx_i2c_remove,
	.driver		= {
		.name	= "IOP3xx-I2C",
		.of_match_table = i2c_iop3xx_match,
	},
};

module_platform_driver(iop3xx_i2c_driver);

MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:IOP3xx-I2C");
Commit	Line	Data
1da177e4 LT	1	/* ------------------------------------------------------------------------- */
	2	/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
	3	/* ------------------------------------------------------------------------- */
	4	/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
	5	* <Peter dot Milne at D hyphen TACQ dot com>
	6	*
67ac88ff	7	* With acknowledgements to i2c-algo-ibm_ocp.c by
1da177e4 LT	8	* Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
	9	*
	10	* And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
	11	*
	12	* Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
67ac88ff	13	*
fbd9a6d7	14	* And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
1da177e4 LT	15	* Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
	16	*
	17	* Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
	18	*
	19	* - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
	20	* - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
	21	* - Make it work with IXP46x chips
	22	* - Cleanup function names, coding style, etc
	23	*
39288e1a PM	24	* - writing to slave address causes latchup on iop331.
	25	* fix: driver refuses to address self.
	26	*
1da177e4 LT	27	* This program is free software; you can redistribute it and/or modify
	28	* it under the terms of the GNU General Public License as published by
	29	* the Free Software Foundation, version 2.
	30	*/
	31
1da177e4 LT	32	#include <linux/interrupt.h>
	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/delay.h>
	36	#include <linux/slab.h>
1da177e4	37	#include <linux/errno.h>
d052d1be	38	#include <linux/platform_device.h>
1da177e4	39	#include <linux/i2c.h>
21782180	40	#include <linux/io.h>
701eb264	41	#include <linux/gpio.h>
1da177e4 LT	42
	43	#include "i2c-iop3xx.h"
	44
	45	/* global unit counter */
60507095	46	static int i2c_id;
1da177e4	47
67ac88ff RH	48	static inline unsigned char
67ac88ff RH	49	iic_cook_addr(struct i2c_msg *msg)
1da177e4 LT	50	{
	51	unsigned char addr;
	52
515e240b	53	addr = i2c_8bit_addr_from_msg(msg);
1da177e4	54
67ac88ff	55	return addr;
1da177e4 LT	56	}
1da177e4 LT	57
67ac88ff	58	static void
1da177e4 LT	59	iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
	60	{
	61	/* Follows devman 9.3 */
	62	__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
	63	__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
	64	__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
67ac88ff	65	}
1da177e4	66
67ac88ff	67	static void
1da177e4 LT	68	iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
	69	{
	70	u32 cr = IOP3XX_ICR_GCD \| IOP3XX_ICR_SCLEN \| IOP3XX_ICR_UE;
	71
67ac88ff	72	/*
44bbe87e	73	* Every time unit enable is asserted, GPOD needs to be cleared
72edd84a	74	* on IOP3XX to avoid data corruption on the bus.
1da177e4	75	*/
588ef769	76	#if defined(CONFIG_ARCH_IOP32X) \|\| defined(CONFIG_ARCH_IOP33X)
72edd84a	77	if (iop3xx_adap->id == 0) {
701eb264 RH	78	gpio_set_value(7, 0);
701eb264 RH	79	gpio_set_value(6, 0);
72edd84a	80	} else {
701eb264 RH	81	gpio_set_value(5, 0);
701eb264 RH	82	gpio_set_value(4, 0);
72edd84a	83	}
1da177e4 LT	84	#endif
1da177e4 LT	85	/* NB SR bits not same position as CR IE bits :-( */
67ac88ff	86	iop3xx_adap->SR_enabled =
1da177e4 LT	87	IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD \|
	88	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_TXEMPTY;
	89
	90	cr \|= IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	91	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE;
	92
	93	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	94	}
	95
67ac88ff	96	static void
1da177e4 LT	97	iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
	98	{
	99	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
67ac88ff RH	100
67ac88ff RH	101	cr &= ~(IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE \|
1da177e4 LT	102	IOP3XX_ICR_MSTOP \| IOP3XX_ICR_SCLEN);
	103
	104	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	105	}
	106
67ac88ff RH	107	/*
67ac88ff RH	108	* NB: the handler has to clear the source of the interrupt!
1da177e4 LT	109	* Then it passes the SR flags of interest to BH via adap data
1da177e4 LT	110	*/
67ac88ff RH	111	static irqreturn_t
67ac88ff RH	112	iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
1da177e4 LT	113	{
	114	struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
	115	u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
	116
	117	if ((sr &= iop3xx_adap->SR_enabled)) {
	118	__raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
	119	iop3xx_adap->SR_received \|= sr;
	120	wake_up_interruptible(&iop3xx_adap->waitq);
	121	}
	122	return IRQ_HANDLED;
	123	}
	124
	125	/* check all error conditions, clear them , report most important */
67ac88ff	126	static int
1da177e4 LT	127	iop3xx_i2c_error(u32 sr)
	128	{
	129	int rc = 0;
	130
	131	if ((sr & IOP3XX_ISR_BERRD)) {
	132	if ( !rc ) rc = -I2C_ERR_BERR;
	133	}
	134	if ((sr & IOP3XX_ISR_ALD)) {
67ac88ff	135	if ( !rc ) rc = -I2C_ERR_ALD;
1da177e4	136	}
67ac88ff	137	return rc;
1da177e4 LT	138	}
1da177e4 LT	139
67ac88ff	140	static inline u32
1da177e4 LT	141	iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
	142	{
	143	unsigned long flags;
	144	u32 sr;
	145
	146	spin_lock_irqsave(&iop3xx_adap->lock, flags);
	147	sr = iop3xx_adap->SR_received;
	148	iop3xx_adap->SR_received = 0;
	149	spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
	150
	151	return sr;
	152	}
	153
	154	/*
	155	* sleep until interrupted, then recover and analyse the SR
	156	* saved by handler
	157	*/
	158	typedef int (* compare_func)(unsigned test, unsigned mask);
	159	/* returns 1 on correct comparison */
	160
67ac88ff RH	161	static int
67ac88ff RH	162	iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
1da177e4 LT	163	unsigned flags, unsigned* status,
	164	compare_func compare)
	165	{
	166	unsigned sr = 0;
	167	int interrupted;
	168	int done;
	169	int rc = 0;
	170
	171	do {
	172	interrupted = wait_event_interruptible_timeout (
	173	iop3xx_adap->waitq,
fbd9a6d7	174	(done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
88a8e4aa	175	1 * HZ
1da177e4 LT	176	);
	177	if ((rc = iop3xx_i2c_error(sr)) < 0) {
	178	*status = sr;
	179	return rc;
	180	} else if (!interrupted) {
	181	*status = sr;
	182	return -ETIMEDOUT;
	183	}
	184	} while(!done);
	185
	186	*status = sr;
	187
	188	return 0;
	189	}
	190
	191	/*
67ac88ff	192	* Concrete compare_funcs
1da177e4	193	*/
67ac88ff	194	static int
1da177e4 LT	195	all_bits_clear(unsigned test, unsigned mask)
	196	{
	197	return (test & mask) == 0;
	198	}
	199
67ac88ff	200	static int
1da177e4 LT	201	any_bits_set(unsigned test, unsigned mask)
	202	{
	203	return (test & mask) != 0;
	204	}
	205
67ac88ff	206	static int
1da177e4 LT	207	iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	208	{
67ac88ff RH	209	return iop3xx_i2c_wait_event(
67ac88ff RH	210	iop3xx_adap,
1da177e4 LT	211	IOP3XX_ISR_TXEMPTY \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	212	status, any_bits_set);
	213	}
	214
67ac88ff	215	static int
1da177e4 LT	216	iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	217	{
67ac88ff RH	218	return iop3xx_i2c_wait_event(
67ac88ff RH	219	iop3xx_adap,
1da177e4 LT	220	IOP3XX_ISR_RXFULL \| IOP3XX_ISR_ALD \| IOP3XX_ISR_BERRD,
	221	status, any_bits_set);
	222	}
	223
67ac88ff	224	static int
1da177e4 LT	225	iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data iop3xx_adap, int status)
1da177e4 LT	226	{
67ac88ff	227	return iop3xx_i2c_wait_event(
1da177e4 LT	228	iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
	229	}
	230
67ac88ff RH	231	static int
67ac88ff RH	232	iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
1da177e4 LT	233	struct i2c_msg* msg)
	234	{
	235	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	236	int status;
	237	int rc;
	238
39288e1a PM	239	/* avoid writing to my slave address (hangs on 80331),
	240	* forbidden in Intel developer manual
	241	*/
	242	if (msg->addr == MYSAR) {
	243	return -EBUSY;
	244	}
	245
1da177e4	246	__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
67ac88ff	247
1da177e4 LT	248	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	249	cr \|= IOP3XX_ICR_MSTART \| IOP3XX_ICR_TBYTE;
	250
	251	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	252	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	253
	254	return rc;
	255	}
	256
67ac88ff RH	257	static int
67ac88ff RH	258	iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
1da177e4 LT	259	int stop)
	260	{
	261	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	262	int status;
	263	int rc = 0;
	264
	265	__raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
	266	cr &= ~IOP3XX_ICR_MSTART;
	267	if (stop) {
	268	cr \|= IOP3XX_ICR_MSTOP;
	269	} else {
	270	cr &= ~IOP3XX_ICR_MSTOP;
	271	}
	272	cr \|= IOP3XX_ICR_TBYTE;
	273	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	274	rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
	275
	276	return rc;
67ac88ff	277	}
1da177e4	278
67ac88ff RH	279	static int
67ac88ff RH	280	iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data iop3xx_adap, char byte,
1da177e4 LT	281	int stop)
	282	{
	283	unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
	284	int status;
	285	int rc = 0;
	286
	287	cr &= ~IOP3XX_ICR_MSTART;
	288
	289	if (stop) {
	290	cr \|= IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK;
	291	} else {
	292	cr &= ~(IOP3XX_ICR_MSTOP \| IOP3XX_ICR_NACK);
	293	}
	294	cr \|= IOP3XX_ICR_TBYTE;
	295	__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
	296
	297	rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
	298
	299	*byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
	300
	301	return rc;
	302	}
	303
67ac88ff	304	static int
1da177e4 LT	305	iop3xx_i2c_writebytes(struct i2c_adapter i2c_adap, const char buf, int count)
	306	{
	307	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	308	int ii;
	309	int rc = 0;
	310
67ac88ff	311	for (ii = 0; rc == 0 && ii != count; ++ii)
1da177e4 LT	312	rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
	313	return rc;
	314	}
	315
67ac88ff	316	static int
1da177e4 LT	317	iop3xx_i2c_readbytes(struct i2c_adapter i2c_adap, char buf, int count)
	318	{
	319	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	320	int ii;
	321	int rc = 0;
	322
	323	for (ii = 0; rc == 0 && ii != count; ++ii)
	324	rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
67ac88ff	325
1da177e4 LT	326	return rc;
	327	}
	328
	329	/*
	330	* Description: This function implements combined transactions. Combined
	331	* transactions consist of combinations of reading and writing blocks of data.
	332	* FROM THE SAME ADDRESS
	333	* Each transfer (i.e. a read or a write) is separated by a repeated start
	334	* condition.
	335	*/
67ac88ff RH	336	static int
67ac88ff RH	337	iop3xx_i2c_handle_msg(struct i2c_adapter i2c_adap, struct i2c_msg pmsg)
1da177e4 LT	338	{
	339	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	340	int rc;
	341
	342	rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
	343	if (rc < 0) {
	344	return rc;
	345	}
	346
	347	if ((pmsg->flags&I2C_M_RD)) {
	348	return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
	349	} else {
	350	return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
	351	}
	352	}
	353
	354	/*
	355	* master_xfer() - main read/write entry
	356	*/
67ac88ff RH	357	static int
67ac88ff RH	358	iop3xx_i2c_master_xfer(struct i2c_adapter i2c_adap, struct i2c_msg msgs,
1da177e4 LT	359	int num)
	360	{
	361	struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
	362	int im = 0;
	363	int ret = 0;
	364	int status;
	365
	366	iop3xx_i2c_wait_idle(iop3xx_adap, &status);
	367	iop3xx_i2c_reset(iop3xx_adap);
	368	iop3xx_i2c_enable(iop3xx_adap);
	369
	370	for (im = 0; ret == 0 && im != num; im++) {
	371	ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
	372	}
	373
	374	iop3xx_i2c_transaction_cleanup(iop3xx_adap);
67ac88ff	375
1da177e4 LT	376	if(ret)
	377	return ret;
	378
67ac88ff	379	return im;
1da177e4 LT	380	}
1da177e4 LT	381
67ac88ff	382	static u32
1da177e4 LT	383	iop3xx_i2c_func(struct i2c_adapter *adap)
	384	{
	385	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	386	}
	387
8f9082c5	388	static const struct i2c_algorithm iop3xx_i2c_algo = {
1da177e4	389	.master_xfer = iop3xx_i2c_master_xfer,
1da177e4 LT	390	.functionality = iop3xx_i2c_func,
	391	};
	392
67ac88ff	393	static int
3ae5eaec	394	iop3xx_i2c_remove(struct platform_device *pdev)
1da177e4	395	{
3ae5eaec	396	struct i2c_adapter *padapter = platform_get_drvdata(pdev);
67ac88ff	397	struct i2c_algo_iop3xx_data *adapter_data =
1da177e4 LT	398	(struct i2c_algo_iop3xx_data *)padapter->algo_data;
	399	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	400	unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
	401
	402	/*
	403	* Disable the actual HW unit
	404	*/
	405	cr &= ~(IOP3XX_ICR_ALD_IE \| IOP3XX_ICR_BERR_IE \|
	406	IOP3XX_ICR_RXFULL_IE \| IOP3XX_ICR_TXEMPTY_IE);
	407	__raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
	408
747fcc91	409	iounmap(adapter_data->ioaddr);
1da177e4 LT	410	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	411	kfree(adapter_data);
	412	kfree(padapter);
	413
1da177e4 LT	414	return 0;
	415	}
	416
67ac88ff	417	static int
3ae5eaec	418	iop3xx_i2c_probe(struct platform_device *pdev)
1da177e4	419	{
1da177e4	420	struct resource *res;
48944738	421	int ret, irq;
1da177e4 LT	422	struct i2c_adapter *new_adapter;
	423	struct i2c_algo_iop3xx_data *adapter_data;
	424
5263ebb5	425	new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
1da177e4 LT	426	if (!new_adapter) {
	427	ret = -ENOMEM;
	428	goto out;
	429	}
1da177e4	430
5263ebb5	431	adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
1da177e4 LT	432	if (!adapter_data) {
	433	ret = -ENOMEM;
	434	goto free_adapter;
	435	}
1da177e4 LT	436
	437	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	438	if (!res) {
	439	ret = -ENODEV;
	440	goto free_both;
	441	}
	442
	443	if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
	444	ret = -EBUSY;
	445	goto free_both;
	446	}
	447
	448	/* set the adapter enumeration # */
	449	adapter_data->id = i2c_id++;
	450
747fcc91	451	adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
1da177e4 LT	452	if (!adapter_data->ioaddr) {
	453	ret = -ENOMEM;
	454	goto release_region;
	455	}
	456
48944738 DV	457	irq = platform_get_irq(pdev, 0);
	458	if (irq < 0) {
	459	ret = -ENXIO;
	460	goto unmap;
	461	}
	462	ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
1da177e4	463	pdev->name, adapter_data);
fbd9a6d7 DW	464
fbd9a6d7 DW	465	if (ret) {
1da177e4 LT	466	ret = -EIO;
	467	goto unmap;
	468	}
	469
	470	memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
1da177e4	471	new_adapter->owner = THIS_MODULE;
3401b2ff	472	new_adapter->class = I2C_CLASS_HWMON \| I2C_CLASS_SPD;
1da177e4	473	new_adapter->dev.parent = &pdev->dev;
cac28ac2	474	new_adapter->dev.of_node = pdev->dev.of_node;
757ba4c6	475	new_adapter->nr = pdev->id;
1da177e4 LT	476
	477	/*
	478	* Default values...should these come in from board code?
	479	*/
8a52c6b4	480	new_adapter->timeout = HZ;
1da177e4 LT	481	new_adapter->algo = &iop3xx_i2c_algo;
	482
	483	init_waitqueue_head(&adapter_data->waitq);
	484	spin_lock_init(&adapter_data->lock);
	485
	486	iop3xx_i2c_reset(adapter_data);
1da177e4 LT	487	iop3xx_i2c_enable(adapter_data);
1da177e4 LT	488
3ae5eaec	489	platform_set_drvdata(pdev, new_adapter);
1da177e4 LT	490	new_adapter->algo_data = adapter_data;
1da177e4 LT	491
757ba4c6	492	i2c_add_numbered_adapter(new_adapter);
1da177e4 LT	493
	494	return 0;
	495
	496	unmap:
747fcc91	497	iounmap(adapter_data->ioaddr);
1da177e4 LT	498
	499	release_region:
	500	release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
	501
	502	free_both:
	503	kfree(adapter_data);
	504
	505	free_adapter:
	506	kfree(new_adapter);
	507
	508	out:
	509	return ret;
	510	}
	511
cac28ac2 LW	512	static const struct of_device_id i2c_iop3xx_match[] = {
	513	{ .compatible = "intel,iop3xx-i2c", },
	514	{ .compatible = "intel,ixp4xx-i2c", },
	515	{},
	516	};
	517	MODULE_DEVICE_TABLE(of, i2c_iop3xx_match);
1da177e4	518
3ae5eaec	519	static struct platform_driver iop3xx_i2c_driver = {
1da177e4	520	.probe = iop3xx_i2c_probe,
3ae5eaec RK	521	.remove = iop3xx_i2c_remove,
3ae5eaec RK	522	.driver = {
3ae5eaec	523	.name = "IOP3xx-I2C",
cac28ac2	524	.of_match_table = i2c_iop3xx_match,
3ae5eaec	525	},
1da177e4 LT	526	};
1da177e4 LT	527
a3664b51	528	module_platform_driver(iop3xx_i2c_driver);
1da177e4 LT	529
	530	MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
	531	MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
	532	MODULE_LICENSE("GPL");
add8eda7	533	MODULE_ALIAS("platform:IOP3xx-I2C");