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[thirdparty/kernel/stable.git] / drivers / i2c / busses / i2c-jz4780.c
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c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
ba92222e
ZLK		 2/*
3 * Ingenic JZ4780 I2C bus driver
4 *
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
6 * Copyright (C) 2015 Imagination Technologies
ba92222e
ZLK		 7 */
8
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/delay.h>
13#include <linux/errno.h>
14#include <linux/i2c.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
c7f94520 17#include <linux/io.h>
ba92222e
ZLK		 18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/time.h>
24
25#define JZ4780_I2C_CTRL 0x00
26#define JZ4780_I2C_TAR 0x04
27#define JZ4780_I2C_SAR 0x08
28#define JZ4780_I2C_DC 0x10
29#define JZ4780_I2C_SHCNT 0x14
30#define JZ4780_I2C_SLCNT 0x18
31#define JZ4780_I2C_FHCNT 0x1C
32#define JZ4780_I2C_FLCNT 0x20
33#define JZ4780_I2C_INTST 0x2C
34#define JZ4780_I2C_INTM 0x30
35#define JZ4780_I2C_RXTL 0x38
36#define JZ4780_I2C_TXTL 0x3C
37#define JZ4780_I2C_CINTR 0x40
38#define JZ4780_I2C_CRXUF 0x44
39#define JZ4780_I2C_CRXOF 0x48
40#define JZ4780_I2C_CTXOF 0x4C
41#define JZ4780_I2C_CRXREQ 0x50
42#define JZ4780_I2C_CTXABRT 0x54
43#define JZ4780_I2C_CRXDONE 0x58
44#define JZ4780_I2C_CACT 0x5C
45#define JZ4780_I2C_CSTP 0x60
46#define JZ4780_I2C_CSTT 0x64
47#define JZ4780_I2C_CGC 0x68
48#define JZ4780_I2C_ENB 0x6C
49#define JZ4780_I2C_STA 0x70
50#define JZ4780_I2C_TXABRT 0x80
51#define JZ4780_I2C_DMACR 0x88
52#define JZ4780_I2C_DMATDLR 0x8C
53#define JZ4780_I2C_DMARDLR 0x90
54#define JZ4780_I2C_SDASU 0x94
55#define JZ4780_I2C_ACKGC 0x98
56#define JZ4780_I2C_ENSTA 0x9C
57#define JZ4780_I2C_SDAHD 0xD0
58
59#define JZ4780_I2C_CTRL_STPHLD BIT(7)
60#define JZ4780_I2C_CTRL_SLVDIS BIT(6)
61#define JZ4780_I2C_CTRL_REST BIT(5)
62#define JZ4780_I2C_CTRL_MATP BIT(4)
63#define JZ4780_I2C_CTRL_SATP BIT(3)
64#define JZ4780_I2C_CTRL_SPDF BIT(2)
65#define JZ4780_I2C_CTRL_SPDS BIT(1)
66#define JZ4780_I2C_CTRL_MD BIT(0)
67
68#define JZ4780_I2C_STA_SLVACT BIT(6)
69#define JZ4780_I2C_STA_MSTACT BIT(5)
70#define JZ4780_I2C_STA_RFF BIT(4)
71#define JZ4780_I2C_STA_RFNE BIT(3)
72#define JZ4780_I2C_STA_TFE BIT(2)
73#define JZ4780_I2C_STA_TFNF BIT(1)
74#define JZ4780_I2C_STA_ACT BIT(0)
75
76static const char * const jz4780_i2c_abrt_src[] = {
77 "ABRT_7B_ADDR_NOACK",
78 "ABRT_10ADDR1_NOACK",
79 "ABRT_10ADDR2_NOACK",
80 "ABRT_XDATA_NOACK",
81 "ABRT_GCALL_NOACK",
82 "ABRT_GCALL_READ",
83 "ABRT_HS_ACKD",
84 "SBYTE_ACKDET",
85 "ABRT_HS_NORSTRT",
86 "SBYTE_NORSTRT",
87 "ABRT_10B_RD_NORSTRT",
88 "ABRT_MASTER_DIS",
89 "ARB_LOST",
90 "SLVFLUSH_TXFIFO",
91 "SLV_ARBLOST",
92 "SLVRD_INTX",
93};
94
95#define JZ4780_I2C_INTST_IGC BIT(11)
96#define JZ4780_I2C_INTST_ISTT BIT(10)
97#define JZ4780_I2C_INTST_ISTP BIT(9)
98#define JZ4780_I2C_INTST_IACT BIT(8)
99#define JZ4780_I2C_INTST_RXDN BIT(7)
100#define JZ4780_I2C_INTST_TXABT BIT(6)
101#define JZ4780_I2C_INTST_RDREQ BIT(5)
102#define JZ4780_I2C_INTST_TXEMP BIT(4)
103#define JZ4780_I2C_INTST_TXOF BIT(3)
104#define JZ4780_I2C_INTST_RXFL BIT(2)
105#define JZ4780_I2C_INTST_RXOF BIT(1)
106#define JZ4780_I2C_INTST_RXUF BIT(0)
107
108#define JZ4780_I2C_INTM_MIGC BIT(11)
109#define JZ4780_I2C_INTM_MISTT BIT(10)
110#define JZ4780_I2C_INTM_MISTP BIT(9)
111#define JZ4780_I2C_INTM_MIACT BIT(8)
112#define JZ4780_I2C_INTM_MRXDN BIT(7)
113#define JZ4780_I2C_INTM_MTXABT BIT(6)
114#define JZ4780_I2C_INTM_MRDREQ BIT(5)
115#define JZ4780_I2C_INTM_MTXEMP BIT(4)
116#define JZ4780_I2C_INTM_MTXOF BIT(3)
117#define JZ4780_I2C_INTM_MRXFL BIT(2)
118#define JZ4780_I2C_INTM_MRXOF BIT(1)
119#define JZ4780_I2C_INTM_MRXUF BIT(0)
120
121#define JZ4780_I2C_DC_READ BIT(8)
122
123#define JZ4780_I2C_SDAHD_HDENB BIT(8)
124
125#define JZ4780_I2C_ENB_I2C BIT(0)
126
127#define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
128#define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
129#define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
130#define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
131
132#define JZ4780_I2C_FIFO_LEN 16
133#define TX_LEVEL 3
134#define RX_LEVEL (JZ4780_I2C_FIFO_LEN - TX_LEVEL - 1)
135
136#define JZ4780_I2C_TIMEOUT 300
137
138#define BUFSIZE 200
139
140struct jz4780_i2c {
141 void __iomem *iomem;
142 int irq;
143 struct clk *clk;
144 struct i2c_adapter adap;
145
146 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
147 spinlock_t lock;
148
149 /* beginning of lock scope */
150 unsigned char *rbuf;
151 int rd_total_len;
152 int rd_data_xfered;
153 int rd_cmd_xfered;
154
155 unsigned char *wbuf;
156 int wt_len;
157
158 int is_write;
159 int stop_hold;
160 int speed;
161
162 int data_buf[BUFSIZE];
163 int cmd_buf[BUFSIZE];
164 int cmd;
165
166 /* end of lock scope */
167 struct completion trans_waitq;
168};
169
170static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
171 unsigned long offset)
172{
173 return readw(i2c->iomem + offset);
174}
175
176static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
177 unsigned long offset, unsigned short val)
178{
179 writew(val, i2c->iomem + offset);
180}
181
182static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
183{
184 unsigned short regval;
185 unsigned long loops = 5;
186
187 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
188
189 do {
190 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
191 if (!(regval & JZ4780_I2C_ENB_I2C))
192 return 0;
193
194 usleep_range(5000, 15000);
195 } while (--loops);
196
197 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
198 return -ETIMEDOUT;
199}
200
201static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
202{
203 unsigned short regval;
204 unsigned long loops = 5;
205
206 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
207
208 do {
209 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
210 if (regval & JZ4780_I2C_ENB_I2C)
211 return 0;
212
213 usleep_range(5000, 15000);
214 } while (--loops);
215
216 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
217 return -ETIMEDOUT;
218}
219
220static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
221{
222 unsigned short regval;
223 unsigned long loops = 5;
224
225 do {
226 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
227 if ((regval & JZ4780_I2C_STA_TFE) &&
228 !(regval & JZ4780_I2C_STA_MSTACT))
229 break;
230
231 usleep_range(5000, 15000);
232 } while (--loops);
233
234 if (loops) {
235 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
236 return 0;
237 }
238
239 dev_err(&i2c->adap.dev,
240 "set device to address 0x%02x failed, STA=0x%04x\n",
241 address, regval);
242
243 return -ENXIO;
244}
245
246static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
247{
248 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
249 int cnt_high = 0; /* HIGH period count of the SCL clock */
250 int cnt_low = 0; /* LOW period count of the SCL clock */
251 int cnt_period = 0; /* period count of the SCL clock */
252 int setup_time = 0;
253 int hold_time = 0;
254 unsigned short tmp = 0;
255 int i2c_clk = i2c->speed;
256
257 if (jz4780_i2c_disable(i2c))
258 dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
259
260 /*
261 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
262 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
263 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
264 */
265 cnt_period = dev_clk_khz / i2c_clk;
266
267 if (i2c_clk <= 100)
268 cnt_high = (cnt_period * 4000) / (4700 + 4000);
269 else
270 cnt_high = (cnt_period * 600) / (1300 + 600);
271
272 cnt_low = cnt_period - cnt_high;
273
274 /*
275 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
276 * normal read are 2 messages, we cannot disable i2c controller
277 * between these two messages, this means that we must always set
278 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
279 *
280 */
281 if (i2c_clk <= 100) {
282 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
283 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
284 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
285
286 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
287 JZ4780_I2CSHCNT_ADJUST(cnt_high));
288 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
289 JZ4780_I2CSLCNT_ADJUST(cnt_low));
290 } else {
291 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
292 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
293 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
294
295 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
296 JZ4780_I2CFHCNT_ADJUST(cnt_high));
297 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
298 JZ4780_I2CFLCNT_ADJUST(cnt_low));
299 }
300
301 /*
302 * a i2c device must internally provide a hold time at least 300ns
303 * tHD:DAT
304 * Standard Mode: min=300ns, max=3450ns
305 * Fast Mode: min=0ns, max=900ns
306 * tSU:DAT
307 * Standard Mode: min=250ns, max=infinite
308 * Fast Mode: min=100(250ns is recommended), max=infinite
309 *
310 * 1i2c_clk = 10^6 / dev_clk_khz
311 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
312 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
313 *
314 * The actual hold time is (SDAHD + 1) * (i2c_clk period).
315 *
316 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
317 *
318 */
319 if (i2c_clk <= 100) { /* standard mode */
320 setup_time = 300;
321 hold_time = 400;
322 } else {
323 setup_time = 450;
324 hold_time = 450;
325 }
326
327 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
328 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
329
330 if (setup_time > 255)
331 setup_time = 255;
332
333 if (setup_time <= 0)
334 setup_time = 1;
335
336 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
337
338 if (hold_time > 255)
339 hold_time = 255;
340
341 if (hold_time >= 0) {
342 /*i2c hold time enable */
343 hold_time |= JZ4780_I2C_SDAHD_HDENB;
344 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
345 } else {
346 /* disable hold time */
347 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
348 }
349
350 return 0;
351}
352
353static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
354{
355 int ret;
356 unsigned long flags;
357 unsigned short tmp;
358
359 spin_lock_irqsave(&i2c->lock, flags);
360
361 /* can send stop now if need */
362 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
363 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
364 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
365
366 /* disable all interrupts first */
367 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
368
369 /* then clear all interrupts */
370 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
371 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
372
373 /* then disable the controller */
374 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
375 tmp &= ~JZ4780_I2C_ENB_I2C;
376 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
377 udelay(10);
378 tmp |= JZ4780_I2C_ENB_I2C;
379 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
380
381 spin_unlock_irqrestore(&i2c->lock, flags);
382
383 ret = jz4780_i2c_disable(i2c);
384 if (ret)
385 dev_err(&i2c->adap.dev,
386 "unable to disable device during cleanup!\n");
387
388 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
389 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
390 dev_err(&i2c->adap.dev,
391 "device has interrupts after a complete cleanup!\n");
392
393 return ret;
394}
395
396static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
397{
398 jz4780_i2c_set_speed(i2c);
399 return jz4780_i2c_enable(i2c);
400}
401
402static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, int cmd_count)
403{
404 int i;
405
406 for (i = 0; i < cmd_count; i++)
407 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
408}
409
410static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
411{
412 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
413 complete(&i2c->trans_waitq);
414}
415
416static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
417{
418 unsigned short tmp;
419 unsigned short intst;
420 unsigned short intmsk;
421 struct jz4780_i2c *i2c = dev_id;
422 unsigned long flags;
423
424 spin_lock_irqsave(&i2c->lock, flags);
425 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
426 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
427
428 intst &= intmsk;
429
430 if (intst & JZ4780_I2C_INTST_TXABT) {
431 jz4780_i2c_trans_done(i2c);
432 goto done;
433 }
434
435 if (intst & JZ4780_I2C_INTST_RXOF) {
436 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
437 jz4780_i2c_trans_done(i2c);
438 goto done;
439 }
440
441 /*
442 * When reading, always drain RX FIFO before we send more Read
443 * Commands to avoid fifo overrun
444 */
445 if (i2c->is_write == 0) {
446 int rd_left;
447
448 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
449 & JZ4780_I2C_STA_RFNE)) {
450 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
451 & 0xff;
452 i2c->rd_data_xfered++;
453 if (i2c->rd_data_xfered == i2c->rd_total_len) {
454 jz4780_i2c_trans_done(i2c);
455 goto done;
456 }
457 }
458
459 rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
460
461 if (rd_left <= JZ4780_I2C_FIFO_LEN)
462 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
463 }
464
465 if (intst & JZ4780_I2C_INTST_TXEMP) {
466 if (i2c->is_write == 0) {
467 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
468 int max_send = (JZ4780_I2C_FIFO_LEN - 1)
469 - (i2c->rd_cmd_xfered
470 - i2c->rd_data_xfered);
471 int cmd_to_send = min(cmd_left, max_send);
472
473 if (i2c->rd_cmd_xfered != 0)
474 cmd_to_send = min(cmd_to_send,
475 JZ4780_I2C_FIFO_LEN
476 - TX_LEVEL - 1);
477
478 if (cmd_to_send) {
479 jz4780_i2c_send_rcmd(i2c, cmd_to_send);
480 i2c->rd_cmd_xfered += cmd_to_send;
481 }
482
483 cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
484 if (cmd_left == 0) {
485 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
486 intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
487 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
488
489 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
490 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
491 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
492 }
493 } else {
494 unsigned short data;
495 unsigned short i2c_sta;
496
497 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
498
499 while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
500 (i2c->wt_len > 0)) {
501 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
502 data = *i2c->wbuf;
503 data &= ~JZ4780_I2C_DC_READ;
504 jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
505 data);
506 i2c->wbuf++;
507 i2c->wt_len--;
508 }
509
510 if (i2c->wt_len == 0) {
511 if (!i2c->stop_hold) {
512 tmp = jz4780_i2c_readw(i2c,
513 JZ4780_I2C_CTRL);
514 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
515 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL,
516 tmp);
517 }
518
519 jz4780_i2c_trans_done(i2c);
520 goto done;
521 }
522 }
523 }
524
525done:
526 spin_unlock_irqrestore(&i2c->lock, flags);
527 return IRQ_HANDLED;
528}
529
530static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
531{
532 int i;
533
534 dev_err(&i2c->adap.dev, "txabrt: 0x%08x\n", src);
535 dev_err(&i2c->adap.dev, "device addr=%x\n",
536 jz4780_i2c_readw(i2c, JZ4780_I2C_TAR));
537 dev_err(&i2c->adap.dev, "send cmd count:%d %d\n",
538 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
539 dev_err(&i2c->adap.dev, "receive data count:%d %d\n",
540 i2c->cmd, i2c->data_buf[i2c->cmd]);
541
542 for (i = 0; i < 16; i++) {
543 if (src & BIT(i))
544 dev_dbg(&i2c->adap.dev, "I2C TXABRT[%d]=%s\n",
545 i, jz4780_i2c_abrt_src[i]);
546 }
547}
548
549static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
550 unsigned char *buf, int len, int cnt,
551 int idx)
552{
553 int ret = 0;
554 long timeout;
555 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
556 unsigned short tmp;
557 unsigned long flags;
558
559 memset(buf, 0, len);
560
561 spin_lock_irqsave(&i2c->lock, flags);
562
563 i2c->stop_hold = 0;
564 i2c->is_write = 0;
565 i2c->rbuf = buf;
566 i2c->rd_total_len = len;
567 i2c->rd_data_xfered = 0;
568 i2c->rd_cmd_xfered = 0;
569
570 if (len <= JZ4780_I2C_FIFO_LEN)
571 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
572 else
573 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, RX_LEVEL);
574
575 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
576
577 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
578 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
579 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
580
581 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
582 tmp |= JZ4780_I2C_CTRL_STPHLD;
583 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
584
585 spin_unlock_irqrestore(&i2c->lock, flags);
586
587 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
588 msecs_to_jiffies(wait_time));
589
590 if (!timeout) {
591 dev_err(&i2c->adap.dev, "irq read timeout\n");
592 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
593 i2c->cmd, i2c->cmd_buf[i2c->cmd]);
594 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
595 i2c->cmd, i2c->data_buf[i2c->cmd]);
596 ret = -EIO;
597 }
598
599 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
600 if (tmp) {
601 jz4780_i2c_txabrt(i2c, tmp);
602 ret = -EIO;
603 }
604
605 return ret;
606}
607
608static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
609 unsigned char *buf, int len,
610 int cnt, int idx)
611{
612 int ret = 0;
613 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
614 long timeout;
615 unsigned short tmp;
616 unsigned long flags;
617
618 spin_lock_irqsave(&i2c->lock, flags);
619
620 if (idx < (cnt - 1))
621 i2c->stop_hold = 1;
622 else
623 i2c->stop_hold = 0;
624
625 i2c->is_write = 1;
626 i2c->wbuf = buf;
627 i2c->wt_len = len;
628
629 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, TX_LEVEL);
630
631 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
632 | JZ4780_I2C_INTM_MTXABT);
633
634 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
635 tmp |= JZ4780_I2C_CTRL_STPHLD;
636 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
637
638 spin_unlock_irqrestore(&i2c->lock, flags);
639
640 timeout = wait_for_completion_timeout(&i2c->trans_waitq,
641 msecs_to_jiffies(wait_time));
642 if (timeout && !i2c->stop_hold) {
643 unsigned short i2c_sta;
644 int write_in_process;
645
646 timeout = JZ4780_I2C_TIMEOUT * 100;
647 for (; timeout > 0; timeout--) {
648 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
649
650 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
651 !(i2c_sta & JZ4780_I2C_STA_TFE);
652 if (!write_in_process)
653 break;
654 udelay(10);
655 }
656 }
657
658 if (!timeout) {
659 dev_err(&i2c->adap.dev, "write wait timeout\n");
660 ret = -EIO;
661 }
662
663 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
664 if (tmp) {
665 jz4780_i2c_txabrt(i2c, tmp);
666 ret = -EIO;
667 }
668
669 return ret;
670}
671
672static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
673 int count)
674{
675 int i = -EIO;
676 int ret = 0;
677 struct jz4780_i2c *i2c = adap->algo_data;
678
679 ret = jz4780_i2c_prepare(i2c);
680 if (ret) {
681 dev_err(&i2c->adap.dev, "I2C prepare failed\n");
682 goto out;
683 }
684
685 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
686 ret = jz4780_i2c_set_target(i2c, msg->addr);
687 if (ret)
688 goto out;
689 }
690 for (i = 0; i < count; i++, msg++) {
691 if (msg->flags & I2C_M_RD)
692 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
693 count, i);
694 else
695 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
696 count, i);
697
698 if (ret)
699 goto out;
700 }
701
702 ret = i;
703
704out:
705 jz4780_i2c_cleanup(i2c);
706 return ret;
707}
708
709static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
710{
711 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
712}
713
714static const struct i2c_algorithm jz4780_i2c_algorithm = {
715 .master_xfer = jz4780_i2c_xfer,
716 .functionality = jz4780_i2c_functionality,
717};
718
719static const struct of_device_id jz4780_i2c_of_matches[] = {
720 { .compatible = "ingenic,jz4780-i2c", },
721 { /* sentinel */ }
722};
3855ada8 723MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches);
ba92222e
ZLK		 724
725static int jz4780_i2c_probe(struct platform_device *pdev)
726{
727 int ret = 0;
728 unsigned int clk_freq = 0;
729 unsigned short tmp;
730 struct resource *r;
731 struct jz4780_i2c *i2c;
732
733 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
734 if (!i2c)
735 return -ENOMEM;
736
737 i2c->adap.owner = THIS_MODULE;
738 i2c->adap.algo = &jz4780_i2c_algorithm;
739 i2c->adap.algo_data = i2c;
740 i2c->adap.retries = 5;
741 i2c->adap.dev.parent = &pdev->dev;
742 i2c->adap.dev.of_node = pdev->dev.of_node;
743 sprintf(i2c->adap.name, "%s", pdev->name);
744
745 init_completion(&i2c->trans_waitq);
746 spin_lock_init(&i2c->lock);
747
748 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
749 i2c->iomem = devm_ioremap_resource(&pdev->dev, r);
750 if (IS_ERR(i2c->iomem))
751 return PTR_ERR(i2c->iomem);
752
753 platform_set_drvdata(pdev, i2c);
754
755 i2c->clk = devm_clk_get(&pdev->dev, NULL);
756 if (IS_ERR(i2c->clk))
757 return PTR_ERR(i2c->clk);
758
eb8173e3
AL		 759 ret = clk_prepare_enable(i2c->clk);
760 if (ret)
761 return ret;
ba92222e 762
eb8173e3
AL		 763 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
764 &clk_freq);
4ececb7d 765 if (ret) {
caf28080 766 dev_err(&pdev->dev, "clock-frequency not specified in DT\n");
eb8173e3 767 goto err;
ba92222e
ZLK		 768 }
769
770 i2c->speed = clk_freq / 1000;
caf28080
WS		 771 if (i2c->speed == 0) {
772 ret = -EINVAL;
773 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n");
774 goto err;
775 }
ba92222e
ZLK		 776 jz4780_i2c_set_speed(i2c);
777
778 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
779
780 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
781 tmp &= ~JZ4780_I2C_CTRL_STPHLD;
782 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
783
784 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
785
ba92222e
ZLK		 786 i2c->irq = platform_get_irq(pdev, 0);
787 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
788 dev_name(&pdev->dev), i2c);
eb8173e3 789 if (ret)
ba92222e 790 goto err;
ba92222e
ZLK		 791
792 ret = i2c_add_adapter(&i2c->adap);
ea734404 793 if (ret < 0)
ba92222e 794 goto err;
ba92222e
ZLK		 795
796 return 0;
797
798err:
799 clk_disable_unprepare(i2c->clk);
800 return ret;
801}
802
803static int jz4780_i2c_remove(struct platform_device *pdev)
804{
805 struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
806
807 clk_disable_unprepare(i2c->clk);
808 i2c_del_adapter(&i2c->adap);
809 return 0;
810}
811
812static struct platform_driver jz4780_i2c_driver = {
813 .probe = jz4780_i2c_probe,
814 .remove = jz4780_i2c_remove,
815 .driver = {
816 .name = "jz4780-i2c",
817 .of_match_table = of_match_ptr(jz4780_i2c_of_matches),
818 },
819};
820
821module_platform_driver(jz4780_i2c_driver);
822
823MODULE_LICENSE("GPL");
824MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
825MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git