[thirdparty/kernel/stable.git] / drivers / i2c / busses / i2c-uniphier.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#define UNIPHIER_I2C_DTRM	0x00	/* TX register */
#define     UNIPHIER_I2C_DTRM_IRQEN	BIT(11)	/* enable interrupt */
#define     UNIPHIER_I2C_DTRM_STA	BIT(10)	/* start condition */
#define     UNIPHIER_I2C_DTRM_STO	BIT(9)	/* stop condition */
#define     UNIPHIER_I2C_DTRM_NACK	BIT(8)	/* do not return ACK */
#define     UNIPHIER_I2C_DTRM_RD	BIT(0)	/* read transaction */
#define UNIPHIER_I2C_DREC	0x04	/* RX register */
#define     UNIPHIER_I2C_DREC_MST	BIT(14)	/* 1 = master, 0 = slave */
#define     UNIPHIER_I2C_DREC_TX	BIT(13)	/* 1 = transmit, 0 = receive */
#define     UNIPHIER_I2C_DREC_STS	BIT(12)	/* stop condition detected */
#define     UNIPHIER_I2C_DREC_LRB	BIT(11)	/* no ACK */
#define     UNIPHIER_I2C_DREC_LAB	BIT(9)	/* arbitration lost */
#define     UNIPHIER_I2C_DREC_BBN	BIT(8)	/* bus not busy */
#define UNIPHIER_I2C_MYAD	0x08	/* slave address */
#define UNIPHIER_I2C_CLK	0x0c	/* clock frequency control */
#define UNIPHIER_I2C_BRST	0x10	/* bus reset */
#define     UNIPHIER_I2C_BRST_FOEN	BIT(1)	/* normal operation */
#define     UNIPHIER_I2C_BRST_RSCL	BIT(0)	/* release SCL */
#define UNIPHIER_I2C_HOLD	0x14	/* hold time control */
#define UNIPHIER_I2C_BSTS	0x18	/* bus status monitor */
#define     UNIPHIER_I2C_BSTS_SDA	BIT(1)	/* readback of SDA line */
#define     UNIPHIER_I2C_BSTS_SCL	BIT(0)	/* readback of SCL line */
#define UNIPHIER_I2C_NOISE	0x1c	/* noise filter control */
#define UNIPHIER_I2C_SETUP	0x20	/* setup time control */

#define UNIPHIER_I2C_DEFAULT_SPEED	100000
#define UNIPHIER_I2C_MAX_SPEED		400000

struct uniphier_i2c_priv {
	struct completion comp;
	struct i2c_adapter adap;
	void __iomem *membase;
	struct clk *clk;
	unsigned int busy_cnt;
	unsigned int clk_cycle;
};

static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
{
	struct uniphier_i2c_priv *priv = dev_id;

	/*
	 * This hardware uses edge triggered interrupt.  Do not touch the
	 * hardware registers in this handler to make sure to catch the next
	 * interrupt edge.  Just send a complete signal and return.
	 */
	complete(&priv->comp);

	return IRQ_HANDLED;
}

static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
				  u32 *rxdatap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	unsigned long time_left;
	u32 rxdata;

	reinit_completion(&priv->comp);

	txdata |= UNIPHIER_I2C_DTRM_IRQEN;
	dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
	writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);

	time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
	if (unlikely(!time_left)) {
		dev_err(&adap->dev, "transaction timeout\n");
		return -ETIMEDOUT;
	}

	rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
	dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);

	if (rxdatap)
		*rxdatap = rxdata;

	return 0;
}

static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
{
	u32 rxdata;
	int ret;

	ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
	if (ret)
		return ret;

	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
		dev_dbg(&adap->dev, "arbitration lost\n");
		return -EAGAIN;
	}
	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
		dev_dbg(&adap->dev, "could not get ACK\n");
		return -ENXIO;
	}

	return 0;
}

static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
			   const u8 *buf)
{
	int ret;

	dev_dbg(&adap->dev, "start condition\n");
	ret = uniphier_i2c_send_byte(adap, addr << 1 |
				     UNIPHIER_I2C_DTRM_STA |
				     UNIPHIER_I2C_DTRM_NACK);
	if (ret)
		return ret;

	while (len--) {
		ret = uniphier_i2c_send_byte(adap,
					     UNIPHIER_I2C_DTRM_NACK | *buf++);
		if (ret)
			return ret;
	}

	return 0;
}

static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
			   u8 *buf)
{
	int ret;

	dev_dbg(&adap->dev, "start condition\n");
	ret = uniphier_i2c_send_byte(adap, addr << 1 |
				     UNIPHIER_I2C_DTRM_STA |
				     UNIPHIER_I2C_DTRM_NACK |
				     UNIPHIER_I2C_DTRM_RD);
	if (ret)
		return ret;

	while (len--) {
		u32 rxdata;

		ret = uniphier_i2c_xfer_byte(adap,
					     len ? 0 : UNIPHIER_I2C_DTRM_NACK,
					     &rxdata);
		if (ret)
			return ret;
		*buf++ = rxdata;
	}

	return 0;
}

static int uniphier_i2c_stop(struct i2c_adapter *adap)
{
	dev_dbg(&adap->dev, "stop condition\n");
	return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
				      UNIPHIER_I2C_DTRM_NACK);
}

static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
					struct i2c_msg *msg, bool stop)
{
	bool is_read = msg->flags & I2C_M_RD;
	bool recovery = false;
	int ret;

	dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
		is_read ? "receive" : "transmit", msg->addr, msg->len, stop);

	if (is_read)
		ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
	else
		ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);

	if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
		return ret;

	if (ret == -ETIMEDOUT) {
		/* This error is fatal.  Needs recovery. */
		stop = false;
		recovery = true;
	}

	if (stop) {
		int ret2 = uniphier_i2c_stop(adap);

		if (ret2) {
			/* Failed to issue STOP.  The bus needs recovery. */
			recovery = true;
			ret = ret ?: ret2;
		}
	}

	if (recovery)
		i2c_recover_bus(adap);

	return ret;
}

static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
						UNIPHIER_I2C_DREC_BBN)) {
		if (priv->busy_cnt++ > 3) {
			/*
			 * If bus busy continues too long, it is probably
			 * in a wrong state.  Try bus recovery.
			 */
			i2c_recover_bus(adap);
			priv->busy_cnt = 0;
		}

		return -EAGAIN;
	}

	priv->busy_cnt = 0;
	return 0;
}

static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
				    struct i2c_msg *msgs, int num)
{
	struct i2c_msg *msg, *emsg = msgs + num;
	int ret;

	ret = uniphier_i2c_check_bus_busy(adap);
	if (ret)
		return ret;

	for (msg = msgs; msg < emsg; msg++) {
		/* Emit STOP if it is the last message or I2C_M_STOP is set. */
		bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);

		ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
		if (ret)
			return ret;
	}

	return num;
}

static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm uniphier_i2c_algo = {
	.master_xfer = uniphier_i2c_master_xfer,
	.functionality = uniphier_i2c_functionality,
};

static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
{
	u32 val = UNIPHIER_I2C_BRST_RSCL;

	val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
	writel(val, priv->membase + UNIPHIER_I2C_BRST);
}

static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
							UNIPHIER_I2C_BSTS_SCL);
}

static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
	       priv->membase + UNIPHIER_I2C_BRST);
}

static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
							UNIPHIER_I2C_BSTS_SDA);
}

static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
{
	uniphier_i2c_reset(i2c_get_adapdata(adap), false);
}

static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
	.recover_bus = i2c_generic_scl_recovery,
	.get_scl = uniphier_i2c_get_scl,
	.set_scl = uniphier_i2c_set_scl,
	.get_sda = uniphier_i2c_get_sda,
	.unprepare_recovery = uniphier_i2c_unprepare_recovery,
};

static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
{
	unsigned int cyc = priv->clk_cycle;

	uniphier_i2c_reset(priv, true);

	/*
	 * Bit30-16: clock cycles of tLOW.
	 *  Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
	 *  Fast-mode:     tLOW = 1.3 us, tHIGH = 0.6 us
	 * "tLow/tHIGH = 5/4" meets both.
	 */
	writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);

	uniphier_i2c_reset(priv, false);
}

static int uniphier_i2c_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct uniphier_i2c_priv *priv;
	struct resource *regs;
	u32 bus_speed;
	unsigned long clk_rate;
	int irq, ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->membase = devm_ioremap_resource(dev, regs);
	if (IS_ERR(priv->membase))
		return PTR_ERR(priv->membase);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "failed to get IRQ number\n");
		return irq;
	}

	if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
		bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;

	if (!bus_speed || bus_speed > UNIPHIER_I2C_MAX_SPEED) {
		dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
		return -EINVAL;
	}

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "failed to get clock\n");
		return PTR_ERR(priv->clk);
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		return ret;

	clk_rate = clk_get_rate(priv->clk);
	if (!clk_rate) {
		dev_err(dev, "input clock rate should not be zero\n");
		ret = -EINVAL;
		goto disable_clk;
	}

	priv->clk_cycle = clk_rate / bus_speed;
	init_completion(&priv->comp);
	priv->adap.owner = THIS_MODULE;
	priv->adap.algo = &uniphier_i2c_algo;
	priv->adap.dev.parent = dev;
	priv->adap.dev.of_node = dev->of_node;
	strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
	i2c_set_adapdata(&priv->adap, priv);
	platform_set_drvdata(pdev, priv);

	uniphier_i2c_hw_init(priv);

	ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
			       priv);
	if (ret) {
		dev_err(dev, "failed to request irq %d\n", irq);
		goto disable_clk;
	}

	ret = i2c_add_adapter(&priv->adap);
disable_clk:
	if (ret)
		clk_disable_unprepare(priv->clk);

	return ret;
}

static int uniphier_i2c_remove(struct platform_device *pdev)
{
	struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);

	i2c_del_adapter(&priv->adap);
	clk_disable_unprepare(priv->clk);

	return 0;
}

static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
{
	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);

	clk_disable_unprepare(priv->clk);

	return 0;
}

static int __maybe_unused uniphier_i2c_resume(struct device *dev)
{
	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		return ret;

	uniphier_i2c_hw_init(priv);

	return 0;
}

static const struct dev_pm_ops uniphier_i2c_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
};

static const struct of_device_id uniphier_i2c_match[] = {
	{ .compatible = "socionext,uniphier-i2c" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_i2c_match);

static struct platform_driver uniphier_i2c_drv = {
	.probe  = uniphier_i2c_probe,
	.remove = uniphier_i2c_remove,
	.driver = {
		.name  = "uniphier-i2c",
		.of_match_table = uniphier_i2c_match,
		.pm = &uniphier_i2c_pm_ops,
	},
};
module_platform_driver(uniphier_i2c_drv);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier I2C bus driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
dd6fd4a3 MY	2	/*
dd6fd4a3 MY	3	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
dd6fd4a3 MY	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/i2c.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/module.h>
	11	#include <linux/platform_device.h>
	12
	13	#define UNIPHIER_I2C_DTRM 0x00 /* TX register */
	14	#define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
	15	#define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
	16	#define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
	17	#define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
	18	#define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
	19	#define UNIPHIER_I2C_DREC 0x04 /* RX register */
	20	#define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
	21	#define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
	22	#define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
	23	#define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
	24	#define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
	25	#define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
	26	#define UNIPHIER_I2C_MYAD 0x08 /* slave address */
	27	#define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
	28	#define UNIPHIER_I2C_BRST 0x10 /* bus reset */
	29	#define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
	30	#define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
	31	#define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
	32	#define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
	33	#define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
	34	#define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
	35	#define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
	36	#define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
	37
	38	#define UNIPHIER_I2C_DEFAULT_SPEED 100000
	39	#define UNIPHIER_I2C_MAX_SPEED 400000
	40
	41	struct uniphier_i2c_priv {
	42	struct completion comp;
	43	struct i2c_adapter adap;
	44	void __iomem *membase;
	45	struct clk *clk;
	46	unsigned int busy_cnt;
9f9d6a40	47	unsigned int clk_cycle;
dd6fd4a3 MY	48	};
	49
	50	static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
	51	{
	52	struct uniphier_i2c_priv *priv = dev_id;
	53
	54	/*
	55	* This hardware uses edge triggered interrupt. Do not touch the
	56	* hardware registers in this handler to make sure to catch the next
	57	* interrupt edge. Just send a complete signal and return.
	58	*/
	59	complete(&priv->comp);
	60
	61	return IRQ_HANDLED;
	62	}
	63
	64	static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
	65	u32 *rxdatap)
	66	{
	67	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	68	unsigned long time_left;
	69	u32 rxdata;
	70
	71	reinit_completion(&priv->comp);
	72
	73	txdata \|= UNIPHIER_I2C_DTRM_IRQEN;
	74	dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
	75	writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
	76
	77	time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
	78	if (unlikely(!time_left)) {
	79	dev_err(&adap->dev, "transaction timeout\n");
	80	return -ETIMEDOUT;
	81	}
	82
	83	rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
	84	dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);
	85
	86	if (rxdatap)
	87	*rxdatap = rxdata;
	88
	89	return 0;
	90	}
	91
	92	static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
	93	{
	94	u32 rxdata;
	95	int ret;
	96
	97	ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
	98	if (ret)
	99	return ret;
	100
	101	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
	102	dev_dbg(&adap->dev, "arbitration lost\n");
	103	return -EAGAIN;
	104	}
	105	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
	106	dev_dbg(&adap->dev, "could not get ACK\n");
	107	return -ENXIO;
	108	}
	109
	110	return 0;
	111	}
112
113	static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
114	const u8 *buf)
115	{
116	int ret;
117
118	dev_dbg(&adap->dev, "start condition\n");
119	ret = uniphier_i2c_send_byte(adap, addr << 1 \|
120	UNIPHIER_I2C_DTRM_STA \|
121	UNIPHIER_I2C_DTRM_NACK);
122	if (ret)
123	return ret;
124
125	while (len--) {
126	ret = uniphier_i2c_send_byte(adap,
127	UNIPHIER_I2C_DTRM_NACK \| *buf++);
128	if (ret)
129	return ret;
130	}
131
132	return 0;
133	}
134
135	static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
136	u8 *buf)
137	{
138	int ret;
139
140	dev_dbg(&adap->dev, "start condition\n");
141	ret = uniphier_i2c_send_byte(adap, addr << 1 \|
142	UNIPHIER_I2C_DTRM_STA \|
143	UNIPHIER_I2C_DTRM_NACK \|
144	UNIPHIER_I2C_DTRM_RD);
145	if (ret)
146	return ret;
147
148	while (len--) {
149	u32 rxdata;
150
151	ret = uniphier_i2c_xfer_byte(adap,
152	len ? 0 : UNIPHIER_I2C_DTRM_NACK,
153	&rxdata);
154	if (ret)
155	return ret;
156	*buf++ = rxdata;
157	}
158
159	return 0;
160	}
161
162	static int uniphier_i2c_stop(struct i2c_adapter *adap)
163	{
164	dev_dbg(&adap->dev, "stop condition\n");
165	return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO \|
166	UNIPHIER_I2C_DTRM_NACK);
167	}
168
169	static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
170	struct i2c_msg *msg, bool stop)
171	{
172	bool is_read = msg->flags & I2C_M_RD;
173	bool recovery = false;
174	int ret;
175
176	dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
177	is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
178
179	if (is_read)
180	ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
181	else
182	ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
183
184	if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
185	return ret;
186
187	if (ret == -ETIMEDOUT) {
188	/* This error is fatal. Needs recovery. */
189	stop = false;
190	recovery = true;
191	}
192
193	if (stop) {
194	int ret2 = uniphier_i2c_stop(adap);
195
196	if (ret2) {
197	/* Failed to issue STOP. The bus needs recovery. */
198	recovery = true;
199	ret = ret ?: ret2;
200	}
201	}
202
203	if (recovery)
204	i2c_recover_bus(adap);
205
206	return ret;
207	}
208
209	static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
210	{
211	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
212
213	if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
214	UNIPHIER_I2C_DREC_BBN)) {
215	if (priv->busy_cnt++ > 3) {
216	/*
217	* If bus busy continues too long, it is probably
218	* in a wrong state. Try bus recovery.
219	*/
220	i2c_recover_bus(adap);
221	priv->busy_cnt = 0;
222	}
223
224	return -EAGAIN;
225	}
226
227	priv->busy_cnt = 0;
228	return 0;
229	}
230
231	static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
232	struct i2c_msg *msgs, int num)
233	{
234	struct i2c_msg msg, emsg = msgs + num;
235	int ret;
236
237	ret = uniphier_i2c_check_bus_busy(adap);
238	if (ret)
239	return ret;
240
241	for (msg = msgs; msg < emsg; msg++) {
38f5d8d8 MY	242	/* Emit STOP if it is the last message or I2C_M_STOP is set. */
38f5d8d8 MY	243	bool stop = (msg + 1 == emsg) \|\| (msg->flags & I2C_M_STOP);
dd6fd4a3 MY	244
	245	ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
	246	if (ret)
	247	return ret;
	248	}
	249
	250	return num;
	251	}
	252
	253	static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
	254	{
	255	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	256	}
	257
	258	static const struct i2c_algorithm uniphier_i2c_algo = {
	259	.master_xfer = uniphier_i2c_master_xfer,
	260	.functionality = uniphier_i2c_functionality,
	261	};
	262
	263	static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
	264	{
	265	u32 val = UNIPHIER_I2C_BRST_RSCL;
	266
	267	val \|= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
	268	writel(val, priv->membase + UNIPHIER_I2C_BRST);
	269	}
	270
	271	static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
	272	{
	273	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	274
	275	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
	276	UNIPHIER_I2C_BSTS_SCL);
	277	}
	278
	279	static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
	280	{
	281	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	282
	283	writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
	284	priv->membase + UNIPHIER_I2C_BRST);
	285	}
	286
	287	static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
	288	{
	289	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	290
	291	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
	292	UNIPHIER_I2C_BSTS_SDA);
	293	}
	294
	295	static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
	296	{
	297	uniphier_i2c_reset(i2c_get_adapdata(adap), false);
	298	}
	299
	300	static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
	301	.recover_bus = i2c_generic_scl_recovery,
	302	.get_scl = uniphier_i2c_get_scl,
	303	.set_scl = uniphier_i2c_set_scl,
	304	.get_sda = uniphier_i2c_get_sda,
	305	.unprepare_recovery = uniphier_i2c_unprepare_recovery,
	306	};
	307
9f9d6a40	308	static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
dd6fd4a3	309	{
9f9d6a40 MY	310	unsigned int cyc = priv->clk_cycle;
9f9d6a40 MY	311
dd6fd4a3 MY	312	uniphier_i2c_reset(priv, true);
dd6fd4a3 MY	313
8469636a MY	314	/*
	315	* Bit30-16: clock cycles of tLOW.
	316	* Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
	317	* Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us
	318	* "tLow/tHIGH = 5/4" meets both.
	319	*/
	320	writel((cyc * 5 / 9 << 16) \| cyc, priv->membase + UNIPHIER_I2C_CLK);
dd6fd4a3 MY	321
dd6fd4a3 MY	322	uniphier_i2c_reset(priv, false);
dd6fd4a3 MY	323	}
	324
	325	static int uniphier_i2c_probe(struct platform_device *pdev)
	326	{
	327	struct device *dev = &pdev->dev;
	328	struct uniphier_i2c_priv *priv;
	329	struct resource *regs;
4c91307c MY	330	u32 bus_speed;
	331	unsigned long clk_rate;
	332	int irq, ret;
dd6fd4a3 MY	333
	334	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	335	if (!priv)
	336	return -ENOMEM;
	337
	338	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	339	priv->membase = devm_ioremap_resource(dev, regs);
	340	if (IS_ERR(priv->membase))
	341	return PTR_ERR(priv->membase);
	342
	343	irq = platform_get_irq(pdev, 0);
	344	if (irq < 0) {
8a350183	345	dev_err(dev, "failed to get IRQ number\n");
dd6fd4a3 MY	346	return irq;
	347	}
	348
4c91307c MY	349	if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
	350	bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;
	351
	352	if (!bus_speed \|\| bus_speed > UNIPHIER_I2C_MAX_SPEED) {
	353	dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
	354	return -EINVAL;
	355	}
	356
	357	priv->clk = devm_clk_get(dev, NULL);
	358	if (IS_ERR(priv->clk)) {
	359	dev_err(dev, "failed to get clock\n");
	360	return PTR_ERR(priv->clk);
	361	}
	362
	363	ret = clk_prepare_enable(priv->clk);
	364	if (ret)
	365	return ret;
	366
	367	clk_rate = clk_get_rate(priv->clk);
	368	if (!clk_rate) {
	369	dev_err(dev, "input clock rate should not be zero\n");
	370	ret = -EINVAL;
a837bad6	371	goto disable_clk;
4c91307c MY	372	}
4c91307c MY	373
9f9d6a40	374	priv->clk_cycle = clk_rate / bus_speed;
dd6fd4a3 MY	375	init_completion(&priv->comp);
	376	priv->adap.owner = THIS_MODULE;
	377	priv->adap.algo = &uniphier_i2c_algo;
	378	priv->adap.dev.parent = dev;
	379	priv->adap.dev.of_node = dev->of_node;
	380	strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
	381	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
	382	i2c_set_adapdata(&priv->adap, priv);
	383	platform_set_drvdata(pdev, priv);
	384
9f9d6a40	385	uniphier_i2c_hw_init(priv);
dd6fd4a3 MY	386
	387	ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
	388	priv);
	389	if (ret) {
	390	dev_err(dev, "failed to request irq %d\n", irq);
a837bad6	391	goto disable_clk;
dd6fd4a3 MY	392	}
	393
	394	ret = i2c_add_adapter(&priv->adap);
a837bad6	395	disable_clk:
dd6fd4a3 MY	396	if (ret)
	397	clk_disable_unprepare(priv->clk);
	398
	399	return ret;
	400	}
	401
	402	static int uniphier_i2c_remove(struct platform_device *pdev)
	403	{
	404	struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
	405
	406	i2c_del_adapter(&priv->adap);
	407	clk_disable_unprepare(priv->clk);
	408
	409	return 0;
	410	}
	411
9f9d6a40 MY	412	static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
	413	{
	414	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	415
	416	clk_disable_unprepare(priv->clk);
	417
	418	return 0;
	419	}
	420
	421	static int __maybe_unused uniphier_i2c_resume(struct device *dev)
	422	{
	423	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	424	int ret;
	425
	426	ret = clk_prepare_enable(priv->clk);
	427	if (ret)
	428	return ret;
	429
	430	uniphier_i2c_hw_init(priv);
	431
	432	return 0;
	433	}
	434
	435	static const struct dev_pm_ops uniphier_i2c_pm_ops = {
	436	SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
	437	};
	438
dd6fd4a3 MY	439	static const struct of_device_id uniphier_i2c_match[] = {
	440	{ .compatible = "socionext,uniphier-i2c" },
	441	{ /* sentinel */ }
	442	};
	443	MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
	444
	445	static struct platform_driver uniphier_i2c_drv = {
	446	.probe = uniphier_i2c_probe,
	447	.remove = uniphier_i2c_remove,
	448	.driver = {
	449	.name = "uniphier-i2c",
	450	.of_match_table = uniphier_i2c_match,
9f9d6a40	451	.pm = &uniphier_i2c_pm_ops,
dd6fd4a3 MY	452	},
	453	};
	454	module_platform_driver(uniphier_i2c_drv);
	455
	456	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
	457	MODULE_DESCRIPTION("UniPhier I2C bus driver");
	458	MODULE_LICENSE("GPL");