[thirdparty/kernel/stable.git] / drivers / i2c / busses / i2c-uniphier.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#define UNIPHIER_I2C_DTRM	0x00	/* TX register */
#define     UNIPHIER_I2C_DTRM_IRQEN	BIT(11)	/* enable interrupt */
#define     UNIPHIER_I2C_DTRM_STA	BIT(10)	/* start condition */
#define     UNIPHIER_I2C_DTRM_STO	BIT(9)	/* stop condition */
#define     UNIPHIER_I2C_DTRM_NACK	BIT(8)	/* do not return ACK */
#define     UNIPHIER_I2C_DTRM_RD	BIT(0)	/* read transaction */
#define UNIPHIER_I2C_DREC	0x04	/* RX register */
#define     UNIPHIER_I2C_DREC_MST	BIT(14)	/* 1 = controller, 0 = target */
#define     UNIPHIER_I2C_DREC_TX	BIT(13)	/* 1 = transmit, 0 = receive */
#define     UNIPHIER_I2C_DREC_STS	BIT(12)	/* stop condition detected */
#define     UNIPHIER_I2C_DREC_LRB	BIT(11)	/* no ACK */
#define     UNIPHIER_I2C_DREC_LAB	BIT(9)	/* arbitration lost */
#define     UNIPHIER_I2C_DREC_BBN	BIT(8)	/* bus not busy */
#define UNIPHIER_I2C_MYAD	0x08	/* local target address */
#define UNIPHIER_I2C_CLK	0x0c	/* clock frequency control */
#define UNIPHIER_I2C_BRST	0x10	/* bus reset */
#define     UNIPHIER_I2C_BRST_FOEN	BIT(1)	/* normal operation */
#define     UNIPHIER_I2C_BRST_RSCL	BIT(0)	/* release SCL */
#define UNIPHIER_I2C_HOLD	0x14	/* hold time control */
#define UNIPHIER_I2C_BSTS	0x18	/* bus status monitor */
#define     UNIPHIER_I2C_BSTS_SDA	BIT(1)	/* readback of SDA line */
#define     UNIPHIER_I2C_BSTS_SCL	BIT(0)	/* readback of SCL line */
#define UNIPHIER_I2C_NOISE	0x1c	/* noise filter control */
#define UNIPHIER_I2C_SETUP	0x20	/* setup time control */

struct uniphier_i2c_priv {
	struct completion comp;
	struct i2c_adapter adap;
	void __iomem *membase;
	struct clk *clk;
	unsigned int busy_cnt;
	unsigned int clk_cycle;
};

static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
{
	struct uniphier_i2c_priv *priv = dev_id;

	/*
	 * This hardware uses edge triggered interrupt.  Do not touch the
	 * hardware registers in this handler to make sure to catch the next
	 * interrupt edge.  Just send a complete signal and return.
	 */
	complete(&priv->comp);

	return IRQ_HANDLED;
}

static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
				  u32 *rxdatap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	unsigned long time_left;
	u32 rxdata;

	reinit_completion(&priv->comp);

	txdata |= UNIPHIER_I2C_DTRM_IRQEN;
	writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);

	time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
	if (unlikely(!time_left))
		return -ETIMEDOUT;

	rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
	if (rxdatap)
		*rxdatap = rxdata;

	return 0;
}

static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
{
	u32 rxdata;
	int ret;

	ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
	if (ret)
		return ret;

	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB))
		return -EAGAIN;

	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB))
		return -ENXIO;

	return 0;
}

static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
			   const u8 *buf)
{
	int ret;

	ret = uniphier_i2c_send_byte(adap, addr << 1 |
				     UNIPHIER_I2C_DTRM_STA |
				     UNIPHIER_I2C_DTRM_NACK);
	if (ret)
		return ret;

	while (len--) {
		ret = uniphier_i2c_send_byte(adap,
					     UNIPHIER_I2C_DTRM_NACK | *buf++);
		if (ret)
			return ret;
	}

	return 0;
}

static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
			   u8 *buf)
{
	int ret;

	ret = uniphier_i2c_send_byte(adap, addr << 1 |
				     UNIPHIER_I2C_DTRM_STA |
				     UNIPHIER_I2C_DTRM_NACK |
				     UNIPHIER_I2C_DTRM_RD);
	if (ret)
		return ret;

	while (len--) {
		u32 rxdata;

		ret = uniphier_i2c_xfer_byte(adap,
					     len ? 0 : UNIPHIER_I2C_DTRM_NACK,
					     &rxdata);
		if (ret)
			return ret;
		*buf++ = rxdata;
	}

	return 0;
}

static int uniphier_i2c_stop(struct i2c_adapter *adap)
{
	return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
				      UNIPHIER_I2C_DTRM_NACK);
}

static int uniphier_i2c_xfer_one(struct i2c_adapter *adap,
				 struct i2c_msg *msg, bool stop)
{
	bool is_read = msg->flags & I2C_M_RD;
	bool recovery = false;
	int ret;

	if (is_read)
		ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
	else
		ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);

	if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
		return ret;

	if (ret == -ETIMEDOUT) {
		/* This error is fatal.  Needs recovery. */
		stop = false;
		recovery = true;
	}

	if (stop) {
		int ret2 = uniphier_i2c_stop(adap);

		if (ret2) {
			/* Failed to issue STOP.  The bus needs recovery. */
			recovery = true;
			ret = ret ?: ret2;
		}
	}

	if (recovery)
		i2c_recover_bus(adap);

	return ret;
}

static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
						UNIPHIER_I2C_DREC_BBN)) {
		if (priv->busy_cnt++ > 3) {
			/*
			 * If bus busy continues too long, it is probably
			 * in a wrong state.  Try bus recovery.
			 */
			i2c_recover_bus(adap);
			priv->busy_cnt = 0;
		}

		return -EAGAIN;
	}

	priv->busy_cnt = 0;
	return 0;
}

static int uniphier_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct i2c_msg *msg, *emsg = msgs + num;
	int ret;

	ret = uniphier_i2c_check_bus_busy(adap);
	if (ret)
		return ret;

	for (msg = msgs; msg < emsg; msg++) {
		/* Emit STOP if it is the last message or I2C_M_STOP is set. */
		bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);

		ret = uniphier_i2c_xfer_one(adap, msg, stop);
		if (ret)
			return ret;
	}

	return num;
}

static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm uniphier_i2c_algo = {
	.xfer = uniphier_i2c_xfer,
	.functionality = uniphier_i2c_functionality,
};

static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
{
	u32 val = UNIPHIER_I2C_BRST_RSCL;

	val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
	writel(val, priv->membase + UNIPHIER_I2C_BRST);
}

static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
							UNIPHIER_I2C_BSTS_SCL);
}

static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
	       priv->membase + UNIPHIER_I2C_BRST);
}

static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
{
	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);

	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
							UNIPHIER_I2C_BSTS_SDA);
}

static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
{
	uniphier_i2c_reset(i2c_get_adapdata(adap), false);
}

static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
	.recover_bus = i2c_generic_scl_recovery,
	.get_scl = uniphier_i2c_get_scl,
	.set_scl = uniphier_i2c_set_scl,
	.get_sda = uniphier_i2c_get_sda,
	.unprepare_recovery = uniphier_i2c_unprepare_recovery,
};

static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
{
	unsigned int cyc = priv->clk_cycle;

	uniphier_i2c_reset(priv, true);

	/*
	 * Bit30-16: clock cycles of tLOW.
	 *  Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
	 *  Fast-mode:     tLOW = 1.3 us, tHIGH = 0.6 us
	 * "tLow/tHIGH = 5/4" meets both.
	 */
	writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);

	uniphier_i2c_reset(priv, false);
}

static int uniphier_i2c_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct uniphier_i2c_priv *priv;
	u32 bus_speed;
	unsigned long clk_rate;
	int irq, ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->membase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->membase))
		return PTR_ERR(priv->membase);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
		bus_speed = I2C_MAX_STANDARD_MODE_FREQ;

	if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ)
		return dev_err_probe(dev, -EINVAL, "invalid clock-frequency %d\n", bus_speed);

	priv->clk = devm_clk_get_enabled(dev, NULL);
	if (IS_ERR(priv->clk))
		return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to enable clock\n");

	clk_rate = clk_get_rate(priv->clk);
	if (!clk_rate)
		return dev_err_probe(dev, -EINVAL, "input clock rate should not be zero\n");

	priv->clk_cycle = clk_rate / bus_speed;
	init_completion(&priv->comp);
	priv->adap.owner = THIS_MODULE;
	priv->adap.algo = &uniphier_i2c_algo;
	priv->adap.dev.parent = dev;
	priv->adap.dev.of_node = dev->of_node;
	strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
	i2c_set_adapdata(&priv->adap, priv);
	platform_set_drvdata(pdev, priv);

	uniphier_i2c_hw_init(priv);

	ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
			       priv);
	if (ret)
		return dev_err_probe(dev, ret, "failed to request irq %d\n", irq);

	return i2c_add_adapter(&priv->adap);
}

static void uniphier_i2c_remove(struct platform_device *pdev)
{
	struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);

	i2c_del_adapter(&priv->adap);
}

static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
{
	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);

	clk_disable_unprepare(priv->clk);

	return 0;
}

static int __maybe_unused uniphier_i2c_resume(struct device *dev)
{
	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		return ret;

	uniphier_i2c_hw_init(priv);

	return 0;
}

static const struct dev_pm_ops uniphier_i2c_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
};

static const struct of_device_id uniphier_i2c_match[] = {
	{ .compatible = "socionext,uniphier-i2c" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_i2c_match);

static struct platform_driver uniphier_i2c_drv = {
	.probe  = uniphier_i2c_probe,
	.remove = uniphier_i2c_remove,
	.driver = {
		.name  = "uniphier-i2c",
		.of_match_table = uniphier_i2c_match,
		.pm = &uniphier_i2c_pm_ops,
	},
};
module_platform_driver(uniphier_i2c_drv);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier I2C bus driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
dd6fd4a3 MY	2	/*
dd6fd4a3 MY	3	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
dd6fd4a3 MY	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/i2c.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/io.h>
	10	#include <linux/module.h>
	11	#include <linux/platform_device.h>
	12
	13	#define UNIPHIER_I2C_DTRM 0x00 /* TX register */
	14	#define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
	15	#define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
	16	#define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
	17	#define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
	18	#define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
	19	#define UNIPHIER_I2C_DREC 0x04 /* RX register */
e02ec4e1	20	#define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = controller, 0 = target */
dd6fd4a3 MY	21	#define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
	22	#define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
	23	#define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
	24	#define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
	25	#define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
e02ec4e1	26	#define UNIPHIER_I2C_MYAD 0x08 /* local target address */
dd6fd4a3 MY	27	#define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
	28	#define UNIPHIER_I2C_BRST 0x10 /* bus reset */
	29	#define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
	30	#define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
	31	#define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
	32	#define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
	33	#define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
	34	#define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
	35	#define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
	36	#define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
	37
dd6fd4a3 MY	38	struct uniphier_i2c_priv {
	39	struct completion comp;
	40	struct i2c_adapter adap;
	41	void __iomem *membase;
	42	struct clk *clk;
	43	unsigned int busy_cnt;
9f9d6a40	44	unsigned int clk_cycle;
dd6fd4a3 MY	45	};
	46
	47	static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
	48	{
	49	struct uniphier_i2c_priv *priv = dev_id;
	50
	51	/*
	52	* This hardware uses edge triggered interrupt. Do not touch the
	53	* hardware registers in this handler to make sure to catch the next
	54	* interrupt edge. Just send a complete signal and return.
	55	*/
	56	complete(&priv->comp);
	57
	58	return IRQ_HANDLED;
	59	}
	60
	61	static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
	62	u32 *rxdatap)
	63	{
	64	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	65	unsigned long time_left;
	66	u32 rxdata;
	67
	68	reinit_completion(&priv->comp);
	69
	70	txdata \|= UNIPHIER_I2C_DTRM_IRQEN;
dd6fd4a3 MY	71	writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
	72
	73	time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
1d428f5d	74	if (unlikely(!time_left))
dd6fd4a3	75	return -ETIMEDOUT;
dd6fd4a3 MY	76
dd6fd4a3 MY	77	rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
dd6fd4a3 MY	78	if (rxdatap)
	79	*rxdatap = rxdata;
	80
	81	return 0;
	82	}
	83
	84	static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
	85	{
	86	u32 rxdata;
	87	int ret;
	88
	89	ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
	90	if (ret)
	91	return ret;
	92
9ee7e72f	93	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB))
dd6fd4a3	94	return -EAGAIN;
9ee7e72f MY	95
9ee7e72f MY	96	if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB))
dd6fd4a3	97	return -ENXIO;
dd6fd4a3 MY	98
	99	return 0;
	100	}
	101
	102	static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
	103	const u8 *buf)
	104	{
	105	int ret;
	106
dd6fd4a3 MY	107	ret = uniphier_i2c_send_byte(adap, addr << 1 \|
	108	UNIPHIER_I2C_DTRM_STA \|
	109	UNIPHIER_I2C_DTRM_NACK);
	110	if (ret)
	111	return ret;
	112
	113	while (len--) {
	114	ret = uniphier_i2c_send_byte(adap,
	115	UNIPHIER_I2C_DTRM_NACK \| *buf++);
	116	if (ret)
	117	return ret;
	118	}
	119
	120	return 0;
	121	}
	122
	123	static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
	124	u8 *buf)
	125	{
	126	int ret;
	127
dd6fd4a3 MY	128	ret = uniphier_i2c_send_byte(adap, addr << 1 \|
	129	UNIPHIER_I2C_DTRM_STA \|
	130	UNIPHIER_I2C_DTRM_NACK \|
	131	UNIPHIER_I2C_DTRM_RD);
	132	if (ret)
	133	return ret;
	134
	135	while (len--) {
	136	u32 rxdata;
	137
	138	ret = uniphier_i2c_xfer_byte(adap,
	139	len ? 0 : UNIPHIER_I2C_DTRM_NACK,
	140	&rxdata);
	141	if (ret)
	142	return ret;
	143	*buf++ = rxdata;
	144	}
	145
	146	return 0;
	147	}
	148
	149	static int uniphier_i2c_stop(struct i2c_adapter *adap)
	150	{
dd6fd4a3 MY	151	return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO \|
	152	UNIPHIER_I2C_DTRM_NACK);
	153	}
	154
e02ec4e1 WS	155	static int uniphier_i2c_xfer_one(struct i2c_adapter *adap,
e02ec4e1 WS	156	struct i2c_msg *msg, bool stop)
dd6fd4a3 MY	157	{
	158	bool is_read = msg->flags & I2C_M_RD;
	159	bool recovery = false;
	160	int ret;
	161
dd6fd4a3 MY	162	if (is_read)
	163	ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
	164	else
	165	ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
	166
	167	if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
	168	return ret;
	169
	170	if (ret == -ETIMEDOUT) {
	171	/* This error is fatal. Needs recovery. */
	172	stop = false;
	173	recovery = true;
	174	}
	175
	176	if (stop) {
	177	int ret2 = uniphier_i2c_stop(adap);
	178
	179	if (ret2) {
	180	/* Failed to issue STOP. The bus needs recovery. */
	181	recovery = true;
	182	ret = ret ?: ret2;
	183	}
	184	}
	185
	186	if (recovery)
	187	i2c_recover_bus(adap);
	188
	189	return ret;
	190	}
	191
	192	static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
	193	{
	194	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	195
	196	if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
	197	UNIPHIER_I2C_DREC_BBN)) {
	198	if (priv->busy_cnt++ > 3) {
	199	/*
	200	* If bus busy continues too long, it is probably
	201	* in a wrong state. Try bus recovery.
	202	*/
	203	i2c_recover_bus(adap);
	204	priv->busy_cnt = 0;
	205	}
	206
	207	return -EAGAIN;
	208	}
	209
	210	priv->busy_cnt = 0;
	211	return 0;
	212	}
	213
e02ec4e1	214	static int uniphier_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
dd6fd4a3 MY	215	{
	216	struct i2c_msg msg, emsg = msgs + num;
	217	int ret;
	218
	219	ret = uniphier_i2c_check_bus_busy(adap);
	220	if (ret)
	221	return ret;
	222
	223	for (msg = msgs; msg < emsg; msg++) {
38f5d8d8 MY	224	/* Emit STOP if it is the last message or I2C_M_STOP is set. */
38f5d8d8 MY	225	bool stop = (msg + 1 == emsg) \|\| (msg->flags & I2C_M_STOP);
dd6fd4a3	226
e02ec4e1	227	ret = uniphier_i2c_xfer_one(adap, msg, stop);
dd6fd4a3 MY	228	if (ret)
	229	return ret;
	230	}
	231
	232	return num;
	233	}
	234
	235	static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
	236	{
	237	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
	238	}
	239
	240	static const struct i2c_algorithm uniphier_i2c_algo = {
e02ec4e1	241	.xfer = uniphier_i2c_xfer,
dd6fd4a3 MY	242	.functionality = uniphier_i2c_functionality,
	243	};
	244
	245	static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
	246	{
	247	u32 val = UNIPHIER_I2C_BRST_RSCL;
	248
	249	val \|= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
	250	writel(val, priv->membase + UNIPHIER_I2C_BRST);
	251	}
	252
	253	static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
	254	{
	255	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	256
	257	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
	258	UNIPHIER_I2C_BSTS_SCL);
	259	}
	260
	261	static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
	262	{
	263	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	264
	265	writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
	266	priv->membase + UNIPHIER_I2C_BRST);
	267	}
	268
	269	static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
	270	{
	271	struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
	272
	273	return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
	274	UNIPHIER_I2C_BSTS_SDA);
	275	}
	276
	277	static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
	278	{
	279	uniphier_i2c_reset(i2c_get_adapdata(adap), false);
	280	}
	281
	282	static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
	283	.recover_bus = i2c_generic_scl_recovery,
	284	.get_scl = uniphier_i2c_get_scl,
	285	.set_scl = uniphier_i2c_set_scl,
	286	.get_sda = uniphier_i2c_get_sda,
	287	.unprepare_recovery = uniphier_i2c_unprepare_recovery,
	288	};
	289
9f9d6a40	290	static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
dd6fd4a3	291	{
9f9d6a40 MY	292	unsigned int cyc = priv->clk_cycle;
9f9d6a40 MY	293
dd6fd4a3 MY	294	uniphier_i2c_reset(priv, true);
dd6fd4a3 MY	295
8469636a MY	296	/*
	297	* Bit30-16: clock cycles of tLOW.
	298	* Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
	299	* Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us
	300	* "tLow/tHIGH = 5/4" meets both.
	301	*/
	302	writel((cyc * 5 / 9 << 16) \| cyc, priv->membase + UNIPHIER_I2C_CLK);
dd6fd4a3 MY	303
dd6fd4a3 MY	304	uniphier_i2c_reset(priv, false);
dd6fd4a3 MY	305	}
	306
	307	static int uniphier_i2c_probe(struct platform_device *pdev)
	308	{
	309	struct device *dev = &pdev->dev;
	310	struct uniphier_i2c_priv *priv;
4c91307c MY	311	u32 bus_speed;
	312	unsigned long clk_rate;
	313	int irq, ret;
dd6fd4a3 MY	314
	315	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	316	if (!priv)
	317	return -ENOMEM;
	318
22ac74a6	319	priv->membase = devm_platform_ioremap_resource(pdev, 0);
dd6fd4a3 MY	320	if (IS_ERR(priv->membase))
	321	return PTR_ERR(priv->membase);
	322
	323	irq = platform_get_irq(pdev, 0);
e42688ed	324	if (irq < 0)
dd6fd4a3	325	return irq;
dd6fd4a3	326
4c91307c	327	if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
90224e64	328	bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
4c91307c	329
c4f62651 EZ	330	if (!bus_speed \|\| bus_speed > I2C_MAX_FAST_MODE_FREQ)
c4f62651 EZ	331	return dev_err_probe(dev, -EINVAL, "invalid clock-frequency %d\n", bus_speed);
4c91307c	332
8a86133e	333	priv->clk = devm_clk_get_enabled(dev, NULL);
c4f62651 EZ	334	if (IS_ERR(priv->clk))
c4f62651 EZ	335	return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to enable clock\n");
4c91307c	336
4c91307c	337	clk_rate = clk_get_rate(priv->clk);
c4f62651 EZ	338	if (!clk_rate)
c4f62651 EZ	339	return dev_err_probe(dev, -EINVAL, "input clock rate should not be zero\n");
4c91307c	340
9f9d6a40	341	priv->clk_cycle = clk_rate / bus_speed;
dd6fd4a3 MY	342	init_completion(&priv->comp);
	343	priv->adap.owner = THIS_MODULE;
	344	priv->adap.algo = &uniphier_i2c_algo;
	345	priv->adap.dev.parent = dev;
	346	priv->adap.dev.of_node = dev->of_node;
ea1558ce	347	strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
dd6fd4a3 MY	348	priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
	349	i2c_set_adapdata(&priv->adap, priv);
	350	platform_set_drvdata(pdev, priv);
	351
9f9d6a40	352	uniphier_i2c_hw_init(priv);
dd6fd4a3 MY	353
	354	ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
	355	priv);
c4f62651 EZ	356	if (ret)
c4f62651 EZ	357	return dev_err_probe(dev, ret, "failed to request irq %d\n", irq);
dd6fd4a3	358
8a86133e	359	return i2c_add_adapter(&priv->adap);
dd6fd4a3 MY	360	}
dd6fd4a3 MY	361
e190a0c3	362	static void uniphier_i2c_remove(struct platform_device *pdev)
dd6fd4a3 MY	363	{
	364	struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
	365
	366	i2c_del_adapter(&priv->adap);
dd6fd4a3 MY	367	}
dd6fd4a3 MY	368
9f9d6a40 MY	369	static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
	370	{
	371	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	372
	373	clk_disable_unprepare(priv->clk);
	374
	375	return 0;
	376	}
	377
	378	static int __maybe_unused uniphier_i2c_resume(struct device *dev)
	379	{
	380	struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
	381	int ret;
	382
	383	ret = clk_prepare_enable(priv->clk);
	384	if (ret)
	385	return ret;
	386
	387	uniphier_i2c_hw_init(priv);
	388
	389	return 0;
	390	}
	391
	392	static const struct dev_pm_ops uniphier_i2c_pm_ops = {
	393	SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
	394	};
	395
dd6fd4a3 MY	396	static const struct of_device_id uniphier_i2c_match[] = {
	397	{ .compatible = "socionext,uniphier-i2c" },
	398	{ /* sentinel */ }
	399	};
	400	MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
	401
	402	static struct platform_driver uniphier_i2c_drv = {
	403	.probe = uniphier_i2c_probe,
32a0a94a	404	.remove = uniphier_i2c_remove,
dd6fd4a3 MY	405	.driver = {
	406	.name = "uniphier-i2c",
	407	.of_match_table = uniphier_i2c_match,
9f9d6a40	408	.pm = &uniphier_i2c_pm_ops,
dd6fd4a3 MY	409	},
	410	};
	411	module_platform_driver(uniphier_i2c_drv);
	412
	413	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
	414	MODULE_DESCRIPTION("UniPhier I2C bus driver");
	415	MODULE_LICENSE("GPL");