[people/ms/u-boot.git] / drivers / i2c / davinci_i2c.c

/*
 * TI DaVinci (TMS320DM644x) I2C driver.
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
 * --------------------------------------------------------
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/i2c_defs.h>
#include <asm/io.h>
#include "davinci_i2c.h"

#define CHECK_NACK() \
	do {\
		if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
			REG(&(i2c_base->i2c_con)) = 0;\
			return 1;\
		} \
	} while (0)

static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);

static int wait_for_bus(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	int	stat, timeout;

	REG(&(i2c_base->i2c_stat)) = 0xffff;

	for (timeout = 0; timeout < 10; timeout++) {
		stat = REG(&(i2c_base->i2c_stat));
		if (!((stat) & I2C_STAT_BB)) {
			REG(&(i2c_base->i2c_stat)) = 0xffff;
			return 0;
		}

		REG(&(i2c_base->i2c_stat)) = stat;
		udelay(50000);
	}

	REG(&(i2c_base->i2c_stat)) = 0xffff;
	return 1;
}


static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	int	stat, timeout;

	for (timeout = 0; timeout < 10; timeout++) {
		udelay(1000);
		stat = REG(&(i2c_base->i2c_stat));
		if (stat & mask)
			return stat;
	}

	REG(&(i2c_base->i2c_stat)) = 0xffff;
	return stat | I2C_TIMEOUT;
}

static void flush_rx(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);

	while (1) {
		if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
			break;

		REG(&(i2c_base->i2c_drr));
		REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
		udelay(1000);
	}
}

static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	uint32_t	div, psc;

	psc = 2;
	/* SCLL + SCLH */
	div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
	REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
	REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
	REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));

	adap->speed	= speed;
	return 0;
}

static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);

	if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
		REG(&(i2c_base->i2c_con)) = 0;
		udelay(50000);
	}

	davinci_i2c_setspeed(adap, speed);

	REG(&(i2c_base->i2c_oa)) = slaveadd;
	REG(&(i2c_base->i2c_cnt)) = 0;

	/* Interrupts must be enabled or I2C module won't work */
	REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
		I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;

	/* Now enable I2C controller (get it out of reset) */
	REG(&(i2c_base->i2c_con)) = I2C_CON_EN;

	udelay(1000);
}

static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	int	rc = 1;

	if (chip == REG(&(i2c_base->i2c_oa)))
		return rc;

	REG(&(i2c_base->i2c_con)) = 0;
	if (wait_for_bus(adap))
		return 1;

	/* try to read one byte from current (or only) address */
	REG(&(i2c_base->i2c_cnt)) = 1;
	REG(&(i2c_base->i2c_sa))  = chip;
	REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
				     I2C_CON_STP);
	udelay(50000);

	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
		rc = 0;
		flush_rx(adap);
		REG(&(i2c_base->i2c_stat)) = 0xffff;
	} else {
		REG(&(i2c_base->i2c_stat)) = 0xffff;
		REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
		udelay(20000);
		if (wait_for_bus(adap))
			return 1;
	}

	flush_rx(adap);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	return rc;
}

static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
				uint32_t addr, int alen, uint8_t *buf, int len)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	uint32_t	tmp;
	int		i;

	if ((alen < 0) || (alen > 2)) {
		printf("%s(): bogus address length %x\n", __func__, alen);
		return 1;
	}

	if (wait_for_bus(adap))
		return 1;

	if (alen != 0) {
		/* Start address phase */
		tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
		REG(&(i2c_base->i2c_cnt)) = alen;
		REG(&(i2c_base->i2c_sa)) = chip;
		REG(&(i2c_base->i2c_con)) = tmp;

		tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		switch (alen) {
		case 2:
			/* Send address MSByte */
			if (tmp & I2C_STAT_XRDY) {
				REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
			} else {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}

			tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);

			CHECK_NACK();
			/* No break, fall through */
		case 1:
			/* Send address LSByte */
			if (tmp & I2C_STAT_XRDY) {
				REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
			} else {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}

			tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
					   I2C_STAT_NACK | I2C_STAT_ARDY);

			CHECK_NACK();

			if (!(tmp & I2C_STAT_ARDY)) {
				REG(&(i2c_base->i2c_con)) = 0;
				return 1;
			}
		}
	}

	/* Address phase is over, now read 'len' bytes and stop */
	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
	REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
	REG(&(i2c_base->i2c_sa)) = chip;
	REG(&(i2c_base->i2c_con)) = tmp;

	for (i = 0; i < len; i++) {
		tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
				   I2C_STAT_ROVR);

		CHECK_NACK();

		if (tmp & I2C_STAT_RRDY) {
			buf[i] = REG(&(i2c_base->i2c_drr));
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
	}

	tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);

	CHECK_NACK();

	if (!(tmp & I2C_STAT_SCD)) {
		REG(&(i2c_base->i2c_con)) = 0;
		return 1;
	}

	flush_rx(adap);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	REG(&(i2c_base->i2c_con)) = 0;

	return 0;
}

static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
				uint32_t addr, int alen, uint8_t *buf, int len)
{
	struct i2c_regs *i2c_base = davinci_get_base(adap);
	uint32_t	tmp;
	int		i;

	if ((alen < 0) || (alen > 2)) {
		printf("%s(): bogus address length %x\n", __func__, alen);
		return 1;
	}
	if (len < 0) {
		printf("%s(): bogus length %x\n", __func__, len);
		return 1;
	}

	if (wait_for_bus(adap))
		return 1;

	/* Start address phase */
	tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
		I2C_CON_TRX | I2C_CON_STP;
	REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
		len & 0xffff : (len & 0xffff) + alen;
	REG(&(i2c_base->i2c_sa)) = chip;
	REG(&(i2c_base->i2c_con)) = tmp;

	switch (alen) {
	case 2:
		/* Send address MSByte */
		tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY) {
			REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
		/* No break, fall through */
	case 1:
		/* Send address LSByte */
		tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY) {
			REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
		} else {
			REG(&(i2c_base->i2c_con)) = 0;
			return 1;
		}
	}

	for (i = 0; i < len; i++) {
		tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);

		CHECK_NACK();

		if (tmp & I2C_STAT_XRDY)
			REG(&(i2c_base->i2c_dxr)) = buf[i];
		else
			return 1;
	}

	tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);

	CHECK_NACK();

	if (!(tmp & I2C_STAT_SCD)) {
		REG(&(i2c_base->i2c_con)) = 0;
		return 1;
	}

	flush_rx(adap);
	REG(&(i2c_base->i2c_stat)) = 0xffff;
	REG(&(i2c_base->i2c_cnt)) = 0;
	REG(&(i2c_base->i2c_con)) = 0;

	return 0;
}

static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)I2C2_BASE;
#endif
#if I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)I2C1_BASE;
#endif
	case 0:
		return (struct i2c_regs *)I2C_BASE;

	default:
		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	}

	return NULL;
}

U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE,
			 0)

#if I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED1,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE1,
			 1)
#endif

#if I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
			 davinci_i2c_read, davinci_i2c_write,
			 davinci_i2c_setspeed,
			 CONFIG_SYS_DAVINCI_I2C_SPEED2,
			 CONFIG_SYS_DAVINCI_I2C_SLAVE2,
			 2)
#endif
Commit	Line	Data
c74b2108 SK	1	/*
	2	* TI DaVinci (TMS320DM644x) I2C driver.
	3	*
e8459dcc VA	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
c74b2108 SK	7	* --------------------------------------------------------
c74b2108 SK	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
c74b2108 SK	10	*/
	11
	12	#include <common.h>
c74b2108 SK	13	#include <i2c.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/i2c_defs.h>
e8459dcc	16	#include <asm/io.h>
356d15eb	17	#include "davinci_i2c.h"
c74b2108 SK	18
	19	#define CHECK_NACK() \
	20	do {\
	21	if (tmp & (I2C_TIMEOUT \| I2C_STAT_NACK)) {\
e8459dcc VA	22	REG(&(i2c_base->i2c_con)) = 0;\
	23	return 1;\
	24	} \
c74b2108 SK	25	} while (0)
c74b2108 SK	26
e8459dcc	27	static struct i2c_regs davinci_get_base(struct i2c_adapter adap);
c74b2108	28
e8459dcc	29	static int wait_for_bus(struct i2c_adapter *adap)
c74b2108	30	{
e8459dcc	31	struct i2c_regs *i2c_base = davinci_get_base(adap);
c74b2108 SK	32	int stat, timeout;
c74b2108 SK	33
e8459dcc	34	REG(&(i2c_base->i2c_stat)) = 0xffff;
c74b2108 SK	35
c74b2108 SK	36	for (timeout = 0; timeout < 10; timeout++) {
e8459dcc VA	37	stat = REG(&(i2c_base->i2c_stat));
	38	if (!((stat) & I2C_STAT_BB)) {
	39	REG(&(i2c_base->i2c_stat)) = 0xffff;
	40	return 0;
c74b2108 SK	41	}
c74b2108 SK	42
e8459dcc	43	REG(&(i2c_base->i2c_stat)) = stat;
c74b2108 SK	44	udelay(50000);
	45	}
	46
e8459dcc VA	47	REG(&(i2c_base->i2c_stat)) = 0xffff;
e8459dcc VA	48	return 1;
c74b2108 SK	49	}
	50
	51
e8459dcc	52	static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
c74b2108	53	{
e8459dcc	54	struct i2c_regs *i2c_base = davinci_get_base(adap);
c74b2108 SK	55	int stat, timeout;
	56
	57	for (timeout = 0; timeout < 10; timeout++) {
	58	udelay(1000);
e8459dcc VA	59	stat = REG(&(i2c_base->i2c_stat));
	60	if (stat & mask)
	61	return stat;
c74b2108 SK	62	}
c74b2108 SK	63
e8459dcc VA	64	REG(&(i2c_base->i2c_stat)) = 0xffff;
e8459dcc VA	65	return stat \| I2C_TIMEOUT;
c74b2108 SK	66	}
c74b2108 SK	67
e8459dcc	68	static void flush_rx(struct i2c_adapter *adap)
c74b2108	69	{
e8459dcc VA	70	struct i2c_regs *i2c_base = davinci_get_base(adap);
e8459dcc VA	71
c74b2108	72	while (1) {
e8459dcc	73	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
c74b2108 SK	74	break;
c74b2108 SK	75
e8459dcc VA	76	REG(&(i2c_base->i2c_drr));
e8459dcc VA	77	REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
c74b2108 SK	78	udelay(1000);
	79	}
	80	}
	81
e8459dcc VA	82	static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
	83	{
	84	struct i2c_regs *i2c_base = davinci_get_base(adap);
	85	uint32_t div, psc;
	86
	87	psc = 2;
	88	/* SCLL + SCLH */
	89	div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
	90	REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
	91	REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
	92	REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
	93
	94	adap->speed = speed;
	95	return 0;
	96	}
c74b2108	97
e8459dcc	98	static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
c74b2108	99	{
e8459dcc	100	struct i2c_regs *i2c_base = davinci_get_base(adap);
c74b2108	101
e8459dcc VA	102	if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
	103	REG(&(i2c_base->i2c_con)) = 0;
	104	udelay(50000);
c74b2108 SK	105	}
c74b2108 SK	106
e8459dcc	107	davinci_i2c_setspeed(adap, speed);
c74b2108	108
e8459dcc VA	109	REG(&(i2c_base->i2c_oa)) = slaveadd;
e8459dcc VA	110	REG(&(i2c_base->i2c_cnt)) = 0;
c74b2108 SK	111
c74b2108 SK	112	/* Interrupts must be enabled or I2C module won't work */
e8459dcc	113	REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE \| I2C_IE_XRDY_IE \|
c74b2108 SK	114	I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \| I2C_IE_NACK_IE;
	115
	116	/* Now enable I2C controller (get it out of reset) */
e8459dcc	117	REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
c74b2108 SK	118
	119	udelay(1000);
	120	}
	121
e8459dcc	122	static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
c74b2108	123	{
e8459dcc	124	struct i2c_regs *i2c_base = davinci_get_base(adap);
c74b2108 SK	125	int rc = 1;
c74b2108 SK	126
e8459dcc VA	127	if (chip == REG(&(i2c_base->i2c_oa)))
e8459dcc VA	128	return rc;
c74b2108	129
e8459dcc VA	130	REG(&(i2c_base->i2c_con)) = 0;
	131	if (wait_for_bus(adap))
	132	return 1;
c74b2108 SK	133
c74b2108 SK	134	/* try to read one byte from current (or only) address */
e8459dcc VA	135	REG(&(i2c_base->i2c_cnt)) = 1;
	136	REG(&(i2c_base->i2c_sa)) = chip;
	137	REG(&(i2c_base->i2c_con)) = (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
	138	I2C_CON_STP);
	139	udelay(50000);
c74b2108	140
e8459dcc	141	if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
c74b2108	142	rc = 0;
e8459dcc VA	143	flush_rx(adap);
e8459dcc VA	144	REG(&(i2c_base->i2c_stat)) = 0xffff;
c74b2108	145	} else {
e8459dcc VA	146	REG(&(i2c_base->i2c_stat)) = 0xffff;
e8459dcc VA	147	REG(&(i2c_base->i2c_con)) \|= I2C_CON_STP;
c74b2108	148	udelay(20000);
e8459dcc VA	149	if (wait_for_bus(adap))
e8459dcc VA	150	return 1;
c74b2108 SK	151	}
c74b2108 SK	152
e8459dcc VA	153	flush_rx(adap);
	154	REG(&(i2c_base->i2c_stat)) = 0xffff;
	155	REG(&(i2c_base->i2c_cnt)) = 0;
	156	return rc;
c74b2108 SK	157	}
c74b2108 SK	158
e8459dcc VA	159	static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
e8459dcc VA	160	uint32_t addr, int alen, uint8_t *buf, int len)
c74b2108	161	{
e8459dcc VA	162	struct i2c_regs *i2c_base = davinci_get_base(adap);
e8459dcc VA	163	uint32_t tmp;
c74b2108 SK	164	int i;
	165
	166	if ((alen < 0) \|\| (alen > 2)) {
e8459dcc VA	167	printf("%s(): bogus address length %x\n", __func__, alen);
e8459dcc VA	168	return 1;
c74b2108 SK	169	}
c74b2108 SK	170
e8459dcc VA	171	if (wait_for_bus(adap))
e8459dcc VA	172	return 1;
c74b2108 SK	173
	174	if (alen != 0) {
	175	/* Start address phase */
	176	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX;
e8459dcc VA	177	REG(&(i2c_base->i2c_cnt)) = alen;
	178	REG(&(i2c_base->i2c_sa)) = chip;
	179	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108	180
e8459dcc	181	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108 SK	182
	183	CHECK_NACK();
	184
	185	switch (alen) {
e8459dcc VA	186	case 2:
	187	/* Send address MSByte */
	188	if (tmp & I2C_STAT_XRDY) {
	189	REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
	190	} else {
	191	REG(&(i2c_base->i2c_con)) = 0;
	192	return 1;
	193	}
	194
	195	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \| I2C_STAT_NACK);
	196
	197	CHECK_NACK();
	198	/* No break, fall through */
	199	case 1:
	200	/* Send address LSByte */
	201	if (tmp & I2C_STAT_XRDY) {
	202	REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
	203	} else {
	204	REG(&(i2c_base->i2c_con)) = 0;
	205	return 1;
	206	}
	207
	208	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \|
	209	I2C_STAT_NACK \| I2C_STAT_ARDY);
	210
	211	CHECK_NACK();
	212
	213	if (!(tmp & I2C_STAT_ARDY)) {
	214	REG(&(i2c_base->i2c_con)) = 0;
	215	return 1;
	216	}
c74b2108 SK	217	}
	218	}
	219
	220	/* Address phase is over, now read 'len' bytes and stop */
	221	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP;
e8459dcc VA	222	REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
	223	REG(&(i2c_base->i2c_sa)) = chip;
	224	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108 SK	225
c74b2108 SK	226	for (i = 0; i < len; i++) {
e8459dcc VA	227	tmp = poll_i2c_irq(adap, I2C_STAT_RRDY \| I2C_STAT_NACK \|
e8459dcc VA	228	I2C_STAT_ROVR);
c74b2108 SK	229
	230	CHECK_NACK();
	231
	232	if (tmp & I2C_STAT_RRDY) {
e8459dcc	233	buf[i] = REG(&(i2c_base->i2c_drr));
c74b2108	234	} else {
e8459dcc VA	235	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	236	return 1;
c74b2108 SK	237	}
	238	}
	239
e8459dcc	240	tmp = poll_i2c_irq(adap, I2C_STAT_SCD \| I2C_STAT_NACK);
c74b2108 SK	241
	242	CHECK_NACK();
	243
	244	if (!(tmp & I2C_STAT_SCD)) {
e8459dcc VA	245	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	246	return 1;
c74b2108 SK	247	}
c74b2108 SK	248
e8459dcc VA	249	flush_rx(adap);
	250	REG(&(i2c_base->i2c_stat)) = 0xffff;
	251	REG(&(i2c_base->i2c_cnt)) = 0;
	252	REG(&(i2c_base->i2c_con)) = 0;
c74b2108	253
e8459dcc	254	return 0;
c74b2108 SK	255	}
c74b2108 SK	256
e8459dcc VA	257	static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
e8459dcc VA	258	uint32_t addr, int alen, uint8_t *buf, int len)
c74b2108	259	{
e8459dcc VA	260	struct i2c_regs *i2c_base = davinci_get_base(adap);
e8459dcc VA	261	uint32_t tmp;
c74b2108 SK	262	int i;
	263
	264	if ((alen < 0) \|\| (alen > 2)) {
e8459dcc VA	265	printf("%s(): bogus address length %x\n", __func__, alen);
e8459dcc VA	266	return 1;
c74b2108 SK	267	}
c74b2108 SK	268	if (len < 0) {
e8459dcc VA	269	printf("%s(): bogus length %x\n", __func__, len);
e8459dcc VA	270	return 1;
c74b2108 SK	271	}
c74b2108 SK	272
e8459dcc VA	273	if (wait_for_bus(adap))
e8459dcc VA	274	return 1;
c74b2108 SK	275
c74b2108 SK	276	/* Start address phase */
e8459dcc VA	277	tmp = I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
	278	I2C_CON_TRX \| I2C_CON_STP;
	279	REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
	280	len & 0xffff : (len & 0xffff) + alen;
	281	REG(&(i2c_base->i2c_sa)) = chip;
	282	REG(&(i2c_base->i2c_con)) = tmp;
c74b2108 SK	283
c74b2108 SK	284	switch (alen) {
e8459dcc VA	285	case 2:
	286	/* Send address MSByte */
	287	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108	288
e8459dcc	289	CHECK_NACK();
c74b2108	290
e8459dcc VA	291	if (tmp & I2C_STAT_XRDY) {
	292	REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
	293	} else {
	294	REG(&(i2c_base->i2c_con)) = 0;
	295	return 1;
	296	}
	297	/* No break, fall through */
	298	case 1:
	299	/* Send address LSByte */
	300	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108	301
e8459dcc	302	CHECK_NACK();
c74b2108	303
e8459dcc VA	304	if (tmp & I2C_STAT_XRDY) {
	305	REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
	306	} else {
	307	REG(&(i2c_base->i2c_con)) = 0;
	308	return 1;
	309	}
c74b2108 SK	310	}
	311
	312	for (i = 0; i < len; i++) {
e8459dcc	313	tmp = poll_i2c_irq(adap, I2C_STAT_XRDY \| I2C_STAT_NACK);
c74b2108 SK	314
	315	CHECK_NACK();
	316
e8459dcc VA	317	if (tmp & I2C_STAT_XRDY)
	318	REG(&(i2c_base->i2c_dxr)) = buf[i];
	319	else
	320	return 1;
c74b2108 SK	321	}
c74b2108 SK	322
e8459dcc	323	tmp = poll_i2c_irq(adap, I2C_STAT_SCD \| I2C_STAT_NACK);
c74b2108 SK	324
	325	CHECK_NACK();
	326
	327	if (!(tmp & I2C_STAT_SCD)) {
e8459dcc VA	328	REG(&(i2c_base->i2c_con)) = 0;
e8459dcc VA	329	return 1;
c74b2108 SK	330	}
c74b2108 SK	331
e8459dcc VA	332	flush_rx(adap);
	333	REG(&(i2c_base->i2c_stat)) = 0xffff;
	334	REG(&(i2c_base->i2c_cnt)) = 0;
	335	REG(&(i2c_base->i2c_con)) = 0;
	336
	337	return 0;
	338	}
	339
	340	static struct i2c_regs davinci_get_base(struct i2c_adapter adap)
	341	{
	342	switch (adap->hwadapnr) {
	343	#if I2C_BUS_MAX >= 3
	344	case 2:
	345	return (struct i2c_regs *)I2C2_BASE;
	346	#endif
	347	#if I2C_BUS_MAX >= 2
	348	case 1:
	349	return (struct i2c_regs *)I2C1_BASE;
	350	#endif
	351	case 0:
	352	return (struct i2c_regs *)I2C_BASE;
	353
	354	default:
	355	printf("wrong hwadapnr: %d\n", adap->hwadapnr);
	356	}
c74b2108	357
e8459dcc	358	return NULL;
c74b2108	359	}
e8459dcc VA	360
	361	U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
	362	davinci_i2c_read, davinci_i2c_write,
	363	davinci_i2c_setspeed,
	364	CONFIG_SYS_DAVINCI_I2C_SPEED,
	365	CONFIG_SYS_DAVINCI_I2C_SLAVE,
	366	0)
	367
	368	#if I2C_BUS_MAX >= 2
	369	U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
	370	davinci_i2c_read, davinci_i2c_write,
	371	davinci_i2c_setspeed,
	372	CONFIG_SYS_DAVINCI_I2C_SPEED1,
	373	CONFIG_SYS_DAVINCI_I2C_SLAVE1,
	374	1)
	375	#endif
	376
	377	#if I2C_BUS_MAX >= 3
	378	U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
	379	davinci_i2c_read, davinci_i2c_write,
	380	davinci_i2c_setspeed,
	381	CONFIG_SYS_DAVINCI_I2C_SPEED2,
	382	CONFIG_SYS_DAVINCI_I2C_SLAVE2,
	383	2)
	384	#endif