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c74b2108 SK |
1 | /* |
2 | * TI DaVinci (TMS320DM644x) I2C driver. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * -------------------------------------------------------- | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
c74b2108 SK |
28 | #include <i2c.h> |
29 | #include <asm/arch/hardware.h> | |
30 | #include <asm/arch/i2c_defs.h> | |
31 | ||
32 | #define CHECK_NACK() \ | |
33 | do {\ | |
34 | if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ | |
35 | REG(I2C_CON) = 0;\ | |
36 | return(1);\ | |
37 | }\ | |
38 | } while (0) | |
39 | ||
40 | ||
41 | static int wait_for_bus(void) | |
42 | { | |
43 | int stat, timeout; | |
44 | ||
45 | REG(I2C_STAT) = 0xffff; | |
46 | ||
47 | for (timeout = 0; timeout < 10; timeout++) { | |
48 | if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { | |
49 | REG(I2C_STAT) = 0xffff; | |
50 | return(0); | |
51 | } | |
52 | ||
53 | REG(I2C_STAT) = stat; | |
54 | udelay(50000); | |
55 | } | |
56 | ||
57 | REG(I2C_STAT) = 0xffff; | |
58 | return(1); | |
59 | } | |
60 | ||
61 | ||
62 | static int poll_i2c_irq(int mask) | |
63 | { | |
64 | int stat, timeout; | |
65 | ||
66 | for (timeout = 0; timeout < 10; timeout++) { | |
67 | udelay(1000); | |
68 | stat = REG(I2C_STAT); | |
69 | if (stat & mask) { | |
70 | return(stat); | |
71 | } | |
72 | } | |
73 | ||
74 | REG(I2C_STAT) = 0xffff; | |
75 | return(stat | I2C_TIMEOUT); | |
76 | } | |
77 | ||
78 | ||
79 | void flush_rx(void) | |
80 | { | |
81 | int dummy; | |
82 | ||
83 | while (1) { | |
84 | if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) | |
85 | break; | |
86 | ||
87 | dummy = REG(I2C_DRR); | |
88 | REG(I2C_STAT) = I2C_STAT_RRDY; | |
89 | udelay(1000); | |
90 | } | |
91 | } | |
92 | ||
93 | ||
94 | void i2c_init(int speed, int slaveadd) | |
95 | { | |
96 | u_int32_t div, psc; | |
97 | ||
98 | if (REG(I2C_CON) & I2C_CON_EN) { | |
99 | REG(I2C_CON) = 0; | |
100 | udelay (50000); | |
101 | } | |
102 | ||
103 | psc = 2; | |
6d0f6bcf | 104 | div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ |
c74b2108 SK |
105 | REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ |
106 | REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ | |
107 | REG(I2C_SCLH) = div - REG(I2C_SCLL); | |
108 | ||
109 | REG(I2C_OA) = slaveadd; | |
110 | REG(I2C_CNT) = 0; | |
111 | ||
112 | /* Interrupts must be enabled or I2C module won't work */ | |
113 | REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | | |
114 | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; | |
115 | ||
116 | /* Now enable I2C controller (get it out of reset) */ | |
117 | REG(I2C_CON) = I2C_CON_EN; | |
118 | ||
119 | udelay(1000); | |
120 | } | |
121 | ||
122 | ||
123 | int i2c_probe(u_int8_t chip) | |
124 | { | |
125 | int rc = 1; | |
126 | ||
127 | if (chip == REG(I2C_OA)) { | |
128 | return(rc); | |
129 | } | |
130 | ||
131 | REG(I2C_CON) = 0; | |
132 | if (wait_for_bus()) {return(1);} | |
133 | ||
134 | /* try to read one byte from current (or only) address */ | |
135 | REG(I2C_CNT) = 1; | |
136 | REG(I2C_SA) = chip; | |
137 | REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); | |
138 | udelay (50000); | |
139 | ||
140 | if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { | |
141 | rc = 0; | |
142 | flush_rx(); | |
143 | REG(I2C_STAT) = 0xffff; | |
144 | } else { | |
145 | REG(I2C_STAT) = 0xffff; | |
146 | REG(I2C_CON) |= I2C_CON_STP; | |
147 | udelay(20000); | |
148 | if (wait_for_bus()) {return(1);} | |
149 | } | |
150 | ||
151 | flush_rx(); | |
152 | REG(I2C_STAT) = 0xffff; | |
153 | REG(I2C_CNT) = 0; | |
154 | return(rc); | |
155 | } | |
156 | ||
157 | ||
158 | int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) | |
159 | { | |
160 | u_int32_t tmp; | |
161 | int i; | |
162 | ||
163 | if ((alen < 0) || (alen > 2)) { | |
164 | printf("%s(): bogus address length %x\n", __FUNCTION__, alen); | |
165 | return(1); | |
166 | } | |
167 | ||
168 | if (wait_for_bus()) {return(1);} | |
169 | ||
170 | if (alen != 0) { | |
171 | /* Start address phase */ | |
172 | tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; | |
173 | REG(I2C_CNT) = alen; | |
174 | REG(I2C_SA) = chip; | |
175 | REG(I2C_CON) = tmp; | |
176 | ||
177 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); | |
178 | ||
179 | CHECK_NACK(); | |
180 | ||
181 | switch (alen) { | |
182 | case 2: | |
183 | /* Send address MSByte */ | |
184 | if (tmp & I2C_STAT_XRDY) { | |
185 | REG(I2C_DXR) = (addr >> 8) & 0xff; | |
186 | } else { | |
187 | REG(I2C_CON) = 0; | |
188 | return(1); | |
189 | } | |
190 | ||
191 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); | |
192 | ||
193 | CHECK_NACK(); | |
194 | /* No break, fall through */ | |
195 | case 1: | |
196 | /* Send address LSByte */ | |
197 | if (tmp & I2C_STAT_XRDY) { | |
198 | REG(I2C_DXR) = addr & 0xff; | |
199 | } else { | |
200 | REG(I2C_CON) = 0; | |
201 | return(1); | |
202 | } | |
203 | ||
204 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); | |
205 | ||
206 | CHECK_NACK(); | |
207 | ||
208 | if (!(tmp & I2C_STAT_ARDY)) { | |
209 | REG(I2C_CON) = 0; | |
210 | return(1); | |
211 | } | |
212 | } | |
213 | } | |
214 | ||
215 | /* Address phase is over, now read 'len' bytes and stop */ | |
216 | tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; | |
217 | REG(I2C_CNT) = len & 0xffff; | |
218 | REG(I2C_SA) = chip; | |
219 | REG(I2C_CON) = tmp; | |
220 | ||
221 | for (i = 0; i < len; i++) { | |
222 | tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); | |
223 | ||
224 | CHECK_NACK(); | |
225 | ||
226 | if (tmp & I2C_STAT_RRDY) { | |
227 | buf[i] = REG(I2C_DRR); | |
228 | } else { | |
229 | REG(I2C_CON) = 0; | |
230 | return(1); | |
231 | } | |
232 | } | |
233 | ||
234 | tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); | |
235 | ||
236 | CHECK_NACK(); | |
237 | ||
238 | if (!(tmp & I2C_STAT_SCD)) { | |
239 | REG(I2C_CON) = 0; | |
240 | return(1); | |
241 | } | |
242 | ||
243 | flush_rx(); | |
244 | REG(I2C_STAT) = 0xffff; | |
245 | REG(I2C_CNT) = 0; | |
246 | REG(I2C_CON) = 0; | |
247 | ||
248 | return(0); | |
249 | } | |
250 | ||
251 | ||
252 | int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) | |
253 | { | |
254 | u_int32_t tmp; | |
255 | int i; | |
256 | ||
257 | if ((alen < 0) || (alen > 2)) { | |
258 | printf("%s(): bogus address length %x\n", __FUNCTION__, alen); | |
259 | return(1); | |
260 | } | |
261 | if (len < 0) { | |
262 | printf("%s(): bogus length %x\n", __FUNCTION__, len); | |
263 | return(1); | |
264 | } | |
265 | ||
266 | if (wait_for_bus()) {return(1);} | |
267 | ||
268 | /* Start address phase */ | |
269 | tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; | |
270 | REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; | |
271 | REG(I2C_SA) = chip; | |
272 | REG(I2C_CON) = tmp; | |
273 | ||
274 | switch (alen) { | |
275 | case 2: | |
276 | /* Send address MSByte */ | |
277 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); | |
278 | ||
279 | CHECK_NACK(); | |
280 | ||
281 | if (tmp & I2C_STAT_XRDY) { | |
282 | REG(I2C_DXR) = (addr >> 8) & 0xff; | |
283 | } else { | |
284 | REG(I2C_CON) = 0; | |
285 | return(1); | |
286 | } | |
287 | /* No break, fall through */ | |
288 | case 1: | |
289 | /* Send address LSByte */ | |
290 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); | |
291 | ||
292 | CHECK_NACK(); | |
293 | ||
294 | if (tmp & I2C_STAT_XRDY) { | |
295 | REG(I2C_DXR) = addr & 0xff; | |
296 | } else { | |
297 | REG(I2C_CON) = 0; | |
298 | return(1); | |
299 | } | |
300 | } | |
301 | ||
302 | for (i = 0; i < len; i++) { | |
303 | tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); | |
304 | ||
305 | CHECK_NACK(); | |
306 | ||
307 | if (tmp & I2C_STAT_XRDY) { | |
308 | REG(I2C_DXR) = buf[i]; | |
309 | } else { | |
310 | return(1); | |
311 | } | |
312 | } | |
313 | ||
314 | tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); | |
315 | ||
316 | CHECK_NACK(); | |
317 | ||
318 | if (!(tmp & I2C_STAT_SCD)) { | |
319 | REG(I2C_CON) = 0; | |
320 | return(1); | |
321 | } | |
322 | ||
323 | flush_rx(); | |
324 | REG(I2C_STAT) = 0xffff; | |
325 | REG(I2C_CNT) = 0; | |
326 | REG(I2C_CON) = 0; | |
327 | ||
328 | return(0); | |
329 | } |