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356d15eb KM |
1 | /* |
2 | * (C) Copyright 2004-2014 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | #ifndef _DAVINCI_I2C_H_ | |
10 | #define _DAVINCI_I2C_H_ | |
11 | ||
12 | #define I2C_WRITE 0 | |
13 | #define I2C_READ 1 | |
14 | ||
e8459dcc VA |
15 | struct i2c_regs { |
16 | u32 i2c_oa; | |
17 | u32 i2c_ie; | |
18 | u32 i2c_stat; | |
19 | u32 i2c_scll; | |
20 | u32 i2c_sclh; | |
21 | u32 i2c_cnt; | |
22 | u32 i2c_drr; | |
23 | u32 i2c_sa; | |
24 | u32 i2c_dxr; | |
25 | u32 i2c_con; | |
26 | u32 i2c_iv; | |
27 | u32 res_2c; | |
28 | u32 i2c_psc; | |
29 | }; | |
356d15eb KM |
30 | |
31 | /* I2C masks */ | |
32 | ||
33 | /* I2C Interrupt Enable Register (I2C_IE): */ | |
34 | #define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ | |
35 | #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ | |
36 | #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ | |
37 | #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ | |
38 | #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ | |
39 | #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ | |
40 | ||
41 | /* I2C Status Register (I2C_STAT): */ | |
42 | ||
43 | #define I2C_STAT_BB (1 << 12) /* Bus busy */ | |
44 | #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
45 | #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
46 | #define I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
47 | #define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ | |
48 | #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
49 | #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
50 | #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
51 | #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ | |
52 | #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ | |
53 | ||
54 | /* I2C Interrupt Code Register (I2C_INTCODE): */ | |
55 | ||
56 | #define I2C_INTCODE_MASK 7 | |
57 | #define I2C_INTCODE_NONE 0 | |
58 | #define I2C_INTCODE_AL 1 /* Arbitration lost */ | |
59 | #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ | |
60 | #define I2C_INTCODE_ARDY 3 /* Register access ready */ | |
61 | #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ | |
62 | #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ | |
63 | #define I2C_INTCODE_SCD 6 /* Stop condition detect */ | |
64 | ||
65 | /* I2C Configuration Register (I2C_CON): */ | |
66 | ||
67 | #define I2C_CON_EN (1 << 5) /* I2C module enable */ | |
68 | #define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ | |
69 | #define I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
70 | #define I2C_CON_TRX (1 << 9) /* Tx/Rx mode (master mode only) */ | |
71 | #define I2C_CON_XA (1 << 8) /* Expand address */ | |
72 | #define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ | |
73 | #define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ | |
74 | #define I2C_CON_FREE (1 << 14) /* Free run on emulation */ | |
75 | ||
76 | #define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ | |
77 | ||
78 | #endif |