[people/ms/u-boot.git] / drivers / i2c / designware_i2c.c

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "designware_i2c.h"

static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

/*
 * set_speed - Set the i2c speed mode (standard, high, fast)
 * @i2c_spd:	required i2c speed mode
 *
 * Set the i2c speed mode (standard, high, fast)
 */
static void set_speed(struct i2c_adapter *adap, int i2c_spd)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned int cntl;
	unsigned int hcnt, lcnt;
	unsigned int enbl;

	/* to set speed cltr must be disabled */
	enbl = readl(&i2c_base->ic_enable);
	enbl &= ~IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
	case IC_SPEED_MODE_MAX:
		cntl |= IC_CON_SPD_HS;
		hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Enable back i2c now speed set */
	enbl |= IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);
}

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	int i2c_spd;

	if (speed >= I2C_MAX_SPEED)
		i2c_spd = IC_SPEED_MODE_MAX;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	set_speed(adap, i2c_spd);
	adap->speed = speed;

	return 0;
}

/*
 * i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static void dw_i2c_init(struct i2c_adapter *adap, int speed,
			int slaveaddr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned int enbl;

	/* Disable i2c */
	enbl = readl(&i2c_base->ic_enable);
	enbl &= ~IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);

	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	dw_i2c_set_bus_speed(adap, speed);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	writel(slaveaddr, &i2c_base->ic_sar);

	/* Enable i2c */
	enbl = readl(&i2c_base->ic_enable);
	enbl |= IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned int enbl;

	/* Disable i2c */
	enbl = readl(&i2c_base->ic_enable);
	enbl &= ~IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	enbl = readl(&i2c_base->ic_enable);
	enbl |= IC_ENABLE_0B;
	writel(enbl, &i2c_base->ic_enable);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
			 int alen)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	if (i2c_wait_for_bb(adap))
		return 1;

	i2c_setaddress(adap, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(adap)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(adap);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_rx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (len == 1)
			writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
		else
			writel(IC_CMD, &i2c_base->ic_cmd_data);

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);

		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_probe - Probe the i2c chip
 */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
Commit	Line	Data
2403f8f4 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	6	*/
	7
	8	#include <common.h>
678398b1	9	#include <i2c.h>
2403f8f4	10	#include <asm/io.h>
031ed2fa	11	#include "designware_i2c.h"
2403f8f4	12
678398b1 SR	13	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	14	{
	15	switch (adap->hwadapnr) {
	16	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	17	case 3:
	18	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	19	#endif
	20	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	21	case 2:
	22	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	23	#endif
	24	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	25	case 1:
	26	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
ac6e2fe6	27	#endif
678398b1 SR	28	case 0:
	29	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	30	default:
	31	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	32	}
ac6e2fe6	33
678398b1 SR	34	return NULL;
678398b1 SR	35	}
2403f8f4 VK	36
	37	/*
	38	* set_speed - Set the i2c speed mode (standard, high, fast)
	39	* @i2c_spd: required i2c speed mode
	40	*
	41	* Set the i2c speed mode (standard, high, fast)
	42	*/
678398b1	43	static void set_speed(struct i2c_adapter *adap, int i2c_spd)
2403f8f4	44	{
678398b1	45	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	46	unsigned int cntl;
2403f8f4 VK	47	unsigned int hcnt, lcnt;
5e3e8dda AV	48	unsigned int enbl;
	49
	50	/* to set speed cltr must be disabled */
678398b1	51	enbl = readl(&i2c_base->ic_enable);
5e3e8dda	52	enbl &= ~IC_ENABLE_0B;
678398b1	53	writel(enbl, &i2c_base->ic_enable);
5e3e8dda	54
678398b1	55	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	56
	57	switch (i2c_spd) {
	58	case IC_SPEED_MODE_MAX:
	59	cntl \|= IC_CON_SPD_HS;
5b8439bb	60	hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	61	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
5b8439bb	62	lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	63	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4 VK	64	break;
	65
	66	case IC_SPEED_MODE_STANDARD:
	67	cntl \|= IC_CON_SPD_SS;
5b8439bb	68	hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	69	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
5b8439bb	70	lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	71	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	72	break;
	73
	74	case IC_SPEED_MODE_FAST:
	75	default:
	76	cntl \|= IC_CON_SPD_FS;
5b8439bb	77	hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	78	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
5b8439bb	79	lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	80	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	81	break;
	82	}
	83
678398b1	84	writel(cntl, &i2c_base->ic_con);
2403f8f4	85
5b8439bb	86	/* Enable back i2c now speed set */
5e3e8dda	87	enbl \|= IC_ENABLE_0B;
678398b1	88	writel(enbl, &i2c_base->ic_enable);
2403f8f4 VK	89	}
	90
	91	/*
	92	* i2c_set_bus_speed - Set the i2c speed
	93	* @speed: required i2c speed
	94	*
	95	* Set the i2c speed.
	96	*/
678398b1 SR	97	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
678398b1 SR	98	unsigned int speed)
2403f8f4	99	{
c69ecd97 JH	100	int i2c_spd;
c69ecd97 JH	101
2403f8f4	102	if (speed >= I2C_MAX_SPEED)
c69ecd97	103	i2c_spd = IC_SPEED_MODE_MAX;
2403f8f4	104	else if (speed >= I2C_FAST_SPEED)
c69ecd97	105	i2c_spd = IC_SPEED_MODE_FAST;
2403f8f4	106	else
c69ecd97	107	i2c_spd = IC_SPEED_MODE_STANDARD;
496ba48f	108
678398b1 SR	109	set_speed(adap, i2c_spd);
678398b1 SR	110	adap->speed = speed;
2403f8f4 VK	111
	112	return 0;
	113	}
	114
	115	/*
	116	* i2c_init - Init function
	117	* @speed: required i2c speed
678398b1	118	* @slaveaddr: slave address for the device
2403f8f4 VK	119	*
	120	* Initialization function.
	121	*/
678398b1 SR	122	static void dw_i2c_init(struct i2c_adapter *adap, int speed,
678398b1 SR	123	int slaveaddr)
2403f8f4	124	{
678398b1	125	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	126	unsigned int enbl;
	127
	128	/* Disable i2c */
678398b1	129	enbl = readl(&i2c_base->ic_enable);
2403f8f4	130	enbl &= ~IC_ENABLE_0B;
678398b1	131	writel(enbl, &i2c_base->ic_enable);
2403f8f4	132
678398b1 SR	133	writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_base->ic_con);
	134	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	135	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	136	dw_i2c_set_bus_speed(adap, speed);
	137	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	138	writel(slaveaddr, &i2c_base->ic_sar);
2403f8f4 VK	139
2403f8f4 VK	140	/* Enable i2c */
678398b1	141	enbl = readl(&i2c_base->ic_enable);
2403f8f4	142	enbl \|= IC_ENABLE_0B;
678398b1	143	writel(enbl, &i2c_base->ic_enable);
2403f8f4 VK	144	}
	145
	146	/*
	147	* i2c_setaddress - Sets the target slave address
	148	* @i2c_addr: target i2c address
	149	*
	150	* Sets the target slave address.
	151	*/
678398b1	152	static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
2403f8f4	153	{
678398b1	154	struct i2c_regs *i2c_base = i2c_get_base(adap);
8b7c8725 AB	155	unsigned int enbl;
	156
	157	/* Disable i2c */
678398b1	158	enbl = readl(&i2c_base->ic_enable);
8b7c8725	159	enbl &= ~IC_ENABLE_0B;
678398b1	160	writel(enbl, &i2c_base->ic_enable);
8b7c8725	161
678398b1	162	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	163
8b7c8725 AB	164	/* Enable i2c */
678398b1	165	enbl = readl(&i2c_base->ic_enable);
8b7c8725	166	enbl \|= IC_ENABLE_0B;
678398b1	167	writel(enbl, &i2c_base->ic_enable);
2403f8f4 VK	168	}
	169
	170	/*
	171	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	172	*
	173	* Flushes the i2c RX FIFO
	174	*/
678398b1	175	static void i2c_flush_rxfifo(struct i2c_adapter *adap)
2403f8f4	176	{
678398b1 SR	177	struct i2c_regs *i2c_base = i2c_get_base(adap);
	178
	179	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
	180	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	181	}
	182
	183	/*
	184	* i2c_wait_for_bb - Waits for bus busy
	185	*
	186	* Waits for bus busy
	187	*/
678398b1	188	static int i2c_wait_for_bb(struct i2c_adapter *adap)
2403f8f4	189	{
678398b1	190	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	191	unsigned long start_time_bb = get_timer(0);
2403f8f4 VK	192
678398b1 SR	193	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	194	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	195
	196	/* Evaluate timeout */
	197	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	198	return 1;
	199	}
	200
	201	return 0;
	202	}
	203
678398b1 SR	204	static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
678398b1 SR	205	int alen)
2403f8f4	206	{
678398b1 SR	207	struct i2c_regs *i2c_base = i2c_get_base(adap);
	208
	209	if (i2c_wait_for_bb(adap))
2403f8f4	210	return 1;
2403f8f4	211
678398b1	212	i2c_setaddress(adap, chip);
070cbaf8 CLS	213	while (alen) {
	214	alen--;
	215	/* high byte address going out first */
	216	writel((addr >> (alen * 8)) & 0xff,
678398b1	217	&i2c_base->ic_cmd_data);
070cbaf8	218	}
2403f8f4 VK	219	return 0;
	220	}
	221
678398b1	222	static int i2c_xfer_finish(struct i2c_adapter *adap)
2403f8f4	223	{
678398b1	224	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	225	ulong start_stop_det = get_timer(0);
	226
	227	while (1) {
678398b1 SR	228	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	229	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	230	break;
	231	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	232	break;
	233	}
	234	}
	235
678398b1	236	if (i2c_wait_for_bb(adap)) {
2403f8f4 VK	237	printf("Timed out waiting for bus\n");
	238	return 1;
	239	}
	240
678398b1	241	i2c_flush_rxfifo(adap);
2403f8f4	242
2403f8f4 VK	243	return 0;
	244	}
	245
	246	/*
	247	* i2c_read - Read from i2c memory
	248	* @chip: target i2c address
	249	* @addr: address to read from
	250	* @alen:
	251	* @buffer: buffer for read data
	252	* @len: no of bytes to be read
	253	*
	254	* Read from i2c memory.
	255	*/
678398b1 SR	256	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	257	int alen, u8 *buffer, int len)
2403f8f4	258	{
678398b1	259	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	260	unsigned long start_time_rx;
2403f8f4 VK	261
32d041e2 AB	262	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	263	/*
	264	* EEPROM chips that implement "address overflow" are ones
	265	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	266	* address and the extra bits end up in the "chip address"
	267	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	268	* four 256 byte chips.
	269	*
	270	* Note that we consider the length of the address field to
	271	* still be one byte because the extra address bits are
	272	* hidden in the chip address.
	273	*/
678398b1	274	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	275	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	276
678398b1	277	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	278	addr);
	279	#endif
	280
678398b1	281	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	282	return 1;
	283
	284	start_time_rx = get_timer(0);
	285	while (len) {
491739bb	286	if (len == 1)
678398b1	287	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
491739bb	288	else
678398b1	289	writel(IC_CMD, &i2c_base->ic_cmd_data);
2403f8f4	290
678398b1 SR	291	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	292	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	293	len--;
	294	start_time_rx = get_timer(0);
	295
	296	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
2403f8f4 VK	297	return 1;
	298	}
	299	}
	300
678398b1	301	return i2c_xfer_finish(adap);
2403f8f4 VK	302	}
	303
	304	/*
	305	* i2c_write - Write to i2c memory
	306	* @chip: target i2c address
	307	* @addr: address to read from
	308	* @alen:
	309	* @buffer: buffer for read data
	310	* @len: no of bytes to be read
	311	*
	312	* Write to i2c memory.
	313	*/
678398b1 SR	314	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	315	int alen, u8 *buffer, int len)
2403f8f4	316	{
678398b1	317	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	318	int nb = len;
	319	unsigned long start_time_tx;
	320
32d041e2 AB	321	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	322	/*
	323	* EEPROM chips that implement "address overflow" are ones
	324	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	325	* address and the extra bits end up in the "chip address"
	326	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	327	* four 256 byte chips.
	328	*
	329	* Note that we consider the length of the address field to
	330	* still be one byte because the extra address bits are
	331	* hidden in the chip address.
	332	*/
678398b1	333	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	334	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	335
678398b1	336	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	337	addr);
	338	#endif
	339
678398b1	340	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	341	return 1;
	342
	343	start_time_tx = get_timer(0);
	344	while (len) {
678398b1 SR	345	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	346	if (--len == 0) {
	347	writel(*buffer \| IC_STOP,
	348	&i2c_base->ic_cmd_data);
	349	} else {
	350	writel(*buffer, &i2c_base->ic_cmd_data);
	351	}
2403f8f4	352	buffer++;
2403f8f4 VK	353	start_time_tx = get_timer(0);
	354
	355	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	356	printf("Timed out. i2c write Failed\n");
	357	return 1;
	358	}
	359	}
	360
678398b1	361	return i2c_xfer_finish(adap);
2403f8f4 VK	362	}
	363
	364	/*
	365	* i2c_probe - Probe the i2c chip
	366	*/
678398b1	367	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4 VK	368	{
2403f8f4 VK	369	u32 tmp;
496ba48f	370	int ret;
2403f8f4 VK	371
	372	/*
	373	* Try to read the first location of the chip.
	374	*/
678398b1	375	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	376	if (ret)
678398b1	377	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	378
496ba48f SR	379	return ret;
2403f8f4	380	}
ac6e2fe6	381
678398b1 SR	382	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	383	dw_i2c_write, dw_i2c_set_bus_speed,
	384	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	385
678398b1 SR	386	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	387	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	388	dw_i2c_write, dw_i2c_set_bus_speed,
	389	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	390	#endif
ac6e2fe6	391
678398b1 SR	392	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	393	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	394	dw_i2c_write, dw_i2c_set_bus_speed,
	395	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	396	#endif
ac6e2fe6	397
678398b1 SR	398	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	399	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	400	dw_i2c_write, dw_i2c_set_bus_speed,
	401	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	402	#endif