[people/ms/u-boot.git] / drivers / i2c / designware_i2c.c

/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include "designware_i2c.h"

static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);

	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned int cntl;
	unsigned int hcnt, lcnt;
	int i2c_spd;

	if (speed >= I2C_MAX_SPEED)
		i2c_spd = IC_SPEED_MODE_MAX;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
	case IC_SPEED_MODE_MAX:
		cntl |= IC_CON_SPD_HS;
		hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Enable back i2c now speed set */
	dw_i2c_enable(i2c_base, true);

	adap->speed = speed;

	return 0;
}

/*
 * i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static void dw_i2c_init(struct i2c_adapter *adap, int speed,
			int slaveaddr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	dw_i2c_set_bus_speed(adap, speed);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	writel(slaveaddr, &i2c_base->ic_sar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
			 int alen)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);

	if (i2c_wait_for_bb(adap))
		return 1;

	i2c_setaddress(adap, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_adapter *adap)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(adap)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(adap);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	unsigned long start_time_rx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (len == 1)
			writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
		else
			writel(IC_CMD, &i2c_base->ic_cmd_data);

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);

		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(adap, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(adap);
}

/*
 * i2c_probe - Probe the i2c chip
 */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
Commit	Line	Data
2403f8f4 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	6	*/
	7
	8	#include <common.h>
678398b1	9	#include <i2c.h>
2403f8f4	10	#include <asm/io.h>
031ed2fa	11	#include "designware_i2c.h"
2403f8f4	12
678398b1 SR	13	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	14	{
	15	switch (adap->hwadapnr) {
	16	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	17	case 3:
	18	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	19	#endif
	20	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	21	case 2:
	22	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	23	#endif
	24	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	25	case 1:
	26	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
ac6e2fe6	27	#endif
678398b1 SR	28	case 0:
	29	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	30	default:
	31	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	32	}
ac6e2fe6	33
678398b1 SR	34	return NULL;
678398b1 SR	35	}
2403f8f4	36
1c8b089b SR	37	static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
	38	{
	39	u32 ena = enable ? IC_ENABLE_0B : 0;
	40	int timeout = 100;
	41
	42	do {
	43	writel(ena, &i2c_base->ic_enable);
	44	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
	45	return;
	46
	47	/*
	48	* Wait 10 times the signaling period of the highest I2C
	49	* transfer supported by the driver (for 400KHz this is
	50	* 25us) as described in the DesignWare I2C databook.
	51	*/
	52	udelay(25);
	53	} while (timeout--);
	54
	55	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
	56	}
	57
2403f8f4	58	/*
11b544ab SR	59	* i2c_set_bus_speed - Set the i2c speed
11b544ab SR	60	* @speed: required i2c speed
2403f8f4	61	*
11b544ab	62	* Set the i2c speed.
2403f8f4	63	*/
11b544ab SR	64	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
11b544ab SR	65	unsigned int speed)
2403f8f4	66	{
678398b1	67	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	68	unsigned int cntl;
2403f8f4 VK	69	unsigned int hcnt, lcnt;
11b544ab SR	70	int i2c_spd;
	71
	72	if (speed >= I2C_MAX_SPEED)
	73	i2c_spd = IC_SPEED_MODE_MAX;
	74	else if (speed >= I2C_FAST_SPEED)
	75	i2c_spd = IC_SPEED_MODE_FAST;
	76	else
	77	i2c_spd = IC_SPEED_MODE_STANDARD;
5e3e8dda AV	78
5e3e8dda AV	79	/* to set speed cltr must be disabled */
1c8b089b	80	dw_i2c_enable(i2c_base, false);
5e3e8dda	81
678398b1	82	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	83
	84	switch (i2c_spd) {
	85	case IC_SPEED_MODE_MAX:
	86	cntl \|= IC_CON_SPD_HS;
5b8439bb	87	hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	88	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
5b8439bb	89	lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	90	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4 VK	91	break;
	92
	93	case IC_SPEED_MODE_STANDARD:
	94	cntl \|= IC_CON_SPD_SS;
5b8439bb	95	hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	96	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
5b8439bb	97	lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	98	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	99	break;
	100
	101	case IC_SPEED_MODE_FAST:
	102	default:
	103	cntl \|= IC_CON_SPD_FS;
5b8439bb	104	hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
678398b1	105	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
5b8439bb	106	lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
678398b1	107	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	108	break;
	109	}
	110
678398b1	111	writel(cntl, &i2c_base->ic_con);
2403f8f4	112
5b8439bb	113	/* Enable back i2c now speed set */
1c8b089b	114	dw_i2c_enable(i2c_base, true);
496ba48f	115
678398b1	116	adap->speed = speed;
2403f8f4 VK	117
	118	return 0;
	119	}
	120
	121	/*
	122	* i2c_init - Init function
	123	* @speed: required i2c speed
678398b1	124	* @slaveaddr: slave address for the device
2403f8f4 VK	125	*
	126	* Initialization function.
	127	*/
678398b1 SR	128	static void dw_i2c_init(struct i2c_adapter *adap, int speed,
678398b1 SR	129	int slaveaddr)
2403f8f4	130	{
678398b1	131	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	132
2403f8f4 VK	133	/* Disable i2c */
1c8b089b	134	dw_i2c_enable(i2c_base, false);
2403f8f4	135
678398b1 SR	136	writel((IC_CON_SD \| IC_CON_SPD_FS \| IC_CON_MM), &i2c_base->ic_con);
	137	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	138	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	139	dw_i2c_set_bus_speed(adap, speed);
	140	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	141	writel(slaveaddr, &i2c_base->ic_sar);
2403f8f4 VK	142
2403f8f4 VK	143	/* Enable i2c */
1c8b089b	144	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	145	}
	146
	147	/*
	148	* i2c_setaddress - Sets the target slave address
	149	* @i2c_addr: target i2c address
	150	*
	151	* Sets the target slave address.
	152	*/
678398b1	153	static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
2403f8f4	154	{
678398b1	155	struct i2c_regs *i2c_base = i2c_get_base(adap);
8b7c8725 AB	156
8b7c8725 AB	157	/* Disable i2c */
1c8b089b	158	dw_i2c_enable(i2c_base, false);
8b7c8725	159
678398b1	160	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	161
8b7c8725 AB	162	/* Enable i2c */
1c8b089b	163	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	164	}
	165
	166	/*
	167	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	168	*
	169	* Flushes the i2c RX FIFO
	170	*/
678398b1	171	static void i2c_flush_rxfifo(struct i2c_adapter *adap)
2403f8f4	172	{
678398b1 SR	173	struct i2c_regs *i2c_base = i2c_get_base(adap);
	174
	175	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
	176	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	177	}
	178
	179	/*
	180	* i2c_wait_for_bb - Waits for bus busy
	181	*
	182	* Waits for bus busy
	183	*/
678398b1	184	static int i2c_wait_for_bb(struct i2c_adapter *adap)
2403f8f4	185	{
678398b1	186	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	187	unsigned long start_time_bb = get_timer(0);
2403f8f4 VK	188
678398b1 SR	189	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	190	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	191
	192	/* Evaluate timeout */
	193	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	194	return 1;
	195	}
	196
	197	return 0;
	198	}
	199
678398b1 SR	200	static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
678398b1 SR	201	int alen)
2403f8f4	202	{
678398b1 SR	203	struct i2c_regs *i2c_base = i2c_get_base(adap);
	204
	205	if (i2c_wait_for_bb(adap))
2403f8f4	206	return 1;
2403f8f4	207
678398b1	208	i2c_setaddress(adap, chip);
070cbaf8 CLS	209	while (alen) {
	210	alen--;
	211	/* high byte address going out first */
	212	writel((addr >> (alen * 8)) & 0xff,
678398b1	213	&i2c_base->ic_cmd_data);
070cbaf8	214	}
2403f8f4 VK	215	return 0;
	216	}
	217
678398b1	218	static int i2c_xfer_finish(struct i2c_adapter *adap)
2403f8f4	219	{
678398b1	220	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	221	ulong start_stop_det = get_timer(0);
	222
	223	while (1) {
678398b1 SR	224	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	225	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	226	break;
	227	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	228	break;
	229	}
	230	}
	231
678398b1	232	if (i2c_wait_for_bb(adap)) {
2403f8f4 VK	233	printf("Timed out waiting for bus\n");
	234	return 1;
	235	}
	236
678398b1	237	i2c_flush_rxfifo(adap);
2403f8f4	238
2403f8f4 VK	239	return 0;
	240	}
	241
	242	/*
	243	* i2c_read - Read from i2c memory
	244	* @chip: target i2c address
	245	* @addr: address to read from
	246	* @alen:
	247	* @buffer: buffer for read data
	248	* @len: no of bytes to be read
	249	*
	250	* Read from i2c memory.
	251	*/
678398b1 SR	252	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	253	int alen, u8 *buffer, int len)
2403f8f4	254	{
678398b1	255	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	256	unsigned long start_time_rx;
2403f8f4 VK	257
32d041e2 AB	258	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	259	/*
	260	* EEPROM chips that implement "address overflow" are ones
	261	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	262	* address and the extra bits end up in the "chip address"
	263	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	264	* four 256 byte chips.
	265	*
	266	* Note that we consider the length of the address field to
	267	* still be one byte because the extra address bits are
	268	* hidden in the chip address.
	269	*/
678398b1	270	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	271	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	272
678398b1	273	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	274	addr);
	275	#endif
	276
678398b1	277	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	278	return 1;
	279
	280	start_time_rx = get_timer(0);
	281	while (len) {
491739bb	282	if (len == 1)
678398b1	283	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
491739bb	284	else
678398b1	285	writel(IC_CMD, &i2c_base->ic_cmd_data);
2403f8f4	286
678398b1 SR	287	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	288	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	289	len--;
	290	start_time_rx = get_timer(0);
	291
	292	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
2403f8f4 VK	293	return 1;
	294	}
	295	}
	296
678398b1	297	return i2c_xfer_finish(adap);
2403f8f4 VK	298	}
	299
	300	/*
	301	* i2c_write - Write to i2c memory
	302	* @chip: target i2c address
	303	* @addr: address to read from
	304	* @alen:
	305	* @buffer: buffer for read data
	306	* @len: no of bytes to be read
	307	*
	308	* Write to i2c memory.
	309	*/
678398b1 SR	310	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
678398b1 SR	311	int alen, u8 *buffer, int len)
2403f8f4	312	{
678398b1	313	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4 VK	314	int nb = len;
	315	unsigned long start_time_tx;
	316
32d041e2 AB	317	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	318	/*
	319	* EEPROM chips that implement "address overflow" are ones
	320	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	321	* address and the extra bits end up in the "chip address"
	322	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	323	* four 256 byte chips.
	324	*
	325	* Note that we consider the length of the address field to
	326	* still be one byte because the extra address bits are
	327	* hidden in the chip address.
	328	*/
678398b1	329	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	330	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	331
678398b1	332	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	333	addr);
	334	#endif
	335
678398b1	336	if (i2c_xfer_init(adap, dev, addr, alen))
2403f8f4 VK	337	return 1;
	338
	339	start_time_tx = get_timer(0);
	340	while (len) {
678398b1 SR	341	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	342	if (--len == 0) {
	343	writel(*buffer \| IC_STOP,
	344	&i2c_base->ic_cmd_data);
	345	} else {
	346	writel(*buffer, &i2c_base->ic_cmd_data);
	347	}
2403f8f4	348	buffer++;
2403f8f4 VK	349	start_time_tx = get_timer(0);
	350
	351	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	352	printf("Timed out. i2c write Failed\n");
	353	return 1;
	354	}
	355	}
	356
678398b1	357	return i2c_xfer_finish(adap);
2403f8f4 VK	358	}
	359
	360	/*
	361	* i2c_probe - Probe the i2c chip
	362	*/
678398b1	363	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4 VK	364	{
2403f8f4 VK	365	u32 tmp;
496ba48f	366	int ret;
2403f8f4 VK	367
	368	/*
	369	* Try to read the first location of the chip.
	370	*/
678398b1	371	ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	372	if (ret)
678398b1	373	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	374
496ba48f SR	375	return ret;
2403f8f4	376	}
ac6e2fe6	377
678398b1 SR	378	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	379	dw_i2c_write, dw_i2c_set_bus_speed,
	380	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	381
678398b1 SR	382	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	383	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	384	dw_i2c_write, dw_i2c_set_bus_speed,
	385	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	386	#endif
ac6e2fe6	387
678398b1 SR	388	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	389	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	390	dw_i2c_write, dw_i2c_set_bus_speed,
	391	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	392	#endif
ac6e2fe6	393
678398b1 SR	394	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	395	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	396	dw_i2c_write, dw_i2c_set_bus_speed,
	397	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	398	#endif