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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
37b8eb37 SG |
2 | /* |
3 | * Copyright (c) 2016, Google Inc | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * David Mueller, ELSOFT AG, d.mueller@elsoft.ch | |
37b8eb37 SG |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <dm.h> | |
11 | #include <i2c.h> | |
12 | #include <asm/arch/clk.h> | |
13 | #include <asm/arch/cpu.h> | |
14 | #include <asm/arch/pinmux.h> | |
15 | #include "s3c24x0_i2c.h" | |
16 | ||
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
19 | /* HSI2C-specific register description */ | |
20 | ||
21 | /* I2C_CTL Register bits */ | |
22 | #define HSI2C_FUNC_MODE_I2C (1u << 0) | |
23 | #define HSI2C_MASTER (1u << 3) | |
24 | #define HSI2C_RXCHON (1u << 6) /* Write/Send */ | |
25 | #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ | |
26 | #define HSI2C_SW_RST (1u << 31) | |
27 | ||
28 | /* I2C_FIFO_CTL Register bits */ | |
29 | #define HSI2C_RXFIFO_EN (1u << 0) | |
30 | #define HSI2C_TXFIFO_EN (1u << 1) | |
31 | #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) | |
32 | #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) | |
33 | ||
34 | /* I2C_TRAILING_CTL Register bits */ | |
35 | #define HSI2C_TRAILING_COUNT (0xff) | |
36 | ||
37 | /* I2C_INT_EN Register bits */ | |
38 | #define HSI2C_TX_UNDERRUN_EN (1u << 2) | |
39 | #define HSI2C_TX_OVERRUN_EN (1u << 3) | |
40 | #define HSI2C_RX_UNDERRUN_EN (1u << 4) | |
41 | #define HSI2C_RX_OVERRUN_EN (1u << 5) | |
42 | #define HSI2C_INT_TRAILING_EN (1u << 6) | |
43 | #define HSI2C_INT_I2C_EN (1u << 9) | |
44 | ||
45 | #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ | |
46 | HSI2C_TX_OVERRUN_EN |\ | |
47 | HSI2C_RX_UNDERRUN_EN |\ | |
48 | HSI2C_RX_OVERRUN_EN |\ | |
49 | HSI2C_INT_TRAILING_EN) | |
50 | ||
51 | /* I2C_CONF Register bits */ | |
52 | #define HSI2C_AUTO_MODE (1u << 31) | |
53 | #define HSI2C_10BIT_ADDR_MODE (1u << 30) | |
54 | #define HSI2C_HS_MODE (1u << 29) | |
55 | ||
56 | /* I2C_AUTO_CONF Register bits */ | |
57 | #define HSI2C_READ_WRITE (1u << 16) | |
58 | #define HSI2C_STOP_AFTER_TRANS (1u << 17) | |
59 | #define HSI2C_MASTER_RUN (1u << 31) | |
60 | ||
61 | /* I2C_TIMEOUT Register bits */ | |
62 | #define HSI2C_TIMEOUT_EN (1u << 31) | |
63 | ||
64 | /* I2C_TRANS_STATUS register bits */ | |
65 | #define HSI2C_MASTER_BUSY (1u << 17) | |
66 | #define HSI2C_SLAVE_BUSY (1u << 16) | |
67 | #define HSI2C_TIMEOUT_AUTO (1u << 4) | |
68 | #define HSI2C_NO_DEV (1u << 3) | |
69 | #define HSI2C_NO_DEV_ACK (1u << 2) | |
70 | #define HSI2C_TRANS_ABORT (1u << 1) | |
71 | #define HSI2C_TRANS_SUCCESS (1u << 0) | |
72 | #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ | |
73 | HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ | |
74 | HSI2C_TRANS_ABORT) | |
75 | #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) | |
76 | ||
77 | ||
78 | /* I2C_FIFO_STAT Register bits */ | |
79 | #define HSI2C_RX_FIFO_EMPTY (1u << 24) | |
80 | #define HSI2C_RX_FIFO_FULL (1u << 23) | |
81 | #define HSI2C_TX_FIFO_EMPTY (1u << 8) | |
82 | #define HSI2C_TX_FIFO_FULL (1u << 7) | |
83 | #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) | |
84 | #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) | |
85 | ||
86 | #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) | |
87 | ||
88 | #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ | |
89 | ||
90 | /* | |
91 | * Wait for transfer completion. | |
92 | * | |
93 | * This function reads the interrupt status register waiting for the INT_I2C | |
94 | * bit to be set, which indicates copletion of a transaction. | |
95 | * | |
96 | * @param i2c: pointer to the appropriate register bank | |
97 | * | |
98 | * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case | |
99 | * the status bits do not get set in time, or an approrpiate error | |
100 | * value in case of transfer errors. | |
101 | */ | |
102 | static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) | |
103 | { | |
104 | int i = HSI2C_TIMEOUT_US; | |
105 | ||
106 | while (i-- > 0) { | |
107 | u32 int_status = readl(&i2c->usi_int_stat); | |
108 | ||
109 | if (int_status & HSI2C_INT_I2C_EN) { | |
110 | u32 trans_status = readl(&i2c->usi_trans_status); | |
111 | ||
112 | /* Deassert pending interrupt. */ | |
113 | writel(int_status, &i2c->usi_int_stat); | |
114 | ||
115 | if (trans_status & HSI2C_NO_DEV_ACK) { | |
116 | debug("%s: no ACK from device\n", __func__); | |
117 | return I2C_NACK; | |
118 | } | |
119 | if (trans_status & HSI2C_NO_DEV) { | |
120 | debug("%s: no device\n", __func__); | |
121 | return I2C_NOK; | |
122 | } | |
123 | if (trans_status & HSI2C_TRANS_ABORT) { | |
124 | debug("%s: arbitration lost\n", __func__); | |
125 | return I2C_NOK_LA; | |
126 | } | |
127 | if (trans_status & HSI2C_TIMEOUT_AUTO) { | |
128 | debug("%s: device timed out\n", __func__); | |
129 | return I2C_NOK_TOUT; | |
130 | } | |
131 | return I2C_OK; | |
132 | } | |
133 | udelay(1); | |
134 | } | |
135 | debug("%s: transaction timeout!\n", __func__); | |
136 | return I2C_NOK_TOUT; | |
137 | } | |
138 | ||
139 | static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) | |
140 | { | |
141 | struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; | |
142 | ulong clkin; | |
143 | unsigned int op_clk = i2c_bus->clock_frequency; | |
144 | unsigned int i = 0, utemp0 = 0, utemp1 = 0; | |
145 | unsigned int t_ftl_cycle; | |
146 | ||
147 | #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) | |
148 | clkin = get_i2c_clk(); | |
149 | #else | |
150 | clkin = get_PCLK(); | |
151 | #endif | |
152 | /* FPCLK / FI2C = | |
153 | * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE | |
154 | * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) | |
155 | * uTemp1 = (TSCLK_L + TSCLK_H + 2) | |
156 | * uTemp2 = TSCLK_L + TSCLK_H | |
157 | */ | |
158 | t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; | |
159 | utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; | |
160 | ||
161 | /* CLK_DIV max is 256 */ | |
162 | for (i = 0; i < 256; i++) { | |
163 | utemp1 = utemp0 / (i + 1); | |
164 | if ((utemp1 < 512) && (utemp1 > 4)) { | |
165 | i2c_bus->clk_cycle = utemp1 - 2; | |
166 | i2c_bus->clk_div = i; | |
167 | return 0; | |
168 | } | |
169 | } | |
170 | return -EINVAL; | |
171 | } | |
172 | ||
173 | static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) | |
174 | { | |
175 | struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; | |
176 | unsigned int t_sr_release; | |
177 | unsigned int n_clkdiv; | |
178 | unsigned int t_start_su, t_start_hd; | |
179 | unsigned int t_stop_su; | |
180 | unsigned int t_data_su, t_data_hd; | |
181 | unsigned int t_scl_l, t_scl_h; | |
182 | u32 i2c_timing_s1; | |
183 | u32 i2c_timing_s2; | |
184 | u32 i2c_timing_s3; | |
185 | u32 i2c_timing_sla; | |
186 | ||
187 | n_clkdiv = i2c_bus->clk_div; | |
188 | t_scl_l = i2c_bus->clk_cycle / 2; | |
189 | t_scl_h = i2c_bus->clk_cycle / 2; | |
190 | t_start_su = t_scl_l; | |
191 | t_start_hd = t_scl_l; | |
192 | t_stop_su = t_scl_l; | |
193 | t_data_su = t_scl_l / 2; | |
194 | t_data_hd = t_scl_l / 2; | |
195 | t_sr_release = i2c_bus->clk_cycle; | |
196 | ||
197 | i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; | |
198 | i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; | |
199 | i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; | |
200 | i2c_timing_sla = t_data_hd << 0; | |
201 | ||
202 | writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); | |
203 | ||
204 | /* Clear to enable Timeout */ | |
205 | clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); | |
206 | ||
207 | /* set AUTO mode */ | |
208 | writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); | |
209 | ||
210 | /* Enable completion conditions' reporting. */ | |
211 | writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); | |
212 | ||
213 | /* Enable FIFOs */ | |
214 | writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); | |
215 | ||
216 | /* Currently operating in Fast speed mode. */ | |
217 | writel(i2c_timing_s1, &hsregs->usi_timing_fs1); | |
218 | writel(i2c_timing_s2, &hsregs->usi_timing_fs2); | |
219 | writel(i2c_timing_s3, &hsregs->usi_timing_fs3); | |
220 | writel(i2c_timing_sla, &hsregs->usi_timing_sla); | |
221 | } | |
222 | ||
223 | /* SW reset for the high speed bus */ | |
224 | static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) | |
225 | { | |
226 | struct exynos5_hsi2c *i2c = i2c_bus->hsregs; | |
227 | u32 i2c_ctl; | |
228 | ||
229 | /* Set and clear the bit for reset */ | |
230 | i2c_ctl = readl(&i2c->usi_ctl); | |
231 | i2c_ctl |= HSI2C_SW_RST; | |
232 | writel(i2c_ctl, &i2c->usi_ctl); | |
233 | ||
234 | i2c_ctl = readl(&i2c->usi_ctl); | |
235 | i2c_ctl &= ~HSI2C_SW_RST; | |
236 | writel(i2c_ctl, &i2c->usi_ctl); | |
237 | ||
238 | /* Initialize the configure registers */ | |
239 | hsi2c_ch_init(i2c_bus); | |
240 | } | |
241 | ||
242 | /* | |
243 | * Poll the appropriate bit of the fifo status register until the interface is | |
244 | * ready to process the next byte or timeout expires. | |
245 | * | |
246 | * In addition to the FIFO status register this function also polls the | |
247 | * interrupt status register to be able to detect unexpected transaction | |
248 | * completion. | |
249 | * | |
250 | * When FIFO is ready to process the next byte, this function returns I2C_OK. | |
251 | * If in course of polling the INT_I2C assertion is detected, the function | |
252 | * returns I2C_NOK. If timeout happens before any of the above conditions is | |
253 | * met - the function returns I2C_NOK_TOUT; | |
254 | ||
255 | * @param i2c: pointer to the appropriate i2c register bank. | |
256 | * @param rx_transfer: set to True if the receive transaction is in progress. | |
257 | * @return: as described above. | |
258 | */ | |
259 | static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) | |
260 | { | |
261 | u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; | |
262 | int i = HSI2C_TIMEOUT_US; | |
263 | ||
264 | while (readl(&i2c->usi_fifo_stat) & fifo_bit) { | |
265 | if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { | |
266 | /* | |
267 | * There is a chance that assertion of | |
268 | * HSI2C_INT_I2C_EN and deassertion of | |
269 | * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's | |
270 | * give FIFO status priority and check it one more | |
271 | * time before reporting interrupt. The interrupt will | |
272 | * be reported next time this function is called. | |
273 | */ | |
274 | if (rx_transfer && | |
275 | !(readl(&i2c->usi_fifo_stat) & fifo_bit)) | |
276 | break; | |
277 | return I2C_NOK; | |
278 | } | |
279 | if (!i--) { | |
280 | debug("%s: FIFO polling timeout!\n", __func__); | |
281 | return I2C_NOK_TOUT; | |
282 | } | |
283 | udelay(1); | |
284 | } | |
285 | return I2C_OK; | |
286 | } | |
287 | ||
288 | /* | |
289 | * Preapre hsi2c transaction, either read or write. | |
290 | * | |
291 | * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of | |
292 | * the 5420 UM. | |
293 | * | |
294 | * @param i2c: pointer to the appropriate i2c register bank. | |
295 | * @param chip: slave address on the i2c bus (with read/write bit exlcuded) | |
296 | * @param len: number of bytes expected to be sent or received | |
297 | * @param rx_transfer: set to true for receive transactions | |
298 | * @param: issue_stop: set to true if i2c stop condition should be generated | |
299 | * after this transaction. | |
300 | * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, | |
301 | * I2C_OK otherwise. | |
302 | */ | |
303 | static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, | |
304 | u8 chip, | |
305 | u16 len, | |
306 | bool rx_transfer, | |
307 | bool issue_stop) | |
308 | { | |
309 | u32 conf; | |
310 | ||
311 | conf = len | HSI2C_MASTER_RUN; | |
312 | ||
313 | if (issue_stop) | |
314 | conf |= HSI2C_STOP_AFTER_TRANS; | |
315 | ||
316 | /* Clear to enable Timeout */ | |
317 | writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); | |
318 | ||
319 | /* Set slave address */ | |
320 | writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); | |
321 | ||
322 | if (rx_transfer) { | |
323 | /* i2c master, read transaction */ | |
324 | writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), | |
325 | &i2c->usi_ctl); | |
326 | ||
327 | /* read up to len bytes, stop after transaction is finished */ | |
328 | writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); | |
329 | } else { | |
330 | /* i2c master, write transaction */ | |
331 | writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), | |
332 | &i2c->usi_ctl); | |
333 | ||
334 | /* write up to len bytes, stop after transaction is finished */ | |
335 | writel(conf, &i2c->usi_auto_conf); | |
336 | } | |
337 | ||
338 | /* Reset all pending interrupt status bits we care about, if any */ | |
339 | writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); | |
340 | ||
341 | return I2C_OK; | |
342 | } | |
343 | ||
344 | /* | |
345 | * Wait while i2c bus is settling down (mostly stop gets completed). | |
346 | */ | |
347 | static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) | |
348 | { | |
349 | int i = HSI2C_TIMEOUT_US; | |
350 | ||
351 | while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { | |
352 | if (!i--) { | |
353 | debug("%s: bus busy\n", __func__); | |
354 | return I2C_NOK_TOUT; | |
355 | } | |
356 | udelay(1); | |
357 | } | |
358 | return I2C_OK; | |
359 | } | |
360 | ||
361 | static int hsi2c_write(struct exynos5_hsi2c *i2c, | |
362 | unsigned char chip, | |
363 | unsigned char addr[], | |
364 | unsigned char alen, | |
365 | unsigned char data[], | |
366 | unsigned short len, | |
367 | bool issue_stop) | |
368 | { | |
369 | int i, rv = 0; | |
370 | ||
371 | if (!(len + alen)) { | |
372 | /* Writes of zero length not supported in auto mode. */ | |
373 | debug("%s: zero length writes not supported\n", __func__); | |
374 | return I2C_NOK; | |
375 | } | |
376 | ||
377 | rv = hsi2c_prepare_transaction | |
378 | (i2c, chip, len + alen, false, issue_stop); | |
379 | if (rv != I2C_OK) | |
380 | return rv; | |
381 | ||
382 | /* Move address, if any, and the data, if any, into the FIFO. */ | |
383 | for (i = 0; i < alen; i++) { | |
384 | rv = hsi2c_poll_fifo(i2c, false); | |
385 | if (rv != I2C_OK) { | |
386 | debug("%s: address write failed\n", __func__); | |
387 | goto write_error; | |
388 | } | |
389 | writel(addr[i], &i2c->usi_txdata); | |
390 | } | |
391 | ||
392 | for (i = 0; i < len; i++) { | |
393 | rv = hsi2c_poll_fifo(i2c, false); | |
394 | if (rv != I2C_OK) { | |
395 | debug("%s: data write failed\n", __func__); | |
396 | goto write_error; | |
397 | } | |
398 | writel(data[i], &i2c->usi_txdata); | |
399 | } | |
400 | ||
401 | rv = hsi2c_wait_for_trx(i2c); | |
402 | ||
403 | write_error: | |
404 | if (issue_stop) { | |
405 | int tmp_ret = hsi2c_wait_while_busy(i2c); | |
406 | if (rv == I2C_OK) | |
407 | rv = tmp_ret; | |
408 | } | |
409 | ||
410 | writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ | |
411 | return rv; | |
412 | } | |
413 | ||
414 | static int hsi2c_read(struct exynos5_hsi2c *i2c, | |
415 | unsigned char chip, | |
416 | unsigned char addr[], | |
417 | unsigned char alen, | |
418 | unsigned char data[], | |
419 | unsigned short len) | |
420 | { | |
421 | int i, rv, tmp_ret; | |
422 | bool drop_data = false; | |
423 | ||
424 | if (!len) { | |
425 | /* Reads of zero length not supported in auto mode. */ | |
426 | debug("%s: zero length read adjusted\n", __func__); | |
427 | drop_data = true; | |
428 | len = 1; | |
429 | } | |
430 | ||
431 | if (alen) { | |
432 | /* Internal register adress needs to be written first. */ | |
433 | rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); | |
434 | if (rv != I2C_OK) | |
435 | return rv; | |
436 | } | |
437 | ||
438 | rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); | |
439 | ||
440 | if (rv != I2C_OK) | |
441 | return rv; | |
442 | ||
443 | for (i = 0; i < len; i++) { | |
444 | rv = hsi2c_poll_fifo(i2c, true); | |
445 | if (rv != I2C_OK) | |
446 | goto read_err; | |
447 | if (drop_data) | |
448 | continue; | |
449 | data[i] = readl(&i2c->usi_rxdata); | |
450 | } | |
451 | ||
452 | rv = hsi2c_wait_for_trx(i2c); | |
453 | ||
454 | read_err: | |
455 | tmp_ret = hsi2c_wait_while_busy(i2c); | |
456 | if (rv == I2C_OK) | |
457 | rv = tmp_ret; | |
458 | ||
459 | writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ | |
460 | return rv; | |
461 | } | |
462 | ||
463 | static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, | |
464 | int nmsgs) | |
465 | { | |
466 | struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); | |
467 | struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; | |
468 | int ret; | |
469 | ||
470 | for (; nmsgs > 0; nmsgs--, msg++) { | |
471 | if (msg->flags & I2C_M_RD) { | |
472 | ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, | |
473 | msg->len); | |
474 | } else { | |
475 | ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, | |
476 | msg->len, true); | |
477 | } | |
478 | if (ret) { | |
479 | exynos5_i2c_reset(i2c_bus); | |
480 | return -EREMOTEIO; | |
481 | } | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) | |
488 | { | |
489 | struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); | |
490 | ||
491 | i2c_bus->clock_frequency = speed; | |
492 | ||
493 | if (hsi2c_get_clk_details(i2c_bus)) | |
494 | return -EFAULT; | |
495 | hsi2c_ch_init(i2c_bus); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) | |
501 | { | |
502 | struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); | |
503 | uchar buf[1]; | |
504 | int ret; | |
505 | ||
506 | buf[0] = 0; | |
507 | ||
508 | /* | |
509 | * What is needed is to send the chip address and verify that the | |
510 | * address was <ACK>ed (i.e. there was a chip at that address which | |
511 | * drove the data line low). | |
512 | */ | |
513 | ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1); | |
514 | ||
515 | return ret != I2C_OK; | |
516 | } | |
517 | ||
518 | static int s3c_i2c_ofdata_to_platdata(struct udevice *dev) | |
519 | { | |
520 | const void *blob = gd->fdt_blob; | |
521 | struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); | |
522 | int node; | |
523 | ||
e160f7d4 | 524 | node = dev_of_offset(dev); |
37b8eb37 | 525 | |
a821c4af | 526 | i2c_bus->hsregs = (struct exynos5_hsi2c *)devfdt_get_addr(dev); |
37b8eb37 SG |
527 | |
528 | i2c_bus->id = pinmux_decode_periph_id(blob, node); | |
529 | ||
530 | i2c_bus->clock_frequency = fdtdec_get_int(blob, node, | |
531 | "clock-frequency", 100000); | |
532 | i2c_bus->node = node; | |
533 | i2c_bus->bus_num = dev->seq; | |
534 | ||
535 | exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); | |
536 | ||
537 | i2c_bus->active = true; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static const struct dm_i2c_ops exynos_hs_i2c_ops = { | |
543 | .xfer = exynos_hs_i2c_xfer, | |
544 | .probe_chip = s3c24x0_i2c_probe, | |
545 | .set_bus_speed = s3c24x0_i2c_set_bus_speed, | |
546 | }; | |
547 | ||
548 | static const struct udevice_id exynos_hs_i2c_ids[] = { | |
549 | { .compatible = "samsung,exynos5-hsi2c" }, | |
550 | { } | |
551 | }; | |
552 | ||
553 | U_BOOT_DRIVER(hs_i2c) = { | |
554 | .name = "i2c_s3c_hs", | |
555 | .id = UCLASS_I2C, | |
556 | .of_match = exynos_hs_i2c_ids, | |
557 | .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, | |
558 | .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), | |
559 | .ops = &exynos_hs_i2c_ops, | |
560 | }; |