[people/ms/u-boot.git] / drivers / i2c / i2c-uniphier-f.c

/*
 * Copyright (C) 2014      Panasonic Corporation
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/errno.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#include <linux/types.h>
#include <dm.h>
#include <i2c.h>
#include <fdtdec.h>

struct uniphier_fi2c_regs {
	u32 cr;				/* control register */
#define I2C_CR_MST	(1 << 3)	/* master mode */
#define I2C_CR_STA	(1 << 2)	/* start condition */
#define I2C_CR_STO	(1 << 1)	/* stop condition */
#define I2C_CR_NACK	(1 << 0)	/* not ACK */
	u32 dttx;			/* send FIFO (write-only) */
#define dtrx		dttx		/* receive FIFO (read-only) */
#define I2C_DTTX_CMD	(1 << 8)	/* send command (slave addr) */
#define I2C_DTTX_RD	(1 << 0)	/* read */
	u32 __reserved;			/* no register at offset 0x08 */
	u32 slad;			/* slave address */
	u32 cyc;			/* clock cycle control */
	u32 lctl;			/* clock low period control */
	u32 ssut;			/* restart/stop setup time control */
	u32 dsut;			/* data setup time control */
	u32 intr;			/* interrupt status */
	u32 ie;				/* interrupt enable */
	u32 ic;				/* interrupt clear */
#define I2C_INT_TE	(1 << 9)	/* TX FIFO empty */
#define I2C_INT_RB	(1 << 4)	/* received specified bytes */
#define I2C_INT_NA	(1 << 2)	/* no answer */
#define I2C_INT_AL	(1 << 1)	/* arbitration lost */
	u32 sr;				/* status register */
#define I2C_SR_DB	(1 << 12)	/* device busy */
#define I2C_SR_BB	(1 << 8)	/* bus busy */
#define I2C_SR_RFF	(1 << 3)	/* Rx FIFO full */
#define I2C_SR_RNE	(1 << 2)	/* Rx FIFO not empty */
#define I2C_SR_TNF	(1 << 1)	/* Tx FIFO not full */
#define I2C_SR_TFE	(1 << 0)	/* Tx FIFO empty */
	u32 __reserved2;		/* no register at offset 0x30 */
	u32 rst;			/* reset control */
#define I2C_RST_TBRST	(1 << 2)	/* clear Tx FIFO */
#define I2C_RST_RBRST	(1 << 1)	/* clear Rx FIFO */
#define I2C_RST_RST	(1 << 0)	/* forcible bus reset */
	u32 bm;				/* bus monitor */
	u32 noise;			/* noise filter control */
	u32 tbc;			/* Tx byte count setting */
	u32 rbc;			/* Rx byte count setting */
	u32 tbcm;			/* Tx byte count monitor */
	u32 rbcm;			/* Rx byte count monitor */
	u32 brst;			/* bus reset */
#define I2C_BRST_FOEN	(1 << 1)	/* normal operation */
#define I2C_BRST_RSCLO	(1 << 0)	/* release SCL low fixing */
};

#define FIOCLK	50000000

struct uniphier_fi2c_priv {
	struct udevice *dev;
	struct uniphier_fi2c_regs __iomem *regs;	/* register base */
	unsigned long fioclk;			/* internal operation clock */
	unsigned long timeout;			/* time out (us) */
};

static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
{
	writel(I2C_RST_RST, &priv->regs->rst);
}

static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv)
{
	u32 val;
	int ret;

	ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100);
	if (ret < 0) {
		dev_dbg(priv->dev, "error: device busy too long. reset...\n");
		uniphier_fi2c_reset(priv);
	}

	return ret;
}

static int uniphier_fi2c_probe(struct udevice *dev)
{
	fdt_addr_t addr;
	struct uniphier_fi2c_priv *priv = dev_get_priv(dev);

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = devm_ioremap(dev, addr, SZ_128);
	if (!priv->regs)
		return -ENOMEM;

	priv->fioclk = FIOCLK;

	priv->dev = dev;

	/* bus forcible reset */
	uniphier_fi2c_reset(priv);

	writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);

	return 0;
}

static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags,
			bool *stop)
{
	u32 irq;
	int ret;

	ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
				 priv->timeout);
	if (ret < 0) {
		dev_dbg(priv->dev, "error: time out\n");
		return ret;
	}

	if (irq & I2C_INT_AL) {
		dev_dbg(priv->dev, "error: arbitration lost\n");
		*stop = false;
		return ret;
	}

	if (irq & I2C_INT_NA) {
		dev_dbg(priv->dev, "error: no answer\n");
		return ret;
	}

	return 0;
}

static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret)
{
	int ret;

	dev_dbg(priv->dev, "stop condition\n");
	writel(I2C_CR_MST | I2C_CR_STO, &priv->regs->cr);

	ret = uniphier_fi2c_check_bus_busy(priv);
	if (ret < 0)
		dev_dbg(priv->dev, "error: device busy after operation\n");

	return old_ret ? old_ret : ret;
}

static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr,
				  uint len, const u8 *buf, bool *stop)
{
	int ret;
	const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
	struct uniphier_fi2c_regs __iomem *regs = priv->regs;

	dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);

	writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);

	writel(irq_flags, &regs->ie);
	writel(irq_flags, &regs->ic);

	dev_dbg(priv->dev, "start condition\n");
	writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);

	ret = wait_for_irq(priv, irq_flags, stop);
	if (ret < 0)
		goto error;

	while (len--) {
		dev_dbg(priv->dev, "sending %x\n", *buf);
		writel(*buf++, &regs->dttx);

		writel(irq_flags, &regs->ic);

		ret = wait_for_irq(priv, irq_flags, stop);
		if (ret < 0)
			goto error;
	}

error:
	writel(irq_flags, &regs->ic);

	if (*stop)
		ret = issue_stop(priv, ret);

	return ret;
}

static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr,
				 uint len, u8 *buf, bool *stop)
{
	int ret = 0;
	const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
	struct uniphier_fi2c_regs __iomem *regs = priv->regs;

	dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);

	/*
	 * In case 'len == 0', only the slave address should be sent
	 * for probing, which is covered by the transmit function.
	 */
	if (len == 0)
		return uniphier_fi2c_transmit(priv, addr, len, buf, stop);

	writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);

	writel(0, &regs->rbc);
	writel(irq_flags, &regs->ie);
	writel(irq_flags, &regs->ic);

	dev_dbg(priv->dev, "start condition\n");
	writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
	       &regs->cr);

	while (len--) {
		ret = wait_for_irq(priv, irq_flags, stop);
		if (ret < 0)
			goto error;

		*buf++ = readl(&regs->dtrx);
		dev_dbg(priv->dev, "received %x\n", *(buf - 1));

		if (len == 1)
			writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);

		writel(irq_flags, &regs->ic);
	}

error:
	writel(irq_flags, &regs->ic);

	if (*stop)
		ret = issue_stop(priv, ret);

	return ret;
}

static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			     int nmsgs)
{
	int ret;
	struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
	bool stop;

	ret = uniphier_fi2c_check_bus_busy(priv);
	if (ret < 0)
		return ret;

	for (; nmsgs > 0; nmsgs--, msg++) {
		/* If next message is read, skip the stop condition */
		stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;

		if (msg->flags & I2C_M_RD)
			ret = uniphier_fi2c_receive(priv, msg->addr, msg->len,
						    msg->buf, &stop);
		else
			ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len,
						     msg->buf, &stop);

		if (ret < 0)
			break;
	}

	return ret;
}

static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	int ret;
	unsigned int clk_count;
	struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
	struct uniphier_fi2c_regs __iomem *regs = priv->regs;

	/* max supported frequency is 400 kHz */
	if (speed > 400000)
		return -EINVAL;

	ret = uniphier_fi2c_check_bus_busy(priv);
	if (ret < 0)
		return ret;

	/* make sure the bus is idle when changing the frequency */
	writel(I2C_BRST_RSCLO, &regs->brst);

	clk_count = priv->fioclk / speed;

	writel(clk_count, &regs->cyc);
	writel(clk_count / 2, &regs->lctl);
	writel(clk_count / 2, &regs->ssut);
	writel(clk_count / 16, &regs->dsut);

	writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);

	/*
	 * Theoretically, each byte can be transferred in
	 * 1000000 * 9 / speed usec.
	 * This time out value is long enough.
	 */
	priv->timeout = 100000000L / speed;

	return 0;
}

static const struct dm_i2c_ops uniphier_fi2c_ops = {
	.xfer = uniphier_fi2c_xfer,
	.set_bus_speed = uniphier_fi2c_set_bus_speed,
};

static const struct udevice_id uniphier_fi2c_of_match[] = {
	{ .compatible = "socionext,uniphier-fi2c" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(uniphier_fi2c) = {
	.name = "uniphier-fi2c",
	.id = UCLASS_I2C,
	.of_match = uniphier_fi2c_of_match,
	.probe = uniphier_fi2c_probe,
	.priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv),
	.ops = &uniphier_fi2c_ops,
};
Commit	Line	Data
238bd0b8	1	/*
4e3d8406 MY	2	* Copyright (C) 2014 Panasonic Corporation
	3	* Copyright (C) 2015-2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
238bd0b8 MY	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
2b7b2df9	9	#include <linux/errno.h>
f6e7f07c	10	#include <linux/io.h>
68578582	11	#include <linux/iopoll.h>
336399fb	12	#include <linux/sizes.h>
2b7b2df9 MY	13	#include <linux/types.h>
2b7b2df9 MY	14	#include <dm.h>
238bd0b8 MY	15	#include <i2c.h>
	16	#include <fdtdec.h>
	17
238bd0b8 MY	18	struct uniphier_fi2c_regs {
	19	u32 cr; /* control register */
	20	#define I2C_CR_MST (1 << 3) /* master mode */
	21	#define I2C_CR_STA (1 << 2) /* start condition */
	22	#define I2C_CR_STO (1 << 1) /* stop condition */
	23	#define I2C_CR_NACK (1 << 0) /* not ACK */
	24	u32 dttx; /* send FIFO (write-only) */
	25	#define dtrx dttx /* receive FIFO (read-only) */
	26	#define I2C_DTTX_CMD (1 << 8) /* send command (slave addr) */
	27	#define I2C_DTTX_RD (1 << 0) /* read */
	28	u32 __reserved; /* no register at offset 0x08 */
	29	u32 slad; /* slave address */
	30	u32 cyc; /* clock cycle control */
	31	u32 lctl; /* clock low period control */
	32	u32 ssut; /* restart/stop setup time control */
	33	u32 dsut; /* data setup time control */
	34	u32 intr; /* interrupt status */
	35	u32 ie; /* interrupt enable */
	36	u32 ic; /* interrupt clear */
	37	#define I2C_INT_TE (1 << 9) /* TX FIFO empty */
	38	#define I2C_INT_RB (1 << 4) /* received specified bytes */
	39	#define I2C_INT_NA (1 << 2) /* no answer */
	40	#define I2C_INT_AL (1 << 1) /* arbitration lost */
	41	u32 sr; /* status register */
	42	#define I2C_SR_DB (1 << 12) /* device busy */
	43	#define I2C_SR_BB (1 << 8) /* bus busy */
	44	#define I2C_SR_RFF (1 << 3) /* Rx FIFO full */
	45	#define I2C_SR_RNE (1 << 2) /* Rx FIFO not empty */
	46	#define I2C_SR_TNF (1 << 1) /* Tx FIFO not full */
	47	#define I2C_SR_TFE (1 << 0) /* Tx FIFO empty */
	48	u32 __reserved2; /* no register at offset 0x30 */
	49	u32 rst; /* reset control */
	50	#define I2C_RST_TBRST (1 << 2) /* clear Tx FIFO */
	51	#define I2C_RST_RBRST (1 << 1) /* clear Rx FIFO */
	52	#define I2C_RST_RST (1 << 0) /* forcible bus reset */
	53	u32 bm; /* bus monitor */
	54	u32 noise; /* noise filter control */
	55	u32 tbc; /* Tx byte count setting */
	56	u32 rbc; /* Rx byte count setting */
	57	u32 tbcm; /* Tx byte count monitor */
	58	u32 rbcm; /* Rx byte count monitor */
	59	u32 brst; /* bus reset */
	60	#define I2C_BRST_FOEN (1 << 1) /* normal operation */
	61	#define I2C_BRST_RSCLO (1 << 0) /* release SCL low fixing */
	62	};
	63
	64	#define FIOCLK 50000000
	65
2b7b2df9 MY	66	struct uniphier_fi2c_priv {
2b7b2df9 MY	67	struct udevice *dev;
238bd0b8 MY	68	struct uniphier_fi2c_regs __iomem regs; / register base */
	69	unsigned long fioclk; /* internal operation clock */
	70	unsigned long timeout; /* time out (us) */
	71	};
	72
2b7b2df9	73	static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
238bd0b8	74	{
2b7b2df9	75	writel(I2C_RST_RST, &priv->regs->rst);
238bd0b8 MY	76	}
238bd0b8 MY	77
2b7b2df9	78	static int uniphier_fi2c_check_bus_busy(struct uniphier_fi2c_priv *priv)
238bd0b8	79	{
68578582	80	u32 val;
238bd0b8 MY	81	int ret;
238bd0b8 MY	82
2b7b2df9	83	ret = readl_poll_timeout(&priv->regs->sr, val, !(val & I2C_SR_DB), 100);
238bd0b8	84	if (ret < 0) {
2b7b2df9 MY	85	dev_dbg(priv->dev, "error: device busy too long. reset...\n");
2b7b2df9 MY	86	uniphier_fi2c_reset(priv);
238bd0b8 MY	87	}
	88
	89	return ret;
	90	}
	91
	92	static int uniphier_fi2c_probe(struct udevice *dev)
	93	{
	94	fdt_addr_t addr;
2b7b2df9	95	struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
238bd0b8	96
a821c4af	97	addr = devfdt_get_addr(dev);
336399fb MY	98	if (addr == FDT_ADDR_T_NONE)
336399fb MY	99	return -EINVAL;
238bd0b8	100
4e3d8406	101	priv->regs = devm_ioremap(dev, addr, SZ_128);
238bd0b8 MY	102	if (!priv->regs)
	103	return -ENOMEM;
	104
	105	priv->fioclk = FIOCLK;
	106
2b7b2df9 MY	107	priv->dev = dev;
2b7b2df9 MY	108
238bd0b8	109	/* bus forcible reset */
2b7b2df9	110	uniphier_fi2c_reset(priv);
238bd0b8 MY	111
	112	writel(I2C_BRST_FOEN \| I2C_BRST_RSCLO, &priv->regs->brst);
	113
	114	return 0;
	115	}
	116
2b7b2df9	117	static int wait_for_irq(struct uniphier_fi2c_priv *priv, u32 flags,
238bd0b8 MY	118	bool *stop)
	119	{
	120	u32 irq;
68578582	121	int ret;
238bd0b8	122
2b7b2df9 MY	123	ret = readl_poll_timeout(&priv->regs->intr, irq, irq & flags,
2b7b2df9 MY	124	priv->timeout);
68578582	125	if (ret < 0) {
2b7b2df9	126	dev_dbg(priv->dev, "error: time out\n");
238bd0b8 MY	127	return ret;
	128	}
	129
	130	if (irq & I2C_INT_AL) {
2b7b2df9	131	dev_dbg(priv->dev, "error: arbitration lost\n");
238bd0b8 MY	132	*stop = false;
	133	return ret;
	134	}
	135
	136	if (irq & I2C_INT_NA) {
2b7b2df9	137	dev_dbg(priv->dev, "error: no answer\n");
238bd0b8 MY	138	return ret;
	139	}
	140
	141	return 0;
	142	}
	143
2b7b2df9	144	static int issue_stop(struct uniphier_fi2c_priv *priv, int old_ret)
238bd0b8 MY	145	{
	146	int ret;
	147
2b7b2df9 MY	148	dev_dbg(priv->dev, "stop condition\n");
2b7b2df9 MY	149	writel(I2C_CR_MST \| I2C_CR_STO, &priv->regs->cr);
238bd0b8	150
2b7b2df9	151	ret = uniphier_fi2c_check_bus_busy(priv);
238bd0b8	152	if (ret < 0)
2b7b2df9	153	dev_dbg(priv->dev, "error: device busy after operation\n");
238bd0b8 MY	154
	155	return old_ret ? old_ret : ret;
	156	}
	157
2b7b2df9	158	static int uniphier_fi2c_transmit(struct uniphier_fi2c_priv *priv, uint addr,
238bd0b8 MY	159	uint len, const u8 buf, bool stop)
	160	{
	161	int ret;
	162	const u32 irq_flags = I2C_INT_TE \| I2C_INT_NA \| I2C_INT_AL;
2b7b2df9	163	struct uniphier_fi2c_regs __iomem *regs = priv->regs;
238bd0b8	164
2b7b2df9	165	dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
238bd0b8 MY	166
	167	writel(I2C_DTTX_CMD \| addr << 1, &regs->dttx);
	168
	169	writel(irq_flags, &regs->ie);
	170	writel(irq_flags, &regs->ic);
	171
2b7b2df9	172	dev_dbg(priv->dev, "start condition\n");
238bd0b8 MY	173	writel(I2C_CR_MST \| I2C_CR_STA, &regs->cr);
238bd0b8 MY	174
2b7b2df9	175	ret = wait_for_irq(priv, irq_flags, stop);
238bd0b8 MY	176	if (ret < 0)
	177	goto error;
	178
	179	while (len--) {
2b7b2df9	180	dev_dbg(priv->dev, "sending %x\n", *buf);
238bd0b8 MY	181	writel(*buf++, &regs->dttx);
	182
	183	writel(irq_flags, &regs->ic);
	184
2b7b2df9	185	ret = wait_for_irq(priv, irq_flags, stop);
238bd0b8 MY	186	if (ret < 0)
	187	goto error;
	188	}
	189
	190	error:
	191	writel(irq_flags, &regs->ic);
	192
	193	if (*stop)
2b7b2df9	194	ret = issue_stop(priv, ret);
238bd0b8 MY	195
	196	return ret;
	197	}
	198
2b7b2df9	199	static int uniphier_fi2c_receive(struct uniphier_fi2c_priv *priv, uint addr,
238bd0b8 MY	200	uint len, u8 buf, bool stop)
	201	{
	202	int ret = 0;
	203	const u32 irq_flags = I2C_INT_RB \| I2C_INT_NA \| I2C_INT_AL;
2b7b2df9	204	struct uniphier_fi2c_regs __iomem *regs = priv->regs;
238bd0b8	205
2b7b2df9	206	dev_dbg(priv->dev, "%s: addr = %x, len = %d\n", __func__, addr, len);
238bd0b8 MY	207
	208	/*
	209	* In case 'len == 0', only the slave address should be sent
	210	* for probing, which is covered by the transmit function.
	211	*/
	212	if (len == 0)
2b7b2df9	213	return uniphier_fi2c_transmit(priv, addr, len, buf, stop);
238bd0b8 MY	214
	215	writel(I2C_DTTX_CMD \| I2C_DTTX_RD \| addr << 1, &regs->dttx);
	216
	217	writel(0, &regs->rbc);
	218	writel(irq_flags, &regs->ie);
	219	writel(irq_flags, &regs->ic);
	220
2b7b2df9	221	dev_dbg(priv->dev, "start condition\n");
238bd0b8 MY	222	writel(I2C_CR_MST \| I2C_CR_STA \| (len == 1 ? I2C_CR_NACK : 0),
	223	&regs->cr);
	224
	225	while (len--) {
2b7b2df9	226	ret = wait_for_irq(priv, irq_flags, stop);
238bd0b8 MY	227	if (ret < 0)
	228	goto error;
	229
	230	*buf++ = readl(&regs->dtrx);
2b7b2df9	231	dev_dbg(priv->dev, "received %x\n", *(buf - 1));
238bd0b8 MY	232
	233	if (len == 1)
	234	writel(I2C_CR_MST \| I2C_CR_NACK, &regs->cr);
	235
	236	writel(irq_flags, &regs->ic);
	237	}
	238
	239	error:
	240	writel(irq_flags, &regs->ic);
	241
	242	if (*stop)
2b7b2df9	243	ret = issue_stop(priv, ret);
238bd0b8 MY	244
	245	return ret;
	246	}
	247
	248	static int uniphier_fi2c_xfer(struct udevice bus, struct i2c_msg msg,
	249	int nmsgs)
	250	{
	251	int ret;
2b7b2df9	252	struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
238bd0b8 MY	253	bool stop;
238bd0b8 MY	254
2b7b2df9	255	ret = uniphier_fi2c_check_bus_busy(priv);
238bd0b8 MY	256	if (ret < 0)
	257	return ret;
	258
	259	for (; nmsgs > 0; nmsgs--, msg++) {
	260	/* If next message is read, skip the stop condition */
	261	stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
	262
	263	if (msg->flags & I2C_M_RD)
2b7b2df9	264	ret = uniphier_fi2c_receive(priv, msg->addr, msg->len,
238bd0b8 MY	265	msg->buf, &stop);
238bd0b8 MY	266	else
2b7b2df9	267	ret = uniphier_fi2c_transmit(priv, msg->addr, msg->len,
238bd0b8 MY	268	msg->buf, &stop);
	269
	270	if (ret < 0)
	271	break;
	272	}
	273
	274	return ret;
	275	}
	276
	277	static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	278	{
	279	int ret;
	280	unsigned int clk_count;
2b7b2df9 MY	281	struct uniphier_fi2c_priv *priv = dev_get_priv(bus);
2b7b2df9 MY	282	struct uniphier_fi2c_regs __iomem *regs = priv->regs;
238bd0b8 MY	283
	284	/* max supported frequency is 400 kHz */
	285	if (speed > 400000)
	286	return -EINVAL;
	287
2b7b2df9	288	ret = uniphier_fi2c_check_bus_busy(priv);
238bd0b8 MY	289	if (ret < 0)
	290	return ret;
	291
	292	/* make sure the bus is idle when changing the frequency */
	293	writel(I2C_BRST_RSCLO, &regs->brst);
	294
2b7b2df9	295	clk_count = priv->fioclk / speed;
238bd0b8 MY	296
	297	writel(clk_count, &regs->cyc);
	298	writel(clk_count / 2, &regs->lctl);
	299	writel(clk_count / 2, &regs->ssut);
	300	writel(clk_count / 16, &regs->dsut);
	301
	302	writel(I2C_BRST_FOEN \| I2C_BRST_RSCLO, &regs->brst);
	303
	304	/*
	305	* Theoretically, each byte can be transferred in
	306	* 1000000 * 9 / speed usec.
	307	* This time out value is long enough.
	308	*/
2b7b2df9	309	priv->timeout = 100000000L / speed;
238bd0b8 MY	310
	311	return 0;
	312	}
	313
	314	static const struct dm_i2c_ops uniphier_fi2c_ops = {
	315	.xfer = uniphier_fi2c_xfer,
	316	.set_bus_speed = uniphier_fi2c_set_bus_speed,
	317	};
	318
	319	static const struct udevice_id uniphier_fi2c_of_match[] = {
6462cded MY	320	{ .compatible = "socionext,uniphier-fi2c" },
6462cded MY	321	{ /* sentinel */ }
238bd0b8 MY	322	};
	323
	324	U_BOOT_DRIVER(uniphier_fi2c) = {
	325	.name = "uniphier-fi2c",
	326	.id = UCLASS_I2C,
	327	.of_match = uniphier_fi2c_of_match,
	328	.probe = uniphier_fi2c_probe,
2b7b2df9	329	.priv_auto_alloc_size = sizeof(struct uniphier_fi2c_priv),
238bd0b8 MY	330	.ops = &uniphier_fi2c_ops,
238bd0b8 MY	331	};