[thirdparty/u-boot.git] / drivers / i2c / ihs_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2013
 * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 */

#include <common.h>
#include <i2c.h>
#ifdef CONFIG_DM_I2C
#include <dm.h>
#include <regmap.h>
#else
#include <gdsys_fpga.h>
#endif
#include <asm/unaligned.h>

#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv {
	uint speed;
	struct regmap *map;
};

struct ihs_i2c_regs {
	u16 interrupt_status;
	u16 interrupt_enable_control;
	u16 write_mailbox_ext;
	u16 write_mailbox;
	u16 read_mailbox_ext;
	u16 read_mailbox;
};

#define ihs_i2c_set(map, member, val) \
	regmap_set(map, struct ihs_i2c_regs, member, val)

#define ihs_i2c_get(map, member, valp) \
	regmap_get(map, struct ihs_i2c_regs, member, valp)

#else /* !CONFIG_DM_I2C */
DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SYS_I2C_IHS_DUAL

#define I2C_SET_REG(fld, val) \
	do { \
		if (I2C_ADAP_HWNR & 0x10) \
			FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
		else \
			FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
	} while (0)
#else
#define I2C_SET_REG(fld, val) \
		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
#endif

#ifdef CONFIG_SYS_I2C_IHS_DUAL
#define I2C_GET_REG(fld, val) \
	do {					\
		if (I2C_ADAP_HWNR & 0x10) \
			FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
		else \
			FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
	} while (0)
#else
#define I2C_GET_REG(fld, val) \
		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
#endif
#endif /* CONFIG_DM_I2C */

enum {
	I2CINT_ERROR_EV = BIT(13),
	I2CINT_TRANSMIT_EV = BIT(14),
	I2CINT_RECEIVE_EV = BIT(15),
};

enum {
	I2CMB_READ = 0 << 10,
	I2CMB_WRITE = 1 << 10,
	I2CMB_1BYTE = 0 << 11,
	I2CMB_2BYTE = 1 << 11,
	I2CMB_DONT_HOLD_BUS = 0 << 13,
	I2CMB_HOLD_BUS = 1 << 13,
	I2CMB_NATIVE = 2 << 14,
};

enum {
	I2COP_WRITE = 0,
	I2COP_READ = 1,
};

#ifdef CONFIG_DM_I2C
static int wait_for_int(struct udevice *dev, int read)
#else
static int wait_for_int(bool read)
#endif
{
	u16 val;
	uint ctr = 0;
#ifdef CONFIG_DM_I2C
	struct ihs_i2c_priv *priv = dev_get_priv(dev);
#endif

#ifdef CONFIG_DM_I2C
	ihs_i2c_get(priv->map, interrupt_status, &val);
#else
	I2C_GET_REG(interrupt_status, &val);
#endif
	/* Wait until error or receive/transmit interrupt was raised */
	while (!(val & (I2CINT_ERROR_EV
	       | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
		udelay(10);
		if (ctr++ > 5000) {
			debug("%s: timed out\n", __func__);
			return -ETIMEDOUT;
		}
#ifdef CONFIG_DM_I2C
		ihs_i2c_get(priv->map, interrupt_status, &val);
#else
		I2C_GET_REG(interrupt_status, &val);
#endif
	}

	return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}

#ifdef CONFIG_DM_I2C
static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
			    uchar *buffer, int len, int read, bool is_last)
#else
static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
			    bool is_last)
#endif
{
	u16 val;
	u16 data;
	int res;
#ifdef CONFIG_DM_I2C
	struct ihs_i2c_priv *priv = dev_get_priv(dev);
#endif

	/* Clear interrupt status */
	data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
#ifdef CONFIG_DM_I2C
	ihs_i2c_set(priv->map, interrupt_status, data);
	ihs_i2c_get(priv->map, interrupt_status, &val);
#else
	I2C_SET_REG(interrupt_status, data);
	I2C_GET_REG(interrupt_status, &val);
#endif

	/* If we want to write and have data, write the bytes to the mailbox */
	if (!read && len) {
		val = buffer[0];

		if (len > 1)
			val |= buffer[1] << 8;
#ifdef CONFIG_DM_I2C
		ihs_i2c_set(priv->map, write_mailbox_ext, val);
#else
		I2C_SET_REG(write_mailbox_ext, val);
#endif
	}

	data = I2CMB_NATIVE
	       | (read ? 0 : I2CMB_WRITE)
	       | (chip << 1)
	       | ((len > 1) ? I2CMB_2BYTE : 0)
	       | (is_last ? 0 : I2CMB_HOLD_BUS);

#ifdef CONFIG_DM_I2C
	ihs_i2c_set(priv->map, write_mailbox, data);
#else
	I2C_SET_REG(write_mailbox, data);
#endif

#ifdef CONFIG_DM_I2C
	res = wait_for_int(dev, read);
#else
	res = wait_for_int(read);
#endif
	if (res) {
		if (res == -ETIMEDOUT)
			debug("%s: time out while waiting for event\n", __func__);

		return res;
	}

	/* If we want to read, get the bytes from the mailbox */
	if (read) {
#ifdef CONFIG_DM_I2C
		ihs_i2c_get(priv->map, read_mailbox_ext, &val);
#else
		I2C_GET_REG(read_mailbox_ext, &val);
#endif
		buffer[0] = val & 0xff;
		if (len > 1)
			buffer[1] = val >> 8;
	}

	return 0;
}

#ifdef CONFIG_DM_I2C
static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
#else
static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
			       int read)
#endif
{
	int res;

	while (len) {
		int transfer = min(len, 2);
		bool is_last = len <= transfer;

#ifdef CONFIG_DM_I2C
		res = ihs_i2c_transfer(dev, chip, data, transfer, read,
				       hold_bus ? false : is_last);
#else
		res = ihs_i2c_transfer(chip, data, transfer, read,
				       hold_bus ? false : is_last);
#endif
		if (res)
			return res;

		data += transfer;
		len -= transfer;
	}

	return 0;
}

#ifdef CONFIG_DM_I2C
static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
			   bool hold_bus)
#else
static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
#endif
{
#ifdef CONFIG_DM_I2C
	return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
#else
	return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
#endif
}

#ifdef CONFIG_DM_I2C
static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
			  int alen, uchar *buffer, int len, int read)
#else
static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
			  int alen, uchar *buffer, int len, int read)
#endif
{
	int res;

	/* Don't hold the bus if length of data to send/receive is zero */
	if (len <= 0)
		return -EINVAL;

#ifdef CONFIG_DM_I2C
	res = ihs_i2c_address(dev, chip, addr, alen, len);
#else
	res = ihs_i2c_address(chip, addr, alen, len);
#endif
	if (res)
		return res;

#ifdef CONFIG_DM_I2C
	return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
#else
	return ihs_i2c_send_buffer(chip, buffer, len, false, read);
#endif
}

#ifdef CONFIG_DM_I2C

int ihs_i2c_probe(struct udevice *bus)
{
	struct ihs_i2c_priv *priv = dev_get_priv(bus);

	regmap_init_mem(dev_ofnode(bus), &priv->map);

	return 0;
}

static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
{
	struct ihs_i2c_priv *priv = dev_get_priv(bus);

	if (speed != priv->speed && priv->speed != 0)
		return -EINVAL;

	priv->speed = speed;

	return 0;
}

static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
	struct i2c_msg *dmsg, *omsg, dummy;

	memset(&dummy, 0, sizeof(struct i2c_msg));

	/* We expect either two messages (one with an offset and one with the
	 * actucal data) or one message (just data)
	 */
	if (nmsgs > 2 || nmsgs == 0) {
		debug("%s: Only one or two messages are supported\n", __func__);
		return -ENOTSUPP;
	}

	omsg = nmsgs == 1 ? &dummy : msg;
	dmsg = nmsgs == 1 ? msg : msg + 1;

	if (dmsg->flags & I2C_M_RD)
		return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
				      omsg->len, dmsg->buf, dmsg->len,
				      I2COP_READ);
	else
		return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
				      omsg->len, dmsg->buf, dmsg->len,
				      I2COP_WRITE);
}

static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
			      u32 chip_flags)
{
	uchar buffer[2];
	int res;

	res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
	if (res)
		return res;

	return 0;
}

static const struct dm_i2c_ops ihs_i2c_ops = {
	.xfer           = ihs_i2c_xfer,
	.probe_chip     = ihs_i2c_probe_chip,
	.set_bus_speed  = ihs_i2c_set_bus_speed,
};

static const struct udevice_id ihs_i2c_ids[] = {
	{ .compatible = "gdsys,ihs_i2cmaster", },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(i2c_ihs) = {
	.name = "i2c_ihs",
	.id = UCLASS_I2C,
	.of_match = ihs_i2c_ids,
	.probe = ihs_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
	.ops = &ihs_i2c_ops,
};

#else /* CONFIG_DM_I2C */

static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
#ifdef CONFIG_SYS_I2C_INIT_BOARD
	/*
	 * Call board specific i2c bus reset routine before accessing the
	 * environment, which might be in a chip on that bus. For details
	 * about this problem see doc/I2C_Edge_Conditions.
	 */
	i2c_init_board();
#endif
}

static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
	uchar buffer[2];
	int res;

	res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
	if (res)
		return res;

	return 0;
}

static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *buffer, int len)
{
	u8 addr_bytes[4];

	put_unaligned_le32(addr, addr_bytes);

	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
			      I2COP_READ);
}

static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
			 int alen, uchar *buffer, int len)
{
	u8 addr_bytes[4];

	put_unaligned_le32(addr, addr_bytes);

	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
			      I2COP_WRITE);
}

static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
					  unsigned int speed)
{
	if (speed != adap->speed)
		return -EINVAL;
	return speed;
}

/*
 * Register IHS i2c adapters
 */
#ifdef CONFIG_SYS_I2C_IHS_CH0
U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_0,
			 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
#ifdef CONFIG_SYS_I2C_IHS_DUAL
U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_0_1,
			 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
#endif
#endif
#ifdef CONFIG_SYS_I2C_IHS_CH1
U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_1,
			 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
#ifdef CONFIG_SYS_I2C_IHS_DUAL
U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_1_1,
			 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
#endif
#endif
#ifdef CONFIG_SYS_I2C_IHS_CH2
U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_2,
			 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
#ifdef CONFIG_SYS_I2C_IHS_DUAL
U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_2_1,
			 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
#endif
#endif
#ifdef CONFIG_SYS_I2C_IHS_CH3
U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_3,
			 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
#ifdef CONFIG_SYS_I2C_IHS_DUAL
U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
			 ihs_i2c_read, ihs_i2c_write,
			 ihs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_IHS_SPEED_3_1,
			 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
#endif
#endif
#endif /* CONFIG_DM_I2C */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b46226bd DE	2	/*
b46226bd DE	3	* (C) Copyright 2013
d38826a3	4	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
b46226bd DE	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
92164216 MS	9	#ifdef CONFIG_DM_I2C
92164216 MS	10	#include <dm.h>
98e4249f	11	#include <regmap.h>
92164216	12	#else
b46226bd	13	#include <gdsys_fpga.h>
92164216	14	#endif
64ef094b	15	#include <asm/unaligned.h>
b46226bd	16
92164216 MS	17	#ifdef CONFIG_DM_I2C
	18	struct ihs_i2c_priv {
	19	uint speed;
98e4249f	20	struct regmap *map;
92164216 MS	21	};
92164216 MS	22
98e4249f MS	23	struct ihs_i2c_regs {
	24	u16 interrupt_status;
	25	u16 interrupt_enable_control;
	26	u16 write_mailbox_ext;
	27	u16 write_mailbox;
	28	u16 read_mailbox_ext;
	29	u16 read_mailbox;
92164216 MS	30	};
92164216 MS	31
98e4249f MS	32	#define ihs_i2c_set(map, member, val) \
	33	regmap_set(map, struct ihs_i2c_regs, member, val)
	34
	35	#define ihs_i2c_get(map, member, valp) \
	36	regmap_get(map, struct ihs_i2c_regs, member, valp)
	37
92164216	38	#else /* !CONFIG_DM_I2C */
b46226bd DE	39	DECLARE_GLOBAL_DATA_PTR;
b46226bd DE	40
071be896	41	#ifdef CONFIG_SYS_I2C_IHS_DUAL
92164216	42
071be896	43	#define I2C_SET_REG(fld, val) \
3af0cdb1 DE	44	do { \
	45	if (I2C_ADAP_HWNR & 0x10) \
	46	FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
	47	else \
	48	FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
	49	} while (0)
071be896 DE	50	#else
071be896 DE	51	#define I2C_SET_REG(fld, val) \
3af0cdb1	52	FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
071be896 DE	53	#endif
	54
	55	#ifdef CONFIG_SYS_I2C_IHS_DUAL
	56	#define I2C_GET_REG(fld, val) \
3af0cdb1 DE	57	do { \
	58	if (I2C_ADAP_HWNR & 0x10) \
	59	FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
	60	else \
	61	FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
	62	} while (0)
071be896 DE	63	#else
071be896 DE	64	#define I2C_GET_REG(fld, val) \
3af0cdb1	65	FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
071be896	66	#endif
92164216	67	#endif /* CONFIG_DM_I2C */
071be896	68
b46226bd	69	enum {
64ef094b MS	70	I2CINT_ERROR_EV = BIT(13),
	71	I2CINT_TRANSMIT_EV = BIT(14),
	72	I2CINT_RECEIVE_EV = BIT(15),
b46226bd DE	73	};
	74
	75	enum {
64ef094b	76	I2CMB_READ = 0 << 10,
b46226bd	77	I2CMB_WRITE = 1 << 10,
64ef094b	78	I2CMB_1BYTE = 0 << 11,
b46226bd	79	I2CMB_2BYTE = 1 << 11,
64ef094b	80	I2CMB_DONT_HOLD_BUS = 0 << 13,
b46226bd DE	81	I2CMB_HOLD_BUS = 1 << 13,
	82	I2CMB_NATIVE = 2 << 14,
	83	};
	84
64ef094b MS	85	enum {
	86	I2COP_WRITE = 0,
	87	I2COP_READ = 1,
	88	};
	89
92164216 MS	90	#ifdef CONFIG_DM_I2C
	91	static int wait_for_int(struct udevice *dev, int read)
	92	#else
b46226bd	93	static int wait_for_int(bool read)
92164216	94	#endif
b46226bd DE	95	{
b46226bd DE	96	u16 val;
64ef094b	97	uint ctr = 0;
92164216 MS	98	#ifdef CONFIG_DM_I2C
92164216 MS	99	struct ihs_i2c_priv *priv = dev_get_priv(dev);
92164216 MS	100	#endif
	101
	102	#ifdef CONFIG_DM_I2C
98e4249f	103	ihs_i2c_get(priv->map, interrupt_status, &val);
92164216	104	#else
071be896	105	I2C_GET_REG(interrupt_status, &val);
92164216	106	#endif
64ef094b	107	/* Wait until error or receive/transmit interrupt was raised */
b46226bd DE	108	while (!(val & (I2CINT_ERROR_EV
	109	\| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
	110	udelay(10);
482c76e7 MS	111	if (ctr++ > 5000) {
	112	debug("%s: timed out\n", __func__);
	113	return -ETIMEDOUT;
	114	}
92164216	115	#ifdef CONFIG_DM_I2C
98e4249f	116	ihs_i2c_get(priv->map, interrupt_status, &val);
92164216	117	#else
071be896	118	I2C_GET_REG(interrupt_status, &val);
92164216	119	#endif
b46226bd DE	120	}
b46226bd DE	121
482c76e7	122	return (val & I2CINT_ERROR_EV) ? -EIO : 0;
b46226bd DE	123	}
b46226bd DE	124
92164216 MS	125	#ifdef CONFIG_DM_I2C
	126	static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
	127	uchar *buffer, int len, int read, bool is_last)
	128	#else
b46226bd DE	129	static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
b46226bd DE	130	bool is_last)
92164216	131	#endif
b46226bd DE	132	{
b46226bd DE	133	u16 val;
2df71d6d	134	u16 data;
482c76e7	135	int res;
92164216 MS	136	#ifdef CONFIG_DM_I2C
92164216 MS	137	struct ihs_i2c_priv *priv = dev_get_priv(dev);
92164216	138	#endif
b46226bd	139
64ef094b	140	/* Clear interrupt status */
2df71d6d	141	data = I2CINT_ERROR_EV \| I2CINT_RECEIVE_EV \| I2CINT_TRANSMIT_EV;
92164216	142	#ifdef CONFIG_DM_I2C
98e4249f MS	143	ihs_i2c_set(priv->map, interrupt_status, data);
98e4249f MS	144	ihs_i2c_get(priv->map, interrupt_status, &val);
92164216	145	#else
2df71d6d	146	I2C_SET_REG(interrupt_status, data);
071be896	147	I2C_GET_REG(interrupt_status, &val);
92164216	148	#endif
b46226bd	149
64ef094b	150	/* If we want to write and have data, write the bytes to the mailbox */
b46226bd DE	151	if (!read && len) {
	152	val = buffer[0];
	153
	154	if (len > 1)
	155	val \|= buffer[1] << 8;
92164216	156	#ifdef CONFIG_DM_I2C
98e4249f	157	ihs_i2c_set(priv->map, write_mailbox_ext, val);
92164216	158	#else
071be896	159	I2C_SET_REG(write_mailbox_ext, val);
92164216	160	#endif
b46226bd DE	161	}
b46226bd DE	162
2df71d6d MS	163	data = I2CMB_NATIVE
	164	\| (read ? 0 : I2CMB_WRITE)
	165	\| (chip << 1)
	166	\| ((len > 1) ? I2CMB_2BYTE : 0)
	167	\| (is_last ? 0 : I2CMB_HOLD_BUS);
	168
92164216	169	#ifdef CONFIG_DM_I2C
98e4249f	170	ihs_i2c_set(priv->map, write_mailbox, data);
92164216	171	#else
2df71d6d	172	I2C_SET_REG(write_mailbox, data);
92164216	173	#endif
b46226bd	174
92164216	175	#ifdef CONFIG_DM_I2C
482c76e7	176	res = wait_for_int(dev, read);
92164216	177	#else
482c76e7	178	res = wait_for_int(read);
92164216	179	#endif
482c76e7 MS	180	if (res) {
	181	if (res == -ETIMEDOUT)
	182	debug("%s: time out while waiting for event\n", __func__);
	183
	184	return res;
	185	}
b46226bd	186
64ef094b	187	/* If we want to read, get the bytes from the mailbox */
b46226bd	188	if (read) {
92164216	189	#ifdef CONFIG_DM_I2C
98e4249f	190	ihs_i2c_get(priv->map, read_mailbox_ext, &val);
92164216	191	#else
071be896	192	I2C_GET_REG(read_mailbox_ext, &val);
92164216	193	#endif
b46226bd DE	194	buffer[0] = val & 0xff;
	195	if (len > 1)
	196	buffer[1] = val >> 8;
	197	}
	198
	199	return 0;
	200	}
	201
92164216	202	#ifdef CONFIG_DM_I2C
9cef983d	203	static int ihs_i2c_send_buffer(struct udevice dev, uchar chip, u8 data, int len, bool hold_bus, int read)
92164216	204	#else
9cef983d MS	205	static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
9cef983d MS	206	int read)
92164216	207	#endif
b46226bd	208	{
482c76e7 MS	209	int res;
482c76e7 MS	210
9cef983d MS	211	while (len) {
	212	int transfer = min(len, 2);
	213	bool is_last = len <= transfer;
b46226bd	214
92164216	215	#ifdef CONFIG_DM_I2C
482c76e7 MS	216	res = ihs_i2c_transfer(dev, chip, data, transfer, read,
482c76e7 MS	217	hold_bus ? false : is_last);
92164216	218	#else
482c76e7 MS	219	res = ihs_i2c_transfer(chip, data, transfer, read,
482c76e7 MS	220	hold_bus ? false : is_last);
92164216	221	#endif
482c76e7 MS	222	if (res)
482c76e7 MS	223	return res;
b46226bd	224
9cef983d MS	225	data += transfer;
9cef983d MS	226	len -= transfer;
b46226bd DE	227	}
	228
	229	return 0;
	230	}
	231
9cef983d MS	232	#ifdef CONFIG_DM_I2C
	233	static int ihs_i2c_address(struct udevice dev, uchar chip, u8 addr, int alen,
	234	bool hold_bus)
	235	#else
	236	static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
	237	#endif
	238	{
	239	#ifdef CONFIG_DM_I2C
	240	return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
	241	#else
	242	return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
	243	#endif
	244	}
	245
92164216 MS	246	#ifdef CONFIG_DM_I2C
	247	static int ihs_i2c_access(struct udevice dev, uchar chip, u8 addr,
	248	int alen, uchar *buffer, int len, int read)
	249	#else
64ef094b MS	250	static int ihs_i2c_access(struct i2c_adapter adap, uchar chip, u8 addr,
64ef094b MS	251	int alen, uchar *buffer, int len, int read)
92164216	252	#endif
b46226bd	253	{
482c76e7 MS	254	int res;
482c76e7 MS	255
64ef094b	256	/* Don't hold the bus if length of data to send/receive is zero */
482c76e7 MS	257	if (len <= 0)
	258	return -EINVAL;
	259
92164216	260	#ifdef CONFIG_DM_I2C
482c76e7	261	res = ihs_i2c_address(dev, chip, addr, alen, len);
92164216	262	#else
482c76e7	263	res = ihs_i2c_address(chip, addr, alen, len);
92164216	264	#endif
482c76e7 MS	265	if (res)
482c76e7 MS	266	return res;
b46226bd	267
92164216	268	#ifdef CONFIG_DM_I2C
9cef983d	269	return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
92164216	270	#else
9cef983d	271	return ihs_i2c_send_buffer(chip, buffer, len, false, read);
92164216	272	#endif
b46226bd DE	273	}
b46226bd DE	274
92164216 MS	275	#ifdef CONFIG_DM_I2C
	276
	277	int ihs_i2c_probe(struct udevice *bus)
	278	{
	279	struct ihs_i2c_priv *priv = dev_get_priv(bus);
92164216	280
98e4249f	281	regmap_init_mem(dev_ofnode(bus), &priv->map);
92164216 MS	282
	283	return 0;
	284	}
	285
	286	static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
	287	{
	288	struct ihs_i2c_priv *priv = dev_get_priv(bus);
	289
	290	if (speed != priv->speed && priv->speed != 0)
482c76e7	291	return -EINVAL;
92164216 MS	292
	293	priv->speed = speed;
	294
	295	return 0;
	296	}
	297
	298	static int ihs_i2c_xfer(struct udevice bus, struct i2c_msg msg, int nmsgs)
	299	{
	300	struct i2c_msg dmsg, omsg, dummy;
	301
	302	memset(&dummy, 0, sizeof(struct i2c_msg));
	303
	304	/* We expect either two messages (one with an offset and one with the
	305	* actucal data) or one message (just data)
	306	*/
	307	if (nmsgs > 2 \|\| nmsgs == 0) {
482c76e7 MS	308	debug("%s: Only one or two messages are supported\n", __func__);
482c76e7 MS	309	return -ENOTSUPP;
92164216 MS	310	}
	311
	312	omsg = nmsgs == 1 ? &dummy : msg;
	313	dmsg = nmsgs == 1 ? msg : msg + 1;
	314
	315	if (dmsg->flags & I2C_M_RD)
	316	return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
	317	omsg->len, dmsg->buf, dmsg->len,
	318	I2COP_READ);
	319	else
	320	return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
	321	omsg->len, dmsg->buf, dmsg->len,
	322	I2COP_WRITE);
	323	}
	324
	325	static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
	326	u32 chip_flags)
	327	{
	328	uchar buffer[2];
482c76e7	329	int res;
92164216	330
482c76e7 MS	331	res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
	332	if (res)
	333	return res;
92164216 MS	334
	335	return 0;
	336	}
	337
	338	static const struct dm_i2c_ops ihs_i2c_ops = {
	339	.xfer = ihs_i2c_xfer,
	340	.probe_chip = ihs_i2c_probe_chip,
	341	.set_bus_speed = ihs_i2c_set_bus_speed,
	342	};
	343
	344	static const struct udevice_id ihs_i2c_ids[] = {
	345	{ .compatible = "gdsys,ihs_i2cmaster", },
	346	{ /* sentinel */ }
	347	};
	348
	349	U_BOOT_DRIVER(i2c_ihs) = {
	350	.name = "i2c_ihs",
	351	.id = UCLASS_I2C,
	352	.of_match = ihs_i2c_ids,
	353	.probe = ihs_i2c_probe,
	354	.priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
	355	.ops = &ihs_i2c_ops,
	356	};
	357
	358	#else /* CONFIG_DM_I2C */
	359
b46226bd DE	360	static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
	361	{
	362	#ifdef CONFIG_SYS_I2C_INIT_BOARD
	363	/*
	364	* Call board specific i2c bus reset routine before accessing the
	365	* environment, which might be in a chip on that bus. For details
	366	* about this problem see doc/I2C_Edge_Conditions.
	367	*/
	368	i2c_init_board();
	369	#endif
	370	}
	371
	372	static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
	373	{
	374	uchar buffer[2];
482c76e7	375	int res;
b46226bd	376
482c76e7 MS	377	res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
	378	if (res)
	379	return res;
b46226bd DE	380
	381	return 0;
	382	}
	383
	384	static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
	385	int alen, uchar *buffer, int len)
	386	{
64ef094b MS	387	u8 addr_bytes[4];
	388
	389	put_unaligned_le32(addr, addr_bytes);
	390
	391	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
	392	I2COP_READ);
b46226bd DE	393	}
	394
	395	static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
	396	int alen, uchar *buffer, int len)
	397	{
64ef094b MS	398	u8 addr_bytes[4];
	399
	400	put_unaligned_le32(addr, addr_bytes);
	401
	402	return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
	403	I2COP_WRITE);
b46226bd DE	404	}
	405
	406	static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
071be896	407	unsigned int speed)
b46226bd DE	408	{
b46226bd DE	409	if (speed != adap->speed)
482c76e7	410	return -EINVAL;
b46226bd DE	411	return speed;
	412	}
	413
	414	/*
	415	* Register IHS i2c adapters
	416	*/
	417	#ifdef CONFIG_SYS_I2C_IHS_CH0
	418	U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
	419	ihs_i2c_read, ihs_i2c_write,
	420	ihs_i2c_set_bus_speed,
	421	CONFIG_SYS_I2C_IHS_SPEED_0,
	422	CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
071be896 DE	423	#ifdef CONFIG_SYS_I2C_IHS_DUAL
	424	U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
	425	ihs_i2c_read, ihs_i2c_write,
	426	ihs_i2c_set_bus_speed,
	427	CONFIG_SYS_I2C_IHS_SPEED_0_1,
	428	CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
	429	#endif
b46226bd DE	430	#endif
	431	#ifdef CONFIG_SYS_I2C_IHS_CH1
	432	U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
	433	ihs_i2c_read, ihs_i2c_write,
	434	ihs_i2c_set_bus_speed,
	435	CONFIG_SYS_I2C_IHS_SPEED_1,
	436	CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
071be896 DE	437	#ifdef CONFIG_SYS_I2C_IHS_DUAL
	438	U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
	439	ihs_i2c_read, ihs_i2c_write,
	440	ihs_i2c_set_bus_speed,
	441	CONFIG_SYS_I2C_IHS_SPEED_1_1,
	442	CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
	443	#endif
b46226bd DE	444	#endif
	445	#ifdef CONFIG_SYS_I2C_IHS_CH2
	446	U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
	447	ihs_i2c_read, ihs_i2c_write,
	448	ihs_i2c_set_bus_speed,
	449	CONFIG_SYS_I2C_IHS_SPEED_2,
	450	CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
071be896 DE	451	#ifdef CONFIG_SYS_I2C_IHS_DUAL
	452	U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
	453	ihs_i2c_read, ihs_i2c_write,
	454	ihs_i2c_set_bus_speed,
	455	CONFIG_SYS_I2C_IHS_SPEED_2_1,
	456	CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
	457	#endif
b46226bd DE	458	#endif
	459	#ifdef CONFIG_SYS_I2C_IHS_CH3
	460	U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
	461	ihs_i2c_read, ihs_i2c_write,
	462	ihs_i2c_set_bus_speed,
	463	CONFIG_SYS_I2C_IHS_SPEED_3,
	464	CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
071be896 DE	465	#ifdef CONFIG_SYS_I2C_IHS_DUAL
	466	U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
	467	ihs_i2c_read, ihs_i2c_write,
	468	ihs_i2c_set_bus_speed,
	469	CONFIG_SYS_I2C_IHS_SPEED_3_1,
	470	CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
	471	#endif
b46226bd	472	#endif
92164216	473	#endif /* CONFIG_DM_I2C */