[people/ms/u-boot.git] / drivers / i2c / lpc32xx_i2c.c

/*
 * LPC32xx I2C interface driver
 *
 * (C) Copyright 2014-2015  DENX Software Engineering GmbH
 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <i2c.h>
#include <linux/errno.h>
#include <asm/arch/clk.h>
#include <asm/arch/i2c.h>
#include <dm.h>
#include <mapmem.h>

/*
 * Provide default speed and slave if target did not
 */

#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
#endif

#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
#endif

/* TX register fields */
#define LPC32XX_I2C_TX_START		0x00000100
#define LPC32XX_I2C_TX_STOP		0x00000200

/* Control register values */
#define LPC32XX_I2C_SOFT_RESET		0x00000100

/* Status register values */
#define LPC32XX_I2C_STAT_TFF		0x00000400
#define LPC32XX_I2C_STAT_RFE		0x00000200
#define LPC32XX_I2C_STAT_DRMI		0x00000008
#define LPC32XX_I2C_STAT_NAI		0x00000004
#define LPC32XX_I2C_STAT_TDI		0x00000001

#ifndef CONFIG_DM_I2C
static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
	(struct lpc32xx_i2c_base *)I2C1_BASE,
	(struct lpc32xx_i2c_base *)I2C2_BASE,
	(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
};
#endif

/* Set I2C bus speed */
static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
					unsigned int speed, unsigned int chip)
{
	int half_period;

	if (speed == 0)
		return -EINVAL;

	/* OTG I2C clock source and CLK registers are different */
	if (chip == 2) {
		half_period = (get_periph_clk_rate() / speed) / 2;
		if (half_period > 0xFF)
			return -EINVAL;
	} else {
		half_period = (get_hclk_clk_rate() / speed) / 2;
		if (half_period > 0x3FF)
			return -EINVAL;
	}

	writel(half_period, &base->clk_hi);
	writel(half_period, &base->clk_lo);
	return 0;
}

/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void __i2c_init(struct lpc32xx_i2c_base *base,
		       int requested_speed, int slaveadd, unsigned int chip)
{
	/* soft reset (auto-clears) */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	/* set HI and LO periods for half of the default speed */
	__i2c_set_bus_speed(base, requested_speed, chip);
}

/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
{
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* Addre slave for write with start before and stop after */
	writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
	       &base->tx);
	/* wait for end of transation */
	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* was there no acknowledge? */
	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 */
static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
		      int alen, u8 *data, int length)
{
	int stat, wlen;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write an address at all? */
	if (alen) {
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
		/* write address bytes */
		while (alen--) {
			/* compute address byte + stop for the last one */
			int a = (addr >> (8 * alen)) & 0xff;
			if (!alen)
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &base->tx);
		}
		/* wait for end of transation */
		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &base->stat);
	}
	/* do we have to read data at all? */
	if (length) {
		/* Address slave in read mode */
		writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
		wlen = length;
		/* get data */
		while (length | wlen) {
			/* read status for TFF and RFE */
			stat = readl(&base->stat);
			/* must we, can we write a trigger byte? */
			if ((wlen > 0)
			   & (!(stat & LPC32XX_I2C_STAT_TFF))) {
				wlen--;
				/* write trigger byte + stop if last */
				writel(wlen ? 0 :
				LPC32XX_I2C_TX_STOP, &base->tx);
			}
			/* must we, can we read a data byte? */
			if ((length > 0)
			   & (!(stat & LPC32XX_I2C_STAT_RFE))) {
				length--;
				/* read byte */
				*(data++) = readl(&base->rx);
			}
		}
		/* wait for end of transation */
		while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
			;
		/* clear end-of-transaction flag */
		writel(1, &base->stat);
	}
	/* success */
	return 0;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
		       int alen, u8 *data, int length)
{
	int stat;

	/* Soft-reset the controller */
	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
		;
	/* do we need to write anything at all? */
	if (alen | length)
		/* Address slave in write mode */
		writel((dev<<1) | LPC32XX_I2C_TX_START, &base->tx);
	else
		return 0;
	/* write address bytes */
	while (alen) {
		/* wait for transmit fifo not full */
		stat = readl(&base->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			alen--;
			int a = (addr >> (8 * alen)) & 0xff;
			if (!(alen | length))
				a |= LPC32XX_I2C_TX_STOP;
			/* Send address byte */
			writel(a, &base->tx);
		}
	}
	while (length) {
		/* wait for transmit fifo not full */
		stat = readl(&base->stat);
		if (!(stat & LPC32XX_I2C_STAT_TFF)) {
			/* compute data byte, add stop if length==0 */
			length--;
			int d = *(data++);
			if (!length)
				d |= LPC32XX_I2C_TX_STOP;
			/* Send data byte */
			writel(d, &base->tx);
		}
	}
	/* wait for end of transation */
	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
		;
	/* clear end-of-transaction flag */
	writel(1, &base->stat);
	return 0;
}

#ifndef CONFIG_DM_I2C
static void lpc32xx_i2c_init(struct i2c_adapter *adap,
			     int requested_speed, int slaveadd)
{
	__i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
		   adap->hwadapnr);
}

static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
{
	return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
}

static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
			    int alen, u8 *data, int length)
{
	return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
			 alen, data, length);
}

static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			     int alen, u8 *data, int length)
{
	return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
			  alen, data, length);
}

static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
					      unsigned int speed)
{
	return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
				  adap->hwadapnr);
}

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_LPC32XX_SPEED,
			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
			 0)

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_LPC32XX_SPEED,
			 CONFIG_SYS_I2C_LPC32XX_SLAVE,
			 1)

U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
			 lpc32xx_i2c_read, lpc32xx_i2c_write,
			 lpc32xx_i2c_set_bus_speed,
			 100000,
			 0,
			 2)
#else /* CONFIG_DM_I2C */
static int lpc32xx_i2c_probe(struct udevice *bus)
{
	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	bus->seq = dev->index;

	__i2c_init(dev->base, dev->speed, 0, dev->index);
	return 0;
}

static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
				  u32 chip_flags)
{
	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	return __i2c_probe_chip(dev->base, chip_addr);
}

static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
		int nmsgs)
{
	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	struct i2c_msg *dmsg, *omsg, dummy;
	uint i = 0, address = 0;

	memset(&dummy, 0, sizeof(struct i2c_msg));

	/* We expect either two messages (one with an offset and one with the
	 * actual data) or one message (just data)
	 */
	if (nmsgs > 2 || nmsgs == 0) {
		debug("%s: Only one or two messages are supported.", __func__);
		return -1;
	}

	omsg = nmsgs == 1 ? &dummy : msg;
	dmsg = nmsgs == 1 ? msg : msg + 1;

	/* the address is expected to be a uint, not a array. */
	address = omsg->buf[0];
	for (i = 1; i < omsg->len; i++)
		address = (address << 8) + omsg->buf[i];

	if (dmsg->flags & I2C_M_RD)
		return __i2c_read(dev->base, dmsg->addr, address,
				  omsg->len, dmsg->buf, dmsg->len);
	else
		return __i2c_write(dev->base, dmsg->addr, address,
				   omsg->len, dmsg->buf, dmsg->len);
}

static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	return __i2c_set_bus_speed(dev->base, speed, dev->index);
}

static int lpc32xx_i2c_reset(struct udevice *bus)
{
	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);

	__i2c_init(dev->base, dev->speed, 0, dev->index);
	return 0;
}

static const struct dm_i2c_ops lpc32xx_i2c_ops = {
	.xfer          = lpc32xx_i2c_xfer,
	.probe_chip    = lpc32xx_i2c_probe_chip,
	.deblock       = lpc32xx_i2c_reset,
	.set_bus_speed = lpc32xx_i2c_set_bus_speed,
};

U_BOOT_DRIVER(i2c_lpc32xx) = {
	.id                   = UCLASS_I2C,
	.name                 = "i2c_lpc32xx",
	.probe                = lpc32xx_i2c_probe,
	.ops                  = &lpc32xx_i2c_ops,
};
#endif /* CONFIG_DM_I2C */
Commit	Line	Data
5e862b95 AA	1	/*
	2	* LPC32xx I2C interface driver
	3	*
1933af15	4	* (C) Copyright 2014-2015 DENX Software Engineering GmbH
5e862b95 AA	5	* Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <asm/io.h>
	12	#include <i2c.h>
1221ce45	13	#include <linux/errno.h>
5e862b95	14	#include <asm/arch/clk.h>
fb057880	15	#include <asm/arch/i2c.h>
d61c7adb LB	16	#include <dm.h>
d61c7adb LB	17	#include <mapmem.h>
5e862b95 AA	18
	19	/*
	20	* Provide default speed and slave if target did not
	21	*/
	22
	23	#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
	24	#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
	25	#endif
	26
	27	#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
	28	#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
	29	#endif
	30
5e862b95 AA	31	/* TX register fields */
	32	#define LPC32XX_I2C_TX_START 0x00000100
	33	#define LPC32XX_I2C_TX_STOP 0x00000200
	34
	35	/* Control register values */
	36	#define LPC32XX_I2C_SOFT_RESET 0x00000100
	37
	38	/* Status register values */
	39	#define LPC32XX_I2C_STAT_TFF 0x00000400
	40	#define LPC32XX_I2C_STAT_RFE 0x00000200
	41	#define LPC32XX_I2C_STAT_DRMI 0x00000008
	42	#define LPC32XX_I2C_STAT_NAI 0x00000004
	43	#define LPC32XX_I2C_STAT_TDI 0x00000001
	44
d61c7adb	45	#ifndef CONFIG_DM_I2C
eddac8e9 LB	46	static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
	47	(struct lpc32xx_i2c_base *)I2C1_BASE,
	48	(struct lpc32xx_i2c_base *)I2C2_BASE,
	49	(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
5e862b95	50	};
d61c7adb	51	#endif
5e862b95 AA	52
5e862b95 AA	53	/* Set I2C bus speed */
eddac8e9 LB	54	static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
eddac8e9 LB	55	unsigned int speed, unsigned int chip)
5e862b95 AA	56	{
	57	int half_period;
	58
	59	if (speed == 0)
	60	return -EINVAL;
	61
ea16c6a1	62	/* OTG I2C clock source and CLK registers are different */
eddac8e9	63	if (chip == 2) {
ea16c6a1 VZ	64	half_period = (get_periph_clk_rate() / speed) / 2;
	65	if (half_period > 0xFF)
	66	return -EINVAL;
	67	} else {
	68	half_period = (get_hclk_clk_rate() / speed) / 2;
	69	if (half_period > 0x3FF)
	70	return -EINVAL;
	71	}
5e862b95	72
eddac8e9 LB	73	writel(half_period, &base->clk_hi);
eddac8e9 LB	74	writel(half_period, &base->clk_lo);
5e862b95 AA	75	return 0;
	76	}
	77
	78	/* I2C init called by cmd_i2c when doing 'i2c reset'. */
eddac8e9 LB	79	static void __i2c_init(struct lpc32xx_i2c_base *base,
eddac8e9 LB	80	int requested_speed, int slaveadd, unsigned int chip)
5e862b95	81	{
5e862b95	82	/* soft reset (auto-clears) */
eddac8e9	83	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
ea16c6a1	84	/* set HI and LO periods for half of the default speed */
eddac8e9	85	__i2c_set_bus_speed(base, requested_speed, chip);
5e862b95 AA	86	}
	87
	88	/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
eddac8e9	89	static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev)
5e862b95	90	{
5e862b95 AA	91	int stat;
	92
	93	/* Soft-reset the controller */
eddac8e9 LB	94	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	95	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	96	;
	97	/* Addre slave for write with start before and stop after */
	98	writel((dev<<1) \| LPC32XX_I2C_TX_START \| LPC32XX_I2C_TX_STOP,
eddac8e9	99	&base->tx);
5e862b95	100	/* wait for end of transation */
eddac8e9	101	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	102	;
	103	/* was there no acknowledge? */
	104	return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
	105	}
	106
	107	/*
	108	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	109	* Begin write, send address byte(s), begin read, receive data bytes, end.
	110	*/
eddac8e9 LB	111	static int __i2c_read(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
eddac8e9 LB	112	int alen, u8 *data, int length)
5e862b95	113	{
5e862b95 AA	114	int stat, wlen;
	115
	116	/* Soft-reset the controller */
eddac8e9 LB	117	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	118	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	119	;
	120	/* do we need to write an address at all? */
	121	if (alen) {
	122	/* Address slave in write mode */
eddac8e9	123	writel((dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
5e862b95 AA	124	/* write address bytes */
	125	while (alen--) {
	126	/* compute address byte + stop for the last one */
	127	int a = (addr >> (8 * alen)) & 0xff;
	128	if (!alen)
	129	a \|= LPC32XX_I2C_TX_STOP;
	130	/* Send address byte */
eddac8e9	131	writel(a, &base->tx);
5e862b95 AA	132	}
5e862b95 AA	133	/* wait for end of transation */
eddac8e9	134	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	135	;
5e862b95 AA	136	/* clear end-of-transaction flag */
eddac8e9	137	writel(1, &base->stat);
5e862b95 AA	138	}
	139	/* do we have to read data at all? */
	140	if (length) {
	141	/* Address slave in read mode */
eddac8e9	142	writel(1 \| (dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
5e862b95 AA	143	wlen = length;
	144	/* get data */
	145	while (length \| wlen) {
	146	/* read status for TFF and RFE */
eddac8e9	147	stat = readl(&base->stat);
5e862b95 AA	148	/* must we, can we write a trigger byte? */
	149	if ((wlen > 0)
	150	& (!(stat & LPC32XX_I2C_STAT_TFF))) {
	151	wlen--;
	152	/* write trigger byte + stop if last */
	153	writel(wlen ? 0 :
eddac8e9	154	LPC32XX_I2C_TX_STOP, &base->tx);
5e862b95 AA	155	}
	156	/* must we, can we read a data byte? */
	157	if ((length > 0)
	158	& (!(stat & LPC32XX_I2C_STAT_RFE))) {
	159	length--;
	160	/* read byte */
eddac8e9	161	*(data++) = readl(&base->rx);
5e862b95 AA	162	}
5e862b95 AA	163	}
3d2b6a2e	164	/* wait for end of transation */
eddac8e9	165	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
3d2b6a2e SL	166	;
3d2b6a2e SL	167	/* clear end-of-transaction flag */
eddac8e9	168	writel(1, &base->stat);
5e862b95	169	}
5e862b95 AA	170	/* success */
	171	return 0;
	172	}
	173
	174	/*
	175	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	176	* Begin write, send address byte(s), send data bytes, end.
	177	*/
eddac8e9 LB	178	static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
eddac8e9 LB	179	int alen, u8 *data, int length)
5e862b95	180	{
5e862b95 AA	181	int stat;
	182
	183	/* Soft-reset the controller */
eddac8e9 LB	184	writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl);
eddac8e9 LB	185	while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET)
5e862b95 AA	186	;
	187	/* do we need to write anything at all? */
	188	if (alen \| length)
	189	/* Address slave in write mode */
eddac8e9	190	writel((dev<<1) \| LPC32XX_I2C_TX_START, &base->tx);
58243001 SL	191	else
58243001 SL	192	return 0;
5e862b95 AA	193	/* write address bytes */
	194	while (alen) {
	195	/* wait for transmit fifo not full */
eddac8e9	196	stat = readl(&base->stat);
5e862b95 AA	197	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	198	alen--;
	199	int a = (addr >> (8 * alen)) & 0xff;
	200	if (!(alen \| length))
	201	a \|= LPC32XX_I2C_TX_STOP;
	202	/* Send address byte */
eddac8e9	203	writel(a, &base->tx);
5e862b95 AA	204	}
	205	}
	206	while (length) {
	207	/* wait for transmit fifo not full */
eddac8e9	208	stat = readl(&base->stat);
5e862b95 AA	209	if (!(stat & LPC32XX_I2C_STAT_TFF)) {
	210	/* compute data byte, add stop if length==0 */
	211	length--;
	212	int d = *(data++);
	213	if (!length)
	214	d \|= LPC32XX_I2C_TX_STOP;
	215	/* Send data byte */
eddac8e9	216	writel(d, &base->tx);
5e862b95 AA	217	}
	218	}
	219	/* wait for end of transation */
eddac8e9	220	while (!((stat = readl(&base->stat)) & LPC32XX_I2C_STAT_TDI))
5e862b95 AA	221	;
5e862b95 AA	222	/* clear end-of-transaction flag */
eddac8e9	223	writel(1, &base->stat);
5e862b95 AA	224	return 0;
	225	}
	226
d61c7adb	227	#ifndef CONFIG_DM_I2C
552531e4 LB	228	static void lpc32xx_i2c_init(struct i2c_adapter *adap,
	229	int requested_speed, int slaveadd)
	230	{
eddac8e9 LB	231	__i2c_init(lpc32xx_i2c[adap->hwadapnr], requested_speed, slaveadd,
eddac8e9 LB	232	adap->hwadapnr);
552531e4 LB	233	}
	234
	235	static int lpc32xx_i2c_probe_chip(struct i2c_adapter *adap, u8 dev)
	236	{
eddac8e9	237	return __i2c_probe_chip(lpc32xx_i2c[adap->hwadapnr], dev);
552531e4 LB	238	}
	239
	240	static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	241	int alen, u8 *data, int length)
	242	{
eddac8e9 LB	243	return __i2c_read(lpc32xx_i2c[adap->hwadapnr], dev, addr,
eddac8e9 LB	244	alen, data, length);
552531e4 LB	245	}
	246
	247	static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	248	int alen, u8 *data, int length)
	249	{
eddac8e9 LB	250	return __i2c_write(lpc32xx_i2c[adap->hwadapnr], dev, addr,
eddac8e9 LB	251	alen, data, length);
552531e4 LB	252	}
	253
	254	static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
	255	unsigned int speed)
	256	{
eddac8e9 LB	257	return __i2c_set_bus_speed(lpc32xx_i2c[adap->hwadapnr], speed,
eddac8e9 LB	258	adap->hwadapnr);
552531e4 LB	259	}
	260
	261	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
5e862b95 AA	262	lpc32xx_i2c_read, lpc32xx_i2c_write,
	263	lpc32xx_i2c_set_bus_speed,
	264	CONFIG_SYS_I2C_LPC32XX_SPEED,
	265	CONFIG_SYS_I2C_LPC32XX_SLAVE,
	266	0)
	267
552531e4	268	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
5e862b95 AA	269	lpc32xx_i2c_read, lpc32xx_i2c_write,
	270	lpc32xx_i2c_set_bus_speed,
	271	CONFIG_SYS_I2C_LPC32XX_SPEED,
	272	CONFIG_SYS_I2C_LPC32XX_SLAVE,
	273	1)
1933af15	274
552531e4	275	U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
1933af15 SL	276	lpc32xx_i2c_read, lpc32xx_i2c_write,
	277	lpc32xx_i2c_set_bus_speed,
	278	100000,
	279	0,
	280	2)
d61c7adb LB	281	#else /* CONFIG_DM_I2C */
	282	static int lpc32xx_i2c_probe(struct udevice *bus)
	283	{
	284	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
0f5b461b	285	bus->seq = dev->index;
d61c7adb LB	286
	287	__i2c_init(dev->base, dev->speed, 0, dev->index);
	288	return 0;
	289	}
	290
	291	static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
	292	u32 chip_flags)
	293	{
	294	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	295	return __i2c_probe_chip(dev->base, chip_addr);
	296	}
	297
	298	static int lpc32xx_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	299	int nmsgs)
	300	{
	301	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	302	struct i2c_msg dmsg, omsg, dummy;
	303	uint i = 0, address = 0;
	304
	305	memset(&dummy, 0, sizeof(struct i2c_msg));
	306
	307	/* We expect either two messages (one with an offset and one with the
	308	* actual data) or one message (just data)
	309	*/
	310	if (nmsgs > 2 \|\| nmsgs == 0) {
	311	debug("%s: Only one or two messages are supported.", __func__);
	312	return -1;
	313	}
	314
	315	omsg = nmsgs == 1 ? &dummy : msg;
	316	dmsg = nmsgs == 1 ? msg : msg + 1;
	317
	318	/* the address is expected to be a uint, not a array. */
	319	address = omsg->buf[0];
	320	for (i = 1; i < omsg->len; i++)
	321	address = (address << 8) + omsg->buf[i];
	322
	323	if (dmsg->flags & I2C_M_RD)
	324	return __i2c_read(dev->base, dmsg->addr, address,
	325	omsg->len, dmsg->buf, dmsg->len);
	326	else
	327	return __i2c_write(dev->base, dmsg->addr, address,
	328	omsg->len, dmsg->buf, dmsg->len);
	329	}
	330
	331	static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	332	{
	333	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	334	return __i2c_set_bus_speed(dev->base, speed, dev->index);
	335	}
	336
	337	static int lpc32xx_i2c_reset(struct udevice *bus)
	338	{
	339	struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
	340
	341	__i2c_init(dev->base, dev->speed, 0, dev->index);
	342	return 0;
	343	}
	344
	345	static const struct dm_i2c_ops lpc32xx_i2c_ops = {
	346	.xfer = lpc32xx_i2c_xfer,
	347	.probe_chip = lpc32xx_i2c_probe_chip,
	348	.deblock = lpc32xx_i2c_reset,
	349	.set_bus_speed = lpc32xx_i2c_set_bus_speed,
350	};
351
352	U_BOOT_DRIVER(i2c_lpc32xx) = {
353	.id = UCLASS_I2C,
354	.name = "i2c_lpc32xx",
355	.probe = lpc32xx_i2c_probe,
356	.ops = &lpc32xx_i2c_ops,
357	};
358	#endif /* CONFIG_DM_I2C */