[people/ms/u-boot.git] / drivers / i2c / mvtwsi.c

/*
 * Driver for the TWSI (i2c) controller found on the Marvell
 * orion5x and kirkwood SoC families.
 *
 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
 * Copyright (c) 2010 Albert Aribaud.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/errno.h>
#include <asm/io.h>

/*
 * include a file that will provide CONFIG_I2C_MVTWSI_BASE*
 * and possibly other settings
 */

#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
#include <asm/arch/soc.h>
#elif defined(CONFIG_SUNXI)
#include <asm/arch/i2c.h>
#else
#error Driver mvtwsi not supported by SoC or board
#endif

/*
 * TWSI register structure
 */

#ifdef CONFIG_SUNXI

struct  mvtwsi_registers {
	u32 slave_address;
	u32 xtnd_slave_addr;
	u32 data;
	u32 control;
	u32 status;
	u32 baudrate;
	u32 soft_reset;
};

#else

struct  mvtwsi_registers {
	u32 slave_address;
	u32 data;
	u32 control;
	union {
		u32 status;	/* when reading */
		u32 baudrate;	/* when writing */
	};
	u32 xtnd_slave_addr;
	u32 reserved[2];
	u32 soft_reset;
};

#endif

/*
 * Control register fields
 */

#define	MVTWSI_CONTROL_ACK	0x00000004
#define	MVTWSI_CONTROL_IFLG	0x00000008
#define	MVTWSI_CONTROL_STOP	0x00000010
#define	MVTWSI_CONTROL_START	0x00000020
#define	MVTWSI_CONTROL_TWSIEN	0x00000040
#define	MVTWSI_CONTROL_INTEN	0x00000080

/*
 * Status register values -- only those expected in normal master
 * operation on non-10-bit-address devices; whatever status we don't
 * expect in nominal conditions (bus errors, arbitration losses,
 * missing ACKs...) we just pass back to the caller as an error
 * code.
 */

#define	MVTWSI_STATUS_START		0x08
#define	MVTWSI_STATUS_REPEATED_START	0x10
#define	MVTWSI_STATUS_ADDR_W_ACK	0x18
#define	MVTWSI_STATUS_DATA_W_ACK	0x28
#define	MVTWSI_STATUS_ADDR_R_ACK	0x40
#define	MVTWSI_STATUS_ADDR_R_NAK	0x48
#define	MVTWSI_STATUS_DATA_R_ACK	0x50
#define	MVTWSI_STATUS_DATA_R_NAK	0x58
#define	MVTWSI_STATUS_IDLE		0xF8

/*
 * MVTWSI controller base
 */

static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#ifdef CONFIG_I2C_MVTWSI_BASE0
	case 0:
		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE1
	case 1:
		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE2
	case 2:
		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE3
	case 3:
		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE4
	case 4:
		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
#endif
	default:
		printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
		break;
	}

	return NULL;
}

/*
 * Returned statuses are 0 for success and nonzero otherwise.
 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
 * Thus to ease debugging, the return status contains some debug info:
 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
 * - bits 23..16 are the last value of the control register.
 * - bits 15..8 are the last value of the status register.
 * - bits 7..0 are the expected value of the status register.
 */

#define MVTWSI_ERROR_WRONG_STATUS	0x01
#define MVTWSI_ERROR_TIMEOUT		0x02

#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
	((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))

/*
 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
 * return 0 (ok) or return 'wrong status'.
 */
static int twsi_wait(struct i2c_adapter *adap, int expected_status)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);
	int control, status;
	int timeout = 1000;

	do {
		control = readl(&twsi->control);
		if (control & MVTWSI_CONTROL_IFLG) {
			status = readl(&twsi->status);
			if (status == expected_status)
				return 0;
			else
				return MVTWSI_ERROR(
					MVTWSI_ERROR_WRONG_STATUS,
					control, status, expected_status);
		}
		udelay(10); /* one clock cycle at 100 kHz */
	} while (timeout--);
	status = readl(&twsi->status);
	return MVTWSI_ERROR(
		MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
}

/*
 * These flags are ORed to any write to the control register
 * They allow global setting of TWSIEN and ACK.
 * By default none are set.
 * twsi_start() sets TWSIEN (in case the controller was disabled)
 * twsi_recv() sets ACK or resets it depending on expected status.
 */
static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;

/*
 * Assert the START condition, either in a single I2C transaction
 * or inside back-to-back ones (repeated starts).
 */
static int twsi_start(struct i2c_adapter *adap, int expected_status)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);

	/* globally set TWSIEN in case it was not */
	twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
	/* assert START */
	writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
	/* wait for controller to process START */
	return twsi_wait(adap, expected_status);
}

/*
 * Send a byte (i2c address or data).
 */
static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);

	/* put byte in data register for sending */
	writel(byte, &twsi->data);
	/* clear any pending interrupt -- that'll cause sending */
	writel(twsi_control_flags, &twsi->control);
	/* wait for controller to receive byte and check ACK */
	return twsi_wait(adap, expected_status);
}

/*
 * Receive a byte.
 * Global mvtwsi_control_flags variable says if we should ack or nak.
 */
static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);
	int expected_status, status;

	/* compute expected status based on ACK bit in global control flags */
	if (twsi_control_flags & MVTWSI_CONTROL_ACK)
		expected_status = MVTWSI_STATUS_DATA_R_ACK;
	else
		expected_status = MVTWSI_STATUS_DATA_R_NAK;
	/* acknowledge *previous state* and launch receive */
	writel(twsi_control_flags, &twsi->control);
	/* wait for controller to receive byte and assert ACK or NAK */
	status = twsi_wait(adap, expected_status);
	/* if we did receive expected byte then store it */
	if (status == 0)
		*byte = readl(&twsi->data);
	/* return status */
	return status;
}

/*
 * Assert the STOP condition.
 * This is also used to force the bus back in idle (SDA=SCL=1).
 */
static int twsi_stop(struct i2c_adapter *adap, int status)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);
	int control, stop_status;
	int timeout = 1000;

	/* assert STOP */
	control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
	writel(control, &twsi->control);
	/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
	do {
		stop_status = readl(&twsi->status);
		if (stop_status == MVTWSI_STATUS_IDLE)
			break;
		udelay(10); /* one clock cycle at 100 kHz */
	} while (timeout--);
	control = readl(&twsi->control);
	if (stop_status != MVTWSI_STATUS_IDLE)
		if (status == 0)
			status = MVTWSI_ERROR(
				MVTWSI_ERROR_TIMEOUT,
				control, status, MVTWSI_STATUS_IDLE);
	return status;
}

static unsigned int twsi_calc_freq(const int n, const int m)
{
#ifdef CONFIG_SUNXI
	return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
#else
	return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
#endif
}

/*
 * Reset controller.
 * Controller reset also resets the baud rate and slave address, so
 * they must be re-established afterwards.
 */
static void twsi_reset(struct i2c_adapter *adap)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);
	/* ensure controller will be enabled by any twsi*() function */
	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
	/* reset controller */
	writel(0, &twsi->soft_reset);
	/* wait 2 ms -- this is what the Marvell LSP does */
	udelay(20000);
}

/*
 * I2C init called by cmd_i2c when doing 'i2c reset'.
 * Sets baud to the highest possible value not exceeding requested one.
 */
static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
					   unsigned int requested_speed)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);
	unsigned int tmp_speed, highest_speed, n, m;
	unsigned int baud = 0x44; /* baudrate at controller reset */

	/* use actual speed to collect progressively higher values */
	highest_speed = 0;
	/* compute m, n setting for highest speed not above requested speed */
	for (n = 0; n < 8; n++) {
		for (m = 0; m < 16; m++) {
			tmp_speed = twsi_calc_freq(n, m);
			if ((tmp_speed <= requested_speed)
			 && (tmp_speed > highest_speed)) {
				highest_speed = tmp_speed;
				baud = (m << 3) | n;
			}
		}
	}
	writel(baud, &twsi->baudrate);
	return 0;
}

static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	struct mvtwsi_registers *twsi = twsi_get_base(adap);

	/* reset controller */
	twsi_reset(adap);
	/* set speed */
	twsi_i2c_set_bus_speed(adap, speed);
	/* set slave address even though we don't use it */
	writel(slaveadd, &twsi->slave_address);
	writel(0, &twsi->xtnd_slave_addr);
	/* assert STOP but don't care for the result */
	(void) twsi_stop(adap, 0);
}

/*
 * Begin I2C transaction with expected start status, at given address.
 * Common to i2c_probe, i2c_read and i2c_write.
 * Expected address status will derive from direction bit (bit 0) in addr.
 */
static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
		     u8 addr)
{
	int status, expected_addr_status;

	/* compute expected address status from direction bit in addr */
	if (addr & 1) /* reading */
		expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
	else /* writing */
		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
	/* assert START */
	status = twsi_start(adap, expected_start_status);
	/* send out the address if the start went well */
	if (status == 0)
		status = twsi_send(adap, addr, expected_addr_status);
	/* return ok or status of first failure to caller */
	return status;
}

/*
 * I2C probe called by cmd_i2c when doing 'i2c probe'.
 * Begin read, nak data byte, end.
 */
static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
	u8 dummy_byte;
	int status;

	/* begin i2c read */
	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
	/* dummy read was accepted: receive byte but NAK it. */
	if (status == 0)
		status = twsi_recv(adap, &dummy_byte);
	/* Stop transaction */
	twsi_stop(adap, 0);
	/* return 0 or status of first failure */
	return status;
}

/*
 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
 * Begin write, send address byte(s), begin read, receive data bytes, end.
 *
 * NOTE: some EEPROMS want a stop right before the second start, while
 * some will choke if it is there. Deciding which we should do is eeprom
 * stuff, not i2c, but at the moment the APIs won't let us put it in
 * cmd_eeprom, so we have to choose here, and for the moment that'll be
 * a repeated start without a preceding stop.
 */
static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *data, int length)
{
	int status;

	/* begin i2c write to send the address bytes */
	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
	/* send addr bytes */
	while ((status == 0) && alen--)
		status = twsi_send(adap, addr >> (8*alen),
			MVTWSI_STATUS_DATA_W_ACK);
	/* begin i2c read to receive eeprom data bytes */
	if (status == 0)
		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
				   (chip << 1) | 1);
	/* prepare ACK if at least one byte must be received */
	if (length > 0)
		twsi_control_flags |= MVTWSI_CONTROL_ACK;
	/* now receive actual bytes */
	while ((status == 0) && length--) {
		/* reset NAK if we if no more to read now */
		if (length == 0)
			twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
		/* read current byte */
		status = twsi_recv(adap, data++);
	}
	/* Stop transaction */
	status = twsi_stop(adap, status);
	/* return 0 or status of first failure */
	return status;
}

/*
 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
 * Begin write, send address byte(s), send data bytes, end.
 */
static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *data, int length)
{
	int status;

	/* begin i2c write to send the eeprom adress bytes then data bytes */
	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
	/* send addr bytes */
	while ((status == 0) && alen--)
		status = twsi_send(adap, addr >> (8*alen),
			MVTWSI_STATUS_DATA_W_ACK);
	/* send data bytes */
	while ((status == 0) && (length-- > 0))
		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
	/* Stop transaction */
	status = twsi_stop(adap, status);
	/* return 0 or status of first failure */
	return status;
}

#ifdef CONFIG_I2C_MVTWSI_BASE0
U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
			 twsi_i2c_read, twsi_i2c_write,
			 twsi_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE1
U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
			 twsi_i2c_read, twsi_i2c_write,
			 twsi_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)

#endif
#ifdef CONFIG_I2C_MVTWSI_BASE2
U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
			 twsi_i2c_read, twsi_i2c_write,
			 twsi_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)

#endif
#ifdef CONFIG_I2C_MVTWSI_BASE3
U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
			 twsi_i2c_read, twsi_i2c_write,
			 twsi_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)

#endif
#ifdef CONFIG_I2C_MVTWSI_BASE4
U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
			 twsi_i2c_read, twsi_i2c_write,
			 twsi_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)

#endif
Commit	Line	Data
4ce5a728	1	/*
306563a7 AA	2	* Driver for the TWSI (i2c) controller found on the Marvell
306563a7 AA	3	* orion5x and kirkwood SoC families.
4ce5a728	4	*
57b4bce9	5	* Author: Albert Aribaud <albert.u.boot@aribaud.net>
306563a7	6	* Copyright (c) 2010 Albert Aribaud.
4ce5a728	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
4ce5a728	9	*/
306563a7	10
4ce5a728 HS	11	#include <common.h>
4ce5a728 HS	12	#include <i2c.h>
4ce5a728 HS	13	#include <asm/errno.h>
	14	#include <asm/io.h>
	15
306563a7	16	/*
dd82242b	17	* include a file that will provide CONFIG_I2C_MVTWSI_BASE*
306563a7 AA	18	* and possibly other settings
306563a7 AA	19	*/
4ce5a728	20
306563a7 AA	21	#if defined(CONFIG_ORION5X)
306563a7 AA	22	#include <asm/arch/orion5x.h>
81e33f4b	23	#elif (defined(CONFIG_KIRKWOOD) \|\| defined(CONFIG_ARCH_MVEBU))
3dc23f78	24	#include <asm/arch/soc.h>
6620377e HG	25	#elif defined(CONFIG_SUNXI)
6620377e HG	26	#include <asm/arch/i2c.h>
306563a7 AA	27	#else
306563a7 AA	28	#error Driver mvtwsi not supported by SoC or board
4ce5a728 HS	29	#endif
4ce5a728 HS	30
306563a7 AA	31	/*
	32	* TWSI register structure
	33	*/
4ce5a728	34
6620377e HG	35	#ifdef CONFIG_SUNXI
	36
	37	struct mvtwsi_registers {
	38	u32 slave_address;
	39	u32 xtnd_slave_addr;
	40	u32 data;
	41	u32 control;
	42	u32 status;
	43	u32 baudrate;
	44	u32 soft_reset;
	45	};
	46
	47	#else
	48
306563a7 AA	49	struct mvtwsi_registers {
	50	u32 slave_address;
	51	u32 data;
	52	u32 control;
	53	union {
	54	u32 status; /* when reading */
	55	u32 baudrate; /* when writing */
	56	};
	57	u32 xtnd_slave_addr;
	58	u32 reserved[2];
	59	u32 soft_reset;
4ce5a728 HS	60	};
4ce5a728 HS	61
6620377e HG	62	#endif
6620377e HG	63
306563a7 AA	64	/*
	65	* Control register fields
	66	*/
4ce5a728	67
306563a7 AA	68	#define MVTWSI_CONTROL_ACK 0x00000004
	69	#define MVTWSI_CONTROL_IFLG 0x00000008
	70	#define MVTWSI_CONTROL_STOP 0x00000010
	71	#define MVTWSI_CONTROL_START 0x00000020
	72	#define MVTWSI_CONTROL_TWSIEN 0x00000040
	73	#define MVTWSI_CONTROL_INTEN 0x00000080
4ce5a728	74
306563a7 AA	75	/*
	76	* Status register values -- only those expected in normal master
	77	* operation on non-10-bit-address devices; whatever status we don't
	78	* expect in nominal conditions (bus errors, arbitration losses,
	79	* missing ACKs...) we just pass back to the caller as an error
	80	* code.
	81	*/
4ce5a728	82
306563a7 AA	83	#define MVTWSI_STATUS_START 0x08
	84	#define MVTWSI_STATUS_REPEATED_START 0x10
	85	#define MVTWSI_STATUS_ADDR_W_ACK 0x18
	86	#define MVTWSI_STATUS_DATA_W_ACK 0x28
	87	#define MVTWSI_STATUS_ADDR_R_ACK 0x40
	88	#define MVTWSI_STATUS_ADDR_R_NAK 0x48
	89	#define MVTWSI_STATUS_DATA_R_ACK 0x50
	90	#define MVTWSI_STATUS_DATA_R_NAK 0x58
	91	#define MVTWSI_STATUS_IDLE 0xF8
	92
	93	/*
dd82242b	94	* MVTWSI controller base
306563a7	95	*/
4ce5a728	96
dd82242b PK	97	static struct mvtwsi_registers twsi_get_base(struct i2c_adapter adap)
	98	{
	99	switch (adap->hwadapnr) {
	100	#ifdef CONFIG_I2C_MVTWSI_BASE0
	101	case 0:
	102	return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
	103	#endif
	104	#ifdef CONFIG_I2C_MVTWSI_BASE1
	105	case 1:
	106	return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
	107	#endif
	108	#ifdef CONFIG_I2C_MVTWSI_BASE2
	109	case 2:
	110	return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
	111	#endif
	112	#ifdef CONFIG_I2C_MVTWSI_BASE3
	113	case 3:
	114	return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
	115	#endif
	116	#ifdef CONFIG_I2C_MVTWSI_BASE4
	117	case 4:
	118	return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
	119	#endif
	120	default:
	121	printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
	122	break;
	123	}
	124
	125	return NULL;
	126	}
4ce5a728 HS	127
4ce5a728 HS	128	/*
306563a7 AA	129	* Returned statuses are 0 for success and nonzero otherwise.
	130	* Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
	131	* Thus to ease debugging, the return status contains some debug info:
	132	* - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
	133	* - bits 23..16 are the last value of the control register.
	134	* - bits 15..8 are the last value of the status register.
	135	* - bits 7..0 are the expected value of the status register.
4ce5a728 HS	136	*/
4ce5a728 HS	137
306563a7 AA	138	#define MVTWSI_ERROR_WRONG_STATUS 0x01
306563a7 AA	139	#define MVTWSI_ERROR_TIMEOUT 0x02
4ce5a728	140
306563a7 AA	141	#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) \| \
306563a7 AA	142	((lc << 16) & 0x00FF0000) \| ((ls<<8) & 0x0000FF00) \| (es & 0xFF))
4ce5a728	143
306563a7 AA	144	/*
	145	* Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
	146	* return 0 (ok) or return 'wrong status'.
	147	*/
dd82242b	148	static int twsi_wait(struct i2c_adapter *adap, int expected_status)
306563a7	149	{
dd82242b	150	struct mvtwsi_registers *twsi = twsi_get_base(adap);
306563a7 AA	151	int control, status;
	152	int timeout = 1000;
	153
	154	do {
	155	control = readl(&twsi->control);
	156	if (control & MVTWSI_CONTROL_IFLG) {
	157	status = readl(&twsi->status);
	158	if (status == expected_status)
	159	return 0;
	160	else
	161	return MVTWSI_ERROR(
	162	MVTWSI_ERROR_WRONG_STATUS,
	163	control, status, expected_status);
4ce5a728	164	}
306563a7 AA	165	udelay(10); /* one clock cycle at 100 kHz */
	166	} while (timeout--);
	167	status = readl(&twsi->status);
	168	return MVTWSI_ERROR(
	169	MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
4ce5a728 HS	170	}
4ce5a728 HS	171
306563a7 AA	172	/*
	173	* These flags are ORed to any write to the control register
	174	* They allow global setting of TWSIEN and ACK.
	175	* By default none are set.
	176	* twsi_start() sets TWSIEN (in case the controller was disabled)
	177	* twsi_recv() sets ACK or resets it depending on expected status.
	178	*/
	179	static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
	180
	181	/*
	182	* Assert the START condition, either in a single I2C transaction
	183	* or inside back-to-back ones (repeated starts).
	184	*/
dd82242b	185	static int twsi_start(struct i2c_adapter *adap, int expected_status)
4ce5a728	186	{
dd82242b PK	187	struct mvtwsi_registers *twsi = twsi_get_base(adap);
dd82242b PK	188
306563a7 AA	189	/* globally set TWSIEN in case it was not */
	190	twsi_control_flags \|= MVTWSI_CONTROL_TWSIEN;
	191	/* assert START */
	192	writel(twsi_control_flags \| MVTWSI_CONTROL_START, &twsi->control);
	193	/* wait for controller to process START */
dd82242b	194	return twsi_wait(adap, expected_status);
4ce5a728 HS	195	}
4ce5a728 HS	196
306563a7 AA	197	/*
	198	* Send a byte (i2c address or data).
	199	*/
dd82242b	200	static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
4ce5a728	201	{
dd82242b PK	202	struct mvtwsi_registers *twsi = twsi_get_base(adap);
dd82242b PK	203
306563a7 AA	204	/* put byte in data register for sending */
	205	writel(byte, &twsi->data);
	206	/* clear any pending interrupt -- that'll cause sending */
	207	writel(twsi_control_flags, &twsi->control);
	208	/* wait for controller to receive byte and check ACK */
dd82242b	209	return twsi_wait(adap, expected_status);
4ce5a728 HS	210	}
4ce5a728 HS	211
306563a7 AA	212	/*
	213	* Receive a byte.
	214	* Global mvtwsi_control_flags variable says if we should ack or nak.
	215	*/
dd82242b	216	static int twsi_recv(struct i2c_adapter adap, u8 byte)
4ce5a728	217	{
dd82242b	218	struct mvtwsi_registers *twsi = twsi_get_base(adap);
306563a7 AA	219	int expected_status, status;
	220
	221	/* compute expected status based on ACK bit in global control flags */
	222	if (twsi_control_flags & MVTWSI_CONTROL_ACK)
	223	expected_status = MVTWSI_STATUS_DATA_R_ACK;
	224	else
	225	expected_status = MVTWSI_STATUS_DATA_R_NAK;
	226	/* acknowledge previous state and launch receive */
	227	writel(twsi_control_flags, &twsi->control);
	228	/* wait for controller to receive byte and assert ACK or NAK */
dd82242b	229	status = twsi_wait(adap, expected_status);
306563a7 AA	230	/* if we did receive expected byte then store it */
	231	if (status == 0)
	232	*byte = readl(&twsi->data);
	233	/* return status */
	234	return status;
4ce5a728 HS	235	}
4ce5a728 HS	236
306563a7 AA	237	/*
	238	* Assert the STOP condition.
	239	* This is also used to force the bus back in idle (SDA=SCL=1).
	240	*/
dd82242b	241	static int twsi_stop(struct i2c_adapter *adap, int status)
4ce5a728	242	{
dd82242b	243	struct mvtwsi_registers *twsi = twsi_get_base(adap);
306563a7 AA	244	int control, stop_status;
	245	int timeout = 1000;
	246
	247	/* assert STOP */
	248	control = MVTWSI_CONTROL_TWSIEN \| MVTWSI_CONTROL_STOP;
	249	writel(control, &twsi->control);
	250	/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
	251	do {
	252	stop_status = readl(&twsi->status);
	253	if (stop_status == MVTWSI_STATUS_IDLE)
	254	break;
	255	udelay(10); /* one clock cycle at 100 kHz */
	256	} while (timeout--);
	257	control = readl(&twsi->control);
	258	if (stop_status != MVTWSI_STATUS_IDLE)
	259	if (status == 0)
	260	status = MVTWSI_ERROR(
	261	MVTWSI_ERROR_TIMEOUT,
	262	control, status, MVTWSI_STATUS_IDLE);
	263	return status;
4ce5a728 HS	264	}
4ce5a728 HS	265
f582a158 SR	266	static unsigned int twsi_calc_freq(const int n, const int m)
	267	{
	268	#ifdef CONFIG_SUNXI
	269	return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
	270	#else
	271	return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
	272	#endif
	273	}
306563a7	274
306563a7 AA	275	/*
306563a7 AA	276	* Reset controller.
306563a7	277	* Controller reset also resets the baud rate and slave address, so
0db2bbdc	278	* they must be re-established afterwards.
306563a7	279	*/
0db2bbdc	280	static void twsi_reset(struct i2c_adapter *adap)
306563a7	281	{
dd82242b	282	struct mvtwsi_registers *twsi = twsi_get_base(adap);
306563a7 AA	283	/* ensure controller will be enabled by any twsi() function /
	284	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
	285	/* reset controller */
	286	writel(0, &twsi->soft_reset);
	287	/* wait 2 ms -- this is what the Marvell LSP does */
	288	udelay(20000);
4ce5a728 HS	289	}
4ce5a728 HS	290
306563a7 AA	291	/*
	292	* I2C init called by cmd_i2c when doing 'i2c reset'.
	293	* Sets baud to the highest possible value not exceeding requested one.
	294	*/
0db2bbdc HG	295	static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
0db2bbdc HG	296	unsigned int requested_speed)
4ce5a728	297	{
dd82242b	298	struct mvtwsi_registers *twsi = twsi_get_base(adap);
0db2bbdc HG	299	unsigned int tmp_speed, highest_speed, n, m;
0db2bbdc HG	300	unsigned int baud = 0x44; /* baudrate at controller reset */
306563a7 AA	301
	302	/* use actual speed to collect progressively higher values */
	303	highest_speed = 0;
	304	/* compute m, n setting for highest speed not above requested speed */
	305	for (n = 0; n < 8; n++) {
	306	for (m = 0; m < 16; m++) {
f582a158	307	tmp_speed = twsi_calc_freq(n, m);
306563a7 AA	308	if ((tmp_speed <= requested_speed)
	309	&& (tmp_speed > highest_speed)) {
	310	highest_speed = tmp_speed;
	311	baud = (m << 3) \| n;
	312	}
	313	}
4ce5a728	314	}
0db2bbdc HG	315	writel(baud, &twsi->baudrate);
	316	return 0;
	317	}
	318
	319	static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
	320	{
dd82242b PK	321	struct mvtwsi_registers *twsi = twsi_get_base(adap);
dd82242b PK	322
306563a7	323	/* reset controller */
0db2bbdc HG	324	twsi_reset(adap);
	325	/* set speed */
	326	twsi_i2c_set_bus_speed(adap, speed);
	327	/* set slave address even though we don't use it */
	328	writel(slaveadd, &twsi->slave_address);
	329	writel(0, &twsi->xtnd_slave_addr);
	330	/* assert STOP but don't care for the result */
dd82242b	331	(void) twsi_stop(adap, 0);
4ce5a728 HS	332	}
4ce5a728 HS	333
306563a7 AA	334	/*
	335	* Begin I2C transaction with expected start status, at given address.
	336	* Common to i2c_probe, i2c_read and i2c_write.
	337	* Expected address status will derive from direction bit (bit 0) in addr.
	338	*/
dd82242b PK	339	static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
dd82242b PK	340	u8 addr)
4ce5a728	341	{
306563a7 AA	342	int status, expected_addr_status;
	343
	344	/* compute expected address status from direction bit in addr */
	345	if (addr & 1) /* reading */
	346	expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
	347	else /* writing */
	348	expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
	349	/* assert START */
dd82242b	350	status = twsi_start(adap, expected_start_status);
306563a7 AA	351	/* send out the address if the start went well */
306563a7 AA	352	if (status == 0)
dd82242b	353	status = twsi_send(adap, addr, expected_addr_status);
306563a7 AA	354	/* return ok or status of first failure to caller */
306563a7 AA	355	return status;
4ce5a728 HS	356	}
4ce5a728 HS	357
306563a7 AA	358	/*
	359	* I2C probe called by cmd_i2c when doing 'i2c probe'.
	360	* Begin read, nak data byte, end.
	361	*/
0db2bbdc	362	static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
4ce5a728	363	{
306563a7 AA	364	u8 dummy_byte;
	365	int status;
	366
	367	/* begin i2c read */
dd82242b	368	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) \| 1);
306563a7 AA	369	/* dummy read was accepted: receive byte but NAK it. */
306563a7 AA	370	if (status == 0)
dd82242b	371	status = twsi_recv(adap, &dummy_byte);
306563a7	372	/* Stop transaction */
dd82242b	373	twsi_stop(adap, 0);
306563a7 AA	374	/* return 0 or status of first failure */
306563a7 AA	375	return status;
4ce5a728 HS	376	}
4ce5a728 HS	377
306563a7 AA	378	/*
	379	* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
	380	* Begin write, send address byte(s), begin read, receive data bytes, end.
	381	*
	382	* NOTE: some EEPROMS want a stop right before the second start, while
	383	* some will choke if it is there. Deciding which we should do is eeprom
	384	* stuff, not i2c, but at the moment the APIs won't let us put it in
	385	* cmd_eeprom, so we have to choose here, and for the moment that'll be
	386	* a repeated start without a preceding stop.
	387	*/
0db2bbdc HG	388	static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
0db2bbdc HG	389	int alen, uchar *data, int length)
4ce5a728	390	{
306563a7 AA	391	int status;
	392
	393	/* begin i2c write to send the address bytes */
dd82242b	394	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
306563a7 AA	395	/* send addr bytes */
306563a7 AA	396	while ((status == 0) && alen--)
dd82242b	397	status = twsi_send(adap, addr >> (8*alen),
306563a7 AA	398	MVTWSI_STATUS_DATA_W_ACK);
	399	/* begin i2c read to receive eeprom data bytes */
	400	if (status == 0)
dd82242b PK	401	status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
dd82242b PK	402	(chip << 1) \| 1);
306563a7 AA	403	/* prepare ACK if at least one byte must be received */
	404	if (length > 0)
	405	twsi_control_flags \|= MVTWSI_CONTROL_ACK;
	406	/* now receive actual bytes */
	407	while ((status == 0) && length--) {
	408	/* reset NAK if we if no more to read now */
	409	if (length == 0)
	410	twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
	411	/* read current byte */
dd82242b	412	status = twsi_recv(adap, data++);
306563a7 AA	413	}
306563a7 AA	414	/* Stop transaction */
dd82242b	415	status = twsi_stop(adap, status);
306563a7 AA	416	/* return 0 or status of first failure */
306563a7 AA	417	return status;
4ce5a728 HS	418	}
4ce5a728 HS	419
306563a7 AA	420	/*
	421	* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
	422	* Begin write, send address byte(s), send data bytes, end.
	423	*/
0db2bbdc HG	424	static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
0db2bbdc HG	425	int alen, uchar *data, int length)
4ce5a728	426	{
306563a7 AA	427	int status;
	428
	429	/* begin i2c write to send the eeprom adress bytes then data bytes */
dd82242b	430	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
306563a7 AA	431	/* send addr bytes */
306563a7 AA	432	while ((status == 0) && alen--)
dd82242b	433	status = twsi_send(adap, addr >> (8*alen),
306563a7 AA	434	MVTWSI_STATUS_DATA_W_ACK);
	435	/* send data bytes */
	436	while ((status == 0) && (length-- > 0))
dd82242b	437	status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
306563a7	438	/* Stop transaction */
dd82242b	439	status = twsi_stop(adap, status);
306563a7 AA	440	/* return 0 or status of first failure */
306563a7 AA	441	return status;
4ce5a728 HS	442	}
4ce5a728 HS	443
dd82242b	444	#ifdef CONFIG_I2C_MVTWSI_BASE0
0db2bbdc HG	445	U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
	446	twsi_i2c_read, twsi_i2c_write,
	447	twsi_i2c_set_bus_speed,
	448	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
dd82242b PK	449	#endif
	450	#ifdef CONFIG_I2C_MVTWSI_BASE1
	451	U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
	452	twsi_i2c_read, twsi_i2c_write,
	453	twsi_i2c_set_bus_speed,
	454	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
	455
	456	#endif
	457	#ifdef CONFIG_I2C_MVTWSI_BASE2
	458	U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
	459	twsi_i2c_read, twsi_i2c_write,
	460	twsi_i2c_set_bus_speed,
	461	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
	462
	463	#endif
	464	#ifdef CONFIG_I2C_MVTWSI_BASE3
	465	U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
	466	twsi_i2c_read, twsi_i2c_write,
	467	twsi_i2c_set_bus_speed,
	468	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
	469
	470	#endif
	471	#ifdef CONFIG_I2C_MVTWSI_BASE4
	472	U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
	473	twsi_i2c_read, twsi_i2c_write,
	474	twsi_i2c_set_bus_speed,
	475	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
	476
	477	#endif