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4ce5a728 | 1 | /* |
306563a7 AA |
2 | * Driver for the TWSI (i2c) controller found on the Marvell |
3 | * orion5x and kirkwood SoC families. | |
4ce5a728 | 4 | * |
57b4bce9 | 5 | * Author: Albert Aribaud <albert.u.boot@aribaud.net> |
306563a7 | 6 | * Copyright (c) 2010 Albert Aribaud. |
4ce5a728 | 7 | * |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
4ce5a728 | 9 | */ |
306563a7 | 10 | |
4ce5a728 HS |
11 | #include <common.h> |
12 | #include <i2c.h> | |
1221ce45 | 13 | #include <linux/errno.h> |
4ce5a728 | 14 | #include <asm/io.h> |
c68c6243 | 15 | #include <linux/compat.h> |
14a6ff2c | 16 | #ifdef CONFIG_DM_I2C |
17 | #include <dm.h> | |
18 | #endif | |
19 | ||
20 | DECLARE_GLOBAL_DATA_PTR; | |
4ce5a728 | 21 | |
306563a7 | 22 | /* |
49c801bf | 23 | * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other |
24 | * settings | |
306563a7 | 25 | */ |
4ce5a728 | 26 | |
14a6ff2c | 27 | #ifndef CONFIG_DM_I2C |
306563a7 AA |
28 | #if defined(CONFIG_ORION5X) |
29 | #include <asm/arch/orion5x.h> | |
81e33f4b | 30 | #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) |
3dc23f78 | 31 | #include <asm/arch/soc.h> |
aec9a0f1 | 32 | #elif defined(CONFIG_ARCH_SUNXI) |
6620377e | 33 | #include <asm/arch/i2c.h> |
306563a7 AA |
34 | #else |
35 | #error Driver mvtwsi not supported by SoC or board | |
4ce5a728 | 36 | #endif |
14a6ff2c | 37 | #endif /* CONFIG_DM_I2C */ |
4ce5a728 | 38 | |
306563a7 AA |
39 | /* |
40 | * TWSI register structure | |
41 | */ | |
4ce5a728 | 42 | |
aec9a0f1 | 43 | #ifdef CONFIG_ARCH_SUNXI |
6620377e HG |
44 | |
45 | struct mvtwsi_registers { | |
46 | u32 slave_address; | |
47 | u32 xtnd_slave_addr; | |
48 | u32 data; | |
49 | u32 control; | |
50 | u32 status; | |
51 | u32 baudrate; | |
52 | u32 soft_reset; | |
53 | }; | |
54 | ||
55 | #else | |
56 | ||
306563a7 AA |
57 | struct mvtwsi_registers { |
58 | u32 slave_address; | |
59 | u32 data; | |
60 | u32 control; | |
61 | union { | |
49c801bf | 62 | u32 status; /* When reading */ |
63 | u32 baudrate; /* When writing */ | |
306563a7 AA |
64 | }; |
65 | u32 xtnd_slave_addr; | |
66 | u32 reserved[2]; | |
67 | u32 soft_reset; | |
4ce5a728 HS |
68 | }; |
69 | ||
6620377e HG |
70 | #endif |
71 | ||
14a6ff2c | 72 | #ifdef CONFIG_DM_I2C |
73 | struct mvtwsi_i2c_dev { | |
74 | /* TWSI Register base for the device */ | |
75 | struct mvtwsi_registers *base; | |
76 | /* Number of the device (determined from cell-index property) */ | |
77 | int index; | |
78 | /* The I2C slave address for the device */ | |
79 | u8 slaveadd; | |
80 | /* The configured I2C speed in Hz */ | |
81 | uint speed; | |
c68c6243 | 82 | /* The current length of a clock period (depending on speed) */ |
83 | uint tick; | |
14a6ff2c | 84 | }; |
85 | #endif /* CONFIG_DM_I2C */ | |
86 | ||
306563a7 | 87 | /* |
dfc3958c | 88 | * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control |
89 | * register | |
306563a7 | 90 | */ |
dfc3958c | 91 | enum mvtwsi_ctrl_register_fields { |
92 | /* Acknowledge bit */ | |
93 | MVTWSI_CONTROL_ACK = 0x00000004, | |
94 | /* Interrupt flag */ | |
95 | MVTWSI_CONTROL_IFLG = 0x00000008, | |
96 | /* Stop bit */ | |
97 | MVTWSI_CONTROL_STOP = 0x00000010, | |
98 | /* Start bit */ | |
99 | MVTWSI_CONTROL_START = 0x00000020, | |
100 | /* I2C enable */ | |
101 | MVTWSI_CONTROL_TWSIEN = 0x00000040, | |
102 | /* Interrupt enable */ | |
103 | MVTWSI_CONTROL_INTEN = 0x00000080, | |
104 | }; | |
4ce5a728 | 105 | |
904dfbfd | 106 | /* |
49c801bf | 107 | * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; |
108 | * on other platforms, it is a normal r/w bit, which is cleared by writing 0. | |
904dfbfd HG |
109 | */ |
110 | ||
111 | #ifdef CONFIG_SUNXI_GEN_SUN6I | |
112 | #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 | |
113 | #else | |
114 | #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 | |
115 | #endif | |
116 | ||
306563a7 | 117 | /* |
dfc3958c | 118 | * enum mvstwsi_status_values - Possible values of I2C controller's status |
119 | * register | |
120 | * | |
121 | * Only those statuses expected in normal master operation on | |
122 | * non-10-bit-address devices are specified. | |
123 | * | |
124 | * Every status that's unexpected during normal operation (bus errors, | |
125 | * arbitration losses, missing ACKs...) is passed back to the caller as an error | |
306563a7 AA |
126 | * code. |
127 | */ | |
dfc3958c | 128 | enum mvstwsi_status_values { |
129 | /* START condition transmitted */ | |
130 | MVTWSI_STATUS_START = 0x08, | |
131 | /* Repeated START condition transmitted */ | |
132 | MVTWSI_STATUS_REPEATED_START = 0x10, | |
133 | /* Address + write bit transmitted, ACK received */ | |
134 | MVTWSI_STATUS_ADDR_W_ACK = 0x18, | |
135 | /* Data transmitted, ACK received */ | |
136 | MVTWSI_STATUS_DATA_W_ACK = 0x28, | |
137 | /* Address + read bit transmitted, ACK received */ | |
138 | MVTWSI_STATUS_ADDR_R_ACK = 0x40, | |
139 | /* Address + read bit transmitted, ACK not received */ | |
140 | MVTWSI_STATUS_ADDR_R_NAK = 0x48, | |
141 | /* Data received, ACK transmitted */ | |
142 | MVTWSI_STATUS_DATA_R_ACK = 0x50, | |
143 | /* Data received, ACK not transmitted */ | |
144 | MVTWSI_STATUS_DATA_R_NAK = 0x58, | |
145 | /* No relevant status */ | |
146 | MVTWSI_STATUS_IDLE = 0xF8, | |
147 | }; | |
306563a7 | 148 | |
670514f5 | 149 | /* |
150 | * enum mvstwsi_ack_flags - Determine whether a read byte should be | |
151 | * acknowledged or not. | |
152 | */ | |
153 | enum mvtwsi_ack_flags { | |
154 | /* Send NAK after received byte */ | |
155 | MVTWSI_READ_NAK = 0, | |
156 | /* Send ACK after received byte */ | |
157 | MVTWSI_READ_ACK = 1, | |
158 | }; | |
159 | ||
6e677caf | 160 | /* |
161 | * calc_tick() - Calculate the duration of a clock cycle from the I2C speed | |
162 | * | |
163 | * @speed: The speed in Hz to calculate the clock cycle duration for. | |
164 | * @return The duration of a clock cycle in ns. | |
165 | */ | |
c68c6243 | 166 | inline uint calc_tick(uint speed) |
167 | { | |
168 | /* One tick = the duration of a period at the specified speed in ns (we | |
169 | * add 100 ns to be on the safe side) */ | |
170 | return (1000000000u / speed) + 100; | |
171 | } | |
172 | ||
14a6ff2c | 173 | #ifndef CONFIG_DM_I2C |
c68c6243 | 174 | |
306563a7 | 175 | /* |
6e677caf | 176 | * twsi_get_base() - Get controller register base for specified adapter |
177 | * | |
178 | * @adap: Adapter to get the register base for. | |
179 | * @return Register base for the specified adapter. | |
306563a7 | 180 | */ |
dd82242b PK |
181 | static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) |
182 | { | |
183 | switch (adap->hwadapnr) { | |
184 | #ifdef CONFIG_I2C_MVTWSI_BASE0 | |
185 | case 0: | |
9ec43b0c | 186 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; |
dd82242b PK |
187 | #endif |
188 | #ifdef CONFIG_I2C_MVTWSI_BASE1 | |
189 | case 1: | |
9ec43b0c | 190 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; |
dd82242b PK |
191 | #endif |
192 | #ifdef CONFIG_I2C_MVTWSI_BASE2 | |
193 | case 2: | |
9ec43b0c | 194 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; |
dd82242b PK |
195 | #endif |
196 | #ifdef CONFIG_I2C_MVTWSI_BASE3 | |
197 | case 3: | |
9ec43b0c | 198 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; |
dd82242b PK |
199 | #endif |
200 | #ifdef CONFIG_I2C_MVTWSI_BASE4 | |
201 | case 4: | |
9ec43b0c | 202 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; |
9d082687 JW |
203 | #endif |
204 | #ifdef CONFIG_I2C_MVTWSI_BASE5 | |
205 | case 5: | |
9ec43b0c | 206 | return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; |
dd82242b PK |
207 | #endif |
208 | default: | |
209 | printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); | |
210 | break; | |
211 | } | |
212 | ||
213 | return NULL; | |
214 | } | |
14a6ff2c | 215 | #endif |
4ce5a728 HS |
216 | |
217 | /* | |
dfc3958c | 218 | * enum mvtwsi_error_class - types of I2C errors |
4ce5a728 | 219 | */ |
dfc3958c | 220 | enum mvtwsi_error_class { |
221 | /* The controller returned a different status than expected */ | |
222 | MVTWSI_ERROR_WRONG_STATUS = 0x01, | |
223 | /* The controller timed out */ | |
224 | MVTWSI_ERROR_TIMEOUT = 0x02, | |
225 | }; | |
4ce5a728 | 226 | |
dfc3958c | 227 | /* |
228 | * mvtwsi_error() - Build I2C return code from error information | |
229 | * | |
230 | * For debugging purposes, this function packs some information of an occurred | |
231 | * error into a return code. These error codes are returned from I2C API | |
232 | * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). | |
233 | * | |
234 | * @ec: The error class of the error (enum mvtwsi_error_class). | |
235 | * @lc: The last value of the control register. | |
236 | * @ls: The last value of the status register. | |
237 | * @es: The expected value of the status register. | |
238 | * @return The generated error code. | |
239 | */ | |
240 | inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) | |
241 | { | |
242 | return ((ec << 24) & 0xFF000000) | |
243 | | ((lc << 16) & 0x00FF0000) | |
244 | | ((ls << 8) & 0x0000FF00) | |
245 | | (es & 0xFF); | |
246 | } | |
4ce5a728 | 247 | |
306563a7 | 248 | /* |
6e677caf | 249 | * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out. |
250 | * | |
251 | * @return Zero if status is as expected, or a non-zero code if either a time | |
252 | * out occurred, or the status was not the expected one. | |
306563a7 | 253 | */ |
c68c6243 | 254 | static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, |
255 | uint tick) | |
306563a7 AA |
256 | { |
257 | int control, status; | |
258 | int timeout = 1000; | |
259 | ||
260 | do { | |
261 | control = readl(&twsi->control); | |
262 | if (control & MVTWSI_CONTROL_IFLG) { | |
263 | status = readl(&twsi->status); | |
264 | if (status == expected_status) | |
265 | return 0; | |
266 | else | |
dfc3958c | 267 | return mvtwsi_error( |
306563a7 AA |
268 | MVTWSI_ERROR_WRONG_STATUS, |
269 | control, status, expected_status); | |
4ce5a728 | 270 | } |
c68c6243 | 271 | ndelay(tick); /* One clock cycle */ |
306563a7 AA |
272 | } while (timeout--); |
273 | status = readl(&twsi->status); | |
dfc3958c | 274 | return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, |
275 | expected_status); | |
4ce5a728 HS |
276 | } |
277 | ||
306563a7 | 278 | /* |
6e677caf | 279 | * twsi_start() - Assert a START condition on the bus. |
280 | * | |
281 | * This function is used in both single I2C transactions and inside | |
282 | * back-to-back transactions (repeated starts). | |
283 | * | |
284 | * @twsi: The MVTWSI register structure to use. | |
285 | * @expected_status: The I2C bus status expected to be asserted after the | |
286 | * operation completion. | |
287 | * @tick: The duration of a clock cycle at the current I2C speed. | |
288 | * @return Zero if status is as expected, or a non-zero code if either a time | |
289 | * out occurred or the status was not the expected one. | |
306563a7 | 290 | */ |
c68c6243 | 291 | static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, |
292 | uint tick) | |
4ce5a728 | 293 | { |
49c801bf | 294 | /* Assert START */ |
670514f5 | 295 | writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | |
49c801bf | 296 | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); |
297 | /* Wait for controller to process START */ | |
c68c6243 | 298 | return twsi_wait(twsi, expected_status, tick); |
4ce5a728 HS |
299 | } |
300 | ||
306563a7 | 301 | /* |
6e677caf | 302 | * twsi_send() - Send a byte on the I2C bus. |
303 | * | |
304 | * The byte may be part of an address byte or data. | |
305 | * | |
306 | * @twsi: The MVTWSI register structure to use. | |
307 | * @byte: The byte to send. | |
308 | * @expected_status: The I2C bus status expected to be asserted after the | |
309 | * operation completion. | |
310 | * @tick: The duration of a clock cycle at the current I2C speed. | |
311 | * @return Zero if status is as expected, or a non-zero code if either a time | |
312 | * out occurred or the status was not the expected one. | |
306563a7 | 313 | */ |
3c4db636 | 314 | static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, |
c68c6243 | 315 | int expected_status, uint tick) |
4ce5a728 | 316 | { |
49c801bf | 317 | /* Write byte to data register for sending */ |
306563a7 | 318 | writel(byte, &twsi->data); |
49c801bf | 319 | /* Clear any pending interrupt -- that will cause sending */ |
670514f5 | 320 | writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, |
321 | &twsi->control); | |
49c801bf | 322 | /* Wait for controller to receive byte, and check ACK */ |
c68c6243 | 323 | return twsi_wait(twsi, expected_status, tick); |
4ce5a728 HS |
324 | } |
325 | ||
306563a7 | 326 | /* |
6e677caf | 327 | * twsi_recv() - Receive a byte on the I2C bus. |
328 | * | |
329 | * The static variable mvtwsi_control_flags controls whether we ack or nak. | |
330 | * | |
331 | * @twsi: The MVTWSI register structure to use. | |
332 | * @byte: The byte to send. | |
333 | * @ack_flag: Flag that determines whether the received byte should | |
334 | * be acknowledged by the controller or not (sent ACK/NAK). | |
335 | * @tick: The duration of a clock cycle at the current I2C speed. | |
336 | * @return Zero if status is as expected, or a non-zero code if either a time | |
337 | * out occurred or the status was not the expected one. | |
306563a7 | 338 | */ |
c68c6243 | 339 | static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, |
340 | uint tick) | |
4ce5a728 | 341 | { |
670514f5 | 342 | int expected_status, status, control; |
306563a7 | 343 | |
670514f5 | 344 | /* Compute expected status based on passed ACK flag */ |
345 | expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : | |
346 | MVTWSI_STATUS_DATA_R_NAK; | |
49c801bf | 347 | /* Acknowledge *previous state*, and launch receive */ |
670514f5 | 348 | control = MVTWSI_CONTROL_TWSIEN; |
349 | control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; | |
350 | writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); | |
49c801bf | 351 | /* Wait for controller to receive byte, and assert ACK or NAK */ |
c68c6243 | 352 | status = twsi_wait(twsi, expected_status, tick); |
49c801bf | 353 | /* If we did receive the expected byte, store it */ |
306563a7 AA |
354 | if (status == 0) |
355 | *byte = readl(&twsi->data); | |
306563a7 | 356 | return status; |
4ce5a728 HS |
357 | } |
358 | ||
306563a7 | 359 | /* |
6e677caf | 360 | * twsi_stop() - Assert a STOP condition on the bus. |
361 | * | |
362 | * This function is also used to force the bus back to idle state (SDA = | |
363 | * SCL = 1). | |
364 | * | |
365 | * @twsi: The MVTWSI register structure to use. | |
366 | * @tick: The duration of a clock cycle at the current I2C speed. | |
367 | * @return Zero if the operation succeeded, or a non-zero code if a time out | |
368 | * occurred. | |
306563a7 | 369 | */ |
c68c6243 | 370 | static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) |
4ce5a728 | 371 | { |
306563a7 | 372 | int control, stop_status; |
059fce9f | 373 | int status = 0; |
306563a7 AA |
374 | int timeout = 1000; |
375 | ||
49c801bf | 376 | /* Assert STOP */ |
306563a7 | 377 | control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; |
904dfbfd | 378 | writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); |
49c801bf | 379 | /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ |
306563a7 AA |
380 | do { |
381 | stop_status = readl(&twsi->status); | |
382 | if (stop_status == MVTWSI_STATUS_IDLE) | |
383 | break; | |
c68c6243 | 384 | ndelay(tick); /* One clock cycle */ |
306563a7 AA |
385 | } while (timeout--); |
386 | control = readl(&twsi->control); | |
387 | if (stop_status != MVTWSI_STATUS_IDLE) | |
059fce9f | 388 | status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, |
389 | control, status, MVTWSI_STATUS_IDLE); | |
306563a7 | 390 | return status; |
4ce5a728 HS |
391 | } |
392 | ||
6e677caf | 393 | /* |
394 | * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters. | |
395 | * | |
396 | * @n: Parameter 'n' for the frequency calculation algorithm. | |
397 | * @m: Parameter 'm' for the frequency calculation algorithm. | |
398 | * @return The I2C frequency corresponding to the passed m and n parameters. | |
399 | */ | |
e0758281 | 400 | static uint twsi_calc_freq(const int n, const int m) |
f582a158 | 401 | { |
aec9a0f1 | 402 | #ifdef CONFIG_ARCH_SUNXI |
f582a158 SR |
403 | return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); |
404 | #else | |
405 | return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); | |
406 | #endif | |
407 | } | |
306563a7 | 408 | |
306563a7 | 409 | /* |
6e677caf | 410 | * twsi_reset() - Reset the I2C controller. |
411 | * | |
412 | * Resetting the controller also resets the baud rate and slave address, hence | |
413 | * they must be re-established after the reset. | |
414 | * | |
415 | * @twsi: The MVTWSI register structure to use. | |
306563a7 | 416 | */ |
3c4db636 | 417 | static void twsi_reset(struct mvtwsi_registers *twsi) |
306563a7 | 418 | { |
49c801bf | 419 | /* Reset controller */ |
306563a7 | 420 | writel(0, &twsi->soft_reset); |
49c801bf | 421 | /* Wait 2 ms -- this is what the Marvell LSP does */ |
306563a7 | 422 | udelay(20000); |
4ce5a728 HS |
423 | } |
424 | ||
306563a7 | 425 | /* |
6e677caf | 426 | * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller. |
427 | * | |
428 | * This function sets baud rate to the highest possible value that does not | |
429 | * exceed the requested rate. | |
430 | * | |
431 | * @twsi: The MVTWSI register structure to use. | |
432 | * @requested_speed: The desired frequency the controller should run at | |
433 | * in Hz. | |
434 | * @return The actual frequency the controller was configured to. | |
306563a7 | 435 | */ |
3c4db636 | 436 | static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, |
61bc02b2 | 437 | uint requested_speed) |
4ce5a728 | 438 | { |
e0758281 | 439 | uint tmp_speed, highest_speed, n, m; |
440 | uint baud = 0x44; /* Baud rate after controller reset */ | |
306563a7 | 441 | |
306563a7 | 442 | highest_speed = 0; |
49c801bf | 443 | /* Successively try m, n combinations, and use the combination |
444 | * resulting in the largest speed that's not above the requested | |
445 | * speed */ | |
306563a7 AA |
446 | for (n = 0; n < 8; n++) { |
447 | for (m = 0; m < 16; m++) { | |
f582a158 | 448 | tmp_speed = twsi_calc_freq(n, m); |
9ec43b0c | 449 | if ((tmp_speed <= requested_speed) && |
450 | (tmp_speed > highest_speed)) { | |
306563a7 AA |
451 | highest_speed = tmp_speed; |
452 | baud = (m << 3) | n; | |
453 | } | |
454 | } | |
4ce5a728 | 455 | } |
0db2bbdc | 456 | writel(baud, &twsi->baudrate); |
c68c6243 | 457 | |
458 | /* Wait for controller for one tick */ | |
459 | #ifdef CONFIG_DM_I2C | |
460 | ndelay(calc_tick(highest_speed)); | |
461 | #else | |
462 | ndelay(10000); | |
463 | #endif | |
464 | return highest_speed; | |
0db2bbdc HG |
465 | } |
466 | ||
6e677caf | 467 | /* |
468 | * __twsi_i2c_init() - Initialize the I2C controller. | |
469 | * | |
470 | * @twsi: The MVTWSI register structure to use. | |
471 | * @speed: The initial frequency the controller should run at | |
472 | * in Hz. | |
473 | * @slaveadd: The I2C address to be set for the I2C master. | |
474 | * @actual_speed: A output parameter that receives the actual frequency | |
475 | * in Hz the controller was set to by the function. | |
476 | * @return Zero if the operation succeeded, or a non-zero code if a time out | |
477 | * occurred. | |
478 | */ | |
3c4db636 | 479 | static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, |
c68c6243 | 480 | int slaveadd, uint *actual_speed) |
0db2bbdc | 481 | { |
49c801bf | 482 | /* Reset controller */ |
3c4db636 | 483 | twsi_reset(twsi); |
49c801bf | 484 | /* Set speed */ |
c68c6243 | 485 | *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); |
49c801bf | 486 | /* Set slave address; even though we don't use it */ |
0db2bbdc HG |
487 | writel(slaveadd, &twsi->slave_address); |
488 | writel(0, &twsi->xtnd_slave_addr); | |
49c801bf | 489 | /* Assert STOP, but don't care for the result */ |
c68c6243 | 490 | #ifdef CONFIG_DM_I2C |
491 | (void) twsi_stop(twsi, calc_tick(*actual_speed)); | |
492 | #else | |
493 | (void) twsi_stop(twsi, 10000); | |
494 | #endif | |
4ce5a728 HS |
495 | } |
496 | ||
306563a7 | 497 | /* |
6e677caf | 498 | * i2c_begin() - Start a I2C transaction. |
499 | * | |
500 | * Begin a I2C transaction with a given expected start status and chip address. | |
501 | * A START is asserted, and the address byte is sent to the I2C controller. The | |
502 | * expected address status will be derived from the direction bit (bit 0) of | |
503 | * the address byte. | |
504 | * | |
505 | * @twsi: The MVTWSI register structure to use. | |
506 | * @expected_start_status: The I2C status the controller is expected to | |
507 | * assert after the address byte was sent. | |
508 | * @addr: The address byte to be sent. | |
509 | * @tick: The duration of a clock cycle at the current | |
510 | * I2C speed. | |
511 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
512 | * unexpected I2C status occurred. | |
306563a7 | 513 | */ |
3c4db636 | 514 | static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, |
c68c6243 | 515 | u8 addr, uint tick) |
4ce5a728 | 516 | { |
306563a7 AA |
517 | int status, expected_addr_status; |
518 | ||
49c801bf | 519 | /* Compute the expected address status from the direction bit in |
520 | * the address byte */ | |
521 | if (addr & 1) /* Reading */ | |
306563a7 | 522 | expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; |
49c801bf | 523 | else /* Writing */ |
306563a7 | 524 | expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; |
49c801bf | 525 | /* Assert START */ |
c68c6243 | 526 | status = twsi_start(twsi, expected_start_status, tick); |
49c801bf | 527 | /* Send out the address if the start went well */ |
306563a7 | 528 | if (status == 0) |
c68c6243 | 529 | status = twsi_send(twsi, addr, expected_addr_status, tick); |
49c801bf | 530 | /* Return 0, or the status of the first failure */ |
306563a7 | 531 | return status; |
4ce5a728 HS |
532 | } |
533 | ||
306563a7 | 534 | /* |
6e677caf | 535 | * __twsi_i2c_probe_chip() - Probe the given I2C chip address. |
536 | * | |
537 | * This function begins a I2C read transaction, does a dummy read and NAKs; if | |
538 | * the procedure succeeds, the chip is considered to be present. | |
539 | * | |
540 | * @twsi: The MVTWSI register structure to use. | |
541 | * @chip: The chip address to probe. | |
542 | * @tick: The duration of a clock cycle at the current I2C speed. | |
543 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
544 | * unexpected I2C status occurred. | |
306563a7 | 545 | */ |
c68c6243 | 546 | static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, |
547 | uint tick) | |
4ce5a728 | 548 | { |
306563a7 AA |
549 | u8 dummy_byte; |
550 | int status; | |
551 | ||
49c801bf | 552 | /* Begin i2c read */ |
c68c6243 | 553 | status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); |
49c801bf | 554 | /* Dummy read was accepted: receive byte, but NAK it. */ |
306563a7 | 555 | if (status == 0) |
c68c6243 | 556 | status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); |
306563a7 | 557 | /* Stop transaction */ |
c68c6243 | 558 | twsi_stop(twsi, tick); |
49c801bf | 559 | /* Return 0, or the status of the first failure */ |
306563a7 | 560 | return status; |
4ce5a728 HS |
561 | } |
562 | ||
306563a7 | 563 | /* |
6e677caf | 564 | * __twsi_i2c_read() - Read data from a I2C chip. |
565 | * | |
566 | * This function begins a I2C write transaction, and transmits the address | |
567 | * bytes; then begins a I2C read transaction, and receives the data bytes. | |
306563a7 | 568 | * |
49c801bf | 569 | * NOTE: Some devices want a stop right before the second start, while some |
570 | * will choke if it is there. Since deciding this is not yet supported in | |
571 | * higher level APIs, we need to make a decision here, and for the moment that | |
572 | * will be a repeated start without a preceding stop. | |
6e677caf | 573 | * |
574 | * @twsi: The MVTWSI register structure to use. | |
575 | * @chip: The chip address to read from. | |
576 | * @addr: The address bytes to send. | |
577 | * @alen: The length of the address bytes in bytes. | |
578 | * @data: The buffer to receive the data read from the chip (has to have | |
579 | * a size of at least 'length' bytes). | |
580 | * @length: The amount of data to be read from the chip in bytes. | |
581 | * @tick: The duration of a clock cycle at the current I2C speed. | |
582 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
583 | * unexpected I2C status occurred. | |
306563a7 | 584 | */ |
3c4db636 | 585 | static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, |
c68c6243 | 586 | u8 *addr, int alen, uchar *data, int length, |
587 | uint tick) | |
4ce5a728 | 588 | { |
059fce9f | 589 | int status = 0; |
590 | int stop_status; | |
24f9c6bb | 591 | int expected_start = MVTWSI_STATUS_START; |
592 | ||
593 | if (alen > 0) { | |
594 | /* Begin i2c write to send the address bytes */ | |
c68c6243 | 595 | status = i2c_begin(twsi, expected_start, (chip << 1), tick); |
24f9c6bb | 596 | /* Send address bytes */ |
597 | while ((status == 0) && alen--) | |
03d6cd97 | 598 | status = twsi_send(twsi, addr[alen], |
c68c6243 | 599 | MVTWSI_STATUS_DATA_W_ACK, tick); |
24f9c6bb | 600 | /* Send repeated STARTs after the initial START */ |
601 | expected_start = MVTWSI_STATUS_REPEATED_START; | |
602 | } | |
49c801bf | 603 | /* Begin i2c read to receive data bytes */ |
306563a7 | 604 | if (status == 0) |
c68c6243 | 605 | status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); |
670514f5 | 606 | /* Receive actual data bytes; set NAK if we if we have nothing more to |
607 | * read */ | |
608 | while ((status == 0) && length--) | |
3c4db636 | 609 | status = twsi_recv(twsi, data++, |
670514f5 | 610 | length > 0 ? |
c68c6243 | 611 | MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); |
306563a7 | 612 | /* Stop transaction */ |
c68c6243 | 613 | stop_status = twsi_stop(twsi, tick); |
49c801bf | 614 | /* Return 0, or the status of the first failure */ |
059fce9f | 615 | return status != 0 ? status : stop_status; |
4ce5a728 HS |
616 | } |
617 | ||
306563a7 | 618 | /* |
6e677caf | 619 | * __twsi_i2c_write() - Send data to a I2C chip. |
620 | * | |
621 | * This function begins a I2C write transaction, and transmits the address | |
622 | * bytes; then begins a new I2C write transaction, and sends the data bytes. | |
623 | * | |
624 | * @twsi: The MVTWSI register structure to use. | |
625 | * @chip: The chip address to read from. | |
626 | * @addr: The address bytes to send. | |
627 | * @alen: The length of the address bytes in bytes. | |
628 | * @data: The buffer containing the data to be sent to the chip. | |
629 | * @length: The length of data to be sent to the chip in bytes. | |
630 | * @tick: The duration of a clock cycle at the current I2C speed. | |
631 | * @return Zero if the operation succeeded, or a non-zero code if a time out or | |
632 | * unexpected I2C status occurred. | |
306563a7 | 633 | */ |
3c4db636 | 634 | static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, |
c68c6243 | 635 | u8 *addr, int alen, uchar *data, int length, |
636 | uint tick) | |
4ce5a728 | 637 | { |
059fce9f | 638 | int status, stop_status; |
306563a7 | 639 | |
49c801bf | 640 | /* Begin i2c write to send first the address bytes, then the |
641 | * data bytes */ | |
c68c6243 | 642 | status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); |
49c801bf | 643 | /* Send address bytes */ |
f8a10ed1 | 644 | while ((status == 0) && (alen-- > 0)) |
03d6cd97 | 645 | status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK, |
c68c6243 | 646 | tick); |
49c801bf | 647 | /* Send data bytes */ |
306563a7 | 648 | while ((status == 0) && (length-- > 0)) |
c68c6243 | 649 | status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, |
650 | tick); | |
306563a7 | 651 | /* Stop transaction */ |
c68c6243 | 652 | stop_status = twsi_stop(twsi, tick); |
49c801bf | 653 | /* Return 0, or the status of the first failure */ |
059fce9f | 654 | return status != 0 ? status : stop_status; |
4ce5a728 HS |
655 | } |
656 | ||
14a6ff2c | 657 | #ifndef CONFIG_DM_I2C |
61bc02b2 | 658 | static void twsi_i2c_init(struct i2c_adapter *adap, int speed, |
659 | int slaveadd) | |
660 | { | |
3c4db636 | 661 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 662 | __twsi_i2c_init(twsi, speed, slaveadd, NULL); |
61bc02b2 | 663 | } |
664 | ||
665 | static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, | |
666 | uint requested_speed) | |
667 | { | |
3c4db636 | 668 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 669 | __twsi_i2c_set_bus_speed(twsi, requested_speed); |
670 | return 0; | |
61bc02b2 | 671 | } |
672 | ||
673 | static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) | |
674 | { | |
3c4db636 | 675 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
c68c6243 | 676 | return __twsi_i2c_probe_chip(twsi, chip, 10000); |
61bc02b2 | 677 | } |
678 | ||
679 | static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, | |
680 | int alen, uchar *data, int length) | |
681 | { | |
3c4db636 | 682 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
f8a10ed1 | 683 | u8 addr_bytes[4]; |
684 | ||
685 | addr_bytes[0] = (addr >> 0) & 0xFF; | |
686 | addr_bytes[1] = (addr >> 8) & 0xFF; | |
687 | addr_bytes[2] = (addr >> 16) & 0xFF; | |
688 | addr_bytes[3] = (addr >> 24) & 0xFF; | |
689 | ||
c68c6243 | 690 | return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, |
691 | 10000); | |
61bc02b2 | 692 | } |
693 | ||
694 | static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, | |
695 | int alen, uchar *data, int length) | |
696 | { | |
3c4db636 | 697 | struct mvtwsi_registers *twsi = twsi_get_base(adap); |
f8a10ed1 | 698 | u8 addr_bytes[4]; |
699 | ||
700 | addr_bytes[0] = (addr >> 0) & 0xFF; | |
701 | addr_bytes[1] = (addr >> 8) & 0xFF; | |
702 | addr_bytes[2] = (addr >> 16) & 0xFF; | |
703 | addr_bytes[3] = (addr >> 24) & 0xFF; | |
704 | ||
c68c6243 | 705 | return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, |
706 | 10000); | |
61bc02b2 | 707 | } |
708 | ||
dd82242b | 709 | #ifdef CONFIG_I2C_MVTWSI_BASE0 |
0db2bbdc HG |
710 | U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, |
711 | twsi_i2c_read, twsi_i2c_write, | |
712 | twsi_i2c_set_bus_speed, | |
713 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) | |
dd82242b PK |
714 | #endif |
715 | #ifdef CONFIG_I2C_MVTWSI_BASE1 | |
716 | U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, | |
717 | twsi_i2c_read, twsi_i2c_write, | |
718 | twsi_i2c_set_bus_speed, | |
719 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) | |
720 | ||
721 | #endif | |
722 | #ifdef CONFIG_I2C_MVTWSI_BASE2 | |
723 | U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, | |
724 | twsi_i2c_read, twsi_i2c_write, | |
725 | twsi_i2c_set_bus_speed, | |
726 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) | |
727 | ||
728 | #endif | |
729 | #ifdef CONFIG_I2C_MVTWSI_BASE3 | |
730 | U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, | |
731 | twsi_i2c_read, twsi_i2c_write, | |
732 | twsi_i2c_set_bus_speed, | |
733 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) | |
734 | ||
735 | #endif | |
736 | #ifdef CONFIG_I2C_MVTWSI_BASE4 | |
737 | U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, | |
738 | twsi_i2c_read, twsi_i2c_write, | |
739 | twsi_i2c_set_bus_speed, | |
740 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) | |
741 | ||
742 | #endif | |
9d082687 JW |
743 | #ifdef CONFIG_I2C_MVTWSI_BASE5 |
744 | U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, | |
745 | twsi_i2c_read, twsi_i2c_write, | |
746 | twsi_i2c_set_bus_speed, | |
747 | CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) | |
748 | ||
749 | #endif | |
14a6ff2c | 750 | #else /* CONFIG_DM_I2C */ |
751 | ||
752 | static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, | |
753 | u32 chip_flags) | |
754 | { | |
755 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 756 | return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); |
14a6ff2c | 757 | } |
758 | ||
759 | static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) | |
760 | { | |
761 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 762 | |
763 | dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); | |
764 | dev->tick = calc_tick(dev->speed); | |
765 | ||
766 | return 0; | |
14a6ff2c | 767 | } |
768 | ||
769 | static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) | |
770 | { | |
771 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
772 | ||
773 | dev->base = dev_get_addr_ptr(bus); | |
774 | ||
775 | if (!dev->base) | |
776 | return -ENOMEM; | |
777 | ||
e160f7d4 | 778 | dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 779 | "cell-index", -1); |
e160f7d4 | 780 | dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 781 | "u-boot,i2c-slave-addr", 0x0); |
e160f7d4 | 782 | dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), |
14a6ff2c | 783 | "clock-frequency", 100000); |
784 | return 0; | |
785 | } | |
786 | ||
787 | static int mvtwsi_i2c_probe(struct udevice *bus) | |
788 | { | |
789 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
c68c6243 | 790 | uint actual_speed; |
791 | ||
792 | __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); | |
793 | dev->speed = actual_speed; | |
794 | dev->tick = calc_tick(dev->speed); | |
14a6ff2c | 795 | return 0; |
796 | } | |
797 | ||
798 | static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) | |
799 | { | |
800 | struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); | |
801 | struct i2c_msg *dmsg, *omsg, dummy; | |
802 | ||
803 | memset(&dummy, 0, sizeof(struct i2c_msg)); | |
804 | ||
805 | /* We expect either two messages (one with an offset and one with the | |
806 | * actual data) or one message (just data or offset/data combined) */ | |
807 | if (nmsgs > 2 || nmsgs == 0) { | |
808 | debug("%s: Only one or two messages are supported.", __func__); | |
809 | return -1; | |
810 | } | |
811 | ||
812 | omsg = nmsgs == 1 ? &dummy : msg; | |
813 | dmsg = nmsgs == 1 ? msg : msg + 1; | |
814 | ||
815 | if (dmsg->flags & I2C_M_RD) | |
816 | return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, | |
c68c6243 | 817 | omsg->len, dmsg->buf, dmsg->len, |
818 | dev->tick); | |
14a6ff2c | 819 | else |
820 | return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, | |
c68c6243 | 821 | omsg->len, dmsg->buf, dmsg->len, |
822 | dev->tick); | |
14a6ff2c | 823 | } |
824 | ||
825 | static const struct dm_i2c_ops mvtwsi_i2c_ops = { | |
826 | .xfer = mvtwsi_i2c_xfer, | |
827 | .probe_chip = mvtwsi_i2c_probe_chip, | |
828 | .set_bus_speed = mvtwsi_i2c_set_bus_speed, | |
829 | }; | |
830 | ||
831 | static const struct udevice_id mvtwsi_i2c_ids[] = { | |
832 | { .compatible = "marvell,mv64xxx-i2c", }, | |
87de0eb3 | 833 | { .compatible = "marvell,mv78230-i2c", }, |
14a6ff2c | 834 | { /* sentinel */ } |
835 | }; | |
836 | ||
837 | U_BOOT_DRIVER(i2c_mvtwsi) = { | |
838 | .name = "i2c_mvtwsi", | |
839 | .id = UCLASS_I2C, | |
840 | .of_match = mvtwsi_i2c_ids, | |
841 | .probe = mvtwsi_i2c_probe, | |
842 | .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, | |
843 | .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), | |
844 | .ops = &mvtwsi_i2c_ops, | |
845 | }; | |
846 | #endif /* CONFIG_DM_I2C */ |