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Commit | Line | Data |
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cdace066 | 1 | /* |
db84140b | 2 | * i2c driver for Freescale i.MX series |
cdace066 SH |
3 | * |
4 | * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
db84140b MV |
5 | * (c) 2011 Marek Vasut <marek.vasut@gmail.com> |
6 | * | |
7 | * Based on i2c-imx.c from linux kernel: | |
8 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> | |
9 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> | |
10 | * Copyright (C) 2007 RightHand Technologies, Inc. | |
11 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> | |
12 | * | |
cdace066 | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
cdace066 SH |
15 | */ |
16 | ||
17 | #include <common.h> | |
127cec18 | 18 | #include <asm/arch/clock.h> |
86271115 | 19 | #include <asm/arch/imx-regs.h> |
cea60b0c | 20 | #include <asm/errno.h> |
71204e95 | 21 | #include <asm/imx-common/mxc_i2c.h> |
24cd738b | 22 | #include <asm/io.h> |
bf0783df | 23 | #include <i2c.h> |
7aa57a01 | 24 | #include <watchdog.h> |
71204e95 | 25 | #include <dm.h> |
e1bed802 | 26 | #include <dm/pinctrl.h> |
71204e95 | 27 | #include <fdtdec.h> |
cdace066 | 28 | |
dec1861b YS |
29 | DECLARE_GLOBAL_DATA_PTR; |
30 | ||
71204e95 PF |
31 | #define I2C_QUIRK_FLAG (1 << 0) |
32 | ||
33 | #define IMX_I2C_REGSHIFT 2 | |
34 | #define VF610_I2C_REGSHIFT 0 | |
35 | /* Register index */ | |
36 | #define IADR 0 | |
37 | #define IFDR 1 | |
38 | #define I2CR 2 | |
39 | #define I2SR 3 | |
40 | #define I2DR 4 | |
cdace066 | 41 | |
cdace066 SH |
42 | #define I2CR_IIEN (1 << 6) |
43 | #define I2CR_MSTA (1 << 5) | |
44 | #define I2CR_MTX (1 << 4) | |
45 | #define I2CR_TX_NO_AK (1 << 3) | |
46 | #define I2CR_RSTA (1 << 2) | |
47 | ||
48 | #define I2SR_ICF (1 << 7) | |
49 | #define I2SR_IBB (1 << 5) | |
d5383a63 | 50 | #define I2SR_IAL (1 << 4) |
cdace066 SH |
51 | #define I2SR_IIF (1 << 1) |
52 | #define I2SR_RX_NO_AK (1 << 0) | |
53 | ||
30ea41a4 AW |
54 | #ifdef I2C_QUIRK_REG |
55 | #define I2CR_IEN (0 << 7) | |
56 | #define I2CR_IDIS (1 << 7) | |
57 | #define I2SR_IIF_CLEAR (1 << 1) | |
58 | #else | |
59 | #define I2CR_IEN (1 << 7) | |
60 | #define I2CR_IDIS (0 << 7) | |
61 | #define I2SR_IIF_CLEAR (0 << 1) | |
62 | #endif | |
63 | ||
e4ff525f | 64 | #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) |
de6f604d | 65 | #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" |
cdace066 SH |
66 | #endif |
67 | ||
30ea41a4 AW |
68 | #ifdef I2C_QUIRK_REG |
69 | static u16 i2c_clk_div[60][2] = { | |
70 | { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, | |
71 | { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, | |
72 | { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, | |
73 | { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, | |
74 | { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, | |
75 | { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, | |
76 | { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, | |
77 | { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, | |
78 | { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, | |
79 | { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, | |
80 | { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, | |
81 | { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, | |
82 | { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, | |
83 | { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, | |
84 | { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, | |
85 | }; | |
86 | #else | |
db84140b MV |
87 | static u16 i2c_clk_div[50][2] = { |
88 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, | |
89 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, | |
90 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, | |
91 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, | |
92 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, | |
93 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, | |
94 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, | |
95 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, | |
96 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, | |
97 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, | |
98 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, | |
99 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, | |
100 | { 3072, 0x1E }, { 3840, 0x1F } | |
101 | }; | |
30ea41a4 | 102 | #endif |
db84140b | 103 | |
fac96408 | 104 | #ifndef CONFIG_SYS_MXC_I2C1_SPEED |
105 | #define CONFIG_SYS_MXC_I2C1_SPEED 100000 | |
106 | #endif | |
107 | #ifndef CONFIG_SYS_MXC_I2C2_SPEED | |
108 | #define CONFIG_SYS_MXC_I2C2_SPEED 100000 | |
109 | #endif | |
110 | #ifndef CONFIG_SYS_MXC_I2C3_SPEED | |
111 | #define CONFIG_SYS_MXC_I2C3_SPEED 100000 | |
112 | #endif | |
f8cb101e YS |
113 | #ifndef CONFIG_SYS_MXC_I2C4_SPEED |
114 | #define CONFIG_SYS_MXC_I2C4_SPEED 100000 | |
115 | #endif | |
fac96408 | 116 | |
117 | #ifndef CONFIG_SYS_MXC_I2C1_SLAVE | |
118 | #define CONFIG_SYS_MXC_I2C1_SLAVE 0 | |
119 | #endif | |
120 | #ifndef CONFIG_SYS_MXC_I2C2_SLAVE | |
121 | #define CONFIG_SYS_MXC_I2C2_SLAVE 0 | |
122 | #endif | |
123 | #ifndef CONFIG_SYS_MXC_I2C3_SLAVE | |
124 | #define CONFIG_SYS_MXC_I2C3_SLAVE 0 | |
125 | #endif | |
f8cb101e YS |
126 | #ifndef CONFIG_SYS_MXC_I2C4_SLAVE |
127 | #define CONFIG_SYS_MXC_I2C4_SLAVE 0 | |
128 | #endif | |
fac96408 | 129 | |
db84140b MV |
130 | /* |
131 | * Calculate and set proper clock divider | |
132 | */ | |
71204e95 | 133 | static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) |
cdace066 | 134 | { |
db84140b MV |
135 | unsigned int i2c_clk_rate; |
136 | unsigned int div; | |
bf0783df | 137 | u8 clk_div; |
cdace066 | 138 | |
127cec18 | 139 | #if defined(CONFIG_MX31) |
1d549ade SB |
140 | struct clock_control_regs *sc_regs = |
141 | (struct clock_control_regs *)CCM_BASE; | |
db84140b | 142 | |
e7de18af | 143 | /* start the required I2C clock */ |
de6f604d | 144 | writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), |
1d549ade | 145 | &sc_regs->cgr0); |
127cec18 | 146 | #endif |
e7de18af | 147 | |
db84140b | 148 | /* Divider value calculation */ |
e7bed5c2 | 149 | i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); |
db84140b MV |
150 | div = (i2c_clk_rate + rate - 1) / rate; |
151 | if (div < i2c_clk_div[0][0]) | |
b567b8ff | 152 | clk_div = 0; |
db84140b | 153 | else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) |
b567b8ff | 154 | clk_div = ARRAY_SIZE(i2c_clk_div) - 1; |
db84140b | 155 | else |
b567b8ff | 156 | for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) |
db84140b MV |
157 | ; |
158 | ||
159 | /* Store divider value */ | |
bf0783df | 160 | return clk_div; |
db84140b | 161 | } |
cdace066 | 162 | |
db84140b | 163 | /* |
e4ff525f | 164 | * Set I2C Bus speed |
db84140b | 165 | */ |
71204e95 | 166 | static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) |
db84140b | 167 | { |
71204e95 PF |
168 | ulong base = i2c_bus->base; |
169 | bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; | |
170 | u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); | |
bf0783df | 171 | u8 idx = i2c_clk_div[clk_idx][1]; |
71204e95 | 172 | int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; |
bf0783df | 173 | |
e6c8b716 HS |
174 | if (!base) |
175 | return -ENODEV; | |
176 | ||
bf0783df | 177 | /* Store divider value */ |
71204e95 | 178 | writeb(idx, base + (IFDR << reg_shift)); |
bf0783df | 179 | |
83a1a190 | 180 | /* Reset module */ |
71204e95 PF |
181 | writeb(I2CR_IDIS, base + (I2CR << reg_shift)); |
182 | writeb(0, base + (I2SR << reg_shift)); | |
b567b8ff MV |
183 | return 0; |
184 | } | |
185 | ||
7aa57a01 TK |
186 | #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) |
187 | #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) | |
188 | #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) | |
81687212 | 189 | |
71204e95 | 190 | static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) |
cdace066 | 191 | { |
7aa57a01 TK |
192 | unsigned sr; |
193 | ulong elapsed; | |
71204e95 PF |
194 | bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; |
195 | int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
196 | ulong base = i2c_bus->base; | |
7aa57a01 TK |
197 | ulong start_time = get_timer(0); |
198 | for (;;) { | |
71204e95 | 199 | sr = readb(base + (I2SR << reg_shift)); |
d5383a63 | 200 | if (sr & I2SR_IAL) { |
71204e95 PF |
201 | if (quirk) |
202 | writeb(sr | I2SR_IAL, base + | |
203 | (I2SR << reg_shift)); | |
204 | else | |
205 | writeb(sr & ~I2SR_IAL, base + | |
206 | (I2SR << reg_shift)); | |
d5383a63 | 207 | printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", |
71204e95 PF |
208 | __func__, sr, readb(base + (I2CR << reg_shift)), |
209 | state); | |
d5383a63 TK |
210 | return -ERESTART; |
211 | } | |
7aa57a01 TK |
212 | if ((sr & (state >> 8)) == (unsigned char)state) |
213 | return sr; | |
214 | WATCHDOG_RESET(); | |
215 | elapsed = get_timer(start_time); | |
216 | if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ | |
217 | break; | |
db84140b | 218 | } |
7aa57a01 | 219 | printf("%s: failed sr=%x cr=%x state=%x\n", __func__, |
71204e95 | 220 | sr, readb(base + (I2CR << reg_shift)), state); |
cea60b0c | 221 | return -ETIMEDOUT; |
cdace066 SH |
222 | } |
223 | ||
71204e95 | 224 | static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) |
81687212 | 225 | { |
cea60b0c | 226 | int ret; |
71204e95 PF |
227 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? |
228 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
229 | ulong base = i2c_bus->base; | |
81687212 | 230 | |
71204e95 PF |
231 | writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); |
232 | writeb(byte, base + (I2DR << reg_shift)); | |
233 | ||
234 | ret = wait_for_sr_state(i2c_bus, ST_IIF); | |
cea60b0c TK |
235 | if (ret < 0) |
236 | return ret; | |
cea60b0c TK |
237 | if (ret & I2SR_RX_NO_AK) |
238 | return -ENODEV; | |
239 | return 0; | |
db84140b | 240 | } |
81687212 | 241 | |
71204e95 PF |
242 | /* |
243 | * Stub implementations for outer i2c slave operations. | |
244 | */ | |
245 | void __i2c_force_reset_slave(void) | |
246 | { | |
247 | } | |
248 | void i2c_force_reset_slave(void) | |
249 | __attribute__((weak, alias("__i2c_force_reset_slave"))); | |
250 | ||
db84140b | 251 | /* |
90a5b70f | 252 | * Stop I2C transaction |
db84140b | 253 | */ |
71204e95 | 254 | static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) |
cdace066 | 255 | { |
7aa57a01 | 256 | int ret; |
71204e95 PF |
257 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? |
258 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
259 | ulong base = i2c_bus->base; | |
260 | unsigned int temp = readb(base + (I2CR << reg_shift)); | |
db84140b | 261 | |
1c076dba | 262 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
71204e95 PF |
263 | writeb(temp, base + (I2CR << reg_shift)); |
264 | ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); | |
7aa57a01 TK |
265 | if (ret < 0) |
266 | printf("%s:trigger stop failed\n", __func__); | |
cdace066 SH |
267 | } |
268 | ||
db84140b | 269 | /* |
b230ddc2 TK |
270 | * Send start signal, chip address and |
271 | * write register address | |
db84140b | 272 | */ |
71204e95 PF |
273 | static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, |
274 | u32 addr, int alen) | |
cdace066 | 275 | { |
71e9f3cb TK |
276 | unsigned int temp; |
277 | int ret; | |
71204e95 PF |
278 | bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; |
279 | ulong base = i2c_bus->base; | |
280 | int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
281 | ||
282 | /* Reset i2c slave */ | |
283 | i2c_force_reset_slave(); | |
71e9f3cb TK |
284 | |
285 | /* Enable I2C controller */ | |
71204e95 PF |
286 | if (quirk) |
287 | ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; | |
288 | else | |
289 | ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); | |
290 | ||
291 | if (ret) { | |
292 | writeb(I2CR_IEN, base + (I2CR << reg_shift)); | |
90a5b70f TK |
293 | /* Wait for controller to be stable */ |
294 | udelay(50); | |
295 | } | |
71204e95 PF |
296 | |
297 | if (readb(base + (IADR << reg_shift)) == (chip << 1)) | |
298 | writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); | |
299 | writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); | |
300 | ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); | |
90a5b70f | 301 | if (ret < 0) |
a7f1a005 | 302 | return ret; |
71e9f3cb TK |
303 | |
304 | /* Start I2C transaction */ | |
71204e95 | 305 | temp = readb(base + (I2CR << reg_shift)); |
71e9f3cb | 306 | temp |= I2CR_MSTA; |
71204e95 | 307 | writeb(temp, base + (I2CR << reg_shift)); |
71e9f3cb | 308 | |
71204e95 | 309 | ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); |
71e9f3cb | 310 | if (ret < 0) |
a7f1a005 | 311 | return ret; |
b230ddc2 | 312 | |
71e9f3cb | 313 | temp |= I2CR_MTX | I2CR_TX_NO_AK; |
71204e95 | 314 | writeb(temp, base + (I2CR << reg_shift)); |
71e9f3cb | 315 | |
b230ddc2 | 316 | /* write slave address */ |
71204e95 | 317 | ret = tx_byte(i2c_bus, chip << 1); |
b230ddc2 | 318 | if (ret < 0) |
a7f1a005 | 319 | return ret; |
db84140b | 320 | |
bf0783df | 321 | while (alen--) { |
71204e95 | 322 | ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); |
cea60b0c | 323 | if (ret < 0) |
a7f1a005 | 324 | return ret; |
81687212 | 325 | } |
b230ddc2 | 326 | return 0; |
a7f1a005 TK |
327 | } |
328 | ||
71204e95 PF |
329 | #ifndef CONFIG_DM_I2C |
330 | int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) | |
331 | { | |
332 | if (i2c_bus && i2c_bus->idle_bus_fn) | |
333 | return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); | |
334 | return 0; | |
335 | } | |
336 | #else | |
337 | /* | |
e1bed802 PF |
338 | * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt |
339 | * " | |
340 | * scl-gpios: specify the gpio related to SCL pin | |
341 | * sda-gpios: specify the gpio related to SDA pin | |
342 | * add pinctrl to configure i2c pins to gpio function for i2c | |
343 | * bus recovery, call it "gpio" state | |
344 | * " | |
345 | * | |
346 | * The i2c_idle_bus is an implementation following Linux Kernel. | |
71204e95 | 347 | */ |
e1bed802 | 348 | int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) |
71204e95 | 349 | { |
e1bed802 PF |
350 | struct udevice *bus = i2c_bus->bus; |
351 | struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio; | |
352 | struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio; | |
353 | int sda, scl; | |
354 | int i, ret = 0; | |
355 | ulong elapsed, start_time; | |
96c19bd3 | 356 | |
e1bed802 PF |
357 | if (pinctrl_select_state(bus, "gpio")) { |
358 | dev_dbg(bus, "Can not to switch to use gpio pinmux\n"); | |
359 | /* | |
360 | * GPIO pinctrl for i2c force idle is not a must, | |
361 | * but it is strongly recommended to be used. | |
362 | * Because it can help you to recover from bad | |
363 | * i2c bus state. Do not return failure, because | |
364 | * it is not a must. | |
365 | */ | |
366 | return 0; | |
367 | } | |
368 | ||
369 | dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); | |
370 | dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); | |
371 | scl = dm_gpio_get_value(scl_gpio); | |
372 | sda = dm_gpio_get_value(sda_gpio); | |
373 | ||
374 | if ((sda & scl) == 1) | |
375 | goto exit; /* Bus is idle already */ | |
376 | ||
377 | /* Send high and low on the SCL line */ | |
378 | for (i = 0; i < 9; i++) { | |
379 | dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT); | |
380 | dm_gpio_set_value(scl_gpio, 0); | |
381 | udelay(50); | |
382 | dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); | |
383 | udelay(50); | |
384 | } | |
385 | start_time = get_timer(0); | |
386 | for (;;) { | |
387 | dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); | |
388 | dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); | |
389 | scl = dm_gpio_get_value(scl_gpio); | |
390 | sda = dm_gpio_get_value(sda_gpio); | |
391 | if ((sda & scl) == 1) | |
392 | break; | |
393 | WATCHDOG_RESET(); | |
394 | elapsed = get_timer(start_time); | |
395 | if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ | |
396 | ret = -EBUSY; | |
397 | printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl); | |
398 | break; | |
399 | } | |
400 | } | |
401 | ||
402 | exit: | |
403 | pinctrl_select_state(bus, "default"); | |
404 | return ret; | |
405 | } | |
71204e95 PF |
406 | #endif |
407 | ||
408 | static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, | |
409 | u32 addr, int alen) | |
a7f1a005 TK |
410 | { |
411 | int retry; | |
412 | int ret; | |
71204e95 PF |
413 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? |
414 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
e6c8b716 HS |
415 | |
416 | if (!i2c_bus->base) | |
417 | return -ENODEV; | |
418 | ||
a7f1a005 | 419 | for (retry = 0; retry < 3; retry++) { |
71204e95 | 420 | ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); |
a7f1a005 TK |
421 | if (ret >= 0) |
422 | return 0; | |
71204e95 | 423 | i2c_imx_stop(i2c_bus); |
a7f1a005 TK |
424 | if (ret == -ENODEV) |
425 | return ret; | |
426 | ||
427 | printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, | |
428 | retry); | |
429 | if (ret != -ERESTART) | |
30ea41a4 | 430 | /* Disable controller */ |
71204e95 | 431 | writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); |
a7f1a005 | 432 | udelay(100); |
71204e95 | 433 | if (i2c_idle_bus(i2c_bus) < 0) |
96c19bd3 | 434 | break; |
a7f1a005 | 435 | } |
71204e95 | 436 | printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); |
db84140b | 437 | return ret; |
cdace066 SH |
438 | } |
439 | ||
71204e95 PF |
440 | |
441 | static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, | |
442 | int len) | |
443 | { | |
444 | int i, ret = 0; | |
445 | ||
446 | debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); | |
447 | debug("write_data: "); | |
448 | /* use rc for counter */ | |
449 | for (i = 0; i < len; ++i) | |
450 | debug(" 0x%02x", buf[i]); | |
451 | debug("\n"); | |
452 | ||
453 | for (i = 0; i < len; i++) { | |
454 | ret = tx_byte(i2c_bus, buf[i]); | |
455 | if (ret < 0) { | |
456 | debug("i2c_write_data(): rc=%d\n", ret); | |
457 | break; | |
458 | } | |
459 | } | |
460 | ||
461 | return ret; | |
462 | } | |
463 | ||
464 | static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, | |
465 | int len) | |
db84140b | 466 | { |
db84140b MV |
467 | int ret; |
468 | unsigned int temp; | |
469 | int i; | |
71204e95 PF |
470 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? |
471 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
472 | ulong base = i2c_bus->base; | |
db84140b | 473 | |
71204e95 | 474 | debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); |
db84140b MV |
475 | |
476 | /* setup bus to read data */ | |
71204e95 | 477 | temp = readb(base + (I2CR << reg_shift)); |
db84140b MV |
478 | temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); |
479 | if (len == 1) | |
480 | temp |= I2CR_TX_NO_AK; | |
71204e95 PF |
481 | writeb(temp, base + (I2CR << reg_shift)); |
482 | writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); | |
483 | /* dummy read to clear ICF */ | |
484 | readb(base + (I2DR << reg_shift)); | |
db84140b MV |
485 | |
486 | /* read data */ | |
487 | for (i = 0; i < len; i++) { | |
71204e95 | 488 | ret = wait_for_sr_state(i2c_bus, ST_IIF); |
7aa57a01 | 489 | if (ret < 0) { |
71204e95 PF |
490 | debug("i2c_read_data(): ret=%d\n", ret); |
491 | i2c_imx_stop(i2c_bus); | |
db84140b | 492 | return ret; |
c4330d28 | 493 | } |
db84140b MV |
494 | |
495 | /* | |
496 | * It must generate STOP before read I2DR to prevent | |
497 | * controller from generating another clock cycle | |
498 | */ | |
499 | if (i == (len - 1)) { | |
71204e95 | 500 | i2c_imx_stop(i2c_bus); |
db84140b | 501 | } else if (i == (len - 2)) { |
71204e95 | 502 | temp = readb(base + (I2CR << reg_shift)); |
db84140b | 503 | temp |= I2CR_TX_NO_AK; |
71204e95 | 504 | writeb(temp, base + (I2CR << reg_shift)); |
db84140b | 505 | } |
71204e95 PF |
506 | writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); |
507 | buf[i] = readb(base + (I2DR << reg_shift)); | |
cdace066 | 508 | } |
71204e95 PF |
509 | |
510 | /* reuse ret for counter*/ | |
511 | for (ret = 0; ret < len; ++ret) | |
512 | debug(" 0x%02x", buf[ret]); | |
513 | debug("\n"); | |
514 | ||
515 | i2c_imx_stop(i2c_bus); | |
7aa57a01 | 516 | return 0; |
cdace066 SH |
517 | } |
518 | ||
71204e95 | 519 | #ifndef CONFIG_DM_I2C |
db84140b | 520 | /* |
71204e95 | 521 | * Read data from I2C device |
db84140b | 522 | */ |
71204e95 PF |
523 | static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, |
524 | int alen, u8 *buf, int len) | |
cdace066 | 525 | { |
71204e95 PF |
526 | int ret = 0; |
527 | u32 temp; | |
528 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? | |
529 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
530 | ulong base = i2c_bus->base; | |
cdace066 | 531 | |
71204e95 | 532 | ret = i2c_init_transfer(i2c_bus, chip, addr, alen); |
cea60b0c | 533 | if (ret < 0) |
db84140b | 534 | return ret; |
cdace066 | 535 | |
71204e95 PF |
536 | temp = readb(base + (I2CR << reg_shift)); |
537 | temp |= I2CR_RSTA; | |
538 | writeb(temp, base + (I2CR << reg_shift)); | |
539 | ||
540 | ret = tx_byte(i2c_bus, (chip << 1) | 1); | |
541 | if (ret < 0) { | |
542 | i2c_imx_stop(i2c_bus); | |
543 | return ret; | |
db84140b | 544 | } |
71204e95 PF |
545 | |
546 | ret = i2c_read_data(i2c_bus, chip, buf, len); | |
547 | ||
548 | i2c_imx_stop(i2c_bus); | |
549 | return ret; | |
550 | } | |
551 | ||
552 | /* | |
553 | * Write data to I2C device | |
554 | */ | |
555 | static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, | |
556 | int alen, const u8 *buf, int len) | |
557 | { | |
558 | int ret = 0; | |
559 | ||
560 | ret = i2c_init_transfer(i2c_bus, chip, addr, alen); | |
561 | if (ret < 0) | |
562 | return ret; | |
563 | ||
564 | ret = i2c_write_data(i2c_bus, chip, buf, len); | |
565 | ||
566 | i2c_imx_stop(i2c_bus); | |
567 | ||
db84140b MV |
568 | return ret; |
569 | } | |
cfbb88d3 | 570 | |
e6c8b716 HS |
571 | #if !defined(I2C2_BASE_ADDR) |
572 | #define I2C2_BASE_ADDR 0 | |
21a26940 | 573 | #endif |
e6c8b716 HS |
574 | |
575 | #if !defined(I2C3_BASE_ADDR) | |
576 | #define I2C3_BASE_ADDR 0 | |
577 | #endif | |
578 | ||
579 | #if !defined(I2C4_BASE_ADDR) | |
580 | #define I2C4_BASE_ADDR 0 | |
581 | #endif | |
582 | ||
583 | static struct mxc_i2c_bus mxc_i2c_buses[] = { | |
9f3183d2 MH |
584 | #if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \ |
585 | defined(CONFIG_FSL_LAYERSCAPE) | |
71204e95 PF |
586 | { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, |
587 | { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, | |
588 | { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, | |
589 | { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, | |
e4ff525f | 590 | #else |
e6c8b716 HS |
591 | { 0, I2C1_BASE_ADDR, 0 }, |
592 | { 1, I2C2_BASE_ADDR, 0 }, | |
593 | { 2, I2C3_BASE_ADDR, 0 }, | |
594 | { 3, I2C4_BASE_ADDR, 0 }, | |
e4ff525f | 595 | #endif |
fac96408 | 596 | }; |
597 | ||
71204e95 | 598 | struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) |
96c19bd3 | 599 | { |
71204e95 | 600 | return &mxc_i2c_buses[adap->hwadapnr]; |
96c19bd3 TK |
601 | } |
602 | ||
fac96408 | 603 | static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, |
604 | uint addr, int alen, uint8_t *buffer, | |
605 | int len) | |
e4ff525f | 606 | { |
fac96408 | 607 | return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); |
e4ff525f TK |
608 | } |
609 | ||
fac96408 | 610 | static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, |
611 | uint addr, int alen, uint8_t *buffer, | |
612 | int len) | |
e4ff525f | 613 | { |
fac96408 | 614 | return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); |
e4ff525f TK |
615 | } |
616 | ||
cfbb88d3 TK |
617 | /* |
618 | * Test if a chip at a given address responds (probe the chip) | |
619 | */ | |
fac96408 | 620 | static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) |
cfbb88d3 | 621 | { |
fac96408 | 622 | return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); |
e4ff525f TK |
623 | } |
624 | ||
71204e95 PF |
625 | int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) |
626 | { | |
627 | return 1; | |
628 | } | |
629 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) | |
630 | __attribute__((weak, alias("__enable_i2c_clk"))); | |
631 | ||
632 | void bus_i2c_init(int index, int speed, int unused, | |
633 | int (*idle_bus_fn)(void *p), void *idle_bus_data) | |
e4ff525f | 634 | { |
71204e95 PF |
635 | int ret; |
636 | ||
637 | if (index >= ARRAY_SIZE(mxc_i2c_buses)) { | |
638 | debug("Error i2c index\n"); | |
e4ff525f | 639 | return; |
e4ff525f | 640 | } |
71204e95 | 641 | |
aee3fddb GQ |
642 | /* |
643 | * Warning: Be careful to allow the assignment to a static | |
644 | * variable here. This function could be called while U-Boot is | |
645 | * still running in flash memory. So such assignment is equal | |
646 | * to write data to flash without erasing. | |
647 | */ | |
648 | if (idle_bus_fn) | |
649 | mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; | |
650 | if (idle_bus_data) | |
651 | mxc_i2c_buses[index].idle_bus_data = idle_bus_data; | |
71204e95 PF |
652 | |
653 | ret = enable_i2c_clk(1, index); | |
654 | if (ret < 0) { | |
655 | debug("I2C-%d clk fail to enable.\n", index); | |
656 | return; | |
657 | } | |
658 | ||
659 | bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); | |
e4ff525f TK |
660 | } |
661 | ||
662 | /* | |
663 | * Init I2C Bus | |
664 | */ | |
fac96408 | 665 | static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
e4ff525f | 666 | { |
71204e95 | 667 | bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); |
e4ff525f TK |
668 | } |
669 | ||
670 | /* | |
671 | * Set I2C Speed | |
672 | */ | |
71204e95 | 673 | static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) |
e4ff525f | 674 | { |
fac96408 | 675 | return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); |
e4ff525f TK |
676 | } |
677 | ||
678 | /* | |
fac96408 | 679 | * Register mxc i2c adapters |
e4ff525f | 680 | */ |
03544c66 | 681 | #ifdef CONFIG_SYS_I2C_MXC_I2C1 |
fac96408 | 682 | U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, |
683 | mxc_i2c_read, mxc_i2c_write, | |
684 | mxc_i2c_set_bus_speed, | |
685 | CONFIG_SYS_MXC_I2C1_SPEED, | |
686 | CONFIG_SYS_MXC_I2C1_SLAVE, 0) | |
03544c66 AA |
687 | #endif |
688 | ||
689 | #ifdef CONFIG_SYS_I2C_MXC_I2C2 | |
fac96408 | 690 | U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, |
691 | mxc_i2c_read, mxc_i2c_write, | |
692 | mxc_i2c_set_bus_speed, | |
693 | CONFIG_SYS_MXC_I2C2_SPEED, | |
694 | CONFIG_SYS_MXC_I2C2_SLAVE, 1) | |
03544c66 AA |
695 | #endif |
696 | ||
f8cb101e | 697 | #ifdef CONFIG_SYS_I2C_MXC_I2C3 |
fac96408 | 698 | U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, |
699 | mxc_i2c_read, mxc_i2c_write, | |
700 | mxc_i2c_set_bus_speed, | |
701 | CONFIG_SYS_MXC_I2C3_SPEED, | |
702 | CONFIG_SYS_MXC_I2C3_SLAVE, 2) | |
703 | #endif | |
71204e95 | 704 | |
f8cb101e YS |
705 | #ifdef CONFIG_SYS_I2C_MXC_I2C4 |
706 | U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, | |
707 | mxc_i2c_read, mxc_i2c_write, | |
708 | mxc_i2c_set_bus_speed, | |
709 | CONFIG_SYS_MXC_I2C4_SPEED, | |
710 | CONFIG_SYS_MXC_I2C4_SLAVE, 3) | |
711 | #endif | |
71204e95 PF |
712 | |
713 | #else | |
714 | ||
715 | static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) | |
716 | { | |
717 | struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); | |
718 | ||
719 | return bus_i2c_set_bus_speed(i2c_bus, speed); | |
720 | } | |
721 | ||
722 | static int mxc_i2c_probe(struct udevice *bus) | |
723 | { | |
724 | struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); | |
e1bed802 PF |
725 | const void *fdt = gd->fdt_blob; |
726 | int node = bus->of_offset; | |
71204e95 | 727 | fdt_addr_t addr; |
e1bed802 | 728 | int ret, ret2; |
71204e95 PF |
729 | |
730 | i2c_bus->driver_data = dev_get_driver_data(bus); | |
731 | ||
732 | addr = dev_get_addr(bus); | |
733 | if (addr == FDT_ADDR_T_NONE) | |
734 | return -ENODEV; | |
735 | ||
736 | i2c_bus->base = addr; | |
737 | i2c_bus->index = bus->seq; | |
e1bed802 | 738 | i2c_bus->bus = bus; |
71204e95 PF |
739 | |
740 | /* Enable clk */ | |
741 | ret = enable_i2c_clk(1, bus->seq); | |
742 | if (ret < 0) | |
743 | return ret; | |
744 | ||
e1bed802 PF |
745 | /* |
746 | * See Documentation/devicetree/bindings/i2c/i2c-imx.txt | |
747 | * Use gpio to force bus idle when necessary. | |
748 | */ | |
749 | ret = fdt_find_string(fdt, node, "pinctrl-names", "gpio"); | |
750 | if (ret < 0) { | |
751 | dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); | |
752 | } else { | |
753 | ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios", | |
754 | 0, &i2c_bus->scl_gpio, | |
755 | GPIOD_IS_OUT); | |
756 | ret2 = gpio_request_by_name_nodev(fdt, node, "sda-gpios", | |
757 | 0, &i2c_bus->sda_gpio, | |
758 | GPIOD_IS_OUT); | |
759 | if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) | | |
760 | !dm_gpio_is_valid(&i2c_bus->scl_gpio) | | |
761 | ret | ret2) { | |
762 | dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); | |
763 | return -ENODEV; | |
764 | } | |
765 | } | |
766 | ||
71204e95 PF |
767 | ret = i2c_idle_bus(i2c_bus); |
768 | if (ret < 0) { | |
769 | /* Disable clk */ | |
770 | enable_i2c_clk(0, bus->seq); | |
771 | return ret; | |
772 | } | |
773 | ||
774 | /* | |
775 | * Pinmux settings are in board file now, until pinmux is supported, | |
776 | * we can set pinmux here in probe function. | |
777 | */ | |
778 | ||
779 | debug("i2c : controller bus %d at %lu , speed %d: ", | |
780 | bus->seq, i2c_bus->base, | |
781 | i2c_bus->speed); | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, | |
787 | u32 chip_flags) | |
788 | { | |
789 | int ret; | |
790 | struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); | |
791 | ||
792 | ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); | |
793 | if (ret < 0) { | |
794 | debug("%s failed, ret = %d\n", __func__, ret); | |
795 | return ret; | |
796 | } | |
797 | ||
798 | i2c_imx_stop(i2c_bus); | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) | |
804 | { | |
805 | struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); | |
806 | int ret = 0; | |
807 | ulong base = i2c_bus->base; | |
808 | int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? | |
809 | VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; | |
810 | ||
811 | /* | |
812 | * Here the 3rd parameter addr and the 4th one alen are set to 0, | |
813 | * because here we only want to send out chip address. The register | |
814 | * address is wrapped in msg. | |
815 | */ | |
816 | ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); | |
817 | if (ret < 0) { | |
818 | debug("i2c_init_transfer error: %d\n", ret); | |
819 | return ret; | |
820 | } | |
821 | ||
822 | for (; nmsgs > 0; nmsgs--, msg++) { | |
823 | bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); | |
824 | debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); | |
825 | if (msg->flags & I2C_M_RD) | |
826 | ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, | |
827 | msg->len); | |
828 | else { | |
829 | ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, | |
830 | msg->len); | |
831 | if (ret) | |
832 | break; | |
833 | if (next_is_read) { | |
834 | /* Reuse ret */ | |
835 | ret = readb(base + (I2CR << reg_shift)); | |
836 | ret |= I2CR_RSTA; | |
837 | writeb(ret, base + (I2CR << reg_shift)); | |
838 | ||
839 | ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); | |
840 | if (ret < 0) { | |
841 | i2c_imx_stop(i2c_bus); | |
842 | break; | |
843 | } | |
844 | } | |
845 | } | |
846 | } | |
847 | ||
848 | if (ret) | |
849 | debug("i2c_write: error sending\n"); | |
850 | ||
851 | i2c_imx_stop(i2c_bus); | |
852 | ||
853 | return ret; | |
854 | } | |
855 | ||
856 | static const struct dm_i2c_ops mxc_i2c_ops = { | |
857 | .xfer = mxc_i2c_xfer, | |
858 | .probe_chip = mxc_i2c_probe_chip, | |
859 | .set_bus_speed = mxc_i2c_set_bus_speed, | |
860 | }; | |
861 | ||
862 | static const struct udevice_id mxc_i2c_ids[] = { | |
863 | { .compatible = "fsl,imx21-i2c", }, | |
864 | { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, | |
865 | {} | |
866 | }; | |
867 | ||
868 | U_BOOT_DRIVER(i2c_mxc) = { | |
869 | .name = "i2c_mxc", | |
870 | .id = UCLASS_I2C, | |
871 | .of_match = mxc_i2c_ids, | |
872 | .probe = mxc_i2c_probe, | |
873 | .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), | |
874 | .ops = &mxc_i2c_ops, | |
875 | }; | |
876 | #endif |