[people/ms/u-boot.git] / drivers / i2c / mxc_i2c.c

/*
 * i2c driver for Freescale i.MX series
 *
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
 *
 * Based on i2c-imx.c from linux kernel:
 *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
 *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
 *  Copyright (C) 2007 RightHand Technologies, Inc.
 *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <i2c.h>
#include <watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef I2C_QUIRK_REG
struct mxc_i2c_regs {
	uint8_t		iadr;
	uint8_t		ifdr;
	uint8_t		i2cr;
	uint8_t		i2sr;
	uint8_t		i2dr;
};
#else
struct mxc_i2c_regs {
	uint32_t	iadr;
	uint32_t	ifdr;
	uint32_t	i2cr;
	uint32_t	i2sr;
	uint32_t	i2dr;
};
#endif

#define I2CR_IIEN	(1 << 6)
#define I2CR_MSTA	(1 << 5)
#define I2CR_MTX	(1 << 4)
#define I2CR_TX_NO_AK	(1 << 3)
#define I2CR_RSTA	(1 << 2)

#define I2SR_ICF	(1 << 7)
#define I2SR_IBB	(1 << 5)
#define I2SR_IAL	(1 << 4)
#define I2SR_IIF	(1 << 1)
#define I2SR_RX_NO_AK	(1 << 0)

#ifdef I2C_QUIRK_REG
#define I2CR_IEN	(0 << 7)
#define I2CR_IDIS	(1 << 7)
#define I2SR_IIF_CLEAR	(1 << 1)
#else
#define I2CR_IEN	(1 << 7)
#define I2CR_IDIS	(0 << 7)
#define I2SR_IIF_CLEAR	(0 << 1)
#endif

#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif

#ifdef I2C_QUIRK_REG
static u16 i2c_clk_div[60][2] = {
	{ 20,	0x00 }, { 22,	0x01 }, { 24,	0x02 }, { 26,	0x03 },
	{ 28,	0x04 },	{ 30,	0x05 },	{ 32,	0x09 }, { 34,	0x06 },
	{ 36,	0x0A }, { 40,	0x07 }, { 44,	0x0C }, { 48,	0x0D },
	{ 52,	0x43 },	{ 56,	0x0E }, { 60,	0x45 }, { 64,	0x12 },
	{ 68,	0x0F },	{ 72,	0x13 },	{ 80,	0x14 },	{ 88,	0x15 },
	{ 96,	0x19 },	{ 104,	0x16 },	{ 112,	0x1A },	{ 128,	0x17 },
	{ 136,	0x4F }, { 144,	0x1C },	{ 160,	0x1D }, { 176,	0x55 },
	{ 192,	0x1E }, { 208,	0x56 },	{ 224,	0x22 }, { 228,	0x24 },
	{ 240,	0x1F },	{ 256,	0x23 }, { 288,	0x5C },	{ 320,	0x25 },
	{ 384,	0x26 }, { 448,	0x2A },	{ 480,	0x27 }, { 512,	0x2B },
	{ 576,	0x2C },	{ 640,	0x2D },	{ 768,	0x31 }, { 896,	0x32 },
	{ 960,	0x2F },	{ 1024,	0x33 },	{ 1152,	0x34 }, { 1280,	0x35 },
	{ 1536,	0x36 }, { 1792,	0x3A },	{ 1920,	0x37 },	{ 2048,	0x3B },
	{ 2304,	0x3C },	{ 2560,	0x3D },	{ 3072,	0x3E }, { 3584,	0x7A },
	{ 3840,	0x3F }, { 4096,	0x7B }, { 5120,	0x7D },	{ 6144,	0x7E },
};
#else
static u16 i2c_clk_div[50][2] = {
	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
	{ 30,	0x00 }, { 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
	{ 42,	0x03 }, { 44,	0x27 }, { 48,	0x28 }, { 52,	0x05 },
	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A }, { 72,	0x2B },
	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
	{ 192,	0x31 }, { 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
	{ 288,	0x10 }, { 320,	0x34 }, { 384,	0x35 }, { 448,	0x36 },
	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 }, { 640,	0x38 },
	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
	{ 1920,	0x1B }, { 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
	{ 3072,	0x1E }, { 3840,	0x1F }
};
#endif


#ifndef CONFIG_SYS_MXC_I2C1_SPEED
#define CONFIG_SYS_MXC_I2C1_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SPEED
#define CONFIG_SYS_MXC_I2C2_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SPEED
#define CONFIG_SYS_MXC_I2C3_SPEED 100000
#endif

#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
#define CONFIG_SYS_MXC_I2C1_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
#define CONFIG_SYS_MXC_I2C2_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
#define CONFIG_SYS_MXC_I2C3_SLAVE 0
#endif


/*
 * Calculate and set proper clock divider
 */
static uint8_t i2c_imx_get_clk(unsigned int rate)
{
	unsigned int i2c_clk_rate;
	unsigned int div;
	u8 clk_div;

#if defined(CONFIG_MX31)
	struct clock_control_regs *sc_regs =
		(struct clock_control_regs *)CCM_BASE;

	/* start the required I2C clock */
	writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
		&sc_regs->cgr0);
#endif

	/* Divider value calculation */
	i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
	div = (i2c_clk_rate + rate - 1) / rate;
	if (div < i2c_clk_div[0][0])
		clk_div = 0;
	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
		clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
	else
		for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
			;

	/* Store divider value */
	return clk_div;
}

/*
 * Set I2C Bus speed
 */
static int bus_i2c_set_bus_speed(void *base, int speed)
{
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
	u8 clk_idx = i2c_imx_get_clk(speed);
	u8 idx = i2c_clk_div[clk_idx][1];

	/* Store divider value */
	writeb(idx, &i2c_regs->ifdr);

	/* Reset module */
	writeb(I2CR_IDIS, &i2c_regs->i2cr);
	writeb(0, &i2c_regs->i2sr);
	return 0;
}

#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))

static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
{
	unsigned sr;
	ulong elapsed;
	ulong start_time = get_timer(0);
	for (;;) {
		sr = readb(&i2c_regs->i2sr);
		if (sr & I2SR_IAL) {
#ifdef I2C_QUIRK_REG
			writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
#else
			writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
#endif
			printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
				__func__, sr, readb(&i2c_regs->i2cr), state);
			return -ERESTART;
		}
		if ((sr & (state >> 8)) == (unsigned char)state)
			return sr;
		WATCHDOG_RESET();
		elapsed = get_timer(start_time);
		if (elapsed > (CONFIG_SYS_HZ / 10))	/* .1 seconds */
			break;
	}
	printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
			sr, readb(&i2c_regs->i2cr), state);
	return -ETIMEDOUT;
}

static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
{
	int ret;

	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	writeb(byte, &i2c_regs->i2dr);
	ret = wait_for_sr_state(i2c_regs, ST_IIF);
	if (ret < 0)
		return ret;
	if (ret & I2SR_RX_NO_AK)
		return -ENODEV;
	return 0;
}

/*
 * Stop I2C transaction
 */
static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
{
	int ret;
	unsigned int temp = readb(&i2c_regs->i2cr);

	temp &= ~(I2CR_MSTA | I2CR_MTX);
	writeb(temp, &i2c_regs->i2cr);
	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	if (ret < 0)
		printf("%s:trigger stop failed\n", __func__);
}

/*
 * Send start signal, chip address and
 * write register address
 */
static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
		uchar chip, uint addr, int alen)
{
	unsigned int temp;
	int ret;

	/* Enable I2C controller */
#ifdef I2C_QUIRK_REG
	if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
#else
	if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
#endif
		writeb(I2CR_IEN, &i2c_regs->i2cr);
		/* Wait for controller to be stable */
		udelay(50);
	}
	if (readb(&i2c_regs->iadr) == (chip << 1))
		writeb((chip << 1) ^ 2, &i2c_regs->iadr);
	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	if (ret < 0)
		return ret;

	/* Start I2C transaction */
	temp = readb(&i2c_regs->i2cr);
	temp |= I2CR_MSTA;
	writeb(temp, &i2c_regs->i2cr);

	ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
	if (ret < 0)
		return ret;

	temp |= I2CR_MTX | I2CR_TX_NO_AK;
	writeb(temp, &i2c_regs->i2cr);

	/* write slave address */
	ret = tx_byte(i2c_regs, chip << 1);
	if (ret < 0)
		return ret;

	while (alen--) {
		ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
		if (ret < 0)
			return ret;
	}
	return 0;
}

static int i2c_idle_bus(void *base);

static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
		uchar chip, uint addr, int alen)
{
	int retry;
	int ret;
	for (retry = 0; retry < 3; retry++) {
		ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
		if (ret >= 0)
			return 0;
		i2c_imx_stop(i2c_regs);
		if (ret == -ENODEV)
			return ret;

		printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
				retry);
		if (ret != -ERESTART)
			/* Disable controller */
			writeb(I2CR_IDIS, &i2c_regs->i2cr);
		udelay(100);
		if (i2c_idle_bus(i2c_regs) < 0)
			break;
	}
	printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
	return ret;
}

/*
 * Read data from I2C device
 */
int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
		int len)
{
	int ret;
	unsigned int temp;
	int i;
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;

	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
	if (ret < 0)
		return ret;

	temp = readb(&i2c_regs->i2cr);
	temp |= I2CR_RSTA;
	writeb(temp, &i2c_regs->i2cr);

	ret = tx_byte(i2c_regs, (chip << 1) | 1);
	if (ret < 0) {
		i2c_imx_stop(i2c_regs);
		return ret;
	}

	/* setup bus to read data */
	temp = readb(&i2c_regs->i2cr);
	temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
	if (len == 1)
		temp |= I2CR_TX_NO_AK;
	writeb(temp, &i2c_regs->i2cr);
	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	readb(&i2c_regs->i2dr);		/* dummy read to clear ICF */

	/* read data */
	for (i = 0; i < len; i++) {
		ret = wait_for_sr_state(i2c_regs, ST_IIF);
		if (ret < 0) {
			i2c_imx_stop(i2c_regs);
			return ret;
		}

		/*
		 * It must generate STOP before read I2DR to prevent
		 * controller from generating another clock cycle
		 */
		if (i == (len - 1)) {
			i2c_imx_stop(i2c_regs);
		} else if (i == (len - 2)) {
			temp = readb(&i2c_regs->i2cr);
			temp |= I2CR_TX_NO_AK;
			writeb(temp, &i2c_regs->i2cr);
		}
		writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
		buf[i] = readb(&i2c_regs->i2dr);
	}
	i2c_imx_stop(i2c_regs);
	return 0;
}

/*
 * Write data to I2C device
 */
int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
		const uchar *buf, int len)
{
	int ret;
	int i;
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;

	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
	if (ret < 0)
		return ret;

	for (i = 0; i < len; i++) {
		ret = tx_byte(i2c_regs, buf[i]);
		if (ret < 0)
			break;
	}
	i2c_imx_stop(i2c_regs);
	return ret;
}

struct i2c_parms {
	void *base;
	void *idle_bus_data;
	int (*idle_bus_fn)(void *p);
};

struct sram_data {
	unsigned curr_i2c_bus;
	struct i2c_parms i2c_data[3];
};

static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
	(void *)IMX_I2C_BASE,
	(void *)IMX_I2C2_BASE,
	(void *)IMX_I2C3_BASE
#elif defined(CONFIG_MX27)
	(void *)IMX_I2C1_BASE,
	(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
	defined(CONFIG_MX6)
	(void *)I2C1_BASE_ADDR,
	(void *)I2C2_BASE_ADDR,
	(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
	(void *)I2C0_BASE_ADDR
#elif defined(CONFIG_FSL_LSCH3)
	(void *)I2C1_BASE_ADDR,
	(void *)I2C2_BASE_ADDR,
	(void *)I2C3_BASE_ADDR,
	(void *)I2C4_BASE_ADDR
#else
#error "architecture not supported"
#endif
};

void *i2c_get_base(struct i2c_adapter *adap)
{
	return i2c_bases[adap->hwadapnr];
}

static struct i2c_parms *i2c_get_parms(void *base)
{
	struct sram_data *srdata = (void *)gd->srdata;
	int i = 0;
	struct i2c_parms *p = srdata->i2c_data;
	while (i < ARRAY_SIZE(srdata->i2c_data)) {
		if (p->base == base)
			return p;
		p++;
		i++;
	}
	printf("Invalid I2C base: %p\n", base);
	return NULL;
}

static int i2c_idle_bus(void *base)
{
	struct i2c_parms *p = i2c_get_parms(base);
	if (p && p->idle_bus_fn)
		return p->idle_bus_fn(p->idle_bus_data);
	return 0;
}

static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len)
{
	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
}

static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len)
{
	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
}

/*
 * Test if a chip at a given address responds (probe the chip)
 */
static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
}

void bus_i2c_init(void *base, int speed, int unused,
		int (*idle_bus_fn)(void *p), void *idle_bus_data)
{
	struct sram_data *srdata = (void *)gd->srdata;
	int i = 0;
	struct i2c_parms *p = srdata->i2c_data;
	if (!base)
		return;
	for (;;) {
		if (!p->base || (p->base == base)) {
			p->base = base;
			if (idle_bus_fn) {
				p->idle_bus_fn = idle_bus_fn;
				p->idle_bus_data = idle_bus_data;
			}
			break;
		}
		p++;
		i++;
		if (i >= ARRAY_SIZE(srdata->i2c_data))
			return;
	}
	bus_i2c_set_bus_speed(base, speed);
}

/*
 * Init I2C Bus
 */
static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
}

/*
 * Set I2C Speed
 */
static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
{
	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
}

/*
 * Register mxc i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C1_SPEED,
			 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C2_SPEED,
			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
	defined(CONFIG_MX6)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C3_SPEED,
			 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
#endif
Commit	Line	Data
cdace066	1	/*
db84140b	2	* i2c driver for Freescale i.MX series
cdace066 SH	3	*
cdace066 SH	4	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
db84140b MV	5	* (c) 2011 Marek Vasut <marek.vasut@gmail.com>
	6	*
	7	* Based on i2c-imx.c from linux kernel:
	8	* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
	9	* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
	10	* Copyright (C) 2007 RightHand Technologies, Inc.
	11	* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
	12	*
cdace066	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
cdace066 SH	15	*/
	16
	17	#include <common.h>
127cec18	18	#include <asm/arch/clock.h>
86271115	19	#include <asm/arch/imx-regs.h>
cea60b0c	20	#include <asm/errno.h>
24cd738b	21	#include <asm/io.h>
bf0783df	22	#include <i2c.h>
7aa57a01	23	#include <watchdog.h>
cdace066	24
dec1861b YS	25	DECLARE_GLOBAL_DATA_PTR;
dec1861b YS	26
30ea41a4 AW	27	#ifdef I2C_QUIRK_REG
	28	struct mxc_i2c_regs {
	29	uint8_t iadr;
	30	uint8_t ifdr;
	31	uint8_t i2cr;
	32	uint8_t i2sr;
	33	uint8_t i2dr;
	34	};
	35	#else
db84140b MV	36	struct mxc_i2c_regs {
	37	uint32_t iadr;
	38	uint32_t ifdr;
	39	uint32_t i2cr;
	40	uint32_t i2sr;
	41	uint32_t i2dr;
	42	};
30ea41a4	43	#endif
cdace066	44
cdace066 SH	45	#define I2CR_IIEN (1 << 6)
	46	#define I2CR_MSTA (1 << 5)
	47	#define I2CR_MTX (1 << 4)
	48	#define I2CR_TX_NO_AK (1 << 3)
	49	#define I2CR_RSTA (1 << 2)
	50
	51	#define I2SR_ICF (1 << 7)
	52	#define I2SR_IBB (1 << 5)
d5383a63	53	#define I2SR_IAL (1 << 4)
cdace066 SH	54	#define I2SR_IIF (1 << 1)
	55	#define I2SR_RX_NO_AK (1 << 0)
	56
30ea41a4 AW	57	#ifdef I2C_QUIRK_REG
	58	#define I2CR_IEN (0 << 7)
	59	#define I2CR_IDIS (1 << 7)
	60	#define I2SR_IIF_CLEAR (1 << 1)
	61	#else
	62	#define I2CR_IEN (1 << 7)
	63	#define I2CR_IDIS (0 << 7)
	64	#define I2SR_IIF_CLEAR (0 << 1)
	65	#endif
	66
e4ff525f	67	#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
de6f604d	68	#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
cdace066 SH	69	#endif
cdace066 SH	70
30ea41a4 AW	71	#ifdef I2C_QUIRK_REG
	72	static u16 i2c_clk_div[60][2] = {
	73	{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
	74	{ 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
	75	{ 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
	76	{ 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
	77	{ 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
	78	{ 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
	79	{ 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
	80	{ 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
	81	{ 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
	82	{ 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
	83	{ 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
	84	{ 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
	85	{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
	86	{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
	87	{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
	88	};
	89	#else
db84140b MV	90	static u16 i2c_clk_div[50][2] = {
	91	{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
	92	{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
	93	{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
	94	{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
	95	{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
	96	{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
	97	{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
	98	{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
	99	{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
	100	{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
	101	{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
	102	{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
	103	{ 3072, 0x1E }, { 3840, 0x1F }
	104	};
30ea41a4	105	#endif
db84140b	106
fac96408	107
	108	#ifndef CONFIG_SYS_MXC_I2C1_SPEED
	109	#define CONFIG_SYS_MXC_I2C1_SPEED 100000
	110	#endif
	111	#ifndef CONFIG_SYS_MXC_I2C2_SPEED
	112	#define CONFIG_SYS_MXC_I2C2_SPEED 100000
	113	#endif
	114	#ifndef CONFIG_SYS_MXC_I2C3_SPEED
	115	#define CONFIG_SYS_MXC_I2C3_SPEED 100000
	116	#endif
	117
	118	#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
	119	#define CONFIG_SYS_MXC_I2C1_SLAVE 0
	120	#endif
	121	#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
	122	#define CONFIG_SYS_MXC_I2C2_SLAVE 0
	123	#endif
	124	#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
	125	#define CONFIG_SYS_MXC_I2C3_SLAVE 0
	126	#endif
	127
	128
db84140b MV	129	/*
	130	* Calculate and set proper clock divider
	131	*/
bf0783df	132	static uint8_t i2c_imx_get_clk(unsigned int rate)
cdace066	133	{
db84140b MV	134	unsigned int i2c_clk_rate;
db84140b MV	135	unsigned int div;
bf0783df	136	u8 clk_div;
cdace066	137
127cec18	138	#if defined(CONFIG_MX31)
1d549ade SB	139	struct clock_control_regs *sc_regs =
1d549ade SB	140	(struct clock_control_regs *)CCM_BASE;
db84140b	141
e7de18af	142	/* start the required I2C clock */
de6f604d	143	writel(readl(&sc_regs->cgr0) \| (3 << CONFIG_SYS_I2C_CLK_OFFSET),
1d549ade	144	&sc_regs->cgr0);
127cec18	145	#endif
e7de18af	146
db84140b	147	/* Divider value calculation */
e7bed5c2	148	i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
db84140b MV	149	div = (i2c_clk_rate + rate - 1) / rate;
db84140b MV	150	if (div < i2c_clk_div[0][0])
b567b8ff	151	clk_div = 0;
db84140b	152	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
b567b8ff	153	clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
db84140b	154	else
b567b8ff	155	for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
db84140b MV	156	;
	157
	158	/* Store divider value */
bf0783df	159	return clk_div;
db84140b	160	}
cdace066	161
db84140b	162	/*
e4ff525f	163	* Set I2C Bus speed
db84140b	164	*/
7f86bd57	165	static int bus_i2c_set_bus_speed(void *base, int speed)
db84140b	166	{
e4ff525f	167	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
bf0783df MV	168	u8 clk_idx = i2c_imx_get_clk(speed);
	169	u8 idx = i2c_clk_div[clk_idx][1];
	170
	171	/* Store divider value */
	172	writeb(idx, &i2c_regs->ifdr);
	173
83a1a190	174	/* Reset module */
30ea41a4	175	writeb(I2CR_IDIS, &i2c_regs->i2cr);
83a1a190	176	writeb(0, &i2c_regs->i2sr);
b567b8ff MV	177	return 0;
	178	}
	179
7aa57a01 TK	180	#define ST_BUS_IDLE (0 \| (I2SR_IBB << 8))
	181	#define ST_BUS_BUSY (I2SR_IBB \| (I2SR_IBB << 8))
	182	#define ST_IIF (I2SR_IIF \| (I2SR_IIF << 8))
81687212	183
7aa57a01	184	static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
cdace066	185	{
7aa57a01 TK	186	unsigned sr;
	187	ulong elapsed;
	188	ulong start_time = get_timer(0);
	189	for (;;) {
	190	sr = readb(&i2c_regs->i2sr);
d5383a63	191	if (sr & I2SR_IAL) {
30ea41a4 AW	192	#ifdef I2C_QUIRK_REG
	193	writeb(sr \| I2SR_IAL, &i2c_regs->i2sr);
	194	#else
d5383a63	195	writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
30ea41a4	196	#endif
d5383a63 TK	197	printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
	198	__func__, sr, readb(&i2c_regs->i2cr), state);
	199	return -ERESTART;
	200	}
7aa57a01 TK	201	if ((sr & (state >> 8)) == (unsigned char)state)
	202	return sr;
	203	WATCHDOG_RESET();
	204	elapsed = get_timer(start_time);
	205	if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
	206	break;
db84140b	207	}
7aa57a01 TK	208	printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
7aa57a01 TK	209	sr, readb(&i2c_regs->i2cr), state);
cea60b0c	210	return -ETIMEDOUT;
cdace066 SH	211	}
cdace066 SH	212
cea60b0c	213	static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
81687212	214	{
cea60b0c	215	int ret;
81687212	216
30ea41a4	217	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
cea60b0c	218	writeb(byte, &i2c_regs->i2dr);
7aa57a01	219	ret = wait_for_sr_state(i2c_regs, ST_IIF);
cea60b0c TK	220	if (ret < 0)
cea60b0c TK	221	return ret;
cea60b0c TK	222	if (ret & I2SR_RX_NO_AK)
	223	return -ENODEV;
	224	return 0;
db84140b	225	}
81687212	226
db84140b	227	/*
90a5b70f	228	* Stop I2C transaction
db84140b	229	*/
27a5da02	230	static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
cdace066	231	{
7aa57a01	232	int ret;
90a5b70f	233	unsigned int temp = readb(&i2c_regs->i2cr);
db84140b	234
1c076dba	235	temp &= ~(I2CR_MSTA \| I2CR_MTX);
db84140b	236	writeb(temp, &i2c_regs->i2cr);
7aa57a01 TK	237	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	238	if (ret < 0)
	239	printf("%s:trigger stop failed\n", __func__);
cdace066 SH	240	}
cdace066 SH	241
db84140b	242	/*
b230ddc2 TK	243	* Send start signal, chip address and
b230ddc2 TK	244	* write register address
db84140b	245	*/
a7f1a005	246	static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
b230ddc2	247	uchar chip, uint addr, int alen)
cdace066	248	{
71e9f3cb TK	249	unsigned int temp;
	250	int ret;
	251
	252	/* Enable I2C controller */
30ea41a4 AW	253	#ifdef I2C_QUIRK_REG
	254	if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
	255	#else
90a5b70f	256	if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
30ea41a4	257	#endif
90a5b70f TK	258	writeb(I2CR_IEN, &i2c_regs->i2cr);
	259	/* Wait for controller to be stable */
	260	udelay(50);
	261	}
ca741da1 TK	262	if (readb(&i2c_regs->iadr) == (chip << 1))
ca741da1 TK	263	writeb((chip << 1) ^ 2, &i2c_regs->iadr);
30ea41a4	264	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
90a5b70f TK	265	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
90a5b70f TK	266	if (ret < 0)
a7f1a005	267	return ret;
71e9f3cb TK	268
	269	/* Start I2C transaction */
	270	temp = readb(&i2c_regs->i2cr);
	271	temp \|= I2CR_MSTA;
	272	writeb(temp, &i2c_regs->i2cr);
	273
	274	ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
	275	if (ret < 0)
a7f1a005	276	return ret;
b230ddc2	277
71e9f3cb TK	278	temp \|= I2CR_MTX \| I2CR_TX_NO_AK;
	279	writeb(temp, &i2c_regs->i2cr);
	280
b230ddc2 TK	281	/* write slave address */
	282	ret = tx_byte(i2c_regs, chip << 1);
	283	if (ret < 0)
a7f1a005	284	return ret;
db84140b	285
bf0783df	286	while (alen--) {
cea60b0c TK	287	ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
cea60b0c TK	288	if (ret < 0)
a7f1a005	289	return ret;
81687212	290	}
b230ddc2	291	return 0;
a7f1a005 TK	292	}
a7f1a005 TK	293
96c19bd3 TK	294	static int i2c_idle_bus(void *base);
96c19bd3 TK	295
a7f1a005 TK	296	static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
	297	uchar chip, uint addr, int alen)
	298	{
	299	int retry;
	300	int ret;
	301	for (retry = 0; retry < 3; retry++) {
	302	ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
	303	if (ret >= 0)
	304	return 0;
27a5da02	305	i2c_imx_stop(i2c_regs);
a7f1a005 TK	306	if (ret == -ENODEV)
	307	return ret;
	308
	309	printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
	310	retry);
	311	if (ret != -ERESTART)
30ea41a4 AW	312	/* Disable controller */
30ea41a4 AW	313	writeb(I2CR_IDIS, &i2c_regs->i2cr);
a7f1a005	314	udelay(100);
96c19bd3 TK	315	if (i2c_idle_bus(i2c_regs) < 0)
96c19bd3 TK	316	break;
a7f1a005 TK	317	}
a7f1a005 TK	318	printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
db84140b	319	return ret;
cdace066 SH	320	}
cdace066 SH	321
db84140b MV	322	/*
	323	* Read data from I2C device
	324	*/
e4ff525f TK	325	int bus_i2c_read(void base, uchar chip, uint addr, int alen, uchar buf,
e4ff525f TK	326	int len)
db84140b	327	{
db84140b MV	328	int ret;
	329	unsigned int temp;
	330	int i;
e4ff525f	331	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
cdace066	332
b230ddc2	333	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
cea60b0c	334	if (ret < 0)
db84140b MV	335	return ret;
db84140b MV	336
db84140b MV	337	temp = readb(&i2c_regs->i2cr);
	338	temp \|= I2CR_RSTA;
	339	writeb(temp, &i2c_regs->i2cr);
	340
cea60b0c	341	ret = tx_byte(i2c_regs, (chip << 1) \| 1);
c4330d28	342	if (ret < 0) {
27a5da02	343	i2c_imx_stop(i2c_regs);
db84140b	344	return ret;
c4330d28	345	}
db84140b MV	346
	347	/* setup bus to read data */
	348	temp = readb(&i2c_regs->i2cr);
	349	temp &= ~(I2CR_MTX \| I2CR_TX_NO_AK);
	350	if (len == 1)
	351	temp \|= I2CR_TX_NO_AK;
	352	writeb(temp, &i2c_regs->i2cr);
30ea41a4	353	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
ea572d85	354	readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
db84140b MV	355
	356	/* read data */
	357	for (i = 0; i < len; i++) {
7aa57a01 TK	358	ret = wait_for_sr_state(i2c_regs, ST_IIF);
7aa57a01 TK	359	if (ret < 0) {
27a5da02	360	i2c_imx_stop(i2c_regs);
db84140b	361	return ret;
c4330d28	362	}
db84140b MV	363
	364	/*
	365	* It must generate STOP before read I2DR to prevent
	366	* controller from generating another clock cycle
	367	*/
	368	if (i == (len - 1)) {
27a5da02	369	i2c_imx_stop(i2c_regs);
db84140b MV	370	} else if (i == (len - 2)) {
	371	temp = readb(&i2c_regs->i2cr);
	372	temp \|= I2CR_TX_NO_AK;
	373	writeb(temp, &i2c_regs->i2cr);
	374	}
30ea41a4	375	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
db84140b	376	buf[i] = readb(&i2c_regs->i2dr);
cdace066	377	}
27a5da02	378	i2c_imx_stop(i2c_regs);
7aa57a01	379	return 0;
cdace066 SH	380	}
cdace066 SH	381
db84140b MV	382	/*
	383	* Write data to I2C device
	384	*/
e4ff525f TK	385	int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
e4ff525f TK	386	const uchar *buf, int len)
cdace066	387	{
db84140b MV	388	int ret;
db84140b MV	389	int i;
e4ff525f	390	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
cdace066	391
b230ddc2	392	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
cea60b0c	393	if (ret < 0)
db84140b	394	return ret;
cdace066	395
db84140b	396	for (i = 0; i < len; i++) {
cea60b0c TK	397	ret = tx_byte(i2c_regs, buf[i]);
cea60b0c TK	398	if (ret < 0)
c4330d28	399	break;
db84140b	400	}
27a5da02	401	i2c_imx_stop(i2c_regs);
db84140b MV	402	return ret;
db84140b MV	403	}
cfbb88d3	404
e4ff525f TK	405	struct i2c_parms {
	406	void *base;
	407	void *idle_bus_data;
	408	int (idle_bus_fn)(void p);
	409	};
	410
	411	struct sram_data {
	412	unsigned curr_i2c_bus;
	413	struct i2c_parms i2c_data[3];
	414	};
	415
fac96408	416	static void * const i2c_bases[] = {
	417	#if defined(CONFIG_MX25)
	418	(void *)IMX_I2C_BASE,
	419	(void *)IMX_I2C2_BASE,
	420	(void *)IMX_I2C3_BASE
	421	#elif defined(CONFIG_MX27)
	422	(void *)IMX_I2C1_BASE,
	423	(void *)IMX_I2C2_BASE
	424	#elif defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\| \
	425	defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\| \
	426	defined(CONFIG_MX6)
	427	(void *)I2C1_BASE_ADDR,
	428	(void *)I2C2_BASE_ADDR,
	429	(void *)I2C3_BASE_ADDR
	430	#elif defined(CONFIG_VF610)
	431	(void *)I2C0_BASE_ADDR
2f78eae5 YS	432	#elif defined(CONFIG_FSL_LSCH3)
	433	(void *)I2C1_BASE_ADDR,
	434	(void *)I2C2_BASE_ADDR,
	435	(void *)I2C3_BASE_ADDR,
	436	(void *)I2C4_BASE_ADDR
e4ff525f	437	#else
fac96408	438	#error "architecture not supported"
e4ff525f	439	#endif
fac96408	440	};
	441
	442	void i2c_get_base(struct i2c_adapter adap)
	443	{
	444	return i2c_bases[adap->hwadapnr];
e4ff525f TK	445	}
e4ff525f TK	446
96c19bd3 TK	447	static struct i2c_parms i2c_get_parms(void base)
96c19bd3 TK	448	{
dec1861b	449	struct sram_data srdata = (void )gd->srdata;
96c19bd3	450	int i = 0;
dec1861b YS	451	struct i2c_parms *p = srdata->i2c_data;
dec1861b YS	452	while (i < ARRAY_SIZE(srdata->i2c_data)) {
96c19bd3 TK	453	if (p->base == base)
	454	return p;
	455	p++;
	456	i++;
	457	}
	458	printf("Invalid I2C base: %p\n", base);
	459	return NULL;
	460	}
	461
	462	static int i2c_idle_bus(void *base)
	463	{
	464	struct i2c_parms *p = i2c_get_parms(base);
	465	if (p && p->idle_bus_fn)
	466	return p->idle_bus_fn(p->idle_bus_data);
	467	return 0;
	468	}
	469
fac96408	470	static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
	471	uint addr, int alen, uint8_t *buffer,
	472	int len)
e4ff525f	473	{
fac96408	474	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f TK	475	}
e4ff525f TK	476
fac96408	477	static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
	478	uint addr, int alen, uint8_t *buffer,
	479	int len)
e4ff525f	480	{
fac96408	481	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f TK	482	}
e4ff525f TK	483
cfbb88d3 TK	484	/*
	485	* Test if a chip at a given address responds (probe the chip)
	486	*/
fac96408	487	static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
cfbb88d3	488	{
fac96408	489	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
e4ff525f TK	490	}
	491
	492	void bus_i2c_init(void *base, int speed, int unused,
	493	int (idle_bus_fn)(void p), void *idle_bus_data)
	494	{
dec1861b	495	struct sram_data srdata = (void )gd->srdata;
e4ff525f	496	int i = 0;
dec1861b	497	struct i2c_parms *p = srdata->i2c_data;
e4ff525f TK	498	if (!base)
	499	return;
	500	for (;;) {
	501	if (!p->base \|\| (p->base == base)) {
	502	p->base = base;
	503	if (idle_bus_fn) {
	504	p->idle_bus_fn = idle_bus_fn;
	505	p->idle_bus_data = idle_bus_data;
	506	}
	507	break;
	508	}
	509	p++;
	510	i++;
dec1861b	511	if (i >= ARRAY_SIZE(srdata->i2c_data))
e4ff525f TK	512	return;
	513	}
	514	bus_i2c_set_bus_speed(base, speed);
	515	}
	516
	517	/*
	518	* Init I2C Bus
	519	*/
fac96408	520	static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
e4ff525f	521	{
fac96408	522	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
e4ff525f TK	523	}
	524
	525	/*
	526	* Set I2C Speed
	527	*/
fac96408	528	static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
e4ff525f	529	{
fac96408	530	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
e4ff525f TK	531	}
	532
	533	/*
fac96408	534	* Register mxc i2c adapters
e4ff525f	535	*/
fac96408	536	U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
	537	mxc_i2c_read, mxc_i2c_write,
	538	mxc_i2c_set_bus_speed,
	539	CONFIG_SYS_MXC_I2C1_SPEED,
	540	CONFIG_SYS_MXC_I2C1_SLAVE, 0)
	541	U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
	542	mxc_i2c_read, mxc_i2c_write,
	543	mxc_i2c_set_bus_speed,
	544	CONFIG_SYS_MXC_I2C2_SPEED,
	545	CONFIG_SYS_MXC_I2C2_SLAVE, 1)
	546	#if defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\|\
	547	defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\|\
	548	defined(CONFIG_MX6)
	549	U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
	550	mxc_i2c_read, mxc_i2c_write,
	551	mxc_i2c_set_bus_speed,
	552	CONFIG_SYS_MXC_I2C3_SPEED,
	553	CONFIG_SYS_MXC_I2C3_SLAVE, 2)
	554	#endif