[people/ms/u-boot.git] / drivers / i2c / mxc_i2c.c

/*
 * i2c driver for Freescale i.MX series
 *
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
 *
 * Based on i2c-imx.c from linux kernel:
 *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
 *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
 *  Copyright (C) 2007 RightHand Technologies, Inc.
 *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <i2c.h>
#include <watchdog.h>

#ifdef I2C_QUIRK_REG
struct mxc_i2c_regs {
	uint8_t		iadr;
	uint8_t		ifdr;
	uint8_t		i2cr;
	uint8_t		i2sr;
	uint8_t		i2dr;
};
#else
struct mxc_i2c_regs {
	uint32_t	iadr;
	uint32_t	ifdr;
	uint32_t	i2cr;
	uint32_t	i2sr;
	uint32_t	i2dr;
};
#endif

#define I2CR_IIEN	(1 << 6)
#define I2CR_MSTA	(1 << 5)
#define I2CR_MTX	(1 << 4)
#define I2CR_TX_NO_AK	(1 << 3)
#define I2CR_RSTA	(1 << 2)

#define I2SR_ICF	(1 << 7)
#define I2SR_IBB	(1 << 5)
#define I2SR_IAL	(1 << 4)
#define I2SR_IIF	(1 << 1)
#define I2SR_RX_NO_AK	(1 << 0)

#ifdef I2C_QUIRK_REG
#define I2CR_IEN	(0 << 7)
#define I2CR_IDIS	(1 << 7)
#define I2SR_IIF_CLEAR	(1 << 1)
#else
#define I2CR_IEN	(1 << 7)
#define I2CR_IDIS	(0 << 7)
#define I2SR_IIF_CLEAR	(0 << 1)
#endif

#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif

#ifdef I2C_QUIRK_REG
static u16 i2c_clk_div[60][2] = {
	{ 20,	0x00 }, { 22,	0x01 }, { 24,	0x02 }, { 26,	0x03 },
	{ 28,	0x04 },	{ 30,	0x05 },	{ 32,	0x09 }, { 34,	0x06 },
	{ 36,	0x0A }, { 40,	0x07 }, { 44,	0x0C }, { 48,	0x0D },
	{ 52,	0x43 },	{ 56,	0x0E }, { 60,	0x45 }, { 64,	0x12 },
	{ 68,	0x0F },	{ 72,	0x13 },	{ 80,	0x14 },	{ 88,	0x15 },
	{ 96,	0x19 },	{ 104,	0x16 },	{ 112,	0x1A },	{ 128,	0x17 },
	{ 136,	0x4F }, { 144,	0x1C },	{ 160,	0x1D }, { 176,	0x55 },
	{ 192,	0x1E }, { 208,	0x56 },	{ 224,	0x22 }, { 228,	0x24 },
	{ 240,	0x1F },	{ 256,	0x23 }, { 288,	0x5C },	{ 320,	0x25 },
	{ 384,	0x26 }, { 448,	0x2A },	{ 480,	0x27 }, { 512,	0x2B },
	{ 576,	0x2C },	{ 640,	0x2D },	{ 768,	0x31 }, { 896,	0x32 },
	{ 960,	0x2F },	{ 1024,	0x33 },	{ 1152,	0x34 }, { 1280,	0x35 },
	{ 1536,	0x36 }, { 1792,	0x3A },	{ 1920,	0x37 },	{ 2048,	0x3B },
	{ 2304,	0x3C },	{ 2560,	0x3D },	{ 3072,	0x3E }, { 3584,	0x7A },
	{ 3840,	0x3F }, { 4096,	0x7B }, { 5120,	0x7D },	{ 6144,	0x7E },
};
#else
static u16 i2c_clk_div[50][2] = {
	{ 22,	0x20 }, { 24,	0x21 }, { 26,	0x22 }, { 28,	0x23 },
	{ 30,	0x00 }, { 32,	0x24 }, { 36,	0x25 }, { 40,	0x26 },
	{ 42,	0x03 }, { 44,	0x27 }, { 48,	0x28 }, { 52,	0x05 },
	{ 56,	0x29 }, { 60,	0x06 }, { 64,	0x2A }, { 72,	0x2B },
	{ 80,	0x2C }, { 88,	0x09 }, { 96,	0x2D }, { 104,	0x0A },
	{ 112,	0x2E }, { 128,	0x2F }, { 144,	0x0C }, { 160,	0x30 },
	{ 192,	0x31 }, { 224,	0x32 }, { 240,	0x0F }, { 256,	0x33 },
	{ 288,	0x10 }, { 320,	0x34 }, { 384,	0x35 }, { 448,	0x36 },
	{ 480,	0x13 }, { 512,	0x37 }, { 576,	0x14 }, { 640,	0x38 },
	{ 768,	0x39 }, { 896,	0x3A }, { 960,	0x17 }, { 1024,	0x3B },
	{ 1152,	0x18 }, { 1280,	0x3C }, { 1536,	0x3D }, { 1792,	0x3E },
	{ 1920,	0x1B }, { 2048,	0x3F }, { 2304,	0x1C }, { 2560,	0x1D },
	{ 3072,	0x1E }, { 3840,	0x1F }
};
#endif


#ifndef CONFIG_SYS_MXC_I2C1_SPEED
#define CONFIG_SYS_MXC_I2C1_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SPEED
#define CONFIG_SYS_MXC_I2C2_SPEED 100000
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SPEED
#define CONFIG_SYS_MXC_I2C3_SPEED 100000
#endif

#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
#define CONFIG_SYS_MXC_I2C1_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
#define CONFIG_SYS_MXC_I2C2_SLAVE 0
#endif
#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
#define CONFIG_SYS_MXC_I2C3_SLAVE 0
#endif


/*
 * Calculate and set proper clock divider
 */
static uint8_t i2c_imx_get_clk(unsigned int rate)
{
	unsigned int i2c_clk_rate;
	unsigned int div;
	u8 clk_div;

#if defined(CONFIG_MX31)
	struct clock_control_regs *sc_regs =
		(struct clock_control_regs *)CCM_BASE;

	/* start the required I2C clock */
	writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
		&sc_regs->cgr0);
#endif

	/* Divider value calculation */
	i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
	div = (i2c_clk_rate + rate - 1) / rate;
	if (div < i2c_clk_div[0][0])
		clk_div = 0;
	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
		clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
	else
		for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
			;

	/* Store divider value */
	return clk_div;
}

/*
 * Set I2C Bus speed
 */
static int bus_i2c_set_bus_speed(void *base, int speed)
{
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
	u8 clk_idx = i2c_imx_get_clk(speed);
	u8 idx = i2c_clk_div[clk_idx][1];

	/* Store divider value */
	writeb(idx, &i2c_regs->ifdr);

	/* Reset module */
	writeb(I2CR_IDIS, &i2c_regs->i2cr);
	writeb(0, &i2c_regs->i2sr);
	return 0;
}

#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))

static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
{
	unsigned sr;
	ulong elapsed;
	ulong start_time = get_timer(0);
	for (;;) {
		sr = readb(&i2c_regs->i2sr);
		if (sr & I2SR_IAL) {
#ifdef I2C_QUIRK_REG
			writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
#else
			writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
#endif
			printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
				__func__, sr, readb(&i2c_regs->i2cr), state);
			return -ERESTART;
		}
		if ((sr & (state >> 8)) == (unsigned char)state)
			return sr;
		WATCHDOG_RESET();
		elapsed = get_timer(start_time);
		if (elapsed > (CONFIG_SYS_HZ / 10))	/* .1 seconds */
			break;
	}
	printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
			sr, readb(&i2c_regs->i2cr), state);
	return -ETIMEDOUT;
}

static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
{
	int ret;

	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	writeb(byte, &i2c_regs->i2dr);
	ret = wait_for_sr_state(i2c_regs, ST_IIF);
	if (ret < 0)
		return ret;
	if (ret & I2SR_RX_NO_AK)
		return -ENODEV;
	return 0;
}

/*
 * Stop I2C transaction
 */
static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
{
	int ret;
	unsigned int temp = readb(&i2c_regs->i2cr);

	temp &= ~(I2CR_MSTA | I2CR_MTX);
	writeb(temp, &i2c_regs->i2cr);
	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	if (ret < 0)
		printf("%s:trigger stop failed\n", __func__);
}

/*
 * Send start signal, chip address and
 * write register address
 */
static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
		uchar chip, uint addr, int alen)
{
	unsigned int temp;
	int ret;

	/* Enable I2C controller */
#ifdef I2C_QUIRK_REG
	if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
#else
	if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
#endif
		writeb(I2CR_IEN, &i2c_regs->i2cr);
		/* Wait for controller to be stable */
		udelay(50);
	}
	if (readb(&i2c_regs->iadr) == (chip << 1))
		writeb((chip << 1) ^ 2, &i2c_regs->iadr);
	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	if (ret < 0)
		return ret;

	/* Start I2C transaction */
	temp = readb(&i2c_regs->i2cr);
	temp |= I2CR_MSTA;
	writeb(temp, &i2c_regs->i2cr);

	ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
	if (ret < 0)
		return ret;

	temp |= I2CR_MTX | I2CR_TX_NO_AK;
	writeb(temp, &i2c_regs->i2cr);

	/* write slave address */
	ret = tx_byte(i2c_regs, chip << 1);
	if (ret < 0)
		return ret;

	while (alen--) {
		ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
		if (ret < 0)
			return ret;
	}
	return 0;
}

static int i2c_idle_bus(void *base);

static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
		uchar chip, uint addr, int alen)
{
	int retry;
	int ret;
	for (retry = 0; retry < 3; retry++) {
		ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
		if (ret >= 0)
			return 0;
		i2c_imx_stop(i2c_regs);
		if (ret == -ENODEV)
			return ret;

		printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
				retry);
		if (ret != -ERESTART)
			/* Disable controller */
			writeb(I2CR_IDIS, &i2c_regs->i2cr);
		udelay(100);
		if (i2c_idle_bus(i2c_regs) < 0)
			break;
	}
	printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
	return ret;
}

/*
 * Read data from I2C device
 */
int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
		int len)
{
	int ret;
	unsigned int temp;
	int i;
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;

	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
	if (ret < 0)
		return ret;

	temp = readb(&i2c_regs->i2cr);
	temp |= I2CR_RSTA;
	writeb(temp, &i2c_regs->i2cr);

	ret = tx_byte(i2c_regs, (chip << 1) | 1);
	if (ret < 0) {
		i2c_imx_stop(i2c_regs);
		return ret;
	}

	/* setup bus to read data */
	temp = readb(&i2c_regs->i2cr);
	temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
	if (len == 1)
		temp |= I2CR_TX_NO_AK;
	writeb(temp, &i2c_regs->i2cr);
	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
	readb(&i2c_regs->i2dr);		/* dummy read to clear ICF */

	/* read data */
	for (i = 0; i < len; i++) {
		ret = wait_for_sr_state(i2c_regs, ST_IIF);
		if (ret < 0) {
			i2c_imx_stop(i2c_regs);
			return ret;
		}

		/*
		 * It must generate STOP before read I2DR to prevent
		 * controller from generating another clock cycle
		 */
		if (i == (len - 1)) {
			i2c_imx_stop(i2c_regs);
		} else if (i == (len - 2)) {
			temp = readb(&i2c_regs->i2cr);
			temp |= I2CR_TX_NO_AK;
			writeb(temp, &i2c_regs->i2cr);
		}
		writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
		buf[i] = readb(&i2c_regs->i2dr);
	}
	i2c_imx_stop(i2c_regs);
	return 0;
}

/*
 * Write data to I2C device
 */
int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
		const uchar *buf, int len)
{
	int ret;
	int i;
	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;

	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
	if (ret < 0)
		return ret;

	for (i = 0; i < len; i++) {
		ret = tx_byte(i2c_regs, buf[i]);
		if (ret < 0)
			break;
	}
	i2c_imx_stop(i2c_regs);
	return ret;
}

struct i2c_parms {
	void *base;
	void *idle_bus_data;
	int (*idle_bus_fn)(void *p);
};

struct sram_data {
	unsigned curr_i2c_bus;
	struct i2c_parms i2c_data[3];
};

/*
 * For SPL boot some boards need i2c before SDRAM is initialized so force
 * variables to live in SRAM
 */
static struct sram_data __attribute__((section(".data"))) srdata;

static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
	(void *)IMX_I2C_BASE,
	(void *)IMX_I2C2_BASE,
	(void *)IMX_I2C3_BASE
#elif defined(CONFIG_MX27)
	(void *)IMX_I2C1_BASE,
	(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
	defined(CONFIG_MX6)
	(void *)I2C1_BASE_ADDR,
	(void *)I2C2_BASE_ADDR,
	(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
	(void *)I2C0_BASE_ADDR
#else
#error "architecture not supported"
#endif
};

void *i2c_get_base(struct i2c_adapter *adap)
{
	return i2c_bases[adap->hwadapnr];
}

static struct i2c_parms *i2c_get_parms(void *base)
{
	int i = 0;
	struct i2c_parms *p = srdata.i2c_data;
	while (i < ARRAY_SIZE(srdata.i2c_data)) {
		if (p->base == base)
			return p;
		p++;
		i++;
	}
	printf("Invalid I2C base: %p\n", base);
	return NULL;
}

static int i2c_idle_bus(void *base)
{
	struct i2c_parms *p = i2c_get_parms(base);
	if (p && p->idle_bus_fn)
		return p->idle_bus_fn(p->idle_bus_data);
	return 0;
}

static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len)
{
	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
}

static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len)
{
	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
}

/*
 * Test if a chip at a given address responds (probe the chip)
 */
static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
}

void bus_i2c_init(void *base, int speed, int unused,
		int (*idle_bus_fn)(void *p), void *idle_bus_data)
{
	int i = 0;
	struct i2c_parms *p = srdata.i2c_data;
	if (!base)
		return;
	for (;;) {
		if (!p->base || (p->base == base)) {
			p->base = base;
			if (idle_bus_fn) {
				p->idle_bus_fn = idle_bus_fn;
				p->idle_bus_data = idle_bus_data;
			}
			break;
		}
		p++;
		i++;
		if (i >= ARRAY_SIZE(srdata.i2c_data))
			return;
	}
	bus_i2c_set_bus_speed(base, speed);
}

/*
 * Init I2C Bus
 */
static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
}

/*
 * Set I2C Speed
 */
static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
{
	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
}

/*
 * Register mxc i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C1_SPEED,
			 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C2_SPEED,
			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
	defined(CONFIG_MX6)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
			 mxc_i2c_read, mxc_i2c_write,
			 mxc_i2c_set_bus_speed,
			 CONFIG_SYS_MXC_I2C3_SPEED,
			 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
#endif
Commit	Line	Data
cdace066	1	/*
db84140b	2	* i2c driver for Freescale i.MX series
cdace066 SH	3	*
cdace066 SH	4	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
db84140b MV	5	* (c) 2011 Marek Vasut <marek.vasut@gmail.com>
	6	*
	7	* Based on i2c-imx.c from linux kernel:
	8	* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
	9	* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
	10	* Copyright (C) 2007 RightHand Technologies, Inc.
	11	* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
	12	*
cdace066	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
cdace066 SH	15	*/
	16
	17	#include <common.h>
127cec18	18	#include <asm/arch/clock.h>
86271115	19	#include <asm/arch/imx-regs.h>
cea60b0c	20	#include <asm/errno.h>
24cd738b	21	#include <asm/io.h>
bf0783df	22	#include <i2c.h>
7aa57a01	23	#include <watchdog.h>
cdace066	24
30ea41a4 AW	25	#ifdef I2C_QUIRK_REG
	26	struct mxc_i2c_regs {
	27	uint8_t iadr;
	28	uint8_t ifdr;
	29	uint8_t i2cr;
	30	uint8_t i2sr;
	31	uint8_t i2dr;
	32	};
	33	#else
db84140b MV	34	struct mxc_i2c_regs {
	35	uint32_t iadr;
	36	uint32_t ifdr;
	37	uint32_t i2cr;
	38	uint32_t i2sr;
	39	uint32_t i2dr;
	40	};
30ea41a4	41	#endif
cdace066	42
cdace066 SH	43	#define I2CR_IIEN (1 << 6)
	44	#define I2CR_MSTA (1 << 5)
	45	#define I2CR_MTX (1 << 4)
	46	#define I2CR_TX_NO_AK (1 << 3)
	47	#define I2CR_RSTA (1 << 2)
	48
	49	#define I2SR_ICF (1 << 7)
	50	#define I2SR_IBB (1 << 5)
d5383a63	51	#define I2SR_IAL (1 << 4)
cdace066 SH	52	#define I2SR_IIF (1 << 1)
	53	#define I2SR_RX_NO_AK (1 << 0)
	54
30ea41a4 AW	55	#ifdef I2C_QUIRK_REG
	56	#define I2CR_IEN (0 << 7)
	57	#define I2CR_IDIS (1 << 7)
	58	#define I2SR_IIF_CLEAR (1 << 1)
	59	#else
	60	#define I2CR_IEN (1 << 7)
	61	#define I2CR_IDIS (0 << 7)
	62	#define I2SR_IIF_CLEAR (0 << 1)
	63	#endif
	64
e4ff525f	65	#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
de6f604d	66	#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
cdace066 SH	67	#endif
cdace066 SH	68
30ea41a4 AW	69	#ifdef I2C_QUIRK_REG
	70	static u16 i2c_clk_div[60][2] = {
	71	{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
	72	{ 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
	73	{ 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
	74	{ 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
	75	{ 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
	76	{ 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
	77	{ 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
	78	{ 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
	79	{ 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
	80	{ 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
	81	{ 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
	82	{ 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
	83	{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
	84	{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
	85	{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
	86	};
	87	#else
db84140b MV	88	static u16 i2c_clk_div[50][2] = {
	89	{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
	90	{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
	91	{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
	92	{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
	93	{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
	94	{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
	95	{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
	96	{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
	97	{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
	98	{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
	99	{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
	100	{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
	101	{ 3072, 0x1E }, { 3840, 0x1F }
	102	};
30ea41a4	103	#endif
db84140b	104
fac96408	105
	106	#ifndef CONFIG_SYS_MXC_I2C1_SPEED
	107	#define CONFIG_SYS_MXC_I2C1_SPEED 100000
	108	#endif
	109	#ifndef CONFIG_SYS_MXC_I2C2_SPEED
	110	#define CONFIG_SYS_MXC_I2C2_SPEED 100000
	111	#endif
	112	#ifndef CONFIG_SYS_MXC_I2C3_SPEED
	113	#define CONFIG_SYS_MXC_I2C3_SPEED 100000
	114	#endif
	115
	116	#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
	117	#define CONFIG_SYS_MXC_I2C1_SLAVE 0
	118	#endif
	119	#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
	120	#define CONFIG_SYS_MXC_I2C2_SLAVE 0
	121	#endif
	122	#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
	123	#define CONFIG_SYS_MXC_I2C3_SLAVE 0
	124	#endif
	125
	126
db84140b MV	127	/*
	128	* Calculate and set proper clock divider
	129	*/
bf0783df	130	static uint8_t i2c_imx_get_clk(unsigned int rate)
cdace066	131	{
db84140b MV	132	unsigned int i2c_clk_rate;
db84140b MV	133	unsigned int div;
bf0783df	134	u8 clk_div;
cdace066	135
127cec18	136	#if defined(CONFIG_MX31)
1d549ade SB	137	struct clock_control_regs *sc_regs =
1d549ade SB	138	(struct clock_control_regs *)CCM_BASE;
db84140b	139
e7de18af	140	/* start the required I2C clock */
de6f604d	141	writel(readl(&sc_regs->cgr0) \| (3 << CONFIG_SYS_I2C_CLK_OFFSET),
1d549ade	142	&sc_regs->cgr0);
127cec18	143	#endif
e7de18af	144
db84140b	145	/* Divider value calculation */
e7bed5c2	146	i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
db84140b MV	147	div = (i2c_clk_rate + rate - 1) / rate;
db84140b MV	148	if (div < i2c_clk_div[0][0])
b567b8ff	149	clk_div = 0;
db84140b	150	else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
b567b8ff	151	clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
db84140b	152	else
b567b8ff	153	for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
db84140b MV	154	;
	155
	156	/* Store divider value */
bf0783df	157	return clk_div;
db84140b	158	}
cdace066	159
db84140b	160	/*
e4ff525f	161	* Set I2C Bus speed
db84140b	162	*/
7f86bd57	163	static int bus_i2c_set_bus_speed(void *base, int speed)
db84140b	164	{
e4ff525f	165	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
bf0783df MV	166	u8 clk_idx = i2c_imx_get_clk(speed);
	167	u8 idx = i2c_clk_div[clk_idx][1];
	168
	169	/* Store divider value */
	170	writeb(idx, &i2c_regs->ifdr);
	171
83a1a190	172	/* Reset module */
30ea41a4	173	writeb(I2CR_IDIS, &i2c_regs->i2cr);
83a1a190	174	writeb(0, &i2c_regs->i2sr);
b567b8ff MV	175	return 0;
	176	}
	177
7aa57a01 TK	178	#define ST_BUS_IDLE (0 \| (I2SR_IBB << 8))
	179	#define ST_BUS_BUSY (I2SR_IBB \| (I2SR_IBB << 8))
	180	#define ST_IIF (I2SR_IIF \| (I2SR_IIF << 8))
81687212	181
7aa57a01	182	static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
cdace066	183	{
7aa57a01 TK	184	unsigned sr;
	185	ulong elapsed;
	186	ulong start_time = get_timer(0);
	187	for (;;) {
	188	sr = readb(&i2c_regs->i2sr);
d5383a63	189	if (sr & I2SR_IAL) {
30ea41a4 AW	190	#ifdef I2C_QUIRK_REG
	191	writeb(sr \| I2SR_IAL, &i2c_regs->i2sr);
	192	#else
d5383a63	193	writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
30ea41a4	194	#endif
d5383a63 TK	195	printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
	196	__func__, sr, readb(&i2c_regs->i2cr), state);
	197	return -ERESTART;
	198	}
7aa57a01 TK	199	if ((sr & (state >> 8)) == (unsigned char)state)
	200	return sr;
	201	WATCHDOG_RESET();
	202	elapsed = get_timer(start_time);
	203	if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
	204	break;
db84140b	205	}
7aa57a01 TK	206	printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
7aa57a01 TK	207	sr, readb(&i2c_regs->i2cr), state);
cea60b0c	208	return -ETIMEDOUT;
cdace066 SH	209	}
cdace066 SH	210
cea60b0c	211	static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
81687212	212	{
cea60b0c	213	int ret;
81687212	214
30ea41a4	215	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
cea60b0c	216	writeb(byte, &i2c_regs->i2dr);
7aa57a01	217	ret = wait_for_sr_state(i2c_regs, ST_IIF);
cea60b0c TK	218	if (ret < 0)
cea60b0c TK	219	return ret;
cea60b0c TK	220	if (ret & I2SR_RX_NO_AK)
	221	return -ENODEV;
	222	return 0;
db84140b	223	}
81687212	224
db84140b	225	/*
90a5b70f	226	* Stop I2C transaction
db84140b	227	*/
27a5da02	228	static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
cdace066	229	{
7aa57a01	230	int ret;
90a5b70f	231	unsigned int temp = readb(&i2c_regs->i2cr);
db84140b	232
1c076dba	233	temp &= ~(I2CR_MSTA \| I2CR_MTX);
db84140b	234	writeb(temp, &i2c_regs->i2cr);
7aa57a01 TK	235	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
	236	if (ret < 0)
	237	printf("%s:trigger stop failed\n", __func__);
cdace066 SH	238	}
cdace066 SH	239
db84140b	240	/*
b230ddc2 TK	241	* Send start signal, chip address and
b230ddc2 TK	242	* write register address
db84140b	243	*/
a7f1a005	244	static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
b230ddc2	245	uchar chip, uint addr, int alen)
cdace066	246	{
71e9f3cb TK	247	unsigned int temp;
	248	int ret;
	249
	250	/* Enable I2C controller */
30ea41a4 AW	251	#ifdef I2C_QUIRK_REG
	252	if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
	253	#else
90a5b70f	254	if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
30ea41a4	255	#endif
90a5b70f TK	256	writeb(I2CR_IEN, &i2c_regs->i2cr);
	257	/* Wait for controller to be stable */
	258	udelay(50);
	259	}
ca741da1 TK	260	if (readb(&i2c_regs->iadr) == (chip << 1))
ca741da1 TK	261	writeb((chip << 1) ^ 2, &i2c_regs->iadr);
30ea41a4	262	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
90a5b70f TK	263	ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
90a5b70f TK	264	if (ret < 0)
a7f1a005	265	return ret;
71e9f3cb TK	266
	267	/* Start I2C transaction */
	268	temp = readb(&i2c_regs->i2cr);
	269	temp \|= I2CR_MSTA;
	270	writeb(temp, &i2c_regs->i2cr);
	271
	272	ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
	273	if (ret < 0)
a7f1a005	274	return ret;
b230ddc2	275
71e9f3cb TK	276	temp \|= I2CR_MTX \| I2CR_TX_NO_AK;
	277	writeb(temp, &i2c_regs->i2cr);
	278
b230ddc2 TK	279	/* write slave address */
	280	ret = tx_byte(i2c_regs, chip << 1);
	281	if (ret < 0)
a7f1a005	282	return ret;
db84140b	283
bf0783df	284	while (alen--) {
cea60b0c TK	285	ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
cea60b0c TK	286	if (ret < 0)
a7f1a005	287	return ret;
81687212	288	}
b230ddc2	289	return 0;
a7f1a005 TK	290	}
a7f1a005 TK	291
96c19bd3 TK	292	static int i2c_idle_bus(void *base);
96c19bd3 TK	293
a7f1a005 TK	294	static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
	295	uchar chip, uint addr, int alen)
	296	{
	297	int retry;
	298	int ret;
	299	for (retry = 0; retry < 3; retry++) {
	300	ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
	301	if (ret >= 0)
	302	return 0;
27a5da02	303	i2c_imx_stop(i2c_regs);
a7f1a005 TK	304	if (ret == -ENODEV)
	305	return ret;
	306
	307	printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
	308	retry);
	309	if (ret != -ERESTART)
30ea41a4 AW	310	/* Disable controller */
30ea41a4 AW	311	writeb(I2CR_IDIS, &i2c_regs->i2cr);
a7f1a005	312	udelay(100);
96c19bd3 TK	313	if (i2c_idle_bus(i2c_regs) < 0)
96c19bd3 TK	314	break;
a7f1a005 TK	315	}
a7f1a005 TK	316	printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
db84140b	317	return ret;
cdace066 SH	318	}
cdace066 SH	319
db84140b MV	320	/*
	321	* Read data from I2C device
	322	*/
e4ff525f TK	323	int bus_i2c_read(void base, uchar chip, uint addr, int alen, uchar buf,
e4ff525f TK	324	int len)
db84140b	325	{
db84140b MV	326	int ret;
	327	unsigned int temp;
	328	int i;
e4ff525f	329	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
cdace066	330
b230ddc2	331	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
cea60b0c	332	if (ret < 0)
db84140b MV	333	return ret;
db84140b MV	334
db84140b MV	335	temp = readb(&i2c_regs->i2cr);
	336	temp \|= I2CR_RSTA;
	337	writeb(temp, &i2c_regs->i2cr);
	338
cea60b0c	339	ret = tx_byte(i2c_regs, (chip << 1) \| 1);
c4330d28	340	if (ret < 0) {
27a5da02	341	i2c_imx_stop(i2c_regs);
db84140b	342	return ret;
c4330d28	343	}
db84140b MV	344
	345	/* setup bus to read data */
	346	temp = readb(&i2c_regs->i2cr);
	347	temp &= ~(I2CR_MTX \| I2CR_TX_NO_AK);
	348	if (len == 1)
	349	temp \|= I2CR_TX_NO_AK;
	350	writeb(temp, &i2c_regs->i2cr);
30ea41a4	351	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
ea572d85	352	readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
db84140b MV	353
	354	/* read data */
	355	for (i = 0; i < len; i++) {
7aa57a01 TK	356	ret = wait_for_sr_state(i2c_regs, ST_IIF);
7aa57a01 TK	357	if (ret < 0) {
27a5da02	358	i2c_imx_stop(i2c_regs);
db84140b	359	return ret;
c4330d28	360	}
db84140b MV	361
	362	/*
	363	* It must generate STOP before read I2DR to prevent
	364	* controller from generating another clock cycle
	365	*/
	366	if (i == (len - 1)) {
27a5da02	367	i2c_imx_stop(i2c_regs);
db84140b MV	368	} else if (i == (len - 2)) {
	369	temp = readb(&i2c_regs->i2cr);
	370	temp \|= I2CR_TX_NO_AK;
	371	writeb(temp, &i2c_regs->i2cr);
	372	}
30ea41a4	373	writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
db84140b	374	buf[i] = readb(&i2c_regs->i2dr);
cdace066	375	}
27a5da02	376	i2c_imx_stop(i2c_regs);
7aa57a01	377	return 0;
cdace066 SH	378	}
cdace066 SH	379
db84140b MV	380	/*
	381	* Write data to I2C device
	382	*/
e4ff525f TK	383	int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
e4ff525f TK	384	const uchar *buf, int len)
cdace066	385	{
db84140b MV	386	int ret;
db84140b MV	387	int i;
e4ff525f	388	struct mxc_i2c_regs i2c_regs = (struct mxc_i2c_regs )base;
cdace066	389
b230ddc2	390	ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
cea60b0c	391	if (ret < 0)
db84140b	392	return ret;
cdace066	393
db84140b	394	for (i = 0; i < len; i++) {
cea60b0c TK	395	ret = tx_byte(i2c_regs, buf[i]);
cea60b0c TK	396	if (ret < 0)
c4330d28	397	break;
db84140b	398	}
27a5da02	399	i2c_imx_stop(i2c_regs);
db84140b MV	400	return ret;
db84140b MV	401	}
cfbb88d3	402
e4ff525f TK	403	struct i2c_parms {
	404	void *base;
	405	void *idle_bus_data;
	406	int (idle_bus_fn)(void p);
	407	};
	408
	409	struct sram_data {
	410	unsigned curr_i2c_bus;
	411	struct i2c_parms i2c_data[3];
	412	};
	413
	414	/*
	415	* For SPL boot some boards need i2c before SDRAM is initialized so force
	416	* variables to live in SRAM
	417	*/
	418	static struct sram_data __attribute__((section(".data"))) srdata;
	419
fac96408	420	static void * const i2c_bases[] = {
	421	#if defined(CONFIG_MX25)
	422	(void *)IMX_I2C_BASE,
	423	(void *)IMX_I2C2_BASE,
	424	(void *)IMX_I2C3_BASE
	425	#elif defined(CONFIG_MX27)
	426	(void *)IMX_I2C1_BASE,
	427	(void *)IMX_I2C2_BASE
	428	#elif defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\| \
	429	defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\| \
	430	defined(CONFIG_MX6)
	431	(void *)I2C1_BASE_ADDR,
	432	(void *)I2C2_BASE_ADDR,
	433	(void *)I2C3_BASE_ADDR
	434	#elif defined(CONFIG_VF610)
	435	(void *)I2C0_BASE_ADDR
e4ff525f	436	#else
fac96408	437	#error "architecture not supported"
e4ff525f	438	#endif
fac96408	439	};
	440
	441	void i2c_get_base(struct i2c_adapter adap)
	442	{
	443	return i2c_bases[adap->hwadapnr];
e4ff525f TK	444	}
e4ff525f TK	445
96c19bd3 TK	446	static struct i2c_parms i2c_get_parms(void base)
	447	{
	448	int i = 0;
	449	struct i2c_parms *p = srdata.i2c_data;
	450	while (i < ARRAY_SIZE(srdata.i2c_data)) {
	451	if (p->base == base)
	452	return p;
	453	p++;
	454	i++;
	455	}
	456	printf("Invalid I2C base: %p\n", base);
	457	return NULL;
	458	}
	459
	460	static int i2c_idle_bus(void *base)
	461	{
	462	struct i2c_parms *p = i2c_get_parms(base);
	463	if (p && p->idle_bus_fn)
	464	return p->idle_bus_fn(p->idle_bus_data);
	465	return 0;
	466	}
	467
fac96408	468	static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
	469	uint addr, int alen, uint8_t *buffer,
	470	int len)
e4ff525f	471	{
fac96408	472	return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f TK	473	}
e4ff525f TK	474
fac96408	475	static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
	476	uint addr, int alen, uint8_t *buffer,
	477	int len)
e4ff525f	478	{
fac96408	479	return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
e4ff525f TK	480	}
e4ff525f TK	481
cfbb88d3 TK	482	/*
	483	* Test if a chip at a given address responds (probe the chip)
	484	*/
fac96408	485	static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
cfbb88d3	486	{
fac96408	487	return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
e4ff525f TK	488	}
	489
	490	void bus_i2c_init(void *base, int speed, int unused,
	491	int (idle_bus_fn)(void p), void *idle_bus_data)
	492	{
	493	int i = 0;
	494	struct i2c_parms *p = srdata.i2c_data;
	495	if (!base)
	496	return;
	497	for (;;) {
	498	if (!p->base \|\| (p->base == base)) {
	499	p->base = base;
	500	if (idle_bus_fn) {
	501	p->idle_bus_fn = idle_bus_fn;
	502	p->idle_bus_data = idle_bus_data;
	503	}
	504	break;
	505	}
	506	p++;
	507	i++;
	508	if (i >= ARRAY_SIZE(srdata.i2c_data))
	509	return;
	510	}
	511	bus_i2c_set_bus_speed(base, speed);
	512	}
	513
	514	/*
	515	* Init I2C Bus
	516	*/
fac96408	517	static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
e4ff525f	518	{
fac96408	519	bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
e4ff525f TK	520	}
	521
	522	/*
	523	* Set I2C Speed
	524	*/
fac96408	525	static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
e4ff525f	526	{
fac96408	527	return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
e4ff525f TK	528	}
	529
	530	/*
fac96408	531	* Register mxc i2c adapters
e4ff525f	532	*/
fac96408	533	U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
	534	mxc_i2c_read, mxc_i2c_write,
	535	mxc_i2c_set_bus_speed,
	536	CONFIG_SYS_MXC_I2C1_SPEED,
	537	CONFIG_SYS_MXC_I2C1_SLAVE, 0)
	538	U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
	539	mxc_i2c_read, mxc_i2c_write,
	540	mxc_i2c_set_bus_speed,
	541	CONFIG_SYS_MXC_I2C2_SPEED,
	542	CONFIG_SYS_MXC_I2C2_SLAVE, 1)
	543	#if defined(CONFIG_MX31) \|\| defined(CONFIG_MX35) \|\|\
	544	defined(CONFIG_MX51) \|\| defined(CONFIG_MX53) \|\|\
	545	defined(CONFIG_MX6)
	546	U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
	547	mxc_i2c_read, mxc_i2c_write,
	548	mxc_i2c_set_bus_speed,
	549	CONFIG_SYS_MXC_I2C3_SPEED,
	550	CONFIG_SYS_MXC_I2C3_SLAVE, 2)
	551	#endif