[thirdparty/u-boot.git] / drivers / i2c / mxs_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale i.MX28 I2C Driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Partly based on Linux kernel i2c-mxs.c driver:
 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
 *
 * Which was based on a (non-working) driver which was:
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 */

#include <common.h>
#include <malloc.h>
#include <i2c.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>

#define	MXS_I2C_MAX_TIMEOUT	1000000

static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap)
{
	if (adap->hwadapnr == 0)
		return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
	else
		return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
}

static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
	uint32_t timing0;

	timing0 = readl(&i2c_regs->hw_i2c_timing0);
	/*
	 * This is a reverse version of the algorithm presented in
	 * i2c_set_bus_speed(). Please refer there for details.
	 */
	return clk / ((((timing0 >> 16) - 3) * 2) + 38);
}

static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	/*
	 * The timing derivation algorithm. There is no documentation for this
	 * algorithm available, it was derived by using the scope and fiddling
	 * with constants until the result observed on the scope was good enough
	 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
	 * possible to assume the algorithm works for other frequencies as well.
	 *
	 * Note it was necessary to cap the frequency on both ends as it's not
	 * possible to configure completely arbitrary frequency for the I2C bus
	 * clock.
	 */
	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
	uint32_t base = ((clk / speed) - 38) / 2;
	uint16_t high_count = base + 3;
	uint16_t low_count = base - 3;
	uint16_t rcv_count = (high_count * 3) / 4;
	uint16_t xmit_count = low_count / 4;

	if (speed > 540000) {
		printf("MXS I2C: Speed too high (%d Hz)\n", speed);
		return -EINVAL;
	}

	if (speed < 12000) {
		printf("MXS I2C: Speed too low (%d Hz)\n", speed);
		return -EINVAL;
	}

	writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
	writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);

	writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
		(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
		&i2c_regs->hw_i2c_timing2);

	return 0;
}

static void mxs_i2c_reset(struct i2c_adapter *adap)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	int ret;
	int speed = mxs_i2c_get_bus_speed(adap);

	ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
	if (ret) {
		debug("MXS I2C: Block reset timeout\n");
		return;
	}

	writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
		I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
		I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
		&i2c_regs->hw_i2c_ctrl1_clr);

	writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);

	mxs_i2c_set_bus_speed(adap, speed);
}

static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);

	writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
		I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
		(1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
		&i2c_regs->hw_i2c_queuecmd);

	writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);

	writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
		(len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
		I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);

	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}

static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
			 int alen, uchar *buf, int blen, int stop)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	uint32_t data, tmp;
	int i, remain, off;
	int timeout = MXS_I2C_MAX_TIMEOUT;

	if ((alen > 4) || (alen == 0)) {
		debug("MXS I2C: Invalid address length\n");
		return -EINVAL;
	}

	if (stop)
		stop = I2C_QUEUECMD_POST_SEND_STOP;

	writel(I2C_QUEUECMD_PRE_SEND_START |
		I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
		((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
		&i2c_regs->hw_i2c_queuecmd);

	data = (chip << 1) << 24;

	for (i = 0; i < alen; i++) {
		data >>= 8;
		data |= ((char *)&addr)[alen - i - 1] << 24;
		if ((i & 3) == 2)
			writel(data, &i2c_regs->hw_i2c_data);
	}

	off = i;
	for (; i < off + blen; i++) {
		data >>= 8;
		data |= buf[i - off] << 24;
		if ((i & 3) == 2)
			writel(data, &i2c_regs->hw_i2c_data);
	}

	remain = 24 - ((i & 3) * 8);
	if (remain)
		writel(data >> remain, &i2c_regs->hw_i2c_data);

	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);

	while (--timeout) {
		tmp = readl(&i2c_regs->hw_i2c_queuestat);
		if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
			break;
	}

	if (!timeout) {
		debug("MXS I2C: Failed transmitting data!\n");
		return -EINVAL;
	}

	return 0;
}

static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	uint32_t tmp;
	int timeout = MXS_I2C_MAX_TIMEOUT;

	for (;;) {
		tmp = readl(&i2c_regs->hw_i2c_ctrl1);
		if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
			debug("MXS I2C: No slave ACK\n");
			goto err;
		}

		if (tmp & (
			I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
			I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
			debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
			goto err;
		}

		if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
			break;

		if (!timeout--) {
			debug("MXS I2C: Operation timed out\n");
			goto err;
		}

		udelay(1);
	}

	return 0;

err:
	mxs_i2c_reset(adap);
	return 1;
}

static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
			   uint addr, int alen, uint8_t *buffer,
			   int len)
{
	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	uint32_t tmp = 0;
	int timeout = MXS_I2C_MAX_TIMEOUT;
	int ret;
	int i;

	ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
	if (ret) {
		debug("MXS I2C: Failed writing address\n");
		return ret;
	}

	ret = mxs_i2c_wait_for_ack(adap);
	if (ret) {
		debug("MXS I2C: Failed writing address\n");
		return ret;
	}

	mxs_i2c_setup_read(adap, chip, len);
	ret = mxs_i2c_wait_for_ack(adap);
	if (ret) {
		debug("MXS I2C: Failed reading address\n");
		return ret;
	}

	for (i = 0; i < len; i++) {
		if (!(i & 3)) {
			while (--timeout) {
				tmp = readl(&i2c_regs->hw_i2c_queuestat);
				if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
					break;
			}

			if (!timeout) {
				debug("MXS I2C: Failed receiving data!\n");
				return -ETIMEDOUT;
			}

			tmp = readl(&i2c_regs->hw_i2c_queuedata);
		}
		buffer[i] = tmp & 0xff;
		tmp >>= 8;
	}

	return 0;
}

static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
			    uint addr, int alen, uint8_t *buffer,
			    int len)
{
	int ret;
	ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
	if (ret) {
		debug("MXS I2C: Failed writing address\n");
		return ret;
	}

	ret = mxs_i2c_wait_for_ack(adap);
	if (ret)
		debug("MXS I2C: Failed writing address\n");

	return ret;
}

static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
{
	int ret;
	ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
	if (!ret)
		ret = mxs_i2c_wait_for_ack(adap);
	mxs_i2c_reset(adap);
	return ret;
}

static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	mxs_i2c_reset(adap);
	mxs_i2c_set_bus_speed(adap, speed);

	return;
}

U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
			 mxs_i2c_if_read, mxs_i2c_if_write,
			 mxs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, 0, 0)
U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
			 mxs_i2c_if_read, mxs_i2c_if_write,
			 mxs_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, 0, 1)
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f4f680aa MV	2	/*
	3	* Freescale i.MX28 I2C Driver
	4	*
	5	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	6	* on behalf of DENX Software Engineering GmbH
	7	*
	8	* Partly based on Linux kernel i2c-mxs.c driver:
	9	* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
	10	*
	11	* Which was based on a (non-working) driver which was:
	12	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
f4f680aa MV	13	*/
	14
	15	#include <common.h>
	16	#include <malloc.h>
fa5e2845	17	#include <i2c.h>
1221ce45	18	#include <linux/errno.h>
f4f680aa MV	19	#include <asm/io.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/imx-regs.h>
	22	#include <asm/arch/sys_proto.h>
	23
	24	#define MXS_I2C_MAX_TIMEOUT 1000000
	25
9536099d MV	26	static struct mxs_i2c_regs mxs_i2c_get_base(struct i2c_adapter adap)
9536099d MV	27	{
318a9cea MV	28	if (adap->hwadapnr == 0)
	29	return (struct mxs_i2c_regs *)MXS_I2C0_BASE;
	30	else
	31	return (struct mxs_i2c_regs *)MXS_I2C1_BASE;
9536099d MV	32	}
9536099d MV	33
58a7d1c1	34	static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap)
1fa96e80	35	{
58a7d1c1	36	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
1fa96e80 MV	37	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
	38	uint32_t timing0;
	39
	40	timing0 = readl(&i2c_regs->hw_i2c_timing0);
	41	/*
	42	* This is a reverse version of the algorithm presented in
	43	* i2c_set_bus_speed(). Please refer there for details.
	44	*/
	45	return clk / ((((timing0 >> 16) - 3) * 2) + 38);
	46	}
	47
58a7d1c1 MV	48	static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
	49	{
	50	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
	51	/*
	52	* The timing derivation algorithm. There is no documentation for this
	53	* algorithm available, it was derived by using the scope and fiddling
	54	* with constants until the result observed on the scope was good enough
	55	* for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
	56	* possible to assume the algorithm works for other frequencies as well.
	57	*
	58	* Note it was necessary to cap the frequency on both ends as it's not
	59	* possible to configure completely arbitrary frequency for the I2C bus
	60	* clock.
	61	*/
	62	uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
	63	uint32_t base = ((clk / speed) - 38) / 2;
	64	uint16_t high_count = base + 3;
	65	uint16_t low_count = base - 3;
	66	uint16_t rcv_count = (high_count * 3) / 4;
	67	uint16_t xmit_count = low_count / 4;
	68
	69	if (speed > 540000) {
	70	printf("MXS I2C: Speed too high (%d Hz)\n", speed);
	71	return -EINVAL;
	72	}
	73
	74	if (speed < 12000) {
	75	printf("MXS I2C: Speed too low (%d Hz)\n", speed);
	76	return -EINVAL;
	77	}
	78
	79	writel((high_count << 16) \| rcv_count, &i2c_regs->hw_i2c_timing0);
	80	writel((low_count << 16) \| xmit_count, &i2c_regs->hw_i2c_timing1);
	81
	82	writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) \|
	83	(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
	84	&i2c_regs->hw_i2c_timing2);
	85
	86	return 0;
	87	}
	88
	89	static void mxs_i2c_reset(struct i2c_adapter *adap)
f4f680aa	90	{
58a7d1c1	91	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
f4f680aa	92	int ret;
58a7d1c1	93	int speed = mxs_i2c_get_bus_speed(adap);
f4f680aa	94
fa7a51cb	95	ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
f4f680aa MV	96	if (ret) {
	97	debug("MXS I2C: Block reset timeout\n");
	98	return;
	99	}
	100
	101	writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ \| I2C_CTRL1_NO_SLAVE_ACK_IRQ \|
	102	I2C_CTRL1_EARLY_TERM_IRQ \| I2C_CTRL1_MASTER_LOSS_IRQ \|
	103	I2C_CTRL1_SLAVE_STOP_IRQ \| I2C_CTRL1_SLAVE_IRQ,
	104	&i2c_regs->hw_i2c_ctrl1_clr);
	105
	106	writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
1e2fc0d1	107
58a7d1c1	108	mxs_i2c_set_bus_speed(adap, speed);
f4f680aa MV	109	}
f4f680aa MV	110
58a7d1c1	111	static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len)
f4f680aa	112	{
58a7d1c1	113	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
f4f680aa MV	114
	115	writel(I2C_QUEUECMD_RETAIN_CLOCK \| I2C_QUEUECMD_PRE_SEND_START \|
	116	I2C_QUEUECMD_MASTER_MODE \| I2C_QUEUECMD_DIRECTION \|
	117	(1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
	118	&i2c_regs->hw_i2c_queuecmd);
	119
	120	writel((chip << 1) \| 1, &i2c_regs->hw_i2c_data);
	121
	122	writel(I2C_QUEUECMD_SEND_NAK_ON_LAST \| I2C_QUEUECMD_MASTER_MODE \|
	123	(len << I2C_QUEUECMD_XFER_COUNT_OFFSET) \|
	124	I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
	125
	126	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
	127	}
	128
58a7d1c1 MV	129	static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
58a7d1c1 MV	130	int alen, uchar *buf, int blen, int stop)
f4f680aa	131	{
58a7d1c1	132	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
d22643e7	133	uint32_t data, tmp;
f4f680aa	134	int i, remain, off;
d22643e7	135	int timeout = MXS_I2C_MAX_TIMEOUT;
f4f680aa MV	136
	137	if ((alen > 4) \|\| (alen == 0)) {
	138	debug("MXS I2C: Invalid address length\n");
d22643e7	139	return -EINVAL;
f4f680aa MV	140	}
	141
	142	if (stop)
	143	stop = I2C_QUEUECMD_POST_SEND_STOP;
	144
	145	writel(I2C_QUEUECMD_PRE_SEND_START \|
	146	I2C_QUEUECMD_MASTER_MODE \| I2C_QUEUECMD_DIRECTION \|
	147	((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) \| stop,
	148	&i2c_regs->hw_i2c_queuecmd);
	149
	150	data = (chip << 1) << 24;
	151
	152	for (i = 0; i < alen; i++) {
	153	data >>= 8;
fa86d1c0	154	data \|= ((char *)&addr)[alen - i - 1] << 24;
f4f680aa MV	155	if ((i & 3) == 2)
	156	writel(data, &i2c_regs->hw_i2c_data);
	157	}
	158
	159	off = i;
	160	for (; i < off + blen; i++) {
	161	data >>= 8;
	162	data \|= buf[i - off] << 24;
	163	if ((i & 3) == 2)
	164	writel(data, &i2c_regs->hw_i2c_data);
	165	}
	166
	167	remain = 24 - ((i & 3) * 8);
	168	if (remain)
	169	writel(data >> remain, &i2c_regs->hw_i2c_data);
	170
	171	writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
d22643e7 MV	172
	173	while (--timeout) {
	174	tmp = readl(&i2c_regs->hw_i2c_queuestat);
	175	if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
	176	break;
	177	}
	178
	179	if (!timeout) {
	180	debug("MXS I2C: Failed transmitting data!\n");
	181	return -EINVAL;
	182	}
	183
	184	return 0;
f4f680aa MV	185	}
f4f680aa MV	186
58a7d1c1	187	static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap)
f4f680aa	188	{
58a7d1c1	189	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
f4f680aa MV	190	uint32_t tmp;
	191	int timeout = MXS_I2C_MAX_TIMEOUT;
	192
	193	for (;;) {
	194	tmp = readl(&i2c_regs->hw_i2c_ctrl1);
	195	if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
	196	debug("MXS I2C: No slave ACK\n");
	197	goto err;
	198	}
	199
	200	if (tmp & (
	201	I2C_CTRL1_EARLY_TERM_IRQ \| I2C_CTRL1_MASTER_LOSS_IRQ \|
	202	I2C_CTRL1_SLAVE_STOP_IRQ \| I2C_CTRL1_SLAVE_IRQ)) {
	203	debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
	204	goto err;
	205	}
	206
	207	if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
	208	break;
	209
	210	if (!timeout--) {
	211	debug("MXS I2C: Operation timed out\n");
	212	goto err;
	213	}
	214
	215	udelay(1);
	216	}
	217
	218	return 0;
	219
	220	err:
58a7d1c1	221	mxs_i2c_reset(adap);
f4f680aa MV	222	return 1;
	223	}
	224
1fa96e80 MV	225	static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip,
	226	uint addr, int alen, uint8_t *buffer,
	227	int len)
f4f680aa	228	{
58a7d1c1	229	struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap);
f4f680aa	230	uint32_t tmp = 0;
12491355	231	int timeout = MXS_I2C_MAX_TIMEOUT;
f4f680aa MV	232	int ret;
	233	int i;
	234
58a7d1c1	235	ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0);
d22643e7 MV	236	if (ret) {
	237	debug("MXS I2C: Failed writing address\n");
	238	return ret;
	239	}
	240
58a7d1c1	241	ret = mxs_i2c_wait_for_ack(adap);
f4f680aa MV	242	if (ret) {
	243	debug("MXS I2C: Failed writing address\n");
	244	return ret;
	245	}
	246
58a7d1c1 MV	247	mxs_i2c_setup_read(adap, chip, len);
58a7d1c1 MV	248	ret = mxs_i2c_wait_for_ack(adap);
f4f680aa MV	249	if (ret) {
	250	debug("MXS I2C: Failed reading address\n");
	251	return ret;
	252	}
	253
	254	for (i = 0; i < len; i++) {
	255	if (!(i & 3)) {
12491355 MV	256	while (--timeout) {
	257	tmp = readl(&i2c_regs->hw_i2c_queuestat);
	258	if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
	259	break;
	260	}
	261
	262	if (!timeout) {
	263	debug("MXS I2C: Failed receiving data!\n");
	264	return -ETIMEDOUT;
	265	}
	266
f4f680aa MV	267	tmp = readl(&i2c_regs->hw_i2c_queuedata);
	268	}
	269	buffer[i] = tmp & 0xff;
	270	tmp >>= 8;
	271	}
	272
	273	return 0;
	274	}
	275
1fa96e80 MV	276	static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip,
	277	uint addr, int alen, uint8_t *buffer,
	278	int len)
f4f680aa MV	279	{
f4f680aa MV	280	int ret;
58a7d1c1	281	ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1);
d22643e7 MV	282	if (ret) {
	283	debug("MXS I2C: Failed writing address\n");
	284	return ret;
	285	}
	286
58a7d1c1	287	ret = mxs_i2c_wait_for_ack(adap);
f4f680aa MV	288	if (ret)
	289	debug("MXS I2C: Failed writing address\n");
	290
	291	return ret;
	292	}
	293
1fa96e80	294	static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
f4f680aa MV	295	{
f4f680aa MV	296	int ret;
58a7d1c1	297	ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1);
d22643e7	298	if (!ret)
58a7d1c1 MV	299	ret = mxs_i2c_wait_for_ack(adap);
58a7d1c1 MV	300	mxs_i2c_reset(adap);
f4f680aa MV	301	return ret;
	302	}
	303
1fa96e80	304	static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
f4f680aa	305	{
58a7d1c1 MV	306	mxs_i2c_reset(adap);
58a7d1c1 MV	307	mxs_i2c_set_bus_speed(adap, speed);
f4f680aa MV	308
	309	return;
	310	}
1fa96e80 MV	311
	312	U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe,
	313	mxs_i2c_if_read, mxs_i2c_if_write,
	314	mxs_i2c_set_bus_speed,
	315	CONFIG_SYS_I2C_SPEED, 0, 0)
318a9cea MV	316	U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe,
	317	mxs_i2c_if_read, mxs_i2c_if_write,
	318	mxs_i2c_set_bus_speed,
	319	CONFIG_SYS_I2C_SPEED, 0, 1)