[people/ms/u-boot.git] / drivers / i2c / omap24xx_i2c.c

/*
 * Basic I2C functions
 *
 * Copyright (c) 2004 Texas Instruments
 *
 * This package is free software;  you can redistribute it and/or
 * modify it under the terms of the license found in the file
 * named COPYING that should have accompanied this file.
 *
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
 *
 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
 * Rewritten to fit into the current U-Boot framework
 *
 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
 *
 */

#include <common.h>

#include <asm/arch/i2c.h>
#include <asm/io.h>

#include "omap24xx_i2c.h"

DECLARE_GLOBAL_DATA_PTR;

#define I2C_TIMEOUT	1000

static void wait_for_bb (void);
static u16 wait_for_pin (void);
static void flush_fifo(void);

static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;

static unsigned int bus_initialized[I2C_BUS_MAX];
static unsigned int current_bus;

void i2c_init (int speed, int slaveadd)
{
	int psc, fsscll, fssclh;
	int hsscll = 0, hssclh = 0;
	u32 scll, sclh;
	int timeout = I2C_TIMEOUT;

	/* Only handle standard, fast and high speeds */
	if ((speed != OMAP_I2C_STANDARD) &&
	    (speed != OMAP_I2C_FAST_MODE) &&
	    (speed != OMAP_I2C_HIGH_SPEED)) {
		printf("Error : I2C unsupported speed %d\n", speed);
		return;
	}

	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	psc -= 1;
	if (psc < I2C_PSC_MIN) {
		printf("Error : I2C unsupported prescalar %d\n", psc);
		return;
	}

	if (speed == OMAP_I2C_HIGH_SPEED) {
		/* High speed */

		/* For first phase of HS mode */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
			(2 * OMAP_I2C_FAST_MODE);

		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing first phase clock\n");
			return;
		}

		/* For second phase of HS mode */
		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing second phase clock\n");
			return;
		}

		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;

	} else {
		/* Standard and fast speed */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing clock\n");
			return;
		}

		scll = (unsigned int)fsscll;
		sclh = (unsigned int)fssclh;
	}

	if (readw (&i2c_base->con) & I2C_CON_EN) {
		writew (0, &i2c_base->con);
		udelay (50000);
	}

	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
	udelay(1000);

	writew(I2C_CON_EN, &i2c_base->con);
	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
		if (timeout <= 0) {
			printf("ERROR: Timeout in soft-reset\n");
			return;
		}
		udelay(1000);
	}

	writew(0, &i2c_base->con);
	writew(psc, &i2c_base->psc);
	writew(scll, &i2c_base->scll);
	writew(sclh, &i2c_base->sclh);

	/* own address */
	writew (slaveadd, &i2c_base->oa);
	writew (I2C_CON_EN, &i2c_base->con);

	/* have to enable intrrupts or OMAP i2c module doesn't work */
	writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
		I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
	udelay (1000);
	flush_fifo();
	writew (0xFFFF, &i2c_base->stat);
	writew (0, &i2c_base->cnt);

	if (gd->flags & GD_FLG_RELOC)
		bus_initialized[current_bus] = 1;
}

static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
{
	int i2c_error = 0;
	u16 status;

	/* wait until bus not busy */
	wait_for_bb ();

	/* one byte only */
	writew (1, &i2c_base->cnt);
	/* set slave address */
	writew (devaddr, &i2c_base->sa);
	/* no stop bit needed here */
	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);

	/* send register offset */
	while (1) {
		status = wait_for_pin();
		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			goto read_exit;
		}
		if (status & I2C_STAT_XRDY) {
			/* Important: have to use byte access */
			writeb(regoffset, &i2c_base->data);
			writew(I2C_STAT_XRDY, &i2c_base->stat);
		}
		if (status & I2C_STAT_ARDY) {
			writew(I2C_STAT_ARDY, &i2c_base->stat);
			break;
		}
	}

	/* set slave address */
	writew(devaddr, &i2c_base->sa);
	/* read one byte from slave */
	writew(1, &i2c_base->cnt);
	/* need stop bit here */
	writew(I2C_CON_EN | I2C_CON_MST |
		I2C_CON_STT | I2C_CON_STP,
		&i2c_base->con);

	/* receive data */
	while (1) {
		status = wait_for_pin();
		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			goto read_exit;
		}
		if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
    defined(CONFIG_OMAP44XX)
			*value = readb(&i2c_base->data);
#else
			*value = readw(&i2c_base->data);
#endif
			writew(I2C_STAT_RRDY, &i2c_base->stat);
		}
		if (status & I2C_STAT_ARDY) {
			writew(I2C_STAT_ARDY, &i2c_base->stat);
			break;
		}
	}

read_exit:
	flush_fifo();
	writew (0xFFFF, &i2c_base->stat);
	writew (0, &i2c_base->cnt);
	return i2c_error;
}

static void flush_fifo(void)
{	u16 stat;

	/* note: if you try and read data when its not there or ready
	 * you get a bus error
	 */
	while(1){
		stat = readw(&i2c_base->stat);
		if(stat == I2C_STAT_RRDY){
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
    defined(CONFIG_OMAP44XX)
			readb(&i2c_base->data);
#else
			readw(&i2c_base->data);
#endif
			writew(I2C_STAT_RRDY,&i2c_base->stat);
			udelay(1000);
		}else
			break;
	}
}

int i2c_probe (uchar chip)
{
	u16 status;
	int res = 1; /* default = fail */

	if (chip == readw (&i2c_base->oa)) {
		return res;
	}

	/* wait until bus not busy */
	wait_for_bb ();

	/* try to write one byte */
	writew (1, &i2c_base->cnt);
	/* set slave address */
	writew (chip, &i2c_base->sa);
	/* stop bit needed here */
	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
	       I2C_CON_STP, &i2c_base->con);

	status = wait_for_pin();

	/* check for ACK (!NAK) */
	if (!(status & I2C_STAT_NACK))
		res = 0;

	/* abort transfer (force idle state) */
	writew(0, &i2c_base->con);

	flush_fifo();
	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
	writew(0xFFFF, &i2c_base->stat);
	return res;
}

int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	int i;

	if (alen > 1) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf ("I2C read: address out of range\n");
		return 1;
	}

	for (i = 0; i < len; i++) {
		if (i2c_read_byte (chip, addr + i, &buffer[i])) {
			printf ("I2C read: I/O error\n");
			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
			return 1;
		}
	}

	return 0;
}

int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	int i;
	u16 status;
	int i2c_error = 0;

	if (alen > 1) {
		printf("I2C write: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf("I2C write: address 0x%x + 0x%x out of range\n",
				addr, len);
		return 1;
	}

	/* wait until bus not busy */
	wait_for_bb();

	/* start address phase - will write regoffset + len bytes data */
	/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
	writew(alen + len, &i2c_base->cnt);
	/* set slave address */
	writew(chip, &i2c_base->sa);
	/* stop bit needed here */
	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
		I2C_CON_STP, &i2c_base->con);

	/* Send address byte */
	status = wait_for_pin();

	if (status == 0 || status & I2C_STAT_NACK) {
		i2c_error = 1;
		printf("error waiting for i2c address ACK (status=0x%x)\n",
		      status);
		goto write_exit;
	}

	if (status & I2C_STAT_XRDY) {
		writeb(addr & 0xFF, &i2c_base->data);
		writew(I2C_STAT_XRDY, &i2c_base->stat);
	} else {
		i2c_error = 1;
		printf("i2c bus not ready for transmit (status=0x%x)\n",
		      status);
		goto write_exit;
	}

	/* address phase is over, now write data */
	for (i = 0; i < len; i++) {
		status = wait_for_pin();

		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			printf("i2c error waiting for data ACK (status=0x%x)\n",
					status);
			goto write_exit;
		}

		if (status & I2C_STAT_XRDY) {
			writeb(buffer[i], &i2c_base->data);
			writew(I2C_STAT_XRDY, &i2c_base->stat);
		} else {
			i2c_error = 1;
			printf("i2c bus not ready for Tx (i=%d)\n", i);
			goto write_exit;
		}
	}

write_exit:
	flush_fifo();
	writew(0xFFFF, &i2c_base->stat);
	return i2c_error;
}

static void wait_for_bb (void)
{
	int timeout = I2C_TIMEOUT;
	u16 stat;

	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
		writew (stat, &i2c_base->stat);
		udelay(1000);
	}

	if (timeout <= 0) {
		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
			readw (&i2c_base->stat));
	}
	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
}

static u16 wait_for_pin (void)
{
	u16 status;
	int timeout = I2C_TIMEOUT;

	do {
		udelay (1000);
		status = readw (&i2c_base->stat);
	} while (  !(status &
		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
		    I2C_STAT_AL)) && timeout--);

	if (timeout <= 0) {
		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
			readw (&i2c_base->stat));
		writew(0xFFFF, &i2c_base->stat);
		status = 0;
	}

	return status;
}

int i2c_set_bus_num(unsigned int bus)
{
	if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
		printf("Bad bus: %d\n", bus);
		return -1;
	}

#if I2C_BUS_MAX==3
	if (bus == 2)
		i2c_base = (struct i2c *)I2C_BASE3;
	else
#endif
	if (bus == 1)
		i2c_base = (struct i2c *)I2C_BASE2;
	else
		i2c_base = (struct i2c *)I2C_BASE1;

	current_bus = bus;

	if(!bus_initialized[current_bus])
		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	return 0;
}

int i2c_get_bus_num(void)
{
	return (int) current_bus;
}
Commit	Line	Data
8ed96046 WD	1	/*
	2	* Basic I2C functions
	3	*
	4	* Copyright (c) 2004 Texas Instruments
	5	*
	6	* This package is free software; you can redistribute it and/or
	7	* modify it under the terms of the license found in the file
	8	* named COPYING that should have accompanied this file.
	9	*
	10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
	11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
	12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
	13	*
	14	* Author: Jian Zhang jzhang@ti.com, Texas Instruments
	15	*
	16	* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
	17	* Rewritten to fit into the current U-Boot framework
	18	*
	19	* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
	20	*
	21	*/
	22
	23	#include <common.h>
289f932c	24
8ed96046 WD	25	#include <asm/arch/i2c.h>
	26	#include <asm/io.h>
	27
938717ce SS	28	#include "omap24xx_i2c.h"
938717ce SS	29
29565326 JR	30	DECLARE_GLOBAL_DATA_PTR;
29565326 JR	31
73e8747f	32	#define I2C_TIMEOUT 1000
d708395d	33
8ed96046 WD	34	static void wait_for_bb (void);
8ed96046 WD	35	static u16 wait_for_pin (void);
49a7581c	36	static void flush_fifo(void);
8ed96046	37
1d2e96de DB	38	static struct i2c i2c_base = (struct i2c )I2C_DEFAULT_BASE;
	39
	40	static unsigned int bus_initialized[I2C_BUS_MAX];
	41	static unsigned int current_bus;
	42
8ed96046 WD	43	void i2c_init (int speed, int slaveadd)
8ed96046 WD	44	{
7f79dfb4 TR	45	int psc, fsscll, fssclh;
	46	int hsscll = 0, hssclh = 0;
	47	u32 scll, sclh;
d708395d	48	int timeout = I2C_TIMEOUT;
7f79dfb4 TR	49
	50	/* Only handle standard, fast and high speeds */
	51	if ((speed != OMAP_I2C_STANDARD) &&
	52	(speed != OMAP_I2C_FAST_MODE) &&
	53	(speed != OMAP_I2C_HIGH_SPEED)) {
	54	printf("Error : I2C unsupported speed %d\n", speed);
	55	return;
	56	}
	57
	58	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	59	psc -= 1;
	60	if (psc < I2C_PSC_MIN) {
	61	printf("Error : I2C unsupported prescalar %d\n", psc);
	62	return;
	63	}
	64
	65	if (speed == OMAP_I2C_HIGH_SPEED) {
	66	/* High speed */
	67
	68	/* For first phase of HS mode */
	69	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
	70	(2 * OMAP_I2C_FAST_MODE);
	71
	72	fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
	73	fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
	74	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	75	((fsscll > 255) \|\| (fssclh > 255))) {
	76	printf("Error : I2C initializing first phase clock\n");
	77	return;
	78	}
	79
	80	/* For second phase of HS mode */
	81	hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	82
	83	hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
	84	hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
	85	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	86	((fsscll > 255) \|\| (fssclh > 255))) {
	87	printf("Error : I2C initializing second phase clock\n");
	88	return;
	89	}
	90
	91	scll = (unsigned int)hsscll << 8 \| (unsigned int)fsscll;
	92	sclh = (unsigned int)hssclh << 8 \| (unsigned int)fssclh;
	93
	94	} else {
	95	/* Standard and fast speed */
	96	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	97
	98	fsscll -= I2C_FASTSPEED_SCLL_TRIM;
	99	fssclh -= I2C_FASTSPEED_SCLH_TRIM;
	100	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	101	((fsscll > 255) \|\| (fssclh > 255))) {
	102	printf("Error : I2C initializing clock\n");
	103	return;
	104	}
	105
	106	scll = (unsigned int)fsscll;
	107	sclh = (unsigned int)fssclh;
	108	}
8ed96046	109
1d2e96de DB	110	if (readw (&i2c_base->con) & I2C_CON_EN) {
1d2e96de DB	111	writew (0, &i2c_base->con);
8ed96046 WD	112	udelay (50000);
	113	}
	114
d708395d SS	115	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
	116	udelay(1000);
	117
	118	writew(I2C_CON_EN, &i2c_base->con);
	119	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
	120	if (timeout <= 0) {
	121	printf("ERROR: Timeout in soft-reset\n");
	122	return;
	123	}
	124	udelay(1000);
	125	}
	126
	127	writew(0, &i2c_base->con);
1d2e96de DB	128	writew(psc, &i2c_base->psc);
	129	writew(scll, &i2c_base->scll);
	130	writew(sclh, &i2c_base->sclh);
7f79dfb4	131
8ed96046	132	/* own address */
1d2e96de DB	133	writew (slaveadd, &i2c_base->oa);
1d2e96de DB	134	writew (I2C_CON_EN, &i2c_base->con);
49a7581c	135
8ed96046	136	/* have to enable intrrupts or OMAP i2c module doesn't work */
e23c7c95	137	writew (I2C_IE_XRDY_IE \| I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \|
1d2e96de	138	I2C_IE_NACK_IE \| I2C_IE_AL_IE, &i2c_base->ie);
8ed96046	139	udelay (1000);
49a7581c	140	flush_fifo();
1d2e96de DB	141	writew (0xFFFF, &i2c_base->stat);
	142	writew (0, &i2c_base->cnt);
	143
1724fe9a HS	144	if (gd->flags & GD_FLG_RELOC)
1724fe9a HS	145	bus_initialized[current_bus] = 1;
8ed96046 WD	146	}
	147
	148	static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
	149	{
	150	int i2c_error = 0;
	151	u16 status;
	152
	153	/* wait until bus not busy */
	154	wait_for_bb ();
	155
	156	/* one byte only */
1d2e96de	157	writew (1, &i2c_base->cnt);
8ed96046	158	/* set slave address */
1d2e96de	159	writew (devaddr, &i2c_base->sa);
8ed96046	160	/* no stop bit needed here */
1d2e96de	161	writew (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX, &i2c_base->con);
8ed96046	162
da0cc665 SS	163	/* send register offset */
	164	while (1) {
	165	status = wait_for_pin();
	166	if (status == 0 \|\| status & I2C_STAT_NACK) {
8ed96046	167	i2c_error = 1;
da0cc665 SS	168	goto read_exit;
	169	}
	170	if (status & I2C_STAT_XRDY) {
	171	/* Important: have to use byte access */
	172	writeb(regoffset, &i2c_base->data);
	173	writew(I2C_STAT_XRDY, &i2c_base->stat);
	174	}
	175	if (status & I2C_STAT_ARDY) {
	176	writew(I2C_STAT_ARDY, &i2c_base->stat);
	177	break;
8ed96046	178	}
8ed96046 WD	179	}
8ed96046 WD	180
da0cc665 SS	181	/* set slave address */
	182	writew(devaddr, &i2c_base->sa);
	183	/* read one byte from slave */
	184	writew(1, &i2c_base->cnt);
	185	/* need stop bit here */
	186	writew(I2C_CON_EN \| I2C_CON_MST \|
	187	I2C_CON_STT \| I2C_CON_STP,
	188	&i2c_base->con);
	189
	190	/* receive data */
	191	while (1) {
	192	status = wait_for_pin();
	193	if (status == 0 \|\| status & I2C_STAT_NACK) {
	194	i2c_error = 1;
	195	goto read_exit;
8ed96046	196	}
8ed96046	197	if (status & I2C_STAT_RRDY) {
938717ce SS	198	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
938717ce SS	199	defined(CONFIG_OMAP44XX)
da0cc665	200	*value = readb(&i2c_base->data);
7d264c1e	201	#else
da0cc665	202	*value = readw(&i2c_base->data);
7d264c1e	203	#endif
da0cc665	204	writew(I2C_STAT_RRDY, &i2c_base->stat);
8ed96046	205	}
da0cc665 SS	206	if (status & I2C_STAT_ARDY) {
	207	writew(I2C_STAT_ARDY, &i2c_base->stat);
	208	break;
8ed96046 WD	209	}
8ed96046 WD	210	}
da0cc665 SS	211
da0cc665 SS	212	read_exit:
8ed96046	213	flush_fifo();
1d2e96de DB	214	writew (0xFFFF, &i2c_base->stat);
1d2e96de DB	215	writew (0, &i2c_base->cnt);
8ed96046 WD	216	return i2c_error;
	217	}
	218
49a7581c	219	static void flush_fifo(void)
8ed96046	220	{ u16 stat;
082acfd4 WD	221
	222	/* note: if you try and read data when its not there or ready
	223	* you get a bus error
	224	*/
8ed96046	225	while(1){
1d2e96de	226	stat = readw(&i2c_base->stat);
8ed96046	227	if(stat == I2C_STAT_RRDY){
938717ce SS	228	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
938717ce SS	229	defined(CONFIG_OMAP44XX)
1d2e96de	230	readb(&i2c_base->data);
7d264c1e	231	#else
1d2e96de	232	readw(&i2c_base->data);
7d264c1e	233	#endif
1d2e96de	234	writew(I2C_STAT_RRDY,&i2c_base->stat);
8ed96046 WD	235	udelay(1000);
	236	}else
	237	break;
	238	}
	239	}
	240
	241	int i2c_probe (uchar chip)
	242	{
fbad3555	243	u16 status;
8ed96046 WD	244	int res = 1; /* default = fail */
8ed96046 WD	245
1d2e96de	246	if (chip == readw (&i2c_base->oa)) {
8ed96046 WD	247	return res;
	248	}
	249
	250	/* wait until bus not busy */
	251	wait_for_bb ();
	252
0e57968a	253	/* try to write one byte */
1d2e96de	254	writew (1, &i2c_base->cnt);
8ed96046	255	/* set slave address */
1d2e96de	256	writew (chip, &i2c_base->sa);
8ed96046	257	/* stop bit needed here */
0e57968a NT	258	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
0e57968a NT	259	I2C_CON_STP, &i2c_base->con);
8ed96046	260
0e57968a NT	261	status = wait_for_pin();
	262
	263	/* check for ACK (!NAK) */
	264	if (!(status & I2C_STAT_NACK))
	265	res = 0;
	266
	267	/* abort transfer (force idle state) */
	268	writew(0, &i2c_base->con);
fbad3555	269
8ed96046	270	flush_fifo();
1d2e96de DB	271	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
1d2e96de DB	272	writew(0xFFFF, &i2c_base->stat);
8ed96046 WD	273	return res;
	274	}
	275
	276	int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
	277	{
	278	int i;
	279
	280	if (alen > 1) {
	281	printf ("I2C read: addr len %d not supported\n", alen);
	282	return 1;
	283	}
	284
	285	if (addr + len > 256) {
	286	printf ("I2C read: address out of range\n");
	287	return 1;
	288	}
	289
	290	for (i = 0; i < len; i++) {
	291	if (i2c_read_byte (chip, addr + i, &buffer[i])) {
	292	printf ("I2C read: I/O error\n");
6d0f6bcf	293	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
8ed96046 WD	294	return 1;
	295	}
	296	}
	297
	298	return 0;
	299	}
	300
	301	int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
	302	{
	303	int i;
0607e2b9 MJ	304	u16 status;
0607e2b9 MJ	305	int i2c_error = 0;
8ed96046 WD	306
8ed96046 WD	307	if (alen > 1) {
0607e2b9	308	printf("I2C write: addr len %d not supported\n", alen);
8ed96046 WD	309	return 1;
	310	}
	311
	312	if (addr + len > 256) {
0607e2b9 MJ	313	printf("I2C write: address 0x%x + 0x%x out of range\n",
0607e2b9 MJ	314	addr, len);
8ed96046 WD	315	return 1;
	316	}
	317
0607e2b9 MJ	318	/* wait until bus not busy */
	319	wait_for_bb();
	320
	321	/* start address phase - will write regoffset + len bytes data */
	322	/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
	323	writew(alen + len, &i2c_base->cnt);
	324	/* set slave address */
	325	writew(chip, &i2c_base->sa);
	326	/* stop bit needed here */
	327	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
	328	I2C_CON_STP, &i2c_base->con);
	329
	330	/* Send address byte */
	331	status = wait_for_pin();
	332
	333	if (status == 0 \|\| status & I2C_STAT_NACK) {
	334	i2c_error = 1;
	335	printf("error waiting for i2c address ACK (status=0x%x)\n",
	336	status);
	337	goto write_exit;
	338	}
	339
	340	if (status & I2C_STAT_XRDY) {
	341	writeb(addr & 0xFF, &i2c_base->data);
	342	writew(I2C_STAT_XRDY, &i2c_base->stat);
	343	} else {
	344	i2c_error = 1;
	345	printf("i2c bus not ready for transmit (status=0x%x)\n",
	346	status);
	347	goto write_exit;
	348	}
	349
	350	/* address phase is over, now write data */
8ed96046	351	for (i = 0; i < len; i++) {
0607e2b9 MJ	352	status = wait_for_pin();
	353
	354	if (status == 0 \|\| status & I2C_STAT_NACK) {
	355	i2c_error = 1;
	356	printf("i2c error waiting for data ACK (status=0x%x)\n",
	357	status);
	358	goto write_exit;
	359	}
	360
	361	if (status & I2C_STAT_XRDY) {
	362	writeb(buffer[i], &i2c_base->data);
	363	writew(I2C_STAT_XRDY, &i2c_base->stat);
	364	} else {
	365	i2c_error = 1;
	366	printf("i2c bus not ready for Tx (i=%d)\n", i);
	367	goto write_exit;
8ed96046 WD	368	}
	369	}
	370
0607e2b9 MJ	371	write_exit:
	372	flush_fifo();
	373	writew(0xFFFF, &i2c_base->stat);
	374	return i2c_error;
8ed96046 WD	375	}
	376
	377	static void wait_for_bb (void)
	378	{
73e8747f	379	int timeout = I2C_TIMEOUT;
8ed96046 WD	380	u16 stat;
8ed96046 WD	381
f9a78b8d	382	writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
1d2e96de DB	383	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
1d2e96de DB	384	writew (stat, &i2c_base->stat);
73e8747f	385	udelay(1000);
8ed96046 WD	386	}
	387
	388	if (timeout <= 0) {
	389	printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
1d2e96de	390	readw (&i2c_base->stat));
8ed96046	391	}
1d2e96de	392	writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
8ed96046 WD	393	}
	394
	395	static u16 wait_for_pin (void)
	396	{
	397	u16 status;
73e8747f	398	int timeout = I2C_TIMEOUT;
8ed96046 WD	399
	400	do {
	401	udelay (1000);
1d2e96de	402	status = readw (&i2c_base->stat);
8ed96046 WD	403	} while ( !(status &
	404	(I2C_STAT_ROVR \| I2C_STAT_XUDF \| I2C_STAT_XRDY \|
	405	I2C_STAT_RRDY \| I2C_STAT_ARDY \| I2C_STAT_NACK \|
	406	I2C_STAT_AL)) && timeout--);
	407
	408	if (timeout <= 0) {
	409	printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
1d2e96de	410	readw (&i2c_base->stat));
73e8747f SS	411	writew(0xFFFF, &i2c_base->stat);
	412	status = 0;
	413	}
	414
8ed96046 WD	415	return status;
8ed96046 WD	416	}
1d2e96de DB	417
	418	int i2c_set_bus_num(unsigned int bus)
	419	{
	420	if ((bus < 0) \|\| (bus >= I2C_BUS_MAX)) {
	421	printf("Bad bus: %d\n", bus);
	422	return -1;
	423	}
	424
	425	#if I2C_BUS_MAX==3
	426	if (bus == 2)
	427	i2c_base = (struct i2c *)I2C_BASE3;
	428	else
	429	#endif
	430	if (bus == 1)
	431	i2c_base = (struct i2c *)I2C_BASE2;
	432	else
	433	i2c_base = (struct i2c *)I2C_BASE1;
	434
	435	current_bus = bus;
	436
	437	if(!bus_initialized[current_bus])
	438	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	439
	440	return 0;
	441	}
938717ce SS	442
	443	int i2c_get_bus_num(void)
	444	{
	445	return (int) current_bus;
	446	}