[people/ms/u-boot.git] / drivers / i2c / omap24xx_i2c.c

/*
 * Basic I2C functions
 *
 * Copyright (c) 2004 Texas Instruments
 *
 * This package is free software;  you can redistribute it and/or
 * modify it under the terms of the license found in the file
 * named COPYING that should have accompanied this file.
 *
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
 *
 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
 * Rewritten to fit into the current U-Boot framework
 *
 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
 *
 */

#include <common.h>

#include <asm/arch/i2c.h>
#include <asm/io.h>

#include "omap24xx_i2c.h"

static void wait_for_bb (void);
static u16 wait_for_pin (void);
static void flush_fifo(void);

static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;

static unsigned int bus_initialized[I2C_BUS_MAX];
static unsigned int current_bus;

void i2c_init (int speed, int slaveadd)
{
	int psc, fsscll, fssclh;
	int hsscll = 0, hssclh = 0;
	u32 scll, sclh;

	/* Only handle standard, fast and high speeds */
	if ((speed != OMAP_I2C_STANDARD) &&
	    (speed != OMAP_I2C_FAST_MODE) &&
	    (speed != OMAP_I2C_HIGH_SPEED)) {
		printf("Error : I2C unsupported speed %d\n", speed);
		return;
	}

	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	psc -= 1;
	if (psc < I2C_PSC_MIN) {
		printf("Error : I2C unsupported prescalar %d\n", psc);
		return;
	}

	if (speed == OMAP_I2C_HIGH_SPEED) {
		/* High speed */

		/* For first phase of HS mode */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
			(2 * OMAP_I2C_FAST_MODE);

		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing first phase clock\n");
			return;
		}

		/* For second phase of HS mode */
		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing second phase clock\n");
			return;
		}

		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;

	} else {
		/* Standard and fast speed */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing clock\n");
			return;
		}

		scll = (unsigned int)fsscll;
		sclh = (unsigned int)fssclh;
	}

	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
	udelay(1000);
	writew(0x0, &i2c_base->sysc); /* will probably self clear but */

	if (readw (&i2c_base->con) & I2C_CON_EN) {
		writew (0, &i2c_base->con);
		udelay (50000);
	}

	writew(psc, &i2c_base->psc);
	writew(scll, &i2c_base->scll);
	writew(sclh, &i2c_base->sclh);

	/* own address */
	writew (slaveadd, &i2c_base->oa);
	writew (I2C_CON_EN, &i2c_base->con);

	/* have to enable intrrupts or OMAP i2c module doesn't work */
	writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
		I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
	udelay (1000);
	flush_fifo();
	writew (0xFFFF, &i2c_base->stat);
	writew (0, &i2c_base->cnt);

	bus_initialized[current_bus] = 1;
}

static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
{
	int i2c_error = 0;
	u16 status;

	/* wait until bus not busy */
	wait_for_bb ();

	/* one byte only */
	writew (1, &i2c_base->cnt);
	/* set slave address */
	writew (devaddr, &i2c_base->sa);
	/* no stop bit needed here */
	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);

	status = wait_for_pin ();

	if (status & I2C_STAT_XRDY) {
		/* Important: have to use byte access */
		writeb (regoffset, &i2c_base->data);
		udelay (20000);
		if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
			i2c_error = 1;
		}
	} else {
		i2c_error = 1;
	}

	if (!i2c_error) {
		/* free bus, otherwise we can't use a combined transction */
		writew (0, &i2c_base->con);
		while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
			udelay (10000);
			/* Have to clear pending interrupt to clear I2C_STAT */
			writew (0xFFFF, &i2c_base->stat);
		}

		wait_for_bb ();
		/* set slave address */
		writew (devaddr, &i2c_base->sa);
		/* read one byte from slave */
		writew (1, &i2c_base->cnt);
		/* need stop bit here */
		writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
			&i2c_base->con);

		status = wait_for_pin ();
		if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
    defined(CONFIG_OMAP44XX)
			*value = readb (&i2c_base->data);
#else
			*value = readw (&i2c_base->data);
#endif
			udelay (20000);
		} else {
			i2c_error = 1;
		}

		if (!i2c_error) {
			writew (I2C_CON_EN, &i2c_base->con);
			while (readw (&i2c_base->stat)
			       || (readw (&i2c_base->con) & I2C_CON_MST)) {
				udelay (10000);
				writew (0xFFFF, &i2c_base->stat);
			}
		}
	}
	flush_fifo();
	writew (0xFFFF, &i2c_base->stat);
	writew (0, &i2c_base->cnt);
	return i2c_error;
}

static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
{
	int i2c_error = 0;
	u16 status, stat;

	/* wait until bus not busy */
	wait_for_bb ();

	/* two bytes */
	writew (2, &i2c_base->cnt);
	/* set slave address */
	writew (devaddr, &i2c_base->sa);
	/* stop bit needed here */
	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
		I2C_CON_STP, &i2c_base->con);

	/* wait until state change */
	status = wait_for_pin ();

	if (status & I2C_STAT_XRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
    defined(CONFIG_OMAP44XX)
		/* send out 1 byte */
		writeb (regoffset, &i2c_base->data);
		writew (I2C_STAT_XRDY, &i2c_base->stat);

		status = wait_for_pin ();
		if ((status & I2C_STAT_XRDY)) {
			/* send out next 1 byte */
			writeb (value, &i2c_base->data);
			writew (I2C_STAT_XRDY, &i2c_base->stat);
		} else {
			i2c_error = 1;
		}
#else
		/* send out two bytes */
		writew ((value << 8) + regoffset, &i2c_base->data);
#endif
		/* must have enough delay to allow BB bit to go low */
		udelay (50000);
		if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
			i2c_error = 1;
		}
	} else {
		i2c_error = 1;
	}

	if (!i2c_error) {
		int eout = 200;

		writew (I2C_CON_EN, &i2c_base->con);
		while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
			udelay (1000);
			/* have to read to clear intrrupt */
			writew (0xFFFF, &i2c_base->stat);
			if(--eout == 0) /* better leave with error than hang */
				break;
		}
	}
	flush_fifo();
	writew (0xFFFF, &i2c_base->stat);
	writew (0, &i2c_base->cnt);
	return i2c_error;
}

static void flush_fifo(void)
{	u16 stat;

	/* note: if you try and read data when its not there or ready
	 * you get a bus error
	 */
	while(1){
		stat = readw(&i2c_base->stat);
		if(stat == I2C_STAT_RRDY){
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
    defined(CONFIG_OMAP44XX)
			readb(&i2c_base->data);
#else
			readw(&i2c_base->data);
#endif
			writew(I2C_STAT_RRDY,&i2c_base->stat);
			udelay(1000);
		}else
			break;
	}
}

int i2c_probe (uchar chip)
{
	int res = 1; /* default = fail */

	if (chip == readw (&i2c_base->oa)) {
		return res;
	}

	/* wait until bus not busy */
	wait_for_bb ();

	/* try to read one byte */
	writew (1, &i2c_base->cnt);
	/* set slave address */
	writew (chip, &i2c_base->sa);
	/* stop bit needed here */
	writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
	/* enough delay for the NACK bit set */
	udelay (50000);

	if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
		res = 0;      /* success case */
		flush_fifo();
		writew(0xFFFF, &i2c_base->stat);
	} else {
		writew(0xFFFF, &i2c_base->stat);	 /* failue, clear sources*/
		writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
		udelay(20000);
		wait_for_bb ();
	}
	flush_fifo();
	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
	writew(0xFFFF, &i2c_base->stat);
	return res;
}

int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	int i;

	if (alen > 1) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf ("I2C read: address out of range\n");
		return 1;
	}

	for (i = 0; i < len; i++) {
		if (i2c_read_byte (chip, addr + i, &buffer[i])) {
			printf ("I2C read: I/O error\n");
			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
			return 1;
		}
	}

	return 0;
}

int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	int i;

	if (alen > 1) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf ("I2C read: address out of range\n");
		return 1;
	}

	for (i = 0; i < len; i++) {
		if (i2c_write_byte (chip, addr + i, buffer[i])) {
			printf ("I2C read: I/O error\n");
			i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
			return 1;
		}
	}

	return 0;
}

static void wait_for_bb (void)
{
	int timeout = 10;
	u16 stat;

	writew(0xFFFF, &i2c_base->stat);	 /* clear current interruts...*/
	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
		writew (stat, &i2c_base->stat);
		udelay (50000);
	}

	if (timeout <= 0) {
		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
			readw (&i2c_base->stat));
	}
	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
}

static u16 wait_for_pin (void)
{
	u16 status;
	int timeout = 10;

	do {
		udelay (1000);
		status = readw (&i2c_base->stat);
	} while (  !(status &
		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
		    I2C_STAT_AL)) && timeout--);

	if (timeout <= 0) {
		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
			readw (&i2c_base->stat));
			writew(0xFFFF, &i2c_base->stat);
}
	return status;
}

int i2c_set_bus_num(unsigned int bus)
{
	if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
		printf("Bad bus: %d\n", bus);
		return -1;
	}

#if I2C_BUS_MAX==3
	if (bus == 2)
		i2c_base = (struct i2c *)I2C_BASE3;
	else
#endif
	if (bus == 1)
		i2c_base = (struct i2c *)I2C_BASE2;
	else
		i2c_base = (struct i2c *)I2C_BASE1;

	current_bus = bus;

	if(!bus_initialized[current_bus])
		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	return 0;
}

int i2c_get_bus_num(void)
{
	return (int) current_bus;
}
Commit	Line	Data
8ed96046 WD	1	/*
	2	* Basic I2C functions
	3	*
	4	* Copyright (c) 2004 Texas Instruments
	5	*
	6	* This package is free software; you can redistribute it and/or
	7	* modify it under the terms of the license found in the file
	8	* named COPYING that should have accompanied this file.
	9	*
	10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
	11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
	12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
	13	*
	14	* Author: Jian Zhang jzhang@ti.com, Texas Instruments
	15	*
	16	* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
	17	* Rewritten to fit into the current U-Boot framework
	18	*
	19	* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
	20	*
	21	*/
	22
	23	#include <common.h>
289f932c	24
8ed96046 WD	25	#include <asm/arch/i2c.h>
	26	#include <asm/io.h>
	27
938717ce SS	28	#include "omap24xx_i2c.h"
938717ce SS	29
8ed96046 WD	30	static void wait_for_bb (void);
8ed96046 WD	31	static u16 wait_for_pin (void);
49a7581c	32	static void flush_fifo(void);
8ed96046	33
1d2e96de DB	34	static struct i2c i2c_base = (struct i2c )I2C_DEFAULT_BASE;
	35
	36	static unsigned int bus_initialized[I2C_BUS_MAX];
	37	static unsigned int current_bus;
	38
8ed96046 WD	39	void i2c_init (int speed, int slaveadd)
8ed96046 WD	40	{
7f79dfb4 TR	41	int psc, fsscll, fssclh;
	42	int hsscll = 0, hssclh = 0;
	43	u32 scll, sclh;
	44
	45	/* Only handle standard, fast and high speeds */
	46	if ((speed != OMAP_I2C_STANDARD) &&
	47	(speed != OMAP_I2C_FAST_MODE) &&
	48	(speed != OMAP_I2C_HIGH_SPEED)) {
	49	printf("Error : I2C unsupported speed %d\n", speed);
	50	return;
	51	}
	52
	53	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	54	psc -= 1;
	55	if (psc < I2C_PSC_MIN) {
	56	printf("Error : I2C unsupported prescalar %d\n", psc);
	57	return;
	58	}
	59
	60	if (speed == OMAP_I2C_HIGH_SPEED) {
	61	/* High speed */
	62
	63	/* For first phase of HS mode */
	64	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
	65	(2 * OMAP_I2C_FAST_MODE);
	66
	67	fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
	68	fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
	69	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	70	((fsscll > 255) \|\| (fssclh > 255))) {
	71	printf("Error : I2C initializing first phase clock\n");
	72	return;
	73	}
	74
	75	/* For second phase of HS mode */
	76	hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	77
	78	hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
	79	hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
	80	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	81	((fsscll > 255) \|\| (fssclh > 255))) {
	82	printf("Error : I2C initializing second phase clock\n");
	83	return;
	84	}
	85
	86	scll = (unsigned int)hsscll << 8 \| (unsigned int)fsscll;
	87	sclh = (unsigned int)hssclh << 8 \| (unsigned int)fssclh;
	88
	89	} else {
	90	/* Standard and fast speed */
	91	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	92
	93	fsscll -= I2C_FASTSPEED_SCLL_TRIM;
	94	fssclh -= I2C_FASTSPEED_SCLH_TRIM;
	95	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	96	((fsscll > 255) \|\| (fssclh > 255))) {
	97	printf("Error : I2C initializing clock\n");
	98	return;
	99	}
	100
	101	scll = (unsigned int)fsscll;
	102	sclh = (unsigned int)fssclh;
	103	}
8ed96046	104
1d2e96de	105	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
49a7581c	106	udelay(1000);
1d2e96de	107	writew(0x0, &i2c_base->sysc); /* will probably self clear but */
49a7581c	108
1d2e96de DB	109	if (readw (&i2c_base->con) & I2C_CON_EN) {
1d2e96de DB	110	writew (0, &i2c_base->con);
8ed96046 WD	111	udelay (50000);
	112	}
	113
1d2e96de DB	114	writew(psc, &i2c_base->psc);
	115	writew(scll, &i2c_base->scll);
	116	writew(sclh, &i2c_base->sclh);
7f79dfb4	117
8ed96046	118	/* own address */
1d2e96de DB	119	writew (slaveadd, &i2c_base->oa);
1d2e96de DB	120	writew (I2C_CON_EN, &i2c_base->con);
49a7581c	121
8ed96046	122	/* have to enable intrrupts or OMAP i2c module doesn't work */
e23c7c95	123	writew (I2C_IE_XRDY_IE \| I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \|
1d2e96de	124	I2C_IE_NACK_IE \| I2C_IE_AL_IE, &i2c_base->ie);
8ed96046	125	udelay (1000);
49a7581c	126	flush_fifo();
1d2e96de DB	127	writew (0xFFFF, &i2c_base->stat);
	128	writew (0, &i2c_base->cnt);
	129
	130	bus_initialized[current_bus] = 1;
8ed96046 WD	131	}
	132
	133	static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
	134	{
	135	int i2c_error = 0;
	136	u16 status;
	137
	138	/* wait until bus not busy */
	139	wait_for_bb ();
	140
	141	/* one byte only */
1d2e96de	142	writew (1, &i2c_base->cnt);
8ed96046	143	/* set slave address */
1d2e96de	144	writew (devaddr, &i2c_base->sa);
8ed96046	145	/* no stop bit needed here */
1d2e96de	146	writew (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX, &i2c_base->con);
8ed96046 WD	147
	148	status = wait_for_pin ();
	149
	150	if (status & I2C_STAT_XRDY) {
	151	/* Important: have to use byte access */
1d2e96de	152	writeb (regoffset, &i2c_base->data);
8ed96046	153	udelay (20000);
1d2e96de	154	if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
8ed96046 WD	155	i2c_error = 1;
	156	}
	157	} else {
	158	i2c_error = 1;
	159	}
	160
	161	if (!i2c_error) {
	162	/* free bus, otherwise we can't use a combined transction */
1d2e96de DB	163	writew (0, &i2c_base->con);
1d2e96de DB	164	while (readw (&i2c_base->stat) \|\| (readw (&i2c_base->con) & I2C_CON_MST)) {
8ed96046 WD	165	udelay (10000);
8ed96046 WD	166	/* Have to clear pending interrupt to clear I2C_STAT */
1d2e96de	167	writew (0xFFFF, &i2c_base->stat);
8ed96046 WD	168	}
	169
	170	wait_for_bb ();
	171	/* set slave address */
1d2e96de	172	writew (devaddr, &i2c_base->sa);
8ed96046	173	/* read one byte from slave */
1d2e96de	174	writew (1, &i2c_base->cnt);
8ed96046	175	/* need stop bit here */
e23c7c95	176	writew (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP,
1d2e96de	177	&i2c_base->con);
8ed96046 WD	178
	179	status = wait_for_pin ();
	180	if (status & I2C_STAT_RRDY) {
938717ce SS	181	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
938717ce SS	182	defined(CONFIG_OMAP44XX)
1d2e96de	183	*value = readb (&i2c_base->data);
7d264c1e	184	#else
1d2e96de	185	*value = readw (&i2c_base->data);
7d264c1e	186	#endif
8ed96046 WD	187	udelay (20000);
	188	} else {
	189	i2c_error = 1;
	190	}
	191
	192	if (!i2c_error) {
1d2e96de DB	193	writew (I2C_CON_EN, &i2c_base->con);
	194	while (readw (&i2c_base->stat)
	195	\|\| (readw (&i2c_base->con) & I2C_CON_MST)) {
8ed96046	196	udelay (10000);
1d2e96de	197	writew (0xFFFF, &i2c_base->stat);
8ed96046 WD	198	}
	199	}
	200	}
	201	flush_fifo();
1d2e96de DB	202	writew (0xFFFF, &i2c_base->stat);
1d2e96de DB	203	writew (0, &i2c_base->cnt);
8ed96046 WD	204	return i2c_error;
	205	}
	206
	207	static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
	208	{
	209	int i2c_error = 0;
	210	u16 status, stat;
	211
	212	/* wait until bus not busy */
	213	wait_for_bb ();
	214
	215	/* two bytes */
1d2e96de	216	writew (2, &i2c_base->cnt);
8ed96046	217	/* set slave address */
1d2e96de	218	writew (devaddr, &i2c_base->sa);
8ed96046	219	/* stop bit needed here */
e23c7c95	220	writew (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
1d2e96de	221	I2C_CON_STP, &i2c_base->con);
8ed96046 WD	222
	223	/* wait until state change */
	224	status = wait_for_pin ();
	225
	226	if (status & I2C_STAT_XRDY) {
938717ce SS	227	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
938717ce SS	228	defined(CONFIG_OMAP44XX)
7d264c1e	229	/* send out 1 byte */
1d2e96de DB	230	writeb (regoffset, &i2c_base->data);
1d2e96de DB	231	writew (I2C_STAT_XRDY, &i2c_base->stat);
7d264c1e DB	232
	233	status = wait_for_pin ();
	234	if ((status & I2C_STAT_XRDY)) {
	235	/* send out next 1 byte */
1d2e96de DB	236	writeb (value, &i2c_base->data);
1d2e96de DB	237	writew (I2C_STAT_XRDY, &i2c_base->stat);
7d264c1e DB	238	} else {
	239	i2c_error = 1;
	240	}
	241	#else
8ed96046	242	/* send out two bytes */
1d2e96de	243	writew ((value << 8) + regoffset, &i2c_base->data);
7d264c1e	244	#endif
8ed96046 WD	245	/* must have enough delay to allow BB bit to go low */
8ed96046 WD	246	udelay (50000);
1d2e96de	247	if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
8ed96046 WD	248	i2c_error = 1;
	249	}
	250	} else {
	251	i2c_error = 1;
	252	}
	253
	254	if (!i2c_error) {
49a7581c WD	255	int eout = 200;
49a7581c WD	256
1d2e96de DB	257	writew (I2C_CON_EN, &i2c_base->con);
1d2e96de DB	258	while ((stat = readw (&i2c_base->stat)) \|\| (readw (&i2c_base->con) & I2C_CON_MST)) {
8ed96046 WD	259	udelay (1000);
8ed96046 WD	260	/* have to read to clear intrrupt */
1d2e96de	261	writew (0xFFFF, &i2c_base->stat);
49a7581c WD	262	if(--eout == 0) /* better leave with error than hang */
49a7581c WD	263	break;
8ed96046 WD	264	}
	265	}
	266	flush_fifo();
1d2e96de DB	267	writew (0xFFFF, &i2c_base->stat);
1d2e96de DB	268	writew (0, &i2c_base->cnt);
8ed96046 WD	269	return i2c_error;
	270	}
	271
49a7581c	272	static void flush_fifo(void)
8ed96046	273	{ u16 stat;
082acfd4 WD	274
	275	/* note: if you try and read data when its not there or ready
	276	* you get a bus error
	277	*/
8ed96046	278	while(1){
1d2e96de	279	stat = readw(&i2c_base->stat);
8ed96046	280	if(stat == I2C_STAT_RRDY){
938717ce SS	281	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
938717ce SS	282	defined(CONFIG_OMAP44XX)
1d2e96de	283	readb(&i2c_base->data);
7d264c1e	284	#else
1d2e96de	285	readw(&i2c_base->data);
7d264c1e	286	#endif
1d2e96de	287	writew(I2C_STAT_RRDY,&i2c_base->stat);
8ed96046 WD	288	udelay(1000);
	289	}else
	290	break;
	291	}
	292	}
	293
	294	int i2c_probe (uchar chip)
	295	{
	296	int res = 1; /* default = fail */
	297
1d2e96de	298	if (chip == readw (&i2c_base->oa)) {
8ed96046 WD	299	return res;
	300	}
	301
	302	/* wait until bus not busy */
	303	wait_for_bb ();
	304
	305	/* try to read one byte */
1d2e96de	306	writew (1, &i2c_base->cnt);
8ed96046	307	/* set slave address */
1d2e96de	308	writew (chip, &i2c_base->sa);
8ed96046	309	/* stop bit needed here */
1d2e96de	310	writew (I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_STP, &i2c_base->con);
8ed96046 WD	311	/* enough delay for the NACK bit set */
	312	udelay (50000);
	313
1d2e96de	314	if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
082acfd4	315	res = 0; /* success case */
8ed96046	316	flush_fifo();
1d2e96de	317	writew(0xFFFF, &i2c_base->stat);
8ed96046	318	} else {
1d2e96de DB	319	writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
1d2e96de DB	320	writew (readw (&i2c_base->con) \| I2C_CON_STP, &i2c_base->con); /* finish up xfer */
8ed96046 WD	321	udelay(20000);
	322	wait_for_bb ();
	323	}
	324	flush_fifo();
1d2e96de DB	325	writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
1d2e96de DB	326	writew(0xFFFF, &i2c_base->stat);
8ed96046 WD	327	return res;
	328	}
	329
	330	int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
	331	{
	332	int i;
	333
	334	if (alen > 1) {
	335	printf ("I2C read: addr len %d not supported\n", alen);
	336	return 1;
	337	}
	338
	339	if (addr + len > 256) {
	340	printf ("I2C read: address out of range\n");
	341	return 1;
	342	}
	343
	344	for (i = 0; i < len; i++) {
	345	if (i2c_read_byte (chip, addr + i, &buffer[i])) {
	346	printf ("I2C read: I/O error\n");
6d0f6bcf	347	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
8ed96046 WD	348	return 1;
	349	}
	350	}
	351
	352	return 0;
	353	}
	354
	355	int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
	356	{
	357	int i;
	358
	359	if (alen > 1) {
	360	printf ("I2C read: addr len %d not supported\n", alen);
	361	return 1;
	362	}
	363
	364	if (addr + len > 256) {
	365	printf ("I2C read: address out of range\n");
	366	return 1;
	367	}
	368
	369	for (i = 0; i < len; i++) {
	370	if (i2c_write_byte (chip, addr + i, buffer[i])) {
	371	printf ("I2C read: I/O error\n");
6d0f6bcf	372	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
8ed96046 WD	373	return 1;
	374	}
	375	}
	376
	377	return 0;
	378	}
	379
	380	static void wait_for_bb (void)
	381	{
	382	int timeout = 10;
	383	u16 stat;
	384
1d2e96de DB	385	writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
	386	while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
	387	writew (stat, &i2c_base->stat);
8ed96046 WD	388	udelay (50000);
	389	}
	390
	391	if (timeout <= 0) {
	392	printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
1d2e96de	393	readw (&i2c_base->stat));
8ed96046	394	}
1d2e96de	395	writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
8ed96046 WD	396	}
	397
	398	static u16 wait_for_pin (void)
	399	{
	400	u16 status;
	401	int timeout = 10;
	402
	403	do {
	404	udelay (1000);
1d2e96de	405	status = readw (&i2c_base->stat);
8ed96046 WD	406	} while ( !(status &
	407	(I2C_STAT_ROVR \| I2C_STAT_XUDF \| I2C_STAT_XRDY \|
	408	I2C_STAT_RRDY \| I2C_STAT_ARDY \| I2C_STAT_NACK \|
	409	I2C_STAT_AL)) && timeout--);
	410
	411	if (timeout <= 0) {
	412	printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
1d2e96de DB	413	readw (&i2c_base->stat));
1d2e96de DB	414	writew(0xFFFF, &i2c_base->stat);
8ed96046 WD	415	}
	416	return status;
	417	}
1d2e96de DB	418
	419	int i2c_set_bus_num(unsigned int bus)
	420	{
	421	if ((bus < 0) \|\| (bus >= I2C_BUS_MAX)) {
	422	printf("Bad bus: %d\n", bus);
	423	return -1;
	424	}
	425
	426	#if I2C_BUS_MAX==3
	427	if (bus == 2)
	428	i2c_base = (struct i2c *)I2C_BASE3;
	429	else
	430	#endif
	431	if (bus == 1)
	432	i2c_base = (struct i2c *)I2C_BASE2;
	433	else
	434	i2c_base = (struct i2c *)I2C_BASE1;
	435
	436	current_bus = bus;
	437
	438	if(!bus_initialized[current_bus])
	439	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	440
	441	return 0;
	442	}
938717ce SS	443
	444	int i2c_get_bus_num(void)
	445	{
	446	return (int) current_bus;
	447	}
	448