[people/ms/u-boot.git] / drivers / i2c / omap24xx_i2c.c

/*
 * Basic I2C functions
 *
 * Copyright (c) 2004 Texas Instruments
 *
 * This package is free software;  you can redistribute it and/or
 * modify it under the terms of the license found in the file
 * named COPYING that should have accompanied this file.
 *
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
 *
 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
 * Rewritten to fit into the current U-Boot framework
 *
 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
 *
 */

#include <common.h>

#include <asm/arch/i2c.h>
#include <asm/io.h>

#include "omap24xx_i2c.h"

DECLARE_GLOBAL_DATA_PTR;

#define I2C_TIMEOUT	1000

static void wait_for_bb(void);
static u16 wait_for_pin(void);
static void flush_fifo(void);

static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;

static unsigned int bus_initialized[I2C_BUS_MAX];
static unsigned int current_bus;

void i2c_init(int speed, int slaveadd)
{
	int psc, fsscll, fssclh;
	int hsscll = 0, hssclh = 0;
	u32 scll, sclh;
	int timeout = I2C_TIMEOUT;

	/* Only handle standard, fast and high speeds */
	if ((speed != OMAP_I2C_STANDARD) &&
	    (speed != OMAP_I2C_FAST_MODE) &&
	    (speed != OMAP_I2C_HIGH_SPEED)) {
		printf("Error : I2C unsupported speed %d\n", speed);
		return;
	}

	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	psc -= 1;
	if (psc < I2C_PSC_MIN) {
		printf("Error : I2C unsupported prescalar %d\n", psc);
		return;
	}

	if (speed == OMAP_I2C_HIGH_SPEED) {
		/* High speed */

		/* For first phase of HS mode */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
			(2 * OMAP_I2C_FAST_MODE);

		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing first phase clock\n");
			return;
		}

		/* For second phase of HS mode */
		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing second phase clock\n");
			return;
		}

		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;

	} else {
		/* Standard and fast speed */
		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);

		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
		if (((fsscll < 0) || (fssclh < 0)) ||
		    ((fsscll > 255) || (fssclh > 255))) {
			printf("Error : I2C initializing clock\n");
			return;
		}

		scll = (unsigned int)fsscll;
		sclh = (unsigned int)fssclh;
	}

	if (readw(&i2c_base->con) & I2C_CON_EN) {
		writew(0, &i2c_base->con);
		udelay(50000);
	}

	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
	udelay(1000);

	writew(I2C_CON_EN, &i2c_base->con);
	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
		if (timeout <= 0) {
			printf("ERROR: Timeout in soft-reset\n");
			return;
		}
		udelay(1000);
	}

	writew(0, &i2c_base->con);
	writew(psc, &i2c_base->psc);
	writew(scll, &i2c_base->scll);
	writew(sclh, &i2c_base->sclh);

	/* own address */
	writew(slaveadd, &i2c_base->oa);
	writew(I2C_CON_EN, &i2c_base->con);

	/* have to enable intrrupts or OMAP i2c module doesn't work */
	writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
		I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
	udelay(1000);
	flush_fifo();
	writew(0xFFFF, &i2c_base->stat);
	writew(0, &i2c_base->cnt);

	if (gd->flags & GD_FLG_RELOC)
		bus_initialized[current_bus] = 1;
}

static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
{
	int i2c_error = 0;
	u16 status;

	/* wait until bus not busy */
	wait_for_bb();

	/* one byte only */
	writew(1, &i2c_base->cnt);
	/* set slave address */
	writew(devaddr, &i2c_base->sa);
	/* no stop bit needed here */
	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
	      I2C_CON_TRX, &i2c_base->con);

	/* send register offset */
	while (1) {
		status = wait_for_pin();
		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			goto read_exit;
		}
		if (status & I2C_STAT_XRDY) {
			/* Important: have to use byte access */
			writeb(regoffset, &i2c_base->data);
			writew(I2C_STAT_XRDY, &i2c_base->stat);
		}
		if (status & I2C_STAT_ARDY) {
			writew(I2C_STAT_ARDY, &i2c_base->stat);
			break;
		}
	}

	/* set slave address */
	writew(devaddr, &i2c_base->sa);
	/* read one byte from slave */
	writew(1, &i2c_base->cnt);
	/* need stop bit here */
	writew(I2C_CON_EN | I2C_CON_MST |
		I2C_CON_STT | I2C_CON_STP,
		&i2c_base->con);

	/* receive data */
	while (1) {
		status = wait_for_pin();
		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			goto read_exit;
		}
		if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
	defined(CONFIG_OMAP44XX)
			*value = readb(&i2c_base->data);
#else
			*value = readw(&i2c_base->data);
#endif
			writew(I2C_STAT_RRDY, &i2c_base->stat);
		}
		if (status & I2C_STAT_ARDY) {
			writew(I2C_STAT_ARDY, &i2c_base->stat);
			break;
		}
	}

read_exit:
	flush_fifo();
	writew(0xFFFF, &i2c_base->stat);
	writew(0, &i2c_base->cnt);
	return i2c_error;
}

static void flush_fifo(void)
{	u16 stat;

	/* note: if you try and read data when its not there or ready
	 * you get a bus error
	 */
	while (1) {
		stat = readw(&i2c_base->stat);
		if (stat == I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
	defined(CONFIG_OMAP44XX)
			readb(&i2c_base->data);
#else
			readw(&i2c_base->data);
#endif
			writew(I2C_STAT_RRDY, &i2c_base->stat);
			udelay(1000);
		} else
			break;
	}
}

int i2c_probe(uchar chip)
{
	u16 status;
	int res = 1; /* default = fail */

	if (chip == readw(&i2c_base->oa))
		return res;

	/* wait until bus not busy */
	wait_for_bb();

	/* try to write one byte */
	writew(1, &i2c_base->cnt);
	/* set slave address */
	writew(chip, &i2c_base->sa);
	/* stop bit needed here */
	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
	       I2C_CON_STP, &i2c_base->con);

	status = wait_for_pin();

	/* check for ACK (!NAK) */
	if (!(status & I2C_STAT_NACK))
		res = 0;

	/* abort transfer (force idle state) */
	writew(0, &i2c_base->con);

	flush_fifo();
	/* don't allow any more data in... we don't want it. */
	writew(0, &i2c_base->cnt);
	writew(0xFFFF, &i2c_base->stat);
	return res;
}

int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	int i;

	if (alen > 1) {
		printf("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf("I2C read: address out of range\n");
		return 1;
	}

	for (i = 0; i < len; i++) {
		if (i2c_read_byte(chip, addr + i, &buffer[i])) {
			printf("I2C read: I/O error\n");
			i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
			return 1;
		}
	}

	return 0;
}

int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	int i;
	u16 status;
	int i2c_error = 0;

	if (alen > 1) {
		printf("I2C write: addr len %d not supported\n", alen);
		return 1;
	}

	if (addr + len > 256) {
		printf("I2C write: address 0x%x + 0x%x out of range\n",
				addr, len);
		return 1;
	}

	/* wait until bus not busy */
	wait_for_bb();

	/* start address phase - will write regoffset + len bytes data */
	/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
	writew(alen + len, &i2c_base->cnt);
	/* set slave address */
	writew(chip, &i2c_base->sa);
	/* stop bit needed here */
	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
		I2C_CON_STP, &i2c_base->con);

	/* Send address byte */
	status = wait_for_pin();

	if (status == 0 || status & I2C_STAT_NACK) {
		i2c_error = 1;
		printf("error waiting for i2c address ACK (status=0x%x)\n",
		      status);
		goto write_exit;
	}

	if (status & I2C_STAT_XRDY) {
		writeb(addr & 0xFF, &i2c_base->data);
		writew(I2C_STAT_XRDY, &i2c_base->stat);
	} else {
		i2c_error = 1;
		printf("i2c bus not ready for transmit (status=0x%x)\n",
		      status);
		goto write_exit;
	}

	/* address phase is over, now write data */
	for (i = 0; i < len; i++) {
		status = wait_for_pin();

		if (status == 0 || status & I2C_STAT_NACK) {
			i2c_error = 1;
			printf("i2c error waiting for data ACK (status=0x%x)\n",
					status);
			goto write_exit;
		}

		if (status & I2C_STAT_XRDY) {
			writeb(buffer[i], &i2c_base->data);
			writew(I2C_STAT_XRDY, &i2c_base->stat);
		} else {
			i2c_error = 1;
			printf("i2c bus not ready for Tx (i=%d)\n", i);
			goto write_exit;
		}
	}

write_exit:
	flush_fifo();
	writew(0xFFFF, &i2c_base->stat);
	return i2c_error;
}

static void wait_for_bb(void)
{
	int timeout = I2C_TIMEOUT;
	u16 stat;

	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
		writew(stat, &i2c_base->stat);
		udelay(1000);
	}

	if (timeout <= 0) {
		printf("timed out in wait_for_bb: I2C_STAT=%x\n",
			readw(&i2c_base->stat));
	}
	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
}

static u16 wait_for_pin(void)
{
	u16 status;
	int timeout = I2C_TIMEOUT;

	do {
		udelay(1000);
		status = readw(&i2c_base->stat);
	} while (!(status &
		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
		    I2C_STAT_AL)) && timeout--);

	if (timeout <= 0) {
		printf("timed out in wait_for_pin: I2C_STAT=%x\n",
			readw(&i2c_base->stat));
		writew(0xFFFF, &i2c_base->stat);
		status = 0;
	}

	return status;
}

int i2c_set_bus_num(unsigned int bus)
{
	if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
		printf("Bad bus: %d\n", bus);
		return -1;
	}

#if I2C_BUS_MAX == 3
	if (bus == 2)
		i2c_base = (struct i2c *)I2C_BASE3;
	else
#endif
	if (bus == 1)
		i2c_base = (struct i2c *)I2C_BASE2;
	else
		i2c_base = (struct i2c *)I2C_BASE1;

	current_bus = bus;

	if (!bus_initialized[current_bus])
		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	return 0;
}

int i2c_get_bus_num(void)
{
	return (int) current_bus;
}
Commit	Line	Data
8ed96046 WD	1	/*
	2	* Basic I2C functions
	3	*
	4	* Copyright (c) 2004 Texas Instruments
	5	*
	6	* This package is free software; you can redistribute it and/or
	7	* modify it under the terms of the license found in the file
	8	* named COPYING that should have accompanied this file.
	9	*
	10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
	11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
	12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
	13	*
	14	* Author: Jian Zhang jzhang@ti.com, Texas Instruments
	15	*
	16	* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
	17	* Rewritten to fit into the current U-Boot framework
	18	*
	19	* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
	20	*
	21	*/
	22
	23	#include <common.h>
289f932c	24
8ed96046 WD	25	#include <asm/arch/i2c.h>
	26	#include <asm/io.h>
	27
938717ce SS	28	#include "omap24xx_i2c.h"
938717ce SS	29
29565326 JR	30	DECLARE_GLOBAL_DATA_PTR;
29565326 JR	31
73e8747f	32	#define I2C_TIMEOUT 1000
d708395d	33
89677b27 MJ	34	static void wait_for_bb(void);
89677b27 MJ	35	static u16 wait_for_pin(void);
49a7581c	36	static void flush_fifo(void);
8ed96046	37
1d2e96de DB	38	static struct i2c i2c_base = (struct i2c )I2C_DEFAULT_BASE;
	39
	40	static unsigned int bus_initialized[I2C_BUS_MAX];
	41	static unsigned int current_bus;
	42
89677b27	43	void i2c_init(int speed, int slaveadd)
8ed96046	44	{
7f79dfb4 TR	45	int psc, fsscll, fssclh;
	46	int hsscll = 0, hssclh = 0;
	47	u32 scll, sclh;
d708395d	48	int timeout = I2C_TIMEOUT;
7f79dfb4 TR	49
	50	/* Only handle standard, fast and high speeds */
	51	if ((speed != OMAP_I2C_STANDARD) &&
	52	(speed != OMAP_I2C_FAST_MODE) &&
	53	(speed != OMAP_I2C_HIGH_SPEED)) {
	54	printf("Error : I2C unsupported speed %d\n", speed);
	55	return;
	56	}
	57
	58	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
	59	psc -= 1;
	60	if (psc < I2C_PSC_MIN) {
	61	printf("Error : I2C unsupported prescalar %d\n", psc);
	62	return;
	63	}
	64
	65	if (speed == OMAP_I2C_HIGH_SPEED) {
	66	/* High speed */
	67
	68	/* For first phase of HS mode */
	69	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
	70	(2 * OMAP_I2C_FAST_MODE);
	71
	72	fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
	73	fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
	74	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	75	((fsscll > 255) \|\| (fssclh > 255))) {
	76	printf("Error : I2C initializing first phase clock\n");
	77	return;
	78	}
	79
	80	/* For second phase of HS mode */
	81	hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	82
	83	hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
	84	hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
	85	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	86	((fsscll > 255) \|\| (fssclh > 255))) {
	87	printf("Error : I2C initializing second phase clock\n");
	88	return;
	89	}
	90
	91	scll = (unsigned int)hsscll << 8 \| (unsigned int)fsscll;
	92	sclh = (unsigned int)hssclh << 8 \| (unsigned int)fssclh;
	93
	94	} else {
	95	/* Standard and fast speed */
	96	fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
	97
	98	fsscll -= I2C_FASTSPEED_SCLL_TRIM;
	99	fssclh -= I2C_FASTSPEED_SCLH_TRIM;
	100	if (((fsscll < 0) \|\| (fssclh < 0)) \|\|
	101	((fsscll > 255) \|\| (fssclh > 255))) {
	102	printf("Error : I2C initializing clock\n");
	103	return;
	104	}
	105
	106	scll = (unsigned int)fsscll;
	107	sclh = (unsigned int)fssclh;
	108	}
8ed96046	109
89677b27 MJ	110	if (readw(&i2c_base->con) & I2C_CON_EN) {
	111	writew(0, &i2c_base->con);
	112	udelay(50000);
8ed96046 WD	113	}
8ed96046 WD	114
d708395d SS	115	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
	116	udelay(1000);
	117
	118	writew(I2C_CON_EN, &i2c_base->con);
	119	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
	120	if (timeout <= 0) {
	121	printf("ERROR: Timeout in soft-reset\n");
	122	return;
	123	}
	124	udelay(1000);
	125	}
	126
	127	writew(0, &i2c_base->con);
1d2e96de DB	128	writew(psc, &i2c_base->psc);
	129	writew(scll, &i2c_base->scll);
	130	writew(sclh, &i2c_base->sclh);
7f79dfb4	131
8ed96046	132	/* own address */
89677b27 MJ	133	writew(slaveadd, &i2c_base->oa);
89677b27 MJ	134	writew(I2C_CON_EN, &i2c_base->con);
49a7581c	135
8ed96046	136	/* have to enable intrrupts or OMAP i2c module doesn't work */
89677b27	137	writew(I2C_IE_XRDY_IE \| I2C_IE_RRDY_IE \| I2C_IE_ARDY_IE \|
1d2e96de	138	I2C_IE_NACK_IE \| I2C_IE_AL_IE, &i2c_base->ie);
89677b27	139	udelay(1000);
49a7581c	140	flush_fifo();
89677b27 MJ	141	writew(0xFFFF, &i2c_base->stat);
89677b27 MJ	142	writew(0, &i2c_base->cnt);
1d2e96de	143
1724fe9a HS	144	if (gd->flags & GD_FLG_RELOC)
1724fe9a HS	145	bus_initialized[current_bus] = 1;
8ed96046 WD	146	}
8ed96046 WD	147
89677b27	148	static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
8ed96046 WD	149	{
	150	int i2c_error = 0;
	151	u16 status;
	152
	153	/* wait until bus not busy */
89677b27	154	wait_for_bb();
8ed96046 WD	155
8ed96046 WD	156	/* one byte only */
89677b27	157	writew(1, &i2c_base->cnt);
8ed96046	158	/* set slave address */
89677b27	159	writew(devaddr, &i2c_base->sa);
8ed96046	160	/* no stop bit needed here */
89677b27 MJ	161	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \|
89677b27 MJ	162	I2C_CON_TRX, &i2c_base->con);
8ed96046	163
da0cc665 SS	164	/* send register offset */
	165	while (1) {
	166	status = wait_for_pin();
	167	if (status == 0 \|\| status & I2C_STAT_NACK) {
8ed96046	168	i2c_error = 1;
da0cc665 SS	169	goto read_exit;
	170	}
	171	if (status & I2C_STAT_XRDY) {
	172	/* Important: have to use byte access */
	173	writeb(regoffset, &i2c_base->data);
	174	writew(I2C_STAT_XRDY, &i2c_base->stat);
	175	}
	176	if (status & I2C_STAT_ARDY) {
	177	writew(I2C_STAT_ARDY, &i2c_base->stat);
	178	break;
8ed96046	179	}
8ed96046 WD	180	}
8ed96046 WD	181
da0cc665 SS	182	/* set slave address */
	183	writew(devaddr, &i2c_base->sa);
	184	/* read one byte from slave */
	185	writew(1, &i2c_base->cnt);
	186	/* need stop bit here */
	187	writew(I2C_CON_EN \| I2C_CON_MST \|
	188	I2C_CON_STT \| I2C_CON_STP,
	189	&i2c_base->con);
	190
	191	/* receive data */
	192	while (1) {
	193	status = wait_for_pin();
	194	if (status == 0 \|\| status & I2C_STAT_NACK) {
	195	i2c_error = 1;
	196	goto read_exit;
8ed96046	197	}
8ed96046	198	if (status & I2C_STAT_RRDY) {
938717ce	199	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
89677b27	200	defined(CONFIG_OMAP44XX)
da0cc665	201	*value = readb(&i2c_base->data);
7d264c1e	202	#else
da0cc665	203	*value = readw(&i2c_base->data);
7d264c1e	204	#endif
da0cc665	205	writew(I2C_STAT_RRDY, &i2c_base->stat);
8ed96046	206	}
da0cc665 SS	207	if (status & I2C_STAT_ARDY) {
	208	writew(I2C_STAT_ARDY, &i2c_base->stat);
	209	break;
8ed96046 WD	210	}
8ed96046 WD	211	}
da0cc665 SS	212
da0cc665 SS	213	read_exit:
8ed96046	214	flush_fifo();
89677b27 MJ	215	writew(0xFFFF, &i2c_base->stat);
89677b27 MJ	216	writew(0, &i2c_base->cnt);
8ed96046 WD	217	return i2c_error;
	218	}
	219
49a7581c	220	static void flush_fifo(void)
8ed96046	221	{ u16 stat;
082acfd4 WD	222
	223	/* note: if you try and read data when its not there or ready
	224	* you get a bus error
	225	*/
89677b27	226	while (1) {
1d2e96de	227	stat = readw(&i2c_base->stat);
89677b27	228	if (stat == I2C_STAT_RRDY) {
938717ce	229	#if defined(CONFIG_OMAP243X) \|\| defined(CONFIG_OMAP34XX) \|\| \
89677b27	230	defined(CONFIG_OMAP44XX)
1d2e96de	231	readb(&i2c_base->data);
7d264c1e	232	#else
1d2e96de	233	readw(&i2c_base->data);
7d264c1e	234	#endif
89677b27	235	writew(I2C_STAT_RRDY, &i2c_base->stat);
8ed96046	236	udelay(1000);
89677b27	237	} else
8ed96046 WD	238	break;
	239	}
	240	}
	241
89677b27	242	int i2c_probe(uchar chip)
8ed96046	243	{
fbad3555	244	u16 status;
8ed96046 WD	245	int res = 1; /* default = fail */
8ed96046 WD	246
89677b27	247	if (chip == readw(&i2c_base->oa))
8ed96046	248	return res;
8ed96046 WD	249
8ed96046 WD	250	/* wait until bus not busy */
89677b27	251	wait_for_bb();
8ed96046	252
0e57968a	253	/* try to write one byte */
89677b27	254	writew(1, &i2c_base->cnt);
8ed96046	255	/* set slave address */
89677b27	256	writew(chip, &i2c_base->sa);
8ed96046	257	/* stop bit needed here */
0e57968a NT	258	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
0e57968a NT	259	I2C_CON_STP, &i2c_base->con);
8ed96046	260
0e57968a NT	261	status = wait_for_pin();
	262
	263	/* check for ACK (!NAK) */
	264	if (!(status & I2C_STAT_NACK))
	265	res = 0;
	266
	267	/* abort transfer (force idle state) */
	268	writew(0, &i2c_base->con);
fbad3555	269
8ed96046	270	flush_fifo();
89677b27 MJ	271	/* don't allow any more data in... we don't want it. */
89677b27 MJ	272	writew(0, &i2c_base->cnt);
1d2e96de	273	writew(0xFFFF, &i2c_base->stat);
8ed96046 WD	274	return res;
	275	}
	276
89677b27	277	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
8ed96046 WD	278	{
	279	int i;
	280
	281	if (alen > 1) {
89677b27	282	printf("I2C read: addr len %d not supported\n", alen);
8ed96046 WD	283	return 1;
	284	}
	285
	286	if (addr + len > 256) {
89677b27	287	printf("I2C read: address out of range\n");
8ed96046 WD	288	return 1;
	289	}
	290
	291	for (i = 0; i < len; i++) {
89677b27 MJ	292	if (i2c_read_byte(chip, addr + i, &buffer[i])) {
	293	printf("I2C read: I/O error\n");
	294	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
8ed96046 WD	295	return 1;
	296	}
	297	}
	298
	299	return 0;
	300	}
	301
89677b27	302	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
8ed96046 WD	303	{
8ed96046 WD	304	int i;
0607e2b9 MJ	305	u16 status;
0607e2b9 MJ	306	int i2c_error = 0;
8ed96046 WD	307
8ed96046 WD	308	if (alen > 1) {
0607e2b9	309	printf("I2C write: addr len %d not supported\n", alen);
8ed96046 WD	310	return 1;
	311	}
	312
	313	if (addr + len > 256) {
0607e2b9 MJ	314	printf("I2C write: address 0x%x + 0x%x out of range\n",
0607e2b9 MJ	315	addr, len);
8ed96046 WD	316	return 1;
	317	}
	318
0607e2b9 MJ	319	/* wait until bus not busy */
	320	wait_for_bb();
	321
	322	/* start address phase - will write regoffset + len bytes data */
	323	/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
	324	writew(alen + len, &i2c_base->cnt);
	325	/* set slave address */
	326	writew(chip, &i2c_base->sa);
	327	/* stop bit needed here */
	328	writew(I2C_CON_EN \| I2C_CON_MST \| I2C_CON_STT \| I2C_CON_TRX \|
	329	I2C_CON_STP, &i2c_base->con);
	330
	331	/* Send address byte */
	332	status = wait_for_pin();
	333
	334	if (status == 0 \|\| status & I2C_STAT_NACK) {
	335	i2c_error = 1;
	336	printf("error waiting for i2c address ACK (status=0x%x)\n",
	337	status);
	338	goto write_exit;
	339	}
	340
	341	if (status & I2C_STAT_XRDY) {
	342	writeb(addr & 0xFF, &i2c_base->data);
	343	writew(I2C_STAT_XRDY, &i2c_base->stat);
	344	} else {
	345	i2c_error = 1;
	346	printf("i2c bus not ready for transmit (status=0x%x)\n",
	347	status);
	348	goto write_exit;
	349	}
	350
	351	/* address phase is over, now write data */
8ed96046	352	for (i = 0; i < len; i++) {
0607e2b9 MJ	353	status = wait_for_pin();
	354
	355	if (status == 0 \|\| status & I2C_STAT_NACK) {
	356	i2c_error = 1;
	357	printf("i2c error waiting for data ACK (status=0x%x)\n",
	358	status);
	359	goto write_exit;
	360	}
	361
	362	if (status & I2C_STAT_XRDY) {
	363	writeb(buffer[i], &i2c_base->data);
	364	writew(I2C_STAT_XRDY, &i2c_base->stat);
	365	} else {
	366	i2c_error = 1;
	367	printf("i2c bus not ready for Tx (i=%d)\n", i);
	368	goto write_exit;
8ed96046 WD	369	}
	370	}
	371
0607e2b9 MJ	372	write_exit:
	373	flush_fifo();
	374	writew(0xFFFF, &i2c_base->stat);
	375	return i2c_error;
8ed96046 WD	376	}
8ed96046 WD	377
89677b27	378	static void wait_for_bb(void)
8ed96046	379	{
73e8747f	380	int timeout = I2C_TIMEOUT;
8ed96046 WD	381	u16 stat;
8ed96046 WD	382
f9a78b8d	383	writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
89677b27 MJ	384	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
89677b27 MJ	385	writew(stat, &i2c_base->stat);
73e8747f	386	udelay(1000);
8ed96046 WD	387	}
	388
	389	if (timeout <= 0) {
89677b27 MJ	390	printf("timed out in wait_for_bb: I2C_STAT=%x\n",
89677b27 MJ	391	readw(&i2c_base->stat));
8ed96046	392	}
1d2e96de	393	writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
8ed96046 WD	394	}
8ed96046 WD	395
89677b27	396	static u16 wait_for_pin(void)
8ed96046 WD	397	{
8ed96046 WD	398	u16 status;
73e8747f	399	int timeout = I2C_TIMEOUT;
8ed96046 WD	400
8ed96046 WD	401	do {
89677b27 MJ	402	udelay(1000);
	403	status = readw(&i2c_base->stat);
	404	} while (!(status &
8ed96046 WD	405	(I2C_STAT_ROVR \| I2C_STAT_XUDF \| I2C_STAT_XRDY \|
	406	I2C_STAT_RRDY \| I2C_STAT_ARDY \| I2C_STAT_NACK \|
	407	I2C_STAT_AL)) && timeout--);
	408
	409	if (timeout <= 0) {
89677b27 MJ	410	printf("timed out in wait_for_pin: I2C_STAT=%x\n",
89677b27 MJ	411	readw(&i2c_base->stat));
73e8747f SS	412	writew(0xFFFF, &i2c_base->stat);
	413	status = 0;
	414	}
	415
8ed96046 WD	416	return status;
8ed96046 WD	417	}
1d2e96de DB	418
	419	int i2c_set_bus_num(unsigned int bus)
	420	{
	421	if ((bus < 0) \|\| (bus >= I2C_BUS_MAX)) {
	422	printf("Bad bus: %d\n", bus);
	423	return -1;
	424	}
	425
89677b27	426	#if I2C_BUS_MAX == 3
1d2e96de DB	427	if (bus == 2)
	428	i2c_base = (struct i2c *)I2C_BASE3;
	429	else
	430	#endif
	431	if (bus == 1)
	432	i2c_base = (struct i2c *)I2C_BASE2;
	433	else
	434	i2c_base = (struct i2c *)I2C_BASE1;
	435
	436	current_bus = bus;
	437
89677b27	438	if (!bus_initialized[current_bus])
1d2e96de DB	439	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	440
	441	return 0;
	442	}
938717ce SS	443
	444	int i2c_get_bus_num(void)
	445	{
	446	return (int) current_bus;
	447	}