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1086bfa9 NI |
1 | /* |
2 | * drivers/i2c/rcar_i2c.c | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0 | |
28527096 SG |
8 | * |
9 | * NOTE: This driver should be converted to driver model before June 2017. | |
10 | * Please see doc/driver-model/i2c-howto.txt for instructions. | |
1086bfa9 NI |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <i2c.h> | |
15 | #include <asm/io.h> | |
16 | ||
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
19 | struct rcar_i2c { | |
20 | u32 icscr; | |
21 | u32 icmcr; | |
22 | u32 icssr; | |
23 | u32 icmsr; | |
24 | u32 icsier; | |
25 | u32 icmier; | |
26 | u32 icccr; | |
27 | u32 icsar; | |
28 | u32 icmar; | |
29 | u32 icrxdtxd; | |
30 | u32 icccr2; | |
31 | u32 icmpr; | |
32 | u32 ichpr; | |
33 | u32 iclpr; | |
34 | }; | |
35 | ||
36 | #define MCR_MDBS 0x80 /* non-fifo mode switch */ | |
37 | #define MCR_FSCL 0x40 /* override SCL pin */ | |
38 | #define MCR_FSDA 0x20 /* override SDA pin */ | |
39 | #define MCR_OBPC 0x10 /* override pins */ | |
40 | #define MCR_MIE 0x08 /* master if enable */ | |
41 | #define MCR_TSBE 0x04 | |
42 | #define MCR_FSB 0x02 /* force stop bit */ | |
43 | #define MCR_ESG 0x01 /* en startbit gen. */ | |
44 | ||
45 | #define MSR_MASK 0x7f | |
46 | #define MSR_MNR 0x40 /* nack received */ | |
47 | #define MSR_MAL 0x20 /* arbitration lost */ | |
48 | #define MSR_MST 0x10 /* sent a stop */ | |
49 | #define MSR_MDE 0x08 | |
50 | #define MSR_MDT 0x04 | |
51 | #define MSR_MDR 0x02 | |
52 | #define MSR_MAT 0x01 /* slave addr xfer done */ | |
53 | ||
54 | static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = { | |
55 | (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE, | |
56 | (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE, | |
57 | (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE, | |
58 | (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE, | |
59 | }; | |
60 | ||
61 | static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr) | |
62 | { | |
63 | /* set slave address */ | |
64 | writel(chip << 1, &dev->icmar); | |
65 | /* set register address */ | |
66 | writel(addr, &dev->icrxdtxd); | |
67 | /* clear status */ | |
68 | writel(0, &dev->icmsr); | |
69 | /* start master send */ | |
70 | writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); | |
71 | ||
72 | while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) | |
73 | != (MSR_MAT | MSR_MDE)) | |
74 | udelay(10); | |
75 | ||
76 | /* clear ESG */ | |
77 | writel(MCR_MDBS | MCR_MIE, &dev->icmcr); | |
78 | /* start SCLclk */ | |
79 | writel(~(MSR_MAT | MSR_MDE), &dev->icmsr); | |
80 | ||
81 | while (!(readl(&dev->icmsr) & MSR_MDE)) | |
82 | udelay(10); | |
83 | } | |
84 | ||
85 | static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev) | |
86 | { | |
87 | while (!(readl(&dev->icmsr) & MSR_MST)) | |
88 | udelay(10); | |
89 | ||
90 | writel(0, &dev->icmcr); | |
91 | } | |
92 | ||
93 | static int | |
94 | rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size) | |
95 | { | |
96 | rcar_i2c_raw_rw_common(dev, chip, addr); | |
97 | ||
98 | /* set send date */ | |
99 | writel(*val, &dev->icrxdtxd); | |
100 | /* start SCLclk */ | |
101 | writel(~MSR_MDE, &dev->icmsr); | |
102 | ||
103 | while (!(readl(&dev->icmsr) & MSR_MDE)) | |
104 | udelay(10); | |
105 | ||
106 | /* set stop condition */ | |
107 | writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); | |
108 | /* start SCLclk */ | |
109 | writel(~MSR_MDE, &dev->icmsr); | |
110 | ||
111 | rcar_i2c_raw_rw_finish(dev); | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | static u8 | |
117 | rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) | |
118 | { | |
119 | u8 ret; | |
120 | ||
121 | rcar_i2c_raw_rw_common(dev, chip, addr); | |
122 | ||
123 | /* set slave address, receive */ | |
124 | writel((chip << 1) | 1, &dev->icmar); | |
125 | /* start master receive */ | |
126 | writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); | |
cd818a38 NI |
127 | /* clear status */ |
128 | writel(0, &dev->icmsr); | |
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ad5e14ec HN |
130 | while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) |
131 | != (MSR_MAT | MSR_MDR)) | |
1086bfa9 NI |
132 | udelay(10); |
133 | ||
134 | /* clear ESG */ | |
135 | writel(MCR_MDBS | MCR_MIE, &dev->icmcr); | |
136 | /* prepare stop condition */ | |
137 | writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); | |
138 | /* start SCLclk */ | |
139 | writel(~(MSR_MAT | MSR_MDR), &dev->icmsr); | |
140 | ||
141 | while (!(readl(&dev->icmsr) & MSR_MDR)) | |
142 | udelay(10); | |
143 | ||
144 | /* get receive data */ | |
145 | ret = (u8)readl(&dev->icrxdtxd); | |
146 | /* start SCLclk */ | |
147 | writel(~MSR_MDR, &dev->icmsr); | |
148 | ||
149 | rcar_i2c_raw_rw_finish(dev); | |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
154 | /* | |
155 | * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck]) | |
156 | * iicck : I2C internal clock < 20 MHz | |
157 | * ticf : I2C SCL falling time: 35 ns | |
158 | * tr : I2C SCL rising time: 200 ns | |
159 | * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5 | |
160 | * F[n] : n rounded up to an integer | |
161 | */ | |
162 | static u32 rcar_clock_gen(int i2c_no, u32 bus_speed) | |
163 | { | |
164 | u32 iicck, f, scl, scgd; | |
165 | u32 intd = 5; | |
166 | ||
167 | int bit = 0, cdf_width = 3; | |
168 | for (bit = 0; bit < (1 << cdf_width); bit++) { | |
169 | iicck = CONFIG_HP_CLK_FREQ / (1 + bit); | |
170 | if (iicck < 20000000) | |
171 | break; | |
172 | } | |
173 | ||
174 | if (bit > (1 << cdf_width)) { | |
175 | puts("rcar-i2c: Can not get CDF\n"); | |
176 | return 0; | |
177 | } | |
178 | ||
179 | if (i2c_no == 0) | |
180 | intd = 50; | |
181 | ||
182 | f = (35 + 200 + intd) * (iicck / 1000000000); | |
183 | ||
184 | for (scgd = 0; scgd < 0x40; scgd++) { | |
185 | scl = iicck / (20 + (scgd * 8) + f); | |
186 | if (scl <= bus_speed) | |
187 | break; | |
188 | } | |
189 | ||
190 | if (scgd > 0x40) { | |
191 | puts("rcar-i2c: Can not get SDGB\n"); | |
192 | return 0; | |
193 | } | |
194 | ||
195 | debug("%s: scl: %d\n", __func__, scl); | |
196 | debug("%s: bit %x\n", __func__, bit); | |
197 | debug("%s: scgd %x\n", __func__, scgd); | |
198 | debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit)); | |
199 | ||
200 | return scgd << (cdf_width) | bit; | |
201 | } | |
202 | ||
203 | static void | |
204 | rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) | |
205 | { | |
206 | struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; | |
207 | u32 icccr = 0; | |
208 | ||
209 | /* No i2c support prior to relocation */ | |
210 | if (!(gd->flags & GD_FLG_RELOC)) | |
211 | return; | |
212 | ||
213 | /* | |
214 | * reset slave mode. | |
215 | * slave mode is not used on this driver | |
216 | */ | |
217 | writel(0, &dev->icsier); | |
218 | writel(0, &dev->icsar); | |
219 | writel(0, &dev->icscr); | |
220 | writel(0, &dev->icssr); | |
221 | ||
222 | /* reset master mode */ | |
223 | writel(0, &dev->icmier); | |
224 | writel(0, &dev->icmcr); | |
225 | writel(0, &dev->icmsr); | |
226 | writel(0, &dev->icmar); | |
227 | ||
228 | icccr = rcar_clock_gen(adap->hwadapnr, adap->speed); | |
229 | if (icccr == 0) | |
230 | puts("I2C: Init failed\n"); | |
231 | else | |
232 | writel(icccr, &dev->icccr); | |
233 | } | |
234 | ||
235 | static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip, | |
236 | uint addr, int alen, u8 *data, int len) | |
237 | { | |
238 | struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; | |
239 | int i; | |
240 | ||
241 | for (i = 0; i < len; i++) | |
242 | data[i] = rcar_i2c_raw_read(dev, chip, addr + i); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, | |
248 | int alen, u8 *data, int len) | |
249 | { | |
250 | struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; | |
251 | return rcar_i2c_raw_write(dev, chip, addr, data, len); | |
252 | } | |
253 | ||
254 | static int | |
255 | rcar_i2c_probe(struct i2c_adapter *adap, u8 dev) | |
256 | { | |
257 | return rcar_i2c_read(adap, dev, 0, 0, NULL, 0); | |
258 | } | |
259 | ||
260 | static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap, | |
261 | unsigned int speed) | |
262 | { | |
263 | struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; | |
264 | u32 icccr; | |
265 | int ret = 0; | |
266 | ||
267 | rcar_i2c_raw_rw_finish(dev); | |
268 | ||
269 | icccr = rcar_clock_gen(adap->hwadapnr, speed); | |
270 | if (icccr == 0) { | |
271 | puts("I2C: Init failed\n"); | |
272 | ret = -1; | |
273 | } else { | |
274 | writel(icccr, &dev->icccr); | |
275 | } | |
276 | return ret; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Register RCAR i2c adapters | |
281 | */ | |
282 | U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, | |
283 | rcar_i2c_write, rcar_i2c_set_bus_speed, | |
284 | CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0) | |
285 | U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, | |
286 | rcar_i2c_write, rcar_i2c_set_bus_speed, | |
287 | CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1) | |
288 | U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, | |
289 | rcar_i2c_write, rcar_i2c_set_bus_speed, | |
290 | CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2) | |
291 | U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, | |
292 | rcar_i2c_write, rcar_i2c_set_bus_speed, | |
293 | CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3) |