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9e75ea46 MV |
1 | /* |
2 | * Renesas RCar IIC driver | |
3 | * | |
4 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
6 | * Based on | |
7 | * Copyright (C) 2011, 2013 Renesas Solutions Corp. | |
8 | * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #include <common.h> | |
14 | #include <clk.h> | |
15 | #include <dm.h> | |
16 | #include <i2c.h> | |
17 | #include <asm/io.h> | |
18 | ||
19 | struct rcar_iic_priv { | |
20 | void __iomem *base; | |
21 | struct clk clk; | |
22 | u8 iccl; | |
23 | u8 icch; | |
24 | }; | |
25 | ||
26 | #define RCAR_IIC_ICDR 0x00 | |
27 | #define RCAR_IIC_ICCR 0x04 | |
28 | #define RCAR_IIC_ICSR 0x08 | |
29 | #define RCAR_IIC_ICIC 0x0c | |
30 | #define RCAR_IIC_ICCL 0x10 | |
31 | #define RCAR_IIC_ICCH 0x14 | |
32 | ||
33 | /* ICCR */ | |
34 | #define RCAR_IIC_ICCR_ICE BIT(7) | |
35 | #define RCAR_IIC_ICCR_RACK BIT(6) | |
36 | #define RCAR_IIC_ICCR_RTS BIT(4) | |
37 | #define RCAR_IIC_ICCR_BUSY BIT(2) | |
38 | #define RCAR_IIC_ICCR_SCP BIT(0) | |
39 | ||
40 | /* ICSR / ICIC */ | |
41 | #define RCAR_IC_BUSY BIT(4) | |
42 | #define RCAR_IC_TACK BIT(2) | |
43 | #define RCAR_IC_DTE BIT(0) | |
44 | ||
45 | #define IRQ_WAIT 1000 | |
46 | ||
47 | static void sh_irq_dte(struct udevice *dev) | |
48 | { | |
49 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
50 | int i; | |
51 | ||
52 | for (i = 0; i < IRQ_WAIT; i++) { | |
53 | if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) | |
54 | break; | |
55 | udelay(10); | |
56 | } | |
57 | } | |
58 | ||
59 | static int sh_irq_dte_with_tack(struct udevice *dev) | |
60 | { | |
61 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
62 | int i; | |
63 | ||
64 | for (i = 0; i < IRQ_WAIT; i++) { | |
65 | if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) | |
66 | break; | |
67 | if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR)) | |
68 | return -ETIMEDOUT; | |
69 | udelay(10); | |
70 | } | |
71 | return 0; | |
72 | } | |
73 | ||
74 | static void sh_irq_busy(struct udevice *dev) | |
75 | { | |
76 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < IRQ_WAIT; i++) { | |
80 | if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) | |
81 | break; | |
82 | udelay(10); | |
83 | } | |
84 | } | |
85 | ||
86 | static int rcar_iic_set_addr(struct udevice *dev, u8 chip, u8 read) | |
87 | { | |
88 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
89 | ||
90 | clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); | |
91 | setbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); | |
92 | ||
93 | writeb(priv->iccl, priv->base + RCAR_IIC_ICCL); | |
94 | writeb(priv->icch, priv->base + RCAR_IIC_ICCH); | |
95 | writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC); | |
96 | ||
97 | writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY, | |
98 | priv->base + RCAR_IIC_ICCR); | |
99 | sh_irq_dte(dev); | |
100 | ||
101 | clrbits_8(priv->base + RCAR_IIC_ICSR, RCAR_IC_TACK); | |
102 | writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR); | |
103 | return sh_irq_dte_with_tack(dev); | |
104 | } | |
105 | ||
106 | static void rcar_iic_finish(struct udevice *dev) | |
107 | { | |
108 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
109 | ||
110 | writeb(0, priv->base + RCAR_IIC_ICSR); | |
111 | clrbits_8(priv->base + RCAR_IIC_ICCR, RCAR_IIC_ICCR_ICE); | |
112 | } | |
113 | ||
114 | static int rcar_iic_read_common(struct udevice *dev, struct i2c_msg *msg) | |
115 | { | |
116 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
117 | int i, ret = -EREMOTEIO; | |
118 | ||
119 | if (rcar_iic_set_addr(dev, msg->addr, 1) != 0) | |
120 | goto err; | |
121 | ||
122 | udelay(10); | |
123 | ||
124 | writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, | |
125 | priv->base + RCAR_IIC_ICCR); | |
126 | ||
127 | for (i = 0; i < msg->len; i++) { | |
128 | if (sh_irq_dte_with_tack(dev) != 0) | |
129 | goto err; | |
130 | ||
131 | msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff; | |
132 | ||
133 | if (msg->len - 1 == i) { | |
134 | writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK, | |
135 | priv->base + RCAR_IIC_ICCR); | |
136 | } | |
137 | } | |
138 | ||
139 | sh_irq_busy(dev); | |
140 | ret = 0; | |
141 | ||
142 | err: | |
143 | rcar_iic_finish(dev); | |
144 | return ret; | |
145 | } | |
146 | ||
147 | static int rcar_iic_write_common(struct udevice *dev, struct i2c_msg *msg) | |
148 | { | |
149 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
150 | int i, ret = -EREMOTEIO; | |
151 | ||
152 | if (rcar_iic_set_addr(dev, msg->addr, 0) != 0) | |
153 | goto err; | |
154 | ||
155 | udelay(10); | |
156 | ||
157 | for (i = 0; i < msg->len; i++) { | |
158 | writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR); | |
159 | if (sh_irq_dte_with_tack(dev) != 0) | |
160 | goto err; | |
161 | } | |
162 | ||
163 | if (msg->flags & I2C_M_STOP) { | |
164 | writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS, | |
165 | priv->base + RCAR_IIC_ICCR); | |
166 | if (sh_irq_dte_with_tack(dev) != 0) | |
167 | goto err; | |
168 | } | |
169 | ||
170 | sh_irq_busy(dev); | |
171 | ret = 0; | |
172 | ||
173 | err: | |
174 | rcar_iic_finish(dev); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) | |
179 | { | |
180 | int ret; | |
181 | ||
182 | for (; nmsgs > 0; nmsgs--, msg++) { | |
183 | if (msg->flags & I2C_M_RD) | |
184 | ret = rcar_iic_read_common(dev, msg); | |
185 | else | |
186 | ret = rcar_iic_write_common(dev, msg); | |
187 | ||
188 | if (ret) | |
189 | return -EREMOTEIO; | |
190 | } | |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
195 | static int rcar_iic_set_speed(struct udevice *dev, uint speed) | |
196 | { | |
197 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
198 | const unsigned int ratio_high = 4; | |
199 | const unsigned int ratio_low = 5; | |
200 | int clkrate, denom; | |
201 | ||
202 | clkrate = clk_get_rate(&priv->clk); | |
203 | if (clkrate < 0) | |
204 | return clkrate; | |
205 | ||
206 | /* | |
207 | * Calculate the value for ICCL and ICCH. From the data sheet: | |
208 | * iccl = (p-clock / transfer-rate) * (L / (L + H)) | |
209 | * icch = (p clock / transfer rate) * (H / (L + H)) | |
210 | * where L and H are the SCL low and high ratio. | |
211 | */ | |
212 | denom = speed * (ratio_high + ratio_low); | |
213 | priv->iccl = DIV_ROUND_CLOSEST(clkrate * ratio_low, denom); | |
214 | priv->icch = DIV_ROUND_CLOSEST(clkrate * ratio_high, denom); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static int rcar_iic_probe_chip(struct udevice *dev, uint addr, uint flags) | |
220 | { | |
221 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
222 | int ret; | |
223 | ||
224 | rcar_iic_set_addr(dev, addr, 1); | |
225 | writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, | |
226 | priv->base + RCAR_IIC_ICCR); | |
227 | ret = sh_irq_dte_with_tack(dev); | |
228 | rcar_iic_finish(dev); | |
229 | ||
230 | return ret; | |
231 | } | |
232 | ||
233 | static int rcar_iic_probe(struct udevice *dev) | |
234 | { | |
235 | struct rcar_iic_priv *priv = dev_get_priv(dev); | |
236 | int ret; | |
237 | ||
238 | priv->base = dev_read_addr_ptr(dev); | |
239 | ||
240 | ret = clk_get_by_index(dev, 0, &priv->clk); | |
241 | if (ret) | |
242 | return ret; | |
243 | ||
244 | ret = clk_enable(&priv->clk); | |
245 | if (ret) | |
246 | return ret; | |
247 | ||
248 | rcar_iic_finish(dev); | |
249 | ||
250 | return rcar_iic_set_speed(dev, 100000); | |
251 | } | |
252 | ||
253 | static const struct dm_i2c_ops rcar_iic_ops = { | |
254 | .xfer = rcar_iic_xfer, | |
255 | .probe_chip = rcar_iic_probe_chip, | |
256 | .set_bus_speed = rcar_iic_set_speed, | |
257 | }; | |
258 | ||
259 | static const struct udevice_id rcar_iic_ids[] = { | |
260 | { .compatible = "renesas,rmobile-iic" }, | |
261 | { } | |
262 | }; | |
263 | ||
264 | U_BOOT_DRIVER(iic_rcar) = { | |
265 | .name = "iic_rcar", | |
266 | .id = UCLASS_I2C, | |
267 | .of_match = rcar_iic_ids, | |
268 | .probe = rcar_iic_probe, | |
269 | .priv_auto_alloc_size = sizeof(struct rcar_iic_priv), | |
270 | .ops = &rcar_iic_ops, | |
271 | }; |