[thirdparty/u-boot.git] / drivers / i2c / s3c24x0_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
 */

#include <common.h>
#include <errno.h>
#include <dm.h>
#include <fdtdec.h>
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pinmux.h>
#else
#include <asm/arch/s3c24x0_cpu.h>
#endif
#include <asm/io.h>
#include <i2c.h>
#include "s3c24x0_i2c.h"

#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
#define SYS_I2C_S3C24X0_SLAVE_ADDR	0
#else
#define SYS_I2C_S3C24X0_SLAVE_ADDR	CONFIG_SYS_I2C_S3C24X0_SLAVE
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * Wait til the byte transfer is completed.
 *
 * @param i2c- pointer to the appropriate i2c register bank.
 * @return I2C_OK, if transmission was ACKED
 *         I2C_NACK, if transmission was NACKED
 *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
 */

static int WaitForXfer(struct s3c24x0_i2c *i2c)
{
	ulong start_time = get_timer(0);

	do {
		if (readl(&i2c->iiccon) & I2CCON_IRPND)
			return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
				I2C_NACK : I2C_OK;
	} while (get_timer(start_time) < I2C_TIMEOUT_MS);

	return I2C_NOK_TOUT;
}

static void read_write_byte(struct s3c24x0_i2c *i2c)
{
	clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}

static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
	ulong freq, pres = 16, div;
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
	freq = get_i2c_clk();
#else
	freq = get_PCLK();
#endif
	/* calculate prescaler and divisor values */
	if ((freq / pres / (16 + 1)) > speed)
		/* set prescaler to 512 */
		pres = 512;

	div = 0;
	while ((freq / pres / (div + 1)) > speed)
		div++;

	/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
	writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);

	/* init to SLAVE REVEIVE and set slaveaddr */
	writel(0, &i2c->iicstat);
	writel(slaveadd, &i2c->iicadd);
	/* program Master Transmit (and implicit STOP) */
	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}

static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->clock_frequency = speed;

	i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
		    SYS_I2C_S3C24X0_SLAVE_ADDR);

	return 0;
}

/*
 * cmd_type is 0 for write, 1 for read.
 *
 * addr_len can take any value from 0-255, it is only limited
 * by the char, we could make it larger if needed. If it is
 * 0 we skip the address write cycle.
 */
static int i2c_transfer(struct s3c24x0_i2c *i2c,
			unsigned char cmd_type,
			unsigned char chip,
			unsigned char addr[],
			unsigned char addr_len,
			unsigned char data[],
			unsigned short data_len)
{
	int i = 0, result;
	ulong start_time = get_timer(0);

	if (data == 0 || data_len == 0) {
		/*Don't support data transfer of no length or to address 0 */
		debug("i2c_transfer: bad call\n");
		return I2C_NOK;
	}

	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
		if (get_timer(start_time) > I2C_TIMEOUT_MS)
			return I2C_NOK_TOUT;
	}

	writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);

	/* Get the slave chip address going */
	writel(chip, &i2c->iicds);
	if ((cmd_type == I2C_WRITE) || (addr && addr_len))
		writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
		       &i2c->iicstat);
	else
		writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
		       &i2c->iicstat);

	/* Wait for chip address to transmit. */
	result = WaitForXfer(i2c);
	if (result != I2C_OK)
		goto bailout;

	/* If register address needs to be transmitted - do it now. */
	if (addr && addr_len) {
		while ((i < addr_len) && (result == I2C_OK)) {
			writel(addr[i++], &i2c->iicds);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
		}
		i = 0;
		if (result != I2C_OK)
			goto bailout;
	}

	switch (cmd_type) {
	case I2C_WRITE:
		while ((i < data_len) && (result == I2C_OK)) {
			writel(data[i++], &i2c->iicds);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
		}
		break;

	case I2C_READ:
		if (addr && addr_len) {
			/*
			 * Register address has been sent, now send slave chip
			 * address again to start the actual read transaction.
			 */
			writel(chip, &i2c->iicds);

			/* Generate a re-START. */
			writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
				&i2c->iicstat);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);

			if (result != I2C_OK)
				goto bailout;
		}

		while ((i < data_len) && (result == I2C_OK)) {
			/* disable ACK for final READ */
			if (i == data_len - 1)
				writel(readl(&i2c->iiccon)
				       & ~I2CCON_ACKGEN,
				       &i2c->iiccon);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
			data[i++] = readl(&i2c->iicds);
		}
		if (result == I2C_NACK)
			result = I2C_OK; /* Normal terminated read. */
		break;

	default:
		debug("i2c_transfer: bad call\n");
		result = I2C_NOK;
		break;
	}

bailout:
	/* Send STOP. */
	writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
	read_write_byte(i2c);

	return result;
}

static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	uchar buf[1];
	int ret;

	buf[0] = 0;

	/*
	 * What is needed is to send the chip address and verify that the
	 * address was <ACK>ed (i.e. there was a chip at that address which
	 * drove the data line low).
	 */
	ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);

	return ret != I2C_OK;
}

static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
			  int seq)
{
	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	bool is_read = msg->flags & I2C_M_RD;
	uint status;
	uint addr;
	int ret, i;

	if (!seq)
		setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);

	/* Get the slave chip address going */
	addr = msg->addr << 1;
	writel(addr, &i2c->iicds);
	status = I2C_TXRX_ENA | I2C_START_STOP;
	if (is_read)
		status |= I2C_MODE_MR;
	else
		status |= I2C_MODE_MT;
	writel(status, &i2c->iicstat);
	if (seq)
		read_write_byte(i2c);

	/* Wait for chip address to transmit */
	ret = WaitForXfer(i2c);
	if (ret)
		goto err;

	if (is_read) {
		for (i = 0; !ret && i < msg->len; i++) {
			/* disable ACK for final READ */
			if (i == msg->len - 1)
				clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
			read_write_byte(i2c);
			ret = WaitForXfer(i2c);
			msg->buf[i] = readl(&i2c->iicds);
		}
		if (ret == I2C_NACK)
			ret = I2C_OK; /* Normal terminated read */
	} else {
		for (i = 0; !ret && i < msg->len; i++) {
			writel(msg->buf[i], &i2c->iicds);
			read_write_byte(i2c);
			ret = WaitForXfer(i2c);
		}
	}

err:
	return ret;
}

static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
			    int nmsgs)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	ulong start_time;
	int ret, i;

	start_time = get_timer(0);
	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
		if (get_timer(start_time) > I2C_TIMEOUT_MS) {
			debug("Timeout\n");
			return -ETIMEDOUT;
		}
	}

	for (ret = 0, i = 0; !ret && i < nmsgs; i++)
		ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);

	/* Send STOP */
	writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
	read_write_byte(i2c);

	return ret ? -EREMOTEIO : 0;
}

static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
{
	const void *blob = gd->fdt_blob;
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	int node;

	node = dev_of_offset(dev);

	i2c_bus->regs = (struct s3c24x0_i2c *)devfdt_get_addr(dev);

	i2c_bus->id = pinmux_decode_periph_id(blob, node);

	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
						  "clock-frequency", 100000);
	i2c_bus->node = node;
	i2c_bus->bus_num = dev->seq;

	exynos_pinmux_config(i2c_bus->id, 0);

	i2c_bus->active = true;

	return 0;
}

static const struct dm_i2c_ops s3c_i2c_ops = {
	.xfer		= s3c24x0_i2c_xfer,
	.probe_chip	= s3c24x0_i2c_probe,
	.set_bus_speed	= s3c24x0_i2c_set_bus_speed,
};

static const struct udevice_id s3c_i2c_ids[] = {
	{ .compatible = "samsung,s3c2440-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_s3c) = {
	.name	= "i2c_s3c",
	.id	= UCLASS_I2C,
	.of_match = s3c_i2c_ids,
	.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
	.ops	= &s3c_i2c_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1cb8e980 WD	2	/*
	3	* (C) Copyright 2002
	4	* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
1cb8e980 WD	5	*/
1cb8e980 WD	6
1cb8e980	7	#include <common.h>
8dfcbaa6 PM	8	#include <errno.h>
8dfcbaa6 PM	9	#include <dm.h>
a9d2ae70	10	#include <fdtdec.h>
c86d9ed3	11	#if (defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5)
ab7e52bb RS	12	#include <asm/arch/clk.h>
ab7e52bb RS	13	#include <asm/arch/cpu.h>
a9d2ae70	14	#include <asm/arch/pinmux.h>
ab7e52bb	15	#else
ac67804f	16	#include <asm/arch/s3c24x0_cpu.h>
ab7e52bb	17	#endif
eb0ae7f5	18	#include <asm/io.h>
1cb8e980	19	#include <i2c.h>
ab7e52bb	20	#include "s3c24x0_i2c.h"
1cb8e980	21
a298712e JC	22	#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
	23	#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
	24	#else
	25	#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
	26	#endif
	27
8dfcbaa6 PM	28	DECLARE_GLOBAL_DATA_PTR;
8dfcbaa6 PM	29
e4e24020 NKC	30	/*
	31	* Wait til the byte transfer is completed.
	32	*
	33	* @param i2c- pointer to the appropriate i2c register bank.
	34	* @return I2C_OK, if transmission was ACKED
	35	* I2C_NACK, if transmission was NACKED
	36	* I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
	37	*/
	38
ab7e52bb	39	static int WaitForXfer(struct s3c24x0_i2c *i2c)
1cb8e980	40	{
e4e24020	41	ulong start_time = get_timer(0);
1cb8e980	42
e4e24020 NKC	43	do {
	44	if (readl(&i2c->iiccon) & I2CCON_IRPND)
	45	return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
	46	I2C_NACK : I2C_OK;
	47	} while (get_timer(start_time) < I2C_TIMEOUT_MS);
1cb8e980	48
e4e24020	49	return I2C_NOK_TOUT;
1cb8e980 WD	50	}
1cb8e980 WD	51
26ea7685	52	static void read_write_byte(struct s3c24x0_i2c *i2c)
1cb8e980	53	{
26ea7685	54	clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
1cb8e980 WD	55	}
1cb8e980 WD	56
ab7e52bb RS	57	static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
	58	{
	59	ulong freq, pres = 16, div;
c86d9ed3	60	#if (defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5)
ab7e52bb RS	61	freq = get_i2c_clk();
	62	#else
	63	freq = get_PCLK();
	64	#endif
	65	/* calculate prescaler and divisor values */
	66	if ((freq / pres / (16 + 1)) > speed)
	67	/* set prescaler to 512 */
	68	pres = 512;
	69
	70	div = 0;
	71	while ((freq / pres / (div + 1)) > speed)
	72	div++;
	73
	74	/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
	75	writel((div & 0x0F) \| 0xA0 \| ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
	76
	77	/* init to SLAVE REVEIVE and set slaveaddr */
	78	writel(0, &i2c->iicstat);
	79	writel(slaveadd, &i2c->iicadd);
	80	/* program Master Transmit (and implicit STOP) */
	81	writel(I2C_MODE_MT \| I2C_TXRX_ENA, &i2c->iicstat);
	82	}
	83
8dfcbaa6	84	static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
2d8f1e27	85	{
9a1bff69	86	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
2d8f1e27	87
2d8f1e27 PW	88	i2c_bus->clock_frequency = speed;
2d8f1e27 PW	89
37b8eb37	90	i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
a298712e	91	SYS_I2C_S3C24X0_SLAVE_ADDR);
2d8f1e27 PW	92
	93	return 0;
	94	}
	95
1cb8e980	96	/*
fc3e2165 WD	97	* cmd_type is 0 for write, 1 for read.
	98	*
	99	* addr_len can take any value from 0-255, it is only limited
	100	* by the char, we could make it larger if needed. If it is
	101	* 0 we skip the address write cycle.
	102	*/
ab7e52bb RS	103	static int i2c_transfer(struct s3c24x0_i2c *i2c,
	104	unsigned char cmd_type,
	105	unsigned char chip,
	106	unsigned char addr[],
	107	unsigned char addr_len,
	108	unsigned char data[],
	109	unsigned short data_len)
1cb8e980	110	{
e4e24020 NKC	111	int i = 0, result;
e4e24020 NKC	112	ulong start_time = get_timer(0);
1cb8e980	113
fc3e2165 WD	114	if (data == 0 \|\| data_len == 0) {
fc3e2165 WD	115	/Don't support data transfer of no length or to address 0 /
ab7e52bb	116	debug("i2c_transfer: bad call\n");
fc3e2165 WD	117	return I2C_NOK;
fc3e2165 WD	118	}
1cb8e980	119
e4e24020 NKC	120	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
	121	if (get_timer(start_time) > I2C_TIMEOUT_MS)
	122	return I2C_NOK_TOUT;
fc3e2165	123	}
1cb8e980	124
ab7e52bb	125	writel(readl(&i2c->iiccon) \| I2CCON_ACKGEN, &i2c->iiccon);
1cb8e980	126
e4e24020 NKC	127	/* Get the slave chip address going */
	128	writel(chip, &i2c->iicds);
	129	if ((cmd_type == I2C_WRITE) \|\| (addr && addr_len))
	130	writel(I2C_MODE_MT \| I2C_TXRX_ENA \| I2C_START_STOP,
	131	&i2c->iicstat);
	132	else
	133	writel(I2C_MODE_MR \| I2C_TXRX_ENA \| I2C_START_STOP,
	134	&i2c->iicstat);
	135
	136	/* Wait for chip address to transmit. */
	137	result = WaitForXfer(i2c);
	138	if (result != I2C_OK)
	139	goto bailout;
	140
	141	/* If register address needs to be transmitted - do it now. */
	142	if (addr && addr_len) {
	143	while ((i < addr_len) && (result == I2C_OK)) {
	144	writel(addr[i++], &i2c->iicds);
26ea7685	145	read_write_byte(i2c);
e4e24020	146	result = WaitForXfer(i2c);
1cb8e980	147	}
e4e24020 NKC	148	i = 0;
	149	if (result != I2C_OK)
	150	goto bailout;
	151	}
1cb8e980	152
e4e24020 NKC	153	switch (cmd_type) {
	154	case I2C_WRITE:
	155	while ((i < data_len) && (result == I2C_OK)) {
	156	writel(data[i++], &i2c->iicds);
26ea7685	157	read_write_byte(i2c);
ab7e52bb	158	result = WaitForXfer(i2c);
e4e24020	159	}
fc3e2165	160	break;
1cb8e980	161
48b42616	162	case I2C_READ:
fc3e2165	163	if (addr && addr_len) {
e4e24020 NKC	164	/*
	165	* Register address has been sent, now send slave chip
	166	* address again to start the actual read transaction.
	167	*/
d9abba82	168	writel(chip, &i2c->iicds);
e4e24020 NKC	169
e4e24020 NKC	170	/* Generate a re-START. */
cb466c05 RS	171	writel(I2C_MODE_MR \| I2C_TXRX_ENA \| I2C_START_STOP,
cb466c05 RS	172	&i2c->iicstat);
26ea7685	173	read_write_byte(i2c);
ab7e52bb	174	result = WaitForXfer(i2c);
fc3e2165	175
e4e24020 NKC	176	if (result != I2C_OK)
e4e24020 NKC	177	goto bailout;
1cb8e980	178	}
1cb8e980	179
e4e24020 NKC	180	while ((i < data_len) && (result == I2C_OK)) {
	181	/* disable ACK for final READ */
	182	if (i == data_len - 1)
	183	writel(readl(&i2c->iiccon)
	184	& ~I2CCON_ACKGEN,
	185	&i2c->iiccon);
26ea7685	186	read_write_byte(i2c);
e4e24020 NKC	187	result = WaitForXfer(i2c);
	188	data[i++] = readl(&i2c->iicds);
	189	}
	190	if (result == I2C_NACK)
	191	result = I2C_OK; /* Normal terminated read. */
fc3e2165	192	break;
1cb8e980 WD	193
1cb8e980 WD	194	default:
ab7e52bb	195	debug("i2c_transfer: bad call\n");
fc3e2165 WD	196	result = I2C_NOK;
	197	break;
	198	}
1cb8e980	199
e4e24020 NKC	200	bailout:
	201	/* Send STOP. */
	202	writel(I2C_MODE_MR \| I2C_TXRX_ENA, &i2c->iicstat);
26ea7685	203	read_write_byte(i2c);
e4e24020	204
ab7e52bb	205	return result;
1cb8e980 WD	206	}
1cb8e980 WD	207
8dfcbaa6	208	static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
1cb8e980	209	{
9a1bff69	210	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
fc3e2165	211	uchar buf[1];
296a461d	212	int ret;
1cb8e980	213
fc3e2165	214	buf[0] = 0;
1cb8e980	215
fc3e2165 WD	216	/*
	217	* What is needed is to send the chip address and verify that the
	218	* address was <ACK>ed (i.e. there was a chip at that address which
	219	* drove the data line low).
	220	*/
37b8eb37	221	ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
296a461d	222
296a461d	223	return ret != I2C_OK;
1cb8e980 WD	224	}
1cb8e980 WD	225
45d9ae87 SG	226	static int s3c24x0_do_msg(struct s3c24x0_i2c_bus i2c_bus, struct i2c_msg msg,
45d9ae87 SG	227	int seq)
8dfcbaa6	228	{
45d9ae87 SG	229	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	230	bool is_read = msg->flags & I2C_M_RD;
	231	uint status;
	232	uint addr;
	233	int ret, i;
8dfcbaa6	234
45d9ae87 SG	235	if (!seq)
	236	setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
	237
	238	/* Get the slave chip address going */
	239	addr = msg->addr << 1;
	240	writel(addr, &i2c->iicds);
	241	status = I2C_TXRX_ENA \| I2C_START_STOP;
	242	if (is_read)
	243	status \|= I2C_MODE_MR;
	244	else
	245	status \|= I2C_MODE_MT;
	246	writel(status, &i2c->iicstat);
	247	if (seq)
	248	read_write_byte(i2c);
	249
	250	/* Wait for chip address to transmit */
	251	ret = WaitForXfer(i2c);
	252	if (ret)
	253	goto err;
	254
	255	if (is_read) {
	256	for (i = 0; !ret && i < msg->len; i++) {
	257	/* disable ACK for final READ */
	258	if (i == msg->len - 1)
	259	clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
	260	read_write_byte(i2c);
	261	ret = WaitForXfer(i2c);
	262	msg->buf[i] = readl(&i2c->iicds);
	263	}
	264	if (ret == I2C_NACK)
	265	ret = I2C_OK; /* Normal terminated read */
8dfcbaa6	266	} else {
45d9ae87 SG	267	for (i = 0; !ret && i < msg->len; i++) {
	268	writel(msg->buf[i], &i2c->iicds);
	269	read_write_byte(i2c);
	270	ret = WaitForXfer(i2c);
	271	}
8dfcbaa6 PM	272	}
8dfcbaa6 PM	273
45d9ae87 SG	274	err:
45d9ae87 SG	275	return ret;
8dfcbaa6 PM	276	}
	277
	278	static int s3c24x0_i2c_xfer(struct udevice dev, struct i2c_msg msg,
	279	int nmsgs)
	280	{
	281	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
45d9ae87 SG	282	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	283	ulong start_time;
	284	int ret, i;
8dfcbaa6	285
45d9ae87 SG	286	start_time = get_timer(0);
	287	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
	288	if (get_timer(start_time) > I2C_TIMEOUT_MS) {
	289	debug("Timeout\n");
	290	return -ETIMEDOUT;
8dfcbaa6	291	}
8dfcbaa6 PM	292	}
8dfcbaa6 PM	293
45d9ae87 SG	294	for (ret = 0, i = 0; !ret && i < nmsgs; i++)
	295	ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
	296
	297	/* Send STOP */
	298	writel(I2C_MODE_MR \| I2C_TXRX_ENA, &i2c->iicstat);
	299	read_write_byte(i2c);
	300
	301	return ret ? -EREMOTEIO : 0;
8dfcbaa6 PM	302	}
	303
	304	static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
	305	{
	306	const void *blob = gd->fdt_blob;
	307	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
37b8eb37	308	int node;
8dfcbaa6	309
e160f7d4	310	node = dev_of_offset(dev);
8dfcbaa6	311
a821c4af	312	i2c_bus->regs = (struct s3c24x0_i2c *)devfdt_get_addr(dev);
8dfcbaa6 PM	313
	314	i2c_bus->id = pinmux_decode_periph_id(blob, node);
	315
	316	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
45d9ae87	317	"clock-frequency", 100000);
8dfcbaa6 PM	318	i2c_bus->node = node;
	319	i2c_bus->bus_num = dev->seq;
	320
37b8eb37	321	exynos_pinmux_config(i2c_bus->id, 0);
8dfcbaa6 PM	322
	323	i2c_bus->active = true;
	324
	325	return 0;
	326	}
	327
	328	static const struct dm_i2c_ops s3c_i2c_ops = {
	329	.xfer = s3c24x0_i2c_xfer,
	330	.probe_chip = s3c24x0_i2c_probe,
	331	.set_bus_speed = s3c24x0_i2c_set_bus_speed,
	332	};
	333
	334	static const struct udevice_id s3c_i2c_ids[] = {
37b8eb37	335	{ .compatible = "samsung,s3c2440-i2c" },
8dfcbaa6 PM	336	{ }
	337	};
	338
	339	U_BOOT_DRIVER(i2c_s3c) = {
	340	.name = "i2c_s3c",
	341	.id = UCLASS_I2C,
	342	.of_match = s3c_i2c_ids,
	343	.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
8dfcbaa6 PM	344	.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
	345	.ops = &s3c_i2c_ops,
	346	};