[people/ms/u-boot.git] / drivers / i2c / s3c24x0_i2c.c

/*
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* This code should work for both the S3C2400 and the S3C2410
 * as they seem to have the same I2C controller inside.
 * The different address mapping is handled by the s3c24xx.h files below.
 */
#include <common.h>
#include <errno.h>
#include <dm.h>
#include <fdtdec.h>
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pinmux.h>
#else
#include <asm/arch/s3c24x0_cpu.h>
#endif
#include <asm/io.h>
#include <i2c.h>
#include "s3c24x0_i2c.h"

#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
#define SYS_I2C_S3C24X0_SLAVE_ADDR	0
#else
#define SYS_I2C_S3C24X0_SLAVE_ADDR	CONFIG_SYS_I2C_S3C24X0_SLAVE
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * Wait til the byte transfer is completed.
 *
 * @param i2c- pointer to the appropriate i2c register bank.
 * @return I2C_OK, if transmission was ACKED
 *         I2C_NACK, if transmission was NACKED
 *         I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
 */

static int WaitForXfer(struct s3c24x0_i2c *i2c)
{
	ulong start_time = get_timer(0);

	do {
		if (readl(&i2c->iiccon) & I2CCON_IRPND)
			return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
				I2C_NACK : I2C_OK;
	} while (get_timer(start_time) < I2C_TIMEOUT_MS);

	return I2C_NOK_TOUT;
}

static void read_write_byte(struct s3c24x0_i2c *i2c)
{
	clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}

static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
	ulong freq, pres = 16, div;
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
	freq = get_i2c_clk();
#else
	freq = get_PCLK();
#endif
	/* calculate prescaler and divisor values */
	if ((freq / pres / (16 + 1)) > speed)
		/* set prescaler to 512 */
		pres = 512;

	div = 0;
	while ((freq / pres / (div + 1)) > speed)
		div++;

	/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
	writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);

	/* init to SLAVE REVEIVE and set slaveaddr */
	writel(0, &i2c->iicstat);
	writel(slaveadd, &i2c->iicadd);
	/* program Master Transmit (and implicit STOP) */
	writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}

static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);

	i2c_bus->clock_frequency = speed;

	i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
		    SYS_I2C_S3C24X0_SLAVE_ADDR);

	return 0;
}

/*
 * cmd_type is 0 for write, 1 for read.
 *
 * addr_len can take any value from 0-255, it is only limited
 * by the char, we could make it larger if needed. If it is
 * 0 we skip the address write cycle.
 */
static int i2c_transfer(struct s3c24x0_i2c *i2c,
			unsigned char cmd_type,
			unsigned char chip,
			unsigned char addr[],
			unsigned char addr_len,
			unsigned char data[],
			unsigned short data_len)
{
	int i = 0, result;
	ulong start_time = get_timer(0);

	if (data == 0 || data_len == 0) {
		/*Don't support data transfer of no length or to address 0 */
		debug("i2c_transfer: bad call\n");
		return I2C_NOK;
	}

	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
		if (get_timer(start_time) > I2C_TIMEOUT_MS)
			return I2C_NOK_TOUT;
	}

	writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);

	/* Get the slave chip address going */
	writel(chip, &i2c->iicds);
	if ((cmd_type == I2C_WRITE) || (addr && addr_len))
		writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
		       &i2c->iicstat);
	else
		writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
		       &i2c->iicstat);

	/* Wait for chip address to transmit. */
	result = WaitForXfer(i2c);
	if (result != I2C_OK)
		goto bailout;

	/* If register address needs to be transmitted - do it now. */
	if (addr && addr_len) {
		while ((i < addr_len) && (result == I2C_OK)) {
			writel(addr[i++], &i2c->iicds);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
		}
		i = 0;
		if (result != I2C_OK)
			goto bailout;
	}

	switch (cmd_type) {
	case I2C_WRITE:
		while ((i < data_len) && (result == I2C_OK)) {
			writel(data[i++], &i2c->iicds);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
		}
		break;

	case I2C_READ:
		if (addr && addr_len) {
			/*
			 * Register address has been sent, now send slave chip
			 * address again to start the actual read transaction.
			 */
			writel(chip, &i2c->iicds);

			/* Generate a re-START. */
			writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
				&i2c->iicstat);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);

			if (result != I2C_OK)
				goto bailout;
		}

		while ((i < data_len) && (result == I2C_OK)) {
			/* disable ACK for final READ */
			if (i == data_len - 1)
				writel(readl(&i2c->iiccon)
				       & ~I2CCON_ACKGEN,
				       &i2c->iiccon);
			read_write_byte(i2c);
			result = WaitForXfer(i2c);
			data[i++] = readl(&i2c->iicds);
		}
		if (result == I2C_NACK)
			result = I2C_OK; /* Normal terminated read. */
		break;

	default:
		debug("i2c_transfer: bad call\n");
		result = I2C_NOK;
		break;
	}

bailout:
	/* Send STOP. */
	writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
	read_write_byte(i2c);

	return result;
}

static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	uchar buf[1];
	int ret;

	buf[0] = 0;

	/*
	 * What is needed is to send the chip address and verify that the
	 * address was <ACK>ed (i.e. there was a chip at that address which
	 * drove the data line low).
	 */
	ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);

	return ret != I2C_OK;
}

static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
			  int seq)
{
	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	bool is_read = msg->flags & I2C_M_RD;
	uint status;
	uint addr;
	int ret, i;

	if (!seq)
		setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);

	/* Get the slave chip address going */
	addr = msg->addr << 1;
	writel(addr, &i2c->iicds);
	status = I2C_TXRX_ENA | I2C_START_STOP;
	if (is_read)
		status |= I2C_MODE_MR;
	else
		status |= I2C_MODE_MT;
	writel(status, &i2c->iicstat);
	if (seq)
		read_write_byte(i2c);

	/* Wait for chip address to transmit */
	ret = WaitForXfer(i2c);
	if (ret)
		goto err;

	if (is_read) {
		for (i = 0; !ret && i < msg->len; i++) {
			/* disable ACK for final READ */
			if (i == msg->len - 1)
				clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
			read_write_byte(i2c);
			ret = WaitForXfer(i2c);
			msg->buf[i] = readl(&i2c->iicds);
		}
		if (ret == I2C_NACK)
			ret = I2C_OK; /* Normal terminated read */
	} else {
		for (i = 0; !ret && i < msg->len; i++) {
			writel(msg->buf[i], &i2c->iicds);
			read_write_byte(i2c);
			ret = WaitForXfer(i2c);
		}
	}

err:
	return ret;
}

static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
			    int nmsgs)
{
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	ulong start_time;
	int ret, i;

	start_time = get_timer(0);
	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
		if (get_timer(start_time) > I2C_TIMEOUT_MS) {
			debug("Timeout\n");
			return -ETIMEDOUT;
		}
	}

	for (ret = 0, i = 0; !ret && i < nmsgs; i++)
		ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);

	/* Send STOP */
	writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
	read_write_byte(i2c);

	return ret ? -EREMOTEIO : 0;
}

static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
{
	const void *blob = gd->fdt_blob;
	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
	int node;

	node = dev_of_offset(dev);

	i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);

	i2c_bus->id = pinmux_decode_periph_id(blob, node);

	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
						  "clock-frequency", 100000);
	i2c_bus->node = node;
	i2c_bus->bus_num = dev->seq;

	exynos_pinmux_config(i2c_bus->id, 0);

	i2c_bus->active = true;

	return 0;
}

static const struct dm_i2c_ops s3c_i2c_ops = {
	.xfer		= s3c24x0_i2c_xfer,
	.probe_chip	= s3c24x0_i2c_probe,
	.set_bus_speed	= s3c24x0_i2c_set_bus_speed,
};

static const struct udevice_id s3c_i2c_ids[] = {
	{ .compatible = "samsung,s3c2440-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_s3c) = {
	.name	= "i2c_s3c",
	.id	= UCLASS_I2C,
	.of_match = s3c_i2c_ids,
	.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
	.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
	.ops	= &s3c_i2c_ops,
};
Commit	Line	Data
1cb8e980 WD	1	/*
	2	* (C) Copyright 2002
	3	* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
1cb8e980 WD	6	*/
	7
	8	/* This code should work for both the S3C2400 and the S3C2410
	9	* as they seem to have the same I2C controller inside.
	10	* The different address mapping is handled by the s3c24xx.h files below.
	11	*/
1cb8e980	12	#include <common.h>
8dfcbaa6 PM	13	#include <errno.h>
8dfcbaa6 PM	14	#include <dm.h>
a9d2ae70	15	#include <fdtdec.h>
c86d9ed3	16	#if (defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5)
ab7e52bb RS	17	#include <asm/arch/clk.h>
ab7e52bb RS	18	#include <asm/arch/cpu.h>
a9d2ae70	19	#include <asm/arch/pinmux.h>
ab7e52bb	20	#else
ac67804f	21	#include <asm/arch/s3c24x0_cpu.h>
ab7e52bb	22	#endif
eb0ae7f5	23	#include <asm/io.h>
1cb8e980	24	#include <i2c.h>
ab7e52bb	25	#include "s3c24x0_i2c.h"
1cb8e980	26
a298712e JC	27	#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
	28	#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
	29	#else
	30	#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
	31	#endif
	32
8dfcbaa6 PM	33	DECLARE_GLOBAL_DATA_PTR;
8dfcbaa6 PM	34
e4e24020 NKC	35	/*
	36	* Wait til the byte transfer is completed.
	37	*
	38	* @param i2c- pointer to the appropriate i2c register bank.
	39	* @return I2C_OK, if transmission was ACKED
	40	* I2C_NACK, if transmission was NACKED
	41	* I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
	42	*/
	43
ab7e52bb	44	static int WaitForXfer(struct s3c24x0_i2c *i2c)
1cb8e980	45	{
e4e24020	46	ulong start_time = get_timer(0);
1cb8e980	47
e4e24020 NKC	48	do {
	49	if (readl(&i2c->iiccon) & I2CCON_IRPND)
	50	return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
	51	I2C_NACK : I2C_OK;
	52	} while (get_timer(start_time) < I2C_TIMEOUT_MS);
1cb8e980	53
e4e24020	54	return I2C_NOK_TOUT;
1cb8e980 WD	55	}
1cb8e980 WD	56
26ea7685	57	static void read_write_byte(struct s3c24x0_i2c *i2c)
1cb8e980	58	{
26ea7685	59	clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
1cb8e980 WD	60	}
1cb8e980 WD	61
ab7e52bb RS	62	static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
	63	{
	64	ulong freq, pres = 16, div;
c86d9ed3	65	#if (defined CONFIG_EXYNOS4 \|\| defined CONFIG_EXYNOS5)
ab7e52bb RS	66	freq = get_i2c_clk();
	67	#else
	68	freq = get_PCLK();
	69	#endif
	70	/* calculate prescaler and divisor values */
	71	if ((freq / pres / (16 + 1)) > speed)
	72	/* set prescaler to 512 */
	73	pres = 512;
	74
	75	div = 0;
	76	while ((freq / pres / (div + 1)) > speed)
	77	div++;
	78
	79	/* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
	80	writel((div & 0x0F) \| 0xA0 \| ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
	81
	82	/* init to SLAVE REVEIVE and set slaveaddr */
	83	writel(0, &i2c->iicstat);
	84	writel(slaveadd, &i2c->iicadd);
	85	/* program Master Transmit (and implicit STOP) */
	86	writel(I2C_MODE_MT \| I2C_TXRX_ENA, &i2c->iicstat);
	87	}
	88
8dfcbaa6	89	static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
2d8f1e27	90	{
9a1bff69	91	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
2d8f1e27	92
2d8f1e27 PW	93	i2c_bus->clock_frequency = speed;
2d8f1e27 PW	94
37b8eb37	95	i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
a298712e	96	SYS_I2C_S3C24X0_SLAVE_ADDR);
2d8f1e27 PW	97
	98	return 0;
	99	}
	100
1cb8e980	101	/*
fc3e2165 WD	102	* cmd_type is 0 for write, 1 for read.
	103	*
	104	* addr_len can take any value from 0-255, it is only limited
	105	* by the char, we could make it larger if needed. If it is
	106	* 0 we skip the address write cycle.
	107	*/
ab7e52bb RS	108	static int i2c_transfer(struct s3c24x0_i2c *i2c,
	109	unsigned char cmd_type,
	110	unsigned char chip,
	111	unsigned char addr[],
	112	unsigned char addr_len,
	113	unsigned char data[],
	114	unsigned short data_len)
1cb8e980	115	{
e4e24020 NKC	116	int i = 0, result;
e4e24020 NKC	117	ulong start_time = get_timer(0);
1cb8e980	118
fc3e2165 WD	119	if (data == 0 \|\| data_len == 0) {
fc3e2165 WD	120	/Don't support data transfer of no length or to address 0 /
ab7e52bb	121	debug("i2c_transfer: bad call\n");
fc3e2165 WD	122	return I2C_NOK;
fc3e2165 WD	123	}
1cb8e980	124
e4e24020 NKC	125	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
	126	if (get_timer(start_time) > I2C_TIMEOUT_MS)
	127	return I2C_NOK_TOUT;
fc3e2165	128	}
1cb8e980	129
ab7e52bb	130	writel(readl(&i2c->iiccon) \| I2CCON_ACKGEN, &i2c->iiccon);
1cb8e980	131
e4e24020 NKC	132	/* Get the slave chip address going */
	133	writel(chip, &i2c->iicds);
	134	if ((cmd_type == I2C_WRITE) \|\| (addr && addr_len))
	135	writel(I2C_MODE_MT \| I2C_TXRX_ENA \| I2C_START_STOP,
	136	&i2c->iicstat);
	137	else
	138	writel(I2C_MODE_MR \| I2C_TXRX_ENA \| I2C_START_STOP,
	139	&i2c->iicstat);
	140
	141	/* Wait for chip address to transmit. */
	142	result = WaitForXfer(i2c);
	143	if (result != I2C_OK)
	144	goto bailout;
	145
	146	/* If register address needs to be transmitted - do it now. */
	147	if (addr && addr_len) {
	148	while ((i < addr_len) && (result == I2C_OK)) {
	149	writel(addr[i++], &i2c->iicds);
26ea7685	150	read_write_byte(i2c);
e4e24020	151	result = WaitForXfer(i2c);
1cb8e980	152	}
e4e24020 NKC	153	i = 0;
	154	if (result != I2C_OK)
	155	goto bailout;
	156	}
1cb8e980	157
e4e24020 NKC	158	switch (cmd_type) {
	159	case I2C_WRITE:
	160	while ((i < data_len) && (result == I2C_OK)) {
	161	writel(data[i++], &i2c->iicds);
26ea7685	162	read_write_byte(i2c);
ab7e52bb	163	result = WaitForXfer(i2c);
e4e24020	164	}
fc3e2165	165	break;
1cb8e980	166
48b42616	167	case I2C_READ:
fc3e2165	168	if (addr && addr_len) {
e4e24020 NKC	169	/*
	170	* Register address has been sent, now send slave chip
	171	* address again to start the actual read transaction.
	172	*/
d9abba82	173	writel(chip, &i2c->iicds);
e4e24020 NKC	174
e4e24020 NKC	175	/* Generate a re-START. */
cb466c05 RS	176	writel(I2C_MODE_MR \| I2C_TXRX_ENA \| I2C_START_STOP,
cb466c05 RS	177	&i2c->iicstat);
26ea7685	178	read_write_byte(i2c);
ab7e52bb	179	result = WaitForXfer(i2c);
fc3e2165	180
e4e24020 NKC	181	if (result != I2C_OK)
e4e24020 NKC	182	goto bailout;
1cb8e980	183	}
1cb8e980	184
e4e24020 NKC	185	while ((i < data_len) && (result == I2C_OK)) {
	186	/* disable ACK for final READ */
	187	if (i == data_len - 1)
	188	writel(readl(&i2c->iiccon)
	189	& ~I2CCON_ACKGEN,
	190	&i2c->iiccon);
26ea7685	191	read_write_byte(i2c);
e4e24020 NKC	192	result = WaitForXfer(i2c);
	193	data[i++] = readl(&i2c->iicds);
	194	}
	195	if (result == I2C_NACK)
	196	result = I2C_OK; /* Normal terminated read. */
fc3e2165	197	break;
1cb8e980 WD	198
1cb8e980 WD	199	default:
ab7e52bb	200	debug("i2c_transfer: bad call\n");
fc3e2165 WD	201	result = I2C_NOK;
	202	break;
	203	}
1cb8e980	204
e4e24020 NKC	205	bailout:
	206	/* Send STOP. */
	207	writel(I2C_MODE_MR \| I2C_TXRX_ENA, &i2c->iicstat);
26ea7685	208	read_write_byte(i2c);
e4e24020	209
ab7e52bb	210	return result;
1cb8e980 WD	211	}
1cb8e980 WD	212
8dfcbaa6	213	static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
1cb8e980	214	{
9a1bff69	215	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
fc3e2165	216	uchar buf[1];
296a461d	217	int ret;
1cb8e980	218
fc3e2165	219	buf[0] = 0;
1cb8e980	220
fc3e2165 WD	221	/*
	222	* What is needed is to send the chip address and verify that the
	223	* address was <ACK>ed (i.e. there was a chip at that address which
	224	* drove the data line low).
	225	*/
37b8eb37	226	ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
296a461d	227
296a461d	228	return ret != I2C_OK;
1cb8e980 WD	229	}
1cb8e980 WD	230
45d9ae87 SG	231	static int s3c24x0_do_msg(struct s3c24x0_i2c_bus i2c_bus, struct i2c_msg msg,
45d9ae87 SG	232	int seq)
8dfcbaa6	233	{
45d9ae87 SG	234	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	235	bool is_read = msg->flags & I2C_M_RD;
	236	uint status;
	237	uint addr;
	238	int ret, i;
8dfcbaa6	239
45d9ae87 SG	240	if (!seq)
	241	setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
	242
	243	/* Get the slave chip address going */
	244	addr = msg->addr << 1;
	245	writel(addr, &i2c->iicds);
	246	status = I2C_TXRX_ENA \| I2C_START_STOP;
	247	if (is_read)
	248	status \|= I2C_MODE_MR;
	249	else
	250	status \|= I2C_MODE_MT;
	251	writel(status, &i2c->iicstat);
	252	if (seq)
	253	read_write_byte(i2c);
	254
	255	/* Wait for chip address to transmit */
	256	ret = WaitForXfer(i2c);
	257	if (ret)
	258	goto err;
	259
	260	if (is_read) {
	261	for (i = 0; !ret && i < msg->len; i++) {
	262	/* disable ACK for final READ */
	263	if (i == msg->len - 1)
	264	clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
	265	read_write_byte(i2c);
	266	ret = WaitForXfer(i2c);
	267	msg->buf[i] = readl(&i2c->iicds);
	268	}
	269	if (ret == I2C_NACK)
	270	ret = I2C_OK; /* Normal terminated read */
8dfcbaa6	271	} else {
45d9ae87 SG	272	for (i = 0; !ret && i < msg->len; i++) {
	273	writel(msg->buf[i], &i2c->iicds);
	274	read_write_byte(i2c);
	275	ret = WaitForXfer(i2c);
	276	}
8dfcbaa6 PM	277	}
8dfcbaa6 PM	278
45d9ae87 SG	279	err:
45d9ae87 SG	280	return ret;
8dfcbaa6 PM	281	}
	282
	283	static int s3c24x0_i2c_xfer(struct udevice dev, struct i2c_msg msg,
	284	int nmsgs)
	285	{
	286	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
45d9ae87 SG	287	struct s3c24x0_i2c *i2c = i2c_bus->regs;
	288	ulong start_time;
	289	int ret, i;
8dfcbaa6	290
45d9ae87 SG	291	start_time = get_timer(0);
	292	while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
	293	if (get_timer(start_time) > I2C_TIMEOUT_MS) {
	294	debug("Timeout\n");
	295	return -ETIMEDOUT;
8dfcbaa6	296	}
8dfcbaa6 PM	297	}
8dfcbaa6 PM	298
45d9ae87 SG	299	for (ret = 0, i = 0; !ret && i < nmsgs; i++)
	300	ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
	301
	302	/* Send STOP */
	303	writel(I2C_MODE_MR \| I2C_TXRX_ENA, &i2c->iicstat);
	304	read_write_byte(i2c);
	305
	306	return ret ? -EREMOTEIO : 0;
8dfcbaa6 PM	307	}
	308
	309	static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
	310	{
	311	const void *blob = gd->fdt_blob;
	312	struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
37b8eb37	313	int node;
8dfcbaa6	314
e160f7d4	315	node = dev_of_offset(dev);
8dfcbaa6	316
37b8eb37	317	i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
8dfcbaa6 PM	318
	319	i2c_bus->id = pinmux_decode_periph_id(blob, node);
	320
	321	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
45d9ae87	322	"clock-frequency", 100000);
8dfcbaa6 PM	323	i2c_bus->node = node;
	324	i2c_bus->bus_num = dev->seq;
	325
37b8eb37	326	exynos_pinmux_config(i2c_bus->id, 0);
8dfcbaa6 PM	327
	328	i2c_bus->active = true;
	329
	330	return 0;
	331	}
	332
	333	static const struct dm_i2c_ops s3c_i2c_ops = {
	334	.xfer = s3c24x0_i2c_xfer,
	335	.probe_chip = s3c24x0_i2c_probe,
	336	.set_bus_speed = s3c24x0_i2c_set_bus_speed,
	337	};
	338
	339	static const struct udevice_id s3c_i2c_ids[] = {
37b8eb37	340	{ .compatible = "samsung,s3c2440-i2c" },
8dfcbaa6 PM	341	{ }
	342	};
	343
	344	U_BOOT_DRIVER(i2c_s3c) = {
	345	.name = "i2c_s3c",
	346	.id = UCLASS_I2C,
	347	.of_match = s3c_i2c_ids,
	348	.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
8dfcbaa6 PM	349	.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
	350	.ops = &s3c_i2c_ops,
	351	};