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Commit | Line | Data |
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91dffb16 RS |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
91dffb16 RS |
5 | */ |
6 | ||
7 | #ifndef _S3C24X0_I2C_H | |
8 | #define _S3C24X0_I2C_H | |
9 | ||
10 | struct s3c24x0_i2c { | |
11 | u32 iiccon; | |
12 | u32 iicstat; | |
13 | u32 iicadd; | |
14 | u32 iicds; | |
15 | u32 iiclc; | |
16 | }; | |
a9d2ae70 | 17 | |
296a461d NKC |
18 | struct exynos5_hsi2c { |
19 | u32 usi_ctl; | |
20 | u32 usi_fifo_ctl; | |
21 | u32 usi_trailing_ctl; | |
22 | u32 usi_clk_ctl; | |
23 | u32 usi_clk_slot; | |
24 | u32 spi_ctl; | |
25 | u32 uart_ctl; | |
26 | u32 res1; | |
27 | u32 usi_int_en; | |
28 | u32 usi_int_stat; | |
29 | u32 usi_modem_stat; | |
30 | u32 usi_error_stat; | |
31 | u32 usi_fifo_stat; | |
32 | u32 usi_txdata; | |
33 | u32 usi_rxdata; | |
34 | u32 res2; | |
35 | u32 usi_conf; | |
36 | u32 usi_auto_conf; | |
37 | u32 usi_timeout; | |
38 | u32 usi_manual_cmd; | |
39 | u32 usi_trans_status; | |
40 | u32 usi_timing_hs1; | |
41 | u32 usi_timing_hs2; | |
42 | u32 usi_timing_hs3; | |
43 | u32 usi_timing_fs1; | |
44 | u32 usi_timing_fs2; | |
45 | u32 usi_timing_fs3; | |
46 | u32 usi_timing_sla; | |
47 | u32 i2c_addr; | |
48 | }; | |
49 | ||
a9d2ae70 | 50 | struct s3c24x0_i2c_bus { |
940dd162 | 51 | bool active; /* port is active and available */ |
a9d2ae70 RS |
52 | int node; /* device tree node */ |
53 | int bus_num; /* i2c bus number */ | |
54 | struct s3c24x0_i2c *regs; | |
296a461d NKC |
55 | struct exynos5_hsi2c *hsregs; |
56 | int is_highspeed; /* High speed type, rather than I2C */ | |
57 | unsigned clock_frequency; | |
d04df3c6 | 58 | int id; |
296a461d NKC |
59 | unsigned clk_cycle; |
60 | unsigned clk_div; | |
a9d2ae70 | 61 | }; |
37b8eb37 SG |
62 | |
63 | #define I2C_WRITE 0 | |
64 | #define I2C_READ 1 | |
65 | ||
66 | #define I2C_OK 0 | |
67 | #define I2C_NOK 1 | |
68 | #define I2C_NACK 2 | |
69 | #define I2C_NOK_LA 3 /* Lost arbitration */ | |
70 | #define I2C_NOK_TOUT 4 /* time out */ | |
71 | ||
72 | /* S3C I2C Controller bits */ | |
73 | #define I2CSTAT_BSY 0x20 /* Busy bit */ | |
74 | #define I2CSTAT_NACK 0x01 /* Nack bit */ | |
75 | #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ | |
76 | #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ | |
77 | #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ | |
78 | #define I2C_MODE_MR 0x80 /* Master Receive Mode */ | |
79 | #define I2C_START_STOP 0x20 /* START / STOP */ | |
80 | #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ | |
81 | ||
82 | #define I2C_TIMEOUT_MS 10 /* 10 ms */ | |
83 | ||
91dffb16 | 84 | #endif /* _S3C24X0_I2C_H */ |