[people/ms/u-boot.git] / drivers / i2c / sh_i2c.c

/*
 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.txt for instructions.
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* Every register is 32bit aligned, but only 8bits in size */
#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
struct sh_i2c {
	ureg(icdr);
	ureg(iccr);
	ureg(icsr);
	ureg(icic);
	ureg(iccl);
	ureg(icch);
};
#undef ureg

/* ICCR */
#define SH_I2C_ICCR_ICE		(1 << 7)
#define SH_I2C_ICCR_RACK	(1 << 6)
#define SH_I2C_ICCR_RTS		(1 << 4)
#define SH_I2C_ICCR_BUSY	(1 << 2)
#define SH_I2C_ICCR_SCP		(1 << 0)

/* ICSR / ICIC */
#define SH_IC_BUSY	(1 << 4)
#define SH_IC_TACK	(1 << 2)
#define SH_IC_WAIT	(1 << 1)
#define SH_IC_DTE	(1 << 0)

#ifdef CONFIG_SH_I2C_8BIT
/* store 8th bit of iccl and icch in ICIC register */
#define SH_I2C_ICIC_ICCLB8	(1 << 7)
#define SH_I2C_ICIC_ICCHB8	(1 << 6)
#endif

static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
#ifdef CONFIG_SYS_I2C_SH_BASE1
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE2
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE3
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE4
	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
#endif
};

static u16 iccl, icch;

#define IRQ_WAIT 1000

static void sh_irq_dte(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (SH_IC_DTE & readb(&dev->icsr))
			break;
		udelay(10);
	}
}

static int sh_irq_dte_with_tack(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (SH_IC_DTE & readb(&dev->icsr))
			break;
		if (SH_IC_TACK & readb(&dev->icsr))
			return -1;
		udelay(10);
	}
	return 0;
}

static void sh_irq_busy(struct sh_i2c *dev)
{
	int i;

	for (i = 0; i < IRQ_WAIT; i++) {
		if (!(SH_IC_BUSY & readb(&dev->icsr)))
			break;
		udelay(10);
	}
}

static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
{
	u8 icic = SH_IC_TACK;

	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
				__func__, chip, addr, iccl, icch);
	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);

	writeb(iccl & 0xff, &dev->iccl);
	writeb(icch & 0xff, &dev->icch);
#ifdef CONFIG_SH_I2C_8BIT
	if (iccl > 0xff)
		icic |= SH_I2C_ICIC_ICCLB8;
	if (icch > 0xff)
		icic |= SH_I2C_ICIC_ICCHB8;
#endif
	writeb(icic, &dev->icic);

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
	sh_irq_dte(dev);

	clrbits_8(&dev->icsr, SH_IC_TACK);
	writeb(chip << 1, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;

	writeb(addr, &dev->icdr);
	if (stop)
		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);

	if (sh_irq_dte_with_tack(dev) != 0)
		return -1;
	return 0;
}

static void sh_i2c_finish(struct sh_i2c *dev)
{
	writeb(0, &dev->icsr);
	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
}

static int
sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
{
	int ret = -1;
	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
		goto exit0;
	udelay(10);

	writeb(val, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;
	sh_irq_busy(dev);
	ret = 0;

exit0:
	sh_i2c_finish(dev);
	return ret;
}

static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
{
	int ret = -1;

#if defined(CONFIG_SH73A0)
	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
		goto exit0;
#else
	if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
		goto exit0;
	udelay(100);
#endif

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
	sh_irq_dte(dev);

	writeb(chip << 1 | 0x01, &dev->icdr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
	if (sh_irq_dte_with_tack(dev) != 0)
		goto exit0;

	ret = readb(&dev->icdr) & 0xff;

	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
	readb(&dev->icdr); /* Dummy read */
	sh_irq_busy(dev);

exit0:
	sh_i2c_finish(dev);

	return ret;
}

static void
sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	int num, denom, tmp;

	/* No i2c support prior to relocation */
	if (!(gd->flags & GD_FLG_RELOC))
		return;

	/*
	 * Calculate the value for iccl. From the data sheet:
	 * iccl = (p-clock / transfer-rate) * (L / (L + H))
	 * where L and H are the SCL low and high ratio.
	 */
	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
	denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		iccl = (u16)((num/denom) + 1);
	else
		iccl = (u16)(num/denom);

	/* Calculate the value for icch. From the data sheet:
	   icch = (p clock / transfer rate) * (H / (L + H)) */
	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		icch = (u16)((num/denom) + 1);
	else
		icch = (u16)(num/denom);

	debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
			CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
}

static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, u8 *data, int len)
{
	int ret, i;
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];

	for (i = 0; i < len; i++) {
		ret = sh_i2c_raw_read(dev, chip, addr + i);
		if (ret < 0)
			return -1;

		data[i] = ret & 0xff;
		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
	}

	return 0;
}

static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
				int alen, u8 *data, int len)
{
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
	int i;

	for (i = 0; i < len; i++) {
		debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
		if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
			return -1;
	}
	return 0;
}

static int
sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	u8 dummy[1];

	return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
}

static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];

	sh_i2c_finish(dev);
	sh_i2c_init(adap, speed, 0);

	return 0;
}

/*
 * Register RCAR i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
#ifdef CONFIG_SYS_I2C_SH_BASE1
U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE2
U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE3
U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
#endif
#ifdef CONFIG_SYS_I2C_SH_BASE4
U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
#endif
Commit	Line	Data
3dab3e0e	1	/*
b55b8eef NI	2	* Copyright (C) 2011, 2013 Renesas Solutions Corp.
b55b8eef NI	3	* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3dab3e0e	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
28527096 SG	6	*
	7	* NOTE: This driver should be converted to driver model before June 2017.
	8	* Please see doc/driver-model/i2c-howto.txt for instructions.
3dab3e0e NI	9	*/
	10
	11	#include <common.h>
2035d77d	12	#include <i2c.h>
3dab3e0e NI	13	#include <asm/io.h>
3dab3e0e NI	14
b55b8eef NI	15	DECLARE_GLOBAL_DATA_PTR;
b55b8eef NI	16
3dab3e0e NI	17	/* Every register is 32bit aligned, but only 8bits in size */
	18	#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
	19	struct sh_i2c {
	20	ureg(icdr);
	21	ureg(iccr);
	22	ureg(icsr);
	23	ureg(icic);
	24	ureg(iccl);
	25	ureg(icch);
	26	};
	27	#undef ureg
	28
3dab3e0e NI	29	/* ICCR */
	30	#define SH_I2C_ICCR_ICE (1 << 7)
	31	#define SH_I2C_ICCR_RACK (1 << 6)
	32	#define SH_I2C_ICCR_RTS (1 << 4)
	33	#define SH_I2C_ICCR_BUSY (1 << 2)
	34	#define SH_I2C_ICCR_SCP (1 << 0)
	35
	36	/* ICSR / ICIC */
57d7c804	37	#define SH_IC_BUSY (1 << 4)
3dab3e0e NI	38	#define SH_IC_TACK (1 << 2)
	39	#define SH_IC_WAIT (1 << 1)
	40	#define SH_IC_DTE (1 << 0)
	41
b1af67fe TK	42	#ifdef CONFIG_SH_I2C_8BIT
	43	/* store 8th bit of iccl and icch in ICIC register */
	44	#define SH_I2C_ICIC_ICCLB8 (1 << 7)
	45	#define SH_I2C_ICIC_ICCHB8 (1 << 6)
	46	#endif
	47
2035d77d NI	48	static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
	49	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
	50	#ifdef CONFIG_SYS_I2C_SH_BASE1
	51	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
	52	#endif
	53	#ifdef CONFIG_SYS_I2C_SH_BASE2
	54	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
	55	#endif
	56	#ifdef CONFIG_SYS_I2C_SH_BASE3
	57	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
	58	#endif
	59	#ifdef CONFIG_SYS_I2C_SH_BASE4
	60	(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
	61	#endif
	62	};
	63
b1af67fe	64	static u16 iccl, icch;
3dab3e0e NI	65
	66	#define IRQ_WAIT 1000
	67
2035d77d	68	static void sh_irq_dte(struct sh_i2c *dev)
3dab3e0e NI	69	{
	70	int i;
	71
2035d77d NI	72	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	73	if (SH_IC_DTE & readb(&dev->icsr))
3dab3e0e NI	74	break;
	75	udelay(10);
	76	}
	77	}
	78
2035d77d	79	static int sh_irq_dte_with_tack(struct sh_i2c *dev)
d042d712 TK	80	{
	81	int i;
	82
2035d77d NI	83	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	84	if (SH_IC_DTE & readb(&dev->icsr))
d042d712	85	break;
2035d77d	86	if (SH_IC_TACK & readb(&dev->icsr))
d042d712 TK	87	return -1;
	88	udelay(10);
	89	}
	90	return 0;
	91	}
	92
2035d77d	93	static void sh_irq_busy(struct sh_i2c *dev)
3dab3e0e NI	94	{
	95	int i;
	96
2035d77d NI	97	for (i = 0; i < IRQ_WAIT; i++) {
2035d77d NI	98	if (!(SH_IC_BUSY & readb(&dev->icsr)))
3dab3e0e NI	99	break;
	100	udelay(10);
	101	}
	102	}
	103
2035d77d	104	static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
3dab3e0e	105	{
d042d712	106	u8 icic = SH_IC_TACK;
b1af67fe	107
2035d77d NI	108	debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
	109	__func__, chip, addr, iccl, icch);
	110	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
	111	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
3dab3e0e	112
2035d77d NI	113	writeb(iccl & 0xff, &dev->iccl);
2035d77d NI	114	writeb(icch & 0xff, &dev->icch);
b1af67fe TK	115	#ifdef CONFIG_SH_I2C_8BIT
	116	if (iccl > 0xff)
	117	icic \|= SH_I2C_ICIC_ICCLB8;
	118	if (icch > 0xff)
	119	icic \|= SH_I2C_ICIC_ICCHB8;
	120	#endif
2035d77d	121	writeb(icic, &dev->icic);
3dab3e0e	122
2035d77d NI	123	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS\|SH_I2C_ICCR_BUSY), &dev->iccr);
2035d77d NI	124	sh_irq_dte(dev);
3dab3e0e	125
2035d77d NI	126	clrbits_8(&dev->icsr, SH_IC_TACK);
	127	writeb(chip << 1, &dev->icdr);
	128	if (sh_irq_dte_with_tack(dev) != 0)
d042d712	129	return -1;
3dab3e0e	130
2035d77d	131	writeb(addr, &dev->icdr);
3dab3e0e	132	if (stop)
2035d77d	133	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS), &dev->iccr);
3dab3e0e	134
2035d77d	135	if (sh_irq_dte_with_tack(dev) != 0)
d042d712 TK	136	return -1;
d042d712 TK	137	return 0;
3dab3e0e NI	138	}
3dab3e0e NI	139
2035d77d	140	static void sh_i2c_finish(struct sh_i2c *dev)
3dab3e0e	141	{
2035d77d NI	142	writeb(0, &dev->icsr);
2035d77d NI	143	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
3dab3e0e NI	144	}
3dab3e0e NI	145
2035d77d NI	146	static int
2035d77d NI	147	sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
3dab3e0e	148	{
0e5fb33c	149	int ret = -1;
2035d77d	150	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
0e5fb33c	151	goto exit0;
3dab3e0e NI	152	udelay(10);
3dab3e0e NI	153
2035d77d NI	154	writeb(val, &dev->icdr);
2035d77d NI	155	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	156	goto exit0;
3dab3e0e	157
2035d77d NI	158	writeb((SH_I2C_ICCR_ICE \| SH_I2C_ICCR_RTS), &dev->iccr);
2035d77d NI	159	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	160	goto exit0;
2035d77d	161	sh_irq_busy(dev);
0e5fb33c	162	ret = 0;
2035d77d	163
0e5fb33c	164	exit0:
2035d77d	165	sh_i2c_finish(dev);
0e5fb33c	166	return ret;
3dab3e0e NI	167	}
3dab3e0e NI	168
2035d77d	169	static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
3dab3e0e	170	{
0e5fb33c	171	int ret = -1;
3dab3e0e	172
3ce2703d	173	#if defined(CONFIG_SH73A0)
2035d77d	174	if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
0e5fb33c	175	goto exit0;
3ce2703d	176	#else
2035d77d	177	if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
0e5fb33c	178	goto exit0;
3dab3e0e	179	udelay(100);
3ce2703d	180	#endif
3dab3e0e	181
2035d77d NI	182	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RTS\|SH_I2C_ICCR_BUSY), &dev->iccr);
2035d77d NI	183	sh_irq_dte(dev);
3dab3e0e	184
2035d77d NI	185	writeb(chip << 1 \| 0x01, &dev->icdr);
2035d77d NI	186	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	187	goto exit0;
3dab3e0e	188
2035d77d NI	189	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_SCP), &dev->iccr);
2035d77d NI	190	if (sh_irq_dte_with_tack(dev) != 0)
0e5fb33c	191	goto exit0;
3dab3e0e	192
2035d77d NI	193	ret = readb(&dev->icdr) & 0xff;
	194
	195	writeb((SH_I2C_ICCR_ICE\|SH_I2C_ICCR_RACK), &dev->iccr);
	196	readb(&dev->icdr); /* Dummy read */
	197	sh_irq_busy(dev);
3dab3e0e	198
0e5fb33c	199	exit0:
2035d77d	200	sh_i2c_finish(dev);
3dab3e0e NI	201
	202	return ret;
	203	}
	204
2035d77d NI	205	static void
2035d77d NI	206	sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
3dab3e0e NI	207	{
	208	int num, denom, tmp;
	209
b55b8eef NI	210	/* No i2c support prior to relocation */
	211	if (!(gd->flags & GD_FLG_RELOC))
	212	return;
	213
3dab3e0e NI	214	/*
	215	* Calculate the value for iccl. From the data sheet:
	216	* iccl = (p-clock / transfer-rate) * (L / (L + H))
	217	* where L and H are the SCL low and high ratio.
	218	*/
	219	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
	220	denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
	221	tmp = num * 10 / denom;
	222	if (tmp % 10 >= 5)
b1af67fe	223	iccl = (u16)((num/denom) + 1);
3dab3e0e	224	else
b1af67fe	225	iccl = (u16)(num/denom);
3dab3e0e NI	226
	227	/* Calculate the value for icch. From the data sheet:
	228	icch = (p clock / transfer rate) * (H / (L + H)) */
	229	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
	230	tmp = num * 10 / denom;
	231	if (tmp % 10 >= 5)
b1af67fe	232	icch = (u16)((num/denom) + 1);
3dab3e0e	233	else
b1af67fe	234	icch = (u16)(num/denom);
2035d77d NI	235
	236	debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
	237	CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
3dab3e0e NI	238	}
3dab3e0e NI	239
2035d77d NI	240	static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
2035d77d NI	241	uint addr, int alen, u8 *data, int len)
3dab3e0e	242	{
2035d77d NI	243	int ret, i;
	244	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	245
	246	for (i = 0; i < len; i++) {
	247	ret = sh_i2c_raw_read(dev, chip, addr + i);
0e5fb33c TK	248	if (ret < 0)
0e5fb33c TK	249	return -1;
2035d77d NI	250
	251	data[i] = ret & 0xff;
	252	debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
0e5fb33c	253	}
2035d77d	254
3dab3e0e NI	255	return 0;
	256	}
	257
2035d77d NI	258	static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
2035d77d NI	259	int alen, u8 *data, int len)
3dab3e0e	260	{
2035d77d NI	261	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	262	int i;
	263
	264	for (i = 0; i < len; i++) {
	265	debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
	266	if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
0e5fb33c	267	return -1;
2035d77d	268	}
3dab3e0e NI	269	return 0;
	270	}
	271
2035d77d NI	272	static int
2035d77d NI	273	sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
3dab3e0e	274	{
7a657689 TK	275	u8 dummy[1];
	276
	277	return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
2035d77d	278	}
d042d712	279
2035d77d NI	280	static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
	281	unsigned int speed)
	282	{
	283	struct sh_i2c dev = (struct sh_i2c )i2c_dev[adap->hwadapnr];
	284
	285	sh_i2c_finish(dev);
	286	sh_i2c_init(adap, speed, 0);
	287
	288	return 0;
3dab3e0e	289	}
2035d77d NI	290
	291	/*
	292	* Register RCAR i2c adapters
	293	*/
	294	U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	295	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
	296	#ifdef CONFIG_SYS_I2C_SH_BASE1
	297	U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	298	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
	299	#endif
	300	#ifdef CONFIG_SYS_I2C_SH_BASE2
	301	U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	302	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
	303	#endif
	304	#ifdef CONFIG_SYS_I2C_SH_BASE3
	305	U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	306	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
	307	#endif
	308	#ifdef CONFIG_SYS_I2C_SH_BASE4
	309	U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
	310	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
	311	#endif