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2d344a2a NI |
1 | /* |
2 | * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
3 | * Copyright (C) 2012 Renesas Solutions Corp. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
28527096 SG |
6 | * |
7 | * NOTE: This driver should be converted to driver model before June 2017. | |
8 | * Please see doc/driver-model/i2c-howto.txt for instructions. | |
2d344a2a NI |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <i2c.h> | |
13 | #include <asm/io.h> | |
14 | ||
15 | struct sh_i2c { | |
16 | u8 iccr1; | |
17 | u8 iccr2; | |
18 | u8 icmr; | |
19 | u8 icier; | |
20 | u8 icsr; | |
21 | u8 sar; | |
22 | u8 icdrt; | |
23 | u8 icdrr; | |
24 | u8 nf2cyc; | |
25 | u8 __pad0; | |
26 | u8 __pad1; | |
27 | }; | |
28 | ||
29 | static struct sh_i2c *base; | |
30 | static u8 iccr1_cks, nf2cyc; | |
31 | ||
32 | /* ICCR1 */ | |
33 | #define SH_I2C_ICCR1_ICE (1 << 7) | |
34 | #define SH_I2C_ICCR1_RCVD (1 << 6) | |
35 | #define SH_I2C_ICCR1_MST (1 << 5) | |
36 | #define SH_I2C_ICCR1_TRS (1 << 4) | |
37 | #define SH_I2C_ICCR1_MTRS \ | |
38 | (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS) | |
39 | ||
40 | /* ICCR1 */ | |
41 | #define SH_I2C_ICCR2_BBSY (1 << 7) | |
42 | #define SH_I2C_ICCR2_SCP (1 << 6) | |
43 | #define SH_I2C_ICCR2_SDAO (1 << 5) | |
44 | #define SH_I2C_ICCR2_SDAOP (1 << 4) | |
45 | #define SH_I2C_ICCR2_SCLO (1 << 3) | |
46 | #define SH_I2C_ICCR2_IICRST (1 << 1) | |
47 | ||
48 | #define SH_I2C_ICIER_TIE (1 << 7) | |
49 | #define SH_I2C_ICIER_TEIE (1 << 6) | |
50 | #define SH_I2C_ICIER_RIE (1 << 5) | |
51 | #define SH_I2C_ICIER_NAKIE (1 << 4) | |
52 | #define SH_I2C_ICIER_STIE (1 << 3) | |
53 | #define SH_I2C_ICIER_ACKE (1 << 2) | |
54 | #define SH_I2C_ICIER_ACKBR (1 << 1) | |
55 | #define SH_I2C_ICIER_ACKBT (1 << 0) | |
56 | ||
57 | #define SH_I2C_ICSR_TDRE (1 << 7) | |
58 | #define SH_I2C_ICSR_TEND (1 << 6) | |
59 | #define SH_I2C_ICSR_RDRF (1 << 5) | |
60 | #define SH_I2C_ICSR_NACKF (1 << 4) | |
61 | #define SH_I2C_ICSR_STOP (1 << 3) | |
62 | #define SH_I2C_ICSR_ALOVE (1 << 2) | |
63 | #define SH_I2C_ICSR_AAS (1 << 1) | |
64 | #define SH_I2C_ICSR_ADZ (1 << 0) | |
65 | ||
66 | #define IRQ_WAIT 1000 | |
67 | ||
68 | static void sh_i2c_send_stop(struct sh_i2c *base) | |
69 | { | |
70 | clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP); | |
71 | } | |
72 | ||
73 | static int check_icsr_bits(struct sh_i2c *base, u8 bits) | |
74 | { | |
75 | int i; | |
76 | ||
77 | for (i = 0; i < IRQ_WAIT; i++) { | |
78 | if (bits & readb(&base->icsr)) | |
79 | return 0; | |
80 | udelay(10); | |
81 | } | |
82 | ||
83 | return 1; | |
84 | } | |
85 | ||
86 | static int check_stop(struct sh_i2c *base) | |
87 | { | |
88 | int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP); | |
89 | clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); | |
90 | ||
91 | return ret; | |
92 | } | |
93 | ||
94 | static int check_tend(struct sh_i2c *base, int stop) | |
95 | { | |
96 | int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND); | |
97 | ||
98 | if (stop) { | |
99 | clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); | |
100 | sh_i2c_send_stop(base); | |
101 | } | |
102 | ||
103 | clrbits_8(&base->icsr, SH_I2C_ICSR_TEND); | |
104 | return ret; | |
105 | } | |
106 | ||
107 | static int check_tdre(struct sh_i2c *base) | |
108 | { | |
109 | return check_icsr_bits(base, SH_I2C_ICSR_TDRE); | |
110 | } | |
111 | ||
112 | static int check_rdrf(struct sh_i2c *base) | |
113 | { | |
114 | return check_icsr_bits(base, SH_I2C_ICSR_RDRF); | |
115 | } | |
116 | ||
117 | static int check_bbsy(struct sh_i2c *base) | |
118 | { | |
119 | int i; | |
120 | ||
121 | for (i = 0 ; i < IRQ_WAIT ; i++) { | |
122 | if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2))) | |
123 | return 0; | |
124 | udelay(10); | |
125 | } | |
126 | return 1; | |
127 | } | |
128 | ||
129 | static int check_ackbr(struct sh_i2c *base) | |
130 | { | |
131 | int i; | |
132 | ||
133 | for (i = 0 ; i < IRQ_WAIT ; i++) { | |
134 | if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier))) | |
135 | return 0; | |
136 | udelay(10); | |
137 | } | |
138 | ||
139 | return 1; | |
140 | } | |
141 | ||
142 | static void sh_i2c_reset(struct sh_i2c *base) | |
143 | { | |
144 | setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); | |
145 | ||
146 | udelay(100); | |
147 | ||
148 | clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); | |
149 | } | |
150 | ||
151 | static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg) | |
152 | { | |
153 | if (check_bbsy(base)) { | |
154 | puts("i2c bus busy\n"); | |
155 | goto fail; | |
156 | } | |
157 | ||
158 | setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); | |
159 | clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); | |
160 | ||
161 | writeb((id << 1), &base->icdrt); | |
162 | ||
163 | if (check_tend(base, 0)) { | |
164 | puts("TEND check fail...\n"); | |
165 | goto fail; | |
166 | } | |
167 | ||
168 | if (check_ackbr(base)) { | |
169 | check_tend(base, 0); | |
170 | sh_i2c_send_stop(base); | |
171 | goto fail; | |
172 | } | |
173 | ||
174 | writeb(reg, &base->icdrt); | |
175 | ||
176 | if (check_tdre(base)) { | |
177 | puts("TDRE check fail...\n"); | |
178 | goto fail; | |
179 | } | |
180 | ||
181 | if (check_tend(base, 0)) { | |
182 | puts("TEND check fail...\n"); | |
183 | goto fail; | |
184 | } | |
185 | ||
186 | return 0; | |
187 | fail: | |
188 | ||
189 | return 1; | |
190 | } | |
191 | ||
192 | static int | |
193 | i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size) | |
194 | { | |
195 | int i; | |
196 | ||
197 | if (i2c_set_addr(base, id, reg)) { | |
198 | puts("Fail set slave address\n"); | |
199 | return 1; | |
200 | } | |
201 | ||
202 | for (i = 0; i < size; i++) { | |
203 | writeb(val[i], &base->icdrt); | |
204 | check_tdre(base); | |
205 | } | |
206 | ||
207 | check_tend(base, 1); | |
208 | check_stop(base); | |
209 | ||
210 | udelay(100); | |
211 | ||
212 | clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); | |
213 | clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); | |
214 | sh_i2c_reset(base); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) | |
220 | { | |
221 | u8 ret = 0; | |
222 | ||
223 | if (i2c_set_addr(base, id, reg)) { | |
224 | puts("Fail set slave address\n"); | |
225 | goto fail; | |
226 | } | |
227 | ||
228 | clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); | |
229 | writeb((id << 1) | 1, &base->icdrt); | |
230 | ||
231 | if (check_tend(base, 0)) | |
232 | puts("TDRE check fail...\n"); | |
233 | ||
234 | clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST); | |
235 | clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); | |
236 | setbits_8(&base->icier, SH_I2C_ICIER_ACKBT); | |
237 | setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); | |
238 | ||
239 | /* read data (dummy) */ | |
240 | ret = readb(&base->icdrr); | |
241 | ||
242 | if (check_rdrf(base)) { | |
243 | puts("check RDRF error\n"); | |
244 | goto fail; | |
245 | } | |
246 | ||
247 | clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); | |
248 | udelay(1000); | |
249 | ||
250 | sh_i2c_send_stop(base); | |
251 | ||
252 | if (check_stop(base)) { | |
253 | puts("check STOP error\n"); | |
254 | goto fail; | |
255 | } | |
256 | ||
257 | clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); | |
258 | clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); | |
259 | ||
260 | /* data read */ | |
261 | ret = readb(&base->icdrr); | |
262 | ||
263 | fail: | |
264 | clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); | |
265 | ||
266 | return ret; | |
267 | } | |
268 | ||
269 | #ifdef CONFIG_I2C_MULTI_BUS | |
270 | static unsigned int current_bus; | |
271 | ||
272 | /** | |
273 | * i2c_set_bus_num - change active I2C bus | |
274 | * @bus: bus index, zero based | |
275 | * @returns: 0 on success, non-0 on failure | |
276 | */ | |
277 | int i2c_set_bus_num(unsigned int bus) | |
278 | { | |
279 | switch (bus) { | |
280 | case 0: | |
281 | base = (void *)CONFIG_SH_I2C_BASE0; | |
282 | break; | |
283 | case 1: | |
284 | base = (void *)CONFIG_SH_I2C_BASE1; | |
285 | break; | |
286 | default: | |
287 | printf("Bad bus: %d\n", bus); | |
288 | return -1; | |
289 | } | |
290 | ||
291 | current_bus = bus; | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | /** | |
297 | * i2c_get_bus_num - returns index of active I2C bus | |
298 | */ | |
299 | unsigned int i2c_get_bus_num(void) | |
300 | { | |
301 | return current_bus; | |
302 | } | |
303 | #endif | |
304 | ||
305 | void i2c_init(int speed, int slaveaddr) | |
306 | { | |
307 | #ifdef CONFIG_I2C_MULTI_BUS | |
308 | current_bus = 0; | |
309 | #endif | |
310 | base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; | |
311 | ||
312 | if (speed == 400000) | |
313 | iccr1_cks = 0x07; | |
314 | else | |
315 | iccr1_cks = 0x0F; | |
316 | ||
317 | nf2cyc = 1; | |
318 | ||
319 | /* Reset */ | |
320 | sh_i2c_reset(base); | |
321 | ||
322 | /* ICE enable and set clock */ | |
323 | writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1); | |
324 | writeb(nf2cyc, &base->nf2cyc); | |
325 | } | |
326 | ||
327 | /* | |
328 | * i2c_read: - Read multiple bytes from an i2c device | |
329 | * | |
330 | * The higher level routines take into account that this function is only | |
331 | * called with len < page length of the device (see configuration file) | |
332 | * | |
333 | * @chip: address of the chip which is to be read | |
334 | * @addr: i2c data address within the chip | |
335 | * @alen: length of the i2c data address (1..2 bytes) | |
336 | * @buffer: where to write the data | |
337 | * @len: how much byte do we want to read | |
338 | * @return: 0 in case of success | |
339 | */ | |
340 | int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) | |
341 | { | |
342 | int i = 0; | |
343 | for (i = 0; i < len; i++) | |
344 | buffer[i] = i2c_raw_read(base, chip, addr + i); | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | /* | |
350 | * i2c_write: - Write multiple bytes to an i2c device | |
351 | * | |
352 | * The higher level routines take into account that this function is only | |
353 | * called with len < page length of the device (see configuration file) | |
354 | * | |
355 | * @chip: address of the chip which is to be written | |
356 | * @addr: i2c data address within the chip | |
357 | * @alen: length of the i2c data address (1..2 bytes) | |
358 | * @buffer: where to find the data to be written | |
359 | * @len: how much byte do we want to read | |
360 | * @return: 0 in case of success | |
361 | */ | |
362 | int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) | |
363 | { | |
364 | return i2c_raw_write(base, chip, addr, buffer, len); | |
365 | } | |
366 | ||
367 | /* | |
368 | * i2c_probe: - Test if a chip answers for a given i2c address | |
369 | * | |
370 | * @chip: address of the chip which is searched for | |
371 | * @return: 0 if a chip was found, -1 otherwhise | |
372 | */ | |
373 | int i2c_probe(u8 chip) | |
374 | { | |
375 | u8 byte; | |
376 | return i2c_read(chip, 0, 0, &byte, 1); | |
377 | } |