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Merge git://git.denx.de/u-boot-i2c
[people/ms/u-boot.git] / drivers / i2c / soft_i2c.c
CommitLineData
c609719b 1/*
ea818dbb
HS		 2 * (C) Copyright 2009
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 * Changes for multibus/multiadapter I2C support.
5 *
c609719b
WD		 6 * (C) Copyright 2001, 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
c609719b
WD		 10 *
11 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
12 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
13 * Neil Russell.
28527096
SG		 14 *
15 * NOTE: This driver should be converted to driver model before June 2017.
16 * Please see doc/driver-model/i2c-howto.txt for instructions.
c609719b
WD		 17 */
18
19#include <common.h>
f3100ff7 20#if defined(CONFIG_AT91FAMILY)
9d5028c2
WD		 21#include <asm/io.h>
22#include <asm/arch/hardware.h>
0cf0b931 23#include <asm/arch/at91_pio.h>
cb96a0a4 24#ifdef CONFIG_ATMEL_LEGACY
4e574c4e 25#include <asm/arch/gpio.h>
0cf0b931 26#endif
4e574c4e 27#endif
b1e41d1c 28#if defined(CONFIG_8xx)
a21ca95f
HS		 29#include <asm/io.h>
30#endif
c609719b
WD		 31#include <i2c.h>
32
793b5726
MF		 33#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
34# include <asm/gpio.h>
35
36# ifndef I2C_GPIO_SYNC
37# define I2C_GPIO_SYNC
38# endif
39
40# ifndef I2C_INIT
41# define I2C_INIT \
42 do { \
43 gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
44 gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
45 } while (0)
46# endif
47
48# ifndef I2C_ACTIVE
49# define I2C_ACTIVE do { } while (0)
50# endif
51
52# ifndef I2C_TRISTATE
53# define I2C_TRISTATE do { } while (0)
54# endif
55
56# ifndef I2C_READ
57# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
58# endif
59
60# ifndef I2C_SDA
61# define I2C_SDA(bit) \
62 do { \
63 if (bit) \
64 gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
65 else \
66 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
67 I2C_GPIO_SYNC; \
68 } while (0)
69# endif
70
71# ifndef I2C_SCL
72# define I2C_SCL(bit) \
73 do { \
74 gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
75 I2C_GPIO_SYNC; \
76 } while (0)
77# endif
78
79# ifndef I2C_DELAY
80# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
81# endif
82
83#endif
84
c609719b
WD		 85/* #define DEBUG_I2C */
86
d87080b7 87DECLARE_GLOBAL_DATA_PTR;
ea818dbb
HS		 88
89#ifndef I2C_SOFT_DECLARATIONS
ea818dbb 90# define I2C_SOFT_DECLARATIONS
ea818dbb
HS		 91#endif
92
90f002a9
MV		 93#if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
94#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
ea818dbb 95#endif
90f002a9
MV		 96#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
97#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
d87080b7
WD		 98#endif
99
c609719b
WD		 100/*-----------------------------------------------------------------------
101 * Definitions
102 */
c609719b
WD		 103#define RETRIES 0
104
c609719b
WD		 105#define I2C_ACK 0 /* PD_SDA level to ack a byte */
106#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
107
108
109#ifdef DEBUG_I2C
110#define PRINTD(fmt,args...) do { \
c609719b
WD		 111 printf (fmt ,##args); \
112 } while (0)
113#else
114#define PRINTD(fmt,args...)
115#endif
116
117/*-----------------------------------------------------------------------
118 * Local functions
119 */
6d0f6bcf 120#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
c609719b 121static void send_reset (void);
4ca107ef 122#endif
c609719b
WD		 123static void send_start (void);
124static void send_stop (void);
125static void send_ack (int);
126static int write_byte (uchar byte);
127static uchar read_byte (int);
128
6d0f6bcf 129#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
c609719b
WD		 130/*-----------------------------------------------------------------------
131 * Send a reset sequence consisting of 9 clocks with the data signal high
132 * to clock any confused device back into an idle state. Also send a
133 * <stop> at the end of the sequence for belts & suspenders.
134 */
135static void send_reset(void)
136{
98aed379 137 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b
WD		 138 int j;
139
60fbe254 140 I2C_SCL(1);
c609719b 141 I2C_SDA(1);
60fbe254
WD		 142#ifdef I2C_INIT
143 I2C_INIT;
144#endif
145 I2C_TRISTATE;
c609719b
WD		 146 for(j = 0; j < 9; j++) {
147 I2C_SCL(0);
148 I2C_DELAY;
149 I2C_DELAY;
150 I2C_SCL(1);
151 I2C_DELAY;
152 I2C_DELAY;
153 }
154 send_stop();
155 I2C_TRISTATE;
156}
4ca107ef 157#endif
c609719b
WD		 158
159/*-----------------------------------------------------------------------
160 * START: High -> Low on SDA while SCL is High
161 */
162static void send_start(void)
163{
98aed379 164 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b
WD		 165
166 I2C_DELAY;
167 I2C_SDA(1);
168 I2C_ACTIVE;
169 I2C_DELAY;
170 I2C_SCL(1);
171 I2C_DELAY;
172 I2C_SDA(0);
173 I2C_DELAY;
174}
175
176/*-----------------------------------------------------------------------
177 * STOP: Low -> High on SDA while SCL is High
178 */
179static void send_stop(void)
180{
98aed379 181 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b
WD		 182
183 I2C_SCL(0);
184 I2C_DELAY;
185 I2C_SDA(0);
186 I2C_ACTIVE;
187 I2C_DELAY;
188 I2C_SCL(1);
189 I2C_DELAY;
190 I2C_SDA(1);
191 I2C_DELAY;
192 I2C_TRISTATE;
193}
194
c609719b
WD		 195/*-----------------------------------------------------------------------
196 * ack should be I2C_ACK or I2C_NOACK
197 */
198static void send_ack(int ack)
199{
98aed379 200 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b 201
c609719b
WD		 202 I2C_SCL(0);
203 I2C_DELAY;
c609719b 204 I2C_ACTIVE;
c15f80ea 205 I2C_SDA(ack);
c609719b
WD		 206 I2C_DELAY;
207 I2C_SCL(1);
208 I2C_DELAY;
209 I2C_DELAY;
210 I2C_SCL(0);
211 I2C_DELAY;
212}
213
c609719b
WD		 214/*-----------------------------------------------------------------------
215 * Send 8 bits and look for an acknowledgement.
216 */
217static int write_byte(uchar data)
218{
98aed379 219 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b
WD		 220 int j;
221 int nack;
222
223 I2C_ACTIVE;
224 for(j = 0; j < 8; j++) {
225 I2C_SCL(0);
226 I2C_DELAY;
227 I2C_SDA(data & 0x80);
228 I2C_DELAY;
229 I2C_SCL(1);
230 I2C_DELAY;
231 I2C_DELAY;
232
233 data <<= 1;
234 }
235
236 /*
237 * Look for an <ACK>(negative logic) and return it.
238 */
239 I2C_SCL(0);
240 I2C_DELAY;
241 I2C_SDA(1);
242 I2C_TRISTATE;
243 I2C_DELAY;
244 I2C_SCL(1);
245 I2C_DELAY;
246 I2C_DELAY;
247 nack = I2C_READ;
248 I2C_SCL(0);
249 I2C_DELAY;
250 I2C_ACTIVE;
251
252 return(nack); /* not a nack is an ack */
253}
254
c609719b
WD		 255/*-----------------------------------------------------------------------
256 * if ack == I2C_ACK, ACK the byte so can continue reading, else
257 * send I2C_NOACK to end the read.
258 */
259static uchar read_byte(int ack)
260{
98aed379 261 I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b
WD		 262 int data;
263 int j;
264
265 /*
266 * Read 8 bits, MSB first.
267 */
268 I2C_TRISTATE;
110e006f 269 I2C_SDA(1);
c609719b
WD		 270 data = 0;
271 for(j = 0; j < 8; j++) {
272 I2C_SCL(0);
273 I2C_DELAY;
274 I2C_SCL(1);
275 I2C_DELAY;
276 data <<= 1;
277 data |= I2C_READ;
278 I2C_DELAY;
279 }
280 send_ack(ack);
281
282 return(data);
283}
284
c609719b
WD		 285/*-----------------------------------------------------------------------
286 * Initialization
287 */
ea818dbb 288static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
c609719b 289{
6d0f6bcf 290#if defined(CONFIG_SYS_I2C_INIT_BOARD)
4ca107ef
HS		 291 /* call board specific i2c bus reset routine before accessing the */
292 /* environment, which might be in a chip on that bus. For details */
293 /* about this problem see doc/I2C_Edge_Conditions. */
294 i2c_init_board();
295#else
c609719b 296 /*
8bde7f77
WD		 297 * WARNING: Do NOT save speed in a static variable: if the
298 * I2C routines are called before RAM is initialized (to read
299 * the DIMM SPD, for instance), RAM won't be usable and your
300 * system will crash.
c609719b
WD		 301 */
302 send_reset ();
4ca107ef 303#endif
c609719b
WD		 304}
305
306/*-----------------------------------------------------------------------
307 * Probe to see if a chip is present. Also good for checking for the
308 * completion of EEPROM writes since the chip stops responding until
309 * the write completes (typically 10mSec).
310 */
ea818dbb 311static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
c609719b
WD		 312{
313 int rc;
314
82d716fd 315 /*
8e7b703a 316 * perform 1 byte write transaction with just address byte
82d716fd
WD		 317 * (fake write)
318 */
c609719b 319 send_start();
6aff3115 320 rc = write_byte ((addr << 1) | 0);
c609719b
WD		 321 send_stop();
322
323 return (rc ? 1 : 0);
324}
325
326/*-----------------------------------------------------------------------
327 * Read bytes
328 */
ea818dbb
HS		 329static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
330 int alen, uchar *buffer, int len)
c609719b
WD		 331{
332 int shift;
333 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
334 chip, addr, alen, buffer, len);
335
6d0f6bcf 336#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
c609719b
WD		 337 /*
338 * EEPROM chips that implement "address overflow" are ones
339 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
340 * address and the extra bits end up in the "chip address"
341 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
342 * four 256 byte chips.
343 *
344 * Note that we consider the length of the address field to
345 * still be one byte because the extra address bits are
346 * hidden in the chip address.
347 */
6d0f6bcf 348 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
c609719b
WD		 349
350 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
351 chip, addr);
352#endif
353
354 /*
355 * Do the addressing portion of a write cycle to set the
356 * chip's address pointer. If the address length is zero,
357 * don't do the normal write cycle to set the address pointer,
358 * there is no address pointer in this chip.
359 */
360 send_start();
361 if(alen > 0) {
362 if(write_byte(chip << 1)) { /* write cycle */
363 send_stop();
364 PRINTD("i2c_read, no chip responded %02X\n", chip);
365 return(1);
366 }
367 shift = (alen-1) * 8;
368 while(alen-- > 0) {
369 if(write_byte(addr >> shift)) {
370 PRINTD("i2c_read, address not <ACK>ed\n");
371 return(1);
372 }
373 shift -= 8;
374 }
2ac6985a
AD		 375
376 /* Some I2C chips need a stop/start sequence here,
377 * other chips don't work with a full stop and need
378 * only a start. Default behaviour is to send the
379 * stop/start sequence.
380 */
381#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
382 send_start();
383#else
384 send_stop();
c609719b 385 send_start();
2ac6985a 386#endif
c609719b
WD		 387 }
388 /*
389 * Send the chip address again, this time for a read cycle.
390 * Then read the data. On the last byte, we do a NACK instead
391 * of an ACK(len == 0) to terminate the read.
392 */
393 write_byte((chip << 1) | 1); /* read cycle */
394 while(len-- > 0) {
395 *buffer++ = read_byte(len == 0);
396 }
397 send_stop();
398 return(0);
399}
400
401/*-----------------------------------------------------------------------
402 * Write bytes
403 */
ea818dbb
HS		 404static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
405 int alen, uchar *buffer, int len)
c609719b
WD		 406{
407 int shift, failures = 0;
408
409 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
410 chip, addr, alen, buffer, len);
411
412 send_start();
413 if(write_byte(chip << 1)) { /* write cycle */
414 send_stop();
415 PRINTD("i2c_write, no chip responded %02X\n", chip);
416 return(1);
417 }
418 shift = (alen-1) * 8;
419 while(alen-- > 0) {
420 if(write_byte(addr >> shift)) {
421 PRINTD("i2c_write, address not <ACK>ed\n");
422 return(1);
423 }
424 shift -= 8;
425 }
426
427 while(len-- > 0) {
428 if(write_byte(*buffer++)) {
429 failures++;
430 }
431 }
432 send_stop();
433 return(failures);
434}
ea818dbb
HS		 435
436/*
437 * Register soft i2c adapters
438 */
37b33254 439U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
ea818dbb
HS		 440 soft_i2c_read, soft_i2c_write, NULL,
441 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
442 0)
443#if defined(I2C_SOFT_DECLARATIONS2)
37b33254 444U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
ea818dbb
HS		 445 soft_i2c_read, soft_i2c_write, NULL,
446 CONFIG_SYS_I2C_SOFT_SPEED_2,
447 CONFIG_SYS_I2C_SOFT_SLAVE_2,
448 1)
449#endif
450#if defined(I2C_SOFT_DECLARATIONS3)
37b33254 451U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
ea818dbb
HS		 452 soft_i2c_read, soft_i2c_write, NULL,
453 CONFIG_SYS_I2C_SOFT_SPEED_3,
454 CONFIG_SYS_I2C_SOFT_SLAVE_3,
455 2)
456#endif
457#if defined(I2C_SOFT_DECLARATIONS4)
37b33254 458U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
ea818dbb
HS		 459 soft_i2c_read, soft_i2c_write, NULL,
460 CONFIG_SYS_I2C_SOFT_SPEED_4,
461 CONFIG_SYS_I2C_SOFT_SLAVE_4,
462 3)
463#endif
7ed45d3d 464#if defined(I2C_SOFT_DECLARATIONS5)
37b33254 465U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
7ed45d3d
DE		 466 soft_i2c_read, soft_i2c_write, NULL,
467 CONFIG_SYS_I2C_SOFT_SPEED_5,
468 CONFIG_SYS_I2C_SOFT_SLAVE_5,
469 4)
470#endif
471#if defined(I2C_SOFT_DECLARATIONS6)
37b33254 472U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
7ed45d3d
DE		 473 soft_i2c_read, soft_i2c_write, NULL,
474 CONFIG_SYS_I2C_SOFT_SPEED_6,
475 CONFIG_SYS_I2C_SOFT_SLAVE_6,
476 5)
477#endif
478#if defined(I2C_SOFT_DECLARATIONS7)
37b33254 479U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
7ed45d3d
DE		 480 soft_i2c_read, soft_i2c_write, NULL,
481 CONFIG_SYS_I2C_SOFT_SPEED_7,
482 CONFIG_SYS_I2C_SOFT_SLAVE_7,
483 6)
484#endif
485#if defined(I2C_SOFT_DECLARATIONS8)
37b33254 486U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
7ed45d3d
DE		 487 soft_i2c_read, soft_i2c_write, NULL,
488 CONFIG_SYS_I2C_SOFT_SPEED_8,
489 CONFIG_SYS_I2C_SOFT_SLAVE_8,
490 7)
491#endif
5c3b6dc1 492#if defined(I2C_SOFT_DECLARATIONS9)
37b33254 493U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
5c3b6dc1
DE		 494 soft_i2c_read, soft_i2c_write, NULL,
495 CONFIG_SYS_I2C_SOFT_SPEED_9,
496 CONFIG_SYS_I2C_SOFT_SLAVE_9,
497 8)
498#endif
499#if defined(I2C_SOFT_DECLARATIONS10)
37b33254 500U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
5c3b6dc1
DE		 501 soft_i2c_read, soft_i2c_write, NULL,
502 CONFIG_SYS_I2C_SOFT_SPEED_10,
503 CONFIG_SYS_I2C_SOFT_SLAVE_10,
504 9)
505#endif
506#if defined(I2C_SOFT_DECLARATIONS11)
507U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
508 soft_i2c_read, soft_i2c_write, NULL,
509 CONFIG_SYS_I2C_SOFT_SPEED_11,
510 CONFIG_SYS_I2C_SOFT_SLAVE_11,
511 10)
512#endif
513#if defined(I2C_SOFT_DECLARATIONS12)
514U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
515 soft_i2c_read, soft_i2c_write, NULL,
516 CONFIG_SYS_I2C_SOFT_SPEED_12,
517 CONFIG_SYS_I2C_SOFT_SLAVE_12,
518 11)
519#endif
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