[people/ms/u-boot.git] / drivers / i2c / soft_i2c.c

/*
 * (C) Copyright 2009
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 * Changes for multibus/multiadapter I2C support.
 *
 * (C) Copyright 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
 * vanbaren@cideas.com.  It was heavily influenced by LiMon, written by
 * Neil Russell.
 *
 * NOTE: This driver should be converted to driver model before June 2017.
 * Please see doc/driver-model/i2c-howto.txt for instructions.
 */

#include <common.h>
#ifdef	CONFIG_MPC8260			/* only valid for MPC8260 */
#include <ioports.h>
#include <asm/io.h>
#endif
#if defined(CONFIG_AT91FAMILY)
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/gpio.h>
#endif
#endif
#if defined(CONFIG_8xx)
#include <asm/io.h>
#endif
#include <i2c.h>

#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
# include <asm/gpio.h>

# ifndef I2C_GPIO_SYNC
#  define I2C_GPIO_SYNC
# endif

# ifndef I2C_INIT
#  define I2C_INIT \
	do { \
		gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
		gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
	} while (0)
# endif

# ifndef I2C_ACTIVE
#  define I2C_ACTIVE do { } while (0)
# endif

# ifndef I2C_TRISTATE
#  define I2C_TRISTATE do { } while (0)
# endif

# ifndef I2C_READ
#  define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
# endif

# ifndef I2C_SDA
#  define I2C_SDA(bit) \
	do { \
		if (bit) \
			gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
		else \
			gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
		I2C_GPIO_SYNC; \
	} while (0)
# endif

# ifndef I2C_SCL
#  define I2C_SCL(bit) \
	do { \
		gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
		I2C_GPIO_SYNC; \
	} while (0)
# endif

# ifndef I2C_DELAY
#  define I2C_DELAY udelay(5)	/* 1/4 I2C clock duration */
# endif

#endif

/* #define	DEBUG_I2C	*/

DECLARE_GLOBAL_DATA_PTR;

#ifndef	I2C_SOFT_DECLARATIONS
#  define I2C_SOFT_DECLARATIONS
#endif

#if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
#endif
#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
#endif

/*-----------------------------------------------------------------------
 * Definitions
 */
#define RETRIES		0

#define I2C_ACK		0		/* PD_SDA level to ack a byte */
#define I2C_NOACK	1		/* PD_SDA level to noack a byte */


#ifdef DEBUG_I2C
#define PRINTD(fmt,args...)	do {	\
		printf (fmt ,##args);	\
	} while (0)
#else
#define PRINTD(fmt,args...)
#endif

/*-----------------------------------------------------------------------
 * Local functions
 */
#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
static void  send_reset	(void);
#endif
static void  send_start	(void);
static void  send_stop	(void);
static void  send_ack	(int);
static int   write_byte	(uchar byte);
static uchar read_byte	(int);

#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
/*-----------------------------------------------------------------------
 * Send a reset sequence consisting of 9 clocks with the data signal high
 * to clock any confused device back into an idle state.  Also send a
 * <stop> at the end of the sequence for belts & suspenders.
 */
static void send_reset(void)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */
	int j;

	I2C_SCL(1);
	I2C_SDA(1);
#ifdef	I2C_INIT
	I2C_INIT;
#endif
	I2C_TRISTATE;
	for(j = 0; j < 9; j++) {
		I2C_SCL(0);
		I2C_DELAY;
		I2C_DELAY;
		I2C_SCL(1);
		I2C_DELAY;
		I2C_DELAY;
	}
	send_stop();
	I2C_TRISTATE;
}
#endif

/*-----------------------------------------------------------------------
 * START: High -> Low on SDA while SCL is High
 */
static void send_start(void)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */

	I2C_DELAY;
	I2C_SDA(1);
	I2C_ACTIVE;
	I2C_DELAY;
	I2C_SCL(1);
	I2C_DELAY;
	I2C_SDA(0);
	I2C_DELAY;
}

/*-----------------------------------------------------------------------
 * STOP: Low -> High on SDA while SCL is High
 */
static void send_stop(void)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */

	I2C_SCL(0);
	I2C_DELAY;
	I2C_SDA(0);
	I2C_ACTIVE;
	I2C_DELAY;
	I2C_SCL(1);
	I2C_DELAY;
	I2C_SDA(1);
	I2C_DELAY;
	I2C_TRISTATE;
}

/*-----------------------------------------------------------------------
 * ack should be I2C_ACK or I2C_NOACK
 */
static void send_ack(int ack)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */

	I2C_SCL(0);
	I2C_DELAY;
	I2C_ACTIVE;
	I2C_SDA(ack);
	I2C_DELAY;
	I2C_SCL(1);
	I2C_DELAY;
	I2C_DELAY;
	I2C_SCL(0);
	I2C_DELAY;
}

/*-----------------------------------------------------------------------
 * Send 8 bits and look for an acknowledgement.
 */
static int write_byte(uchar data)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */
	int j;
	int nack;

	I2C_ACTIVE;
	for(j = 0; j < 8; j++) {
		I2C_SCL(0);
		I2C_DELAY;
		I2C_SDA(data & 0x80);
		I2C_DELAY;
		I2C_SCL(1);
		I2C_DELAY;
		I2C_DELAY;

		data <<= 1;
	}

	/*
	 * Look for an <ACK>(negative logic) and return it.
	 */
	I2C_SCL(0);
	I2C_DELAY;
	I2C_SDA(1);
	I2C_TRISTATE;
	I2C_DELAY;
	I2C_SCL(1);
	I2C_DELAY;
	I2C_DELAY;
	nack = I2C_READ;
	I2C_SCL(0);
	I2C_DELAY;
	I2C_ACTIVE;

	return(nack);	/* not a nack is an ack */
}

/*-----------------------------------------------------------------------
 * if ack == I2C_ACK, ACK the byte so can continue reading, else
 * send I2C_NOACK to end the read.
 */
static uchar read_byte(int ack)
{
	I2C_SOFT_DECLARATIONS	/* intentional without ';' */
	int  data;
	int  j;

	/*
	 * Read 8 bits, MSB first.
	 */
	I2C_TRISTATE;
	I2C_SDA(1);
	data = 0;
	for(j = 0; j < 8; j++) {
		I2C_SCL(0);
		I2C_DELAY;
		I2C_SCL(1);
		I2C_DELAY;
		data <<= 1;
		data |= I2C_READ;
		I2C_DELAY;
	}
	send_ack(ack);

	return(data);
}

/*-----------------------------------------------------------------------
 * Initialization
 */
static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
#if defined(CONFIG_SYS_I2C_INIT_BOARD)
	/* call board specific i2c bus reset routine before accessing the   */
	/* environment, which might be in a chip on that bus. For details   */
	/* about this problem see doc/I2C_Edge_Conditions.                  */
	i2c_init_board();
#else
	/*
	 * WARNING: Do NOT save speed in a static variable: if the
	 * I2C routines are called before RAM is initialized (to read
	 * the DIMM SPD, for instance), RAM won't be usable and your
	 * system will crash.
	 */
	send_reset ();
#endif
}

/*-----------------------------------------------------------------------
 * Probe to see if a chip is present.  Also good for checking for the
 * completion of EEPROM writes since the chip stops responding until
 * the write completes (typically 10mSec).
 */
static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
{
	int rc;

	/*
	 * perform 1 byte write transaction with just address byte
	 * (fake write)
	 */
	send_start();
	rc = write_byte ((addr << 1) | 0);
	send_stop();

	return (rc ? 1 : 0);
}

/*-----------------------------------------------------------------------
 * Read bytes
 */
static int  soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *buffer, int len)
{
	int shift;
	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
		chip, addr, alen, buffer, len);

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);

	PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
		chip, addr);
#endif

	/*
	 * Do the addressing portion of a write cycle to set the
	 * chip's address pointer.  If the address length is zero,
	 * don't do the normal write cycle to set the address pointer,
	 * there is no address pointer in this chip.
	 */
	send_start();
	if(alen > 0) {
		if(write_byte(chip << 1)) {	/* write cycle */
			send_stop();
			PRINTD("i2c_read, no chip responded %02X\n", chip);
			return(1);
		}
		shift = (alen-1) * 8;
		while(alen-- > 0) {
			if(write_byte(addr >> shift)) {
				PRINTD("i2c_read, address not <ACK>ed\n");
				return(1);
			}
			shift -= 8;
		}

		/* Some I2C chips need a stop/start sequence here,
		 * other chips don't work with a full stop and need
		 * only a start.  Default behaviour is to send the
		 * stop/start sequence.
		 */
#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
		send_start();
#else
		send_stop();
		send_start();
#endif
	}
	/*
	 * Send the chip address again, this time for a read cycle.
	 * Then read the data.  On the last byte, we do a NACK instead
	 * of an ACK(len == 0) to terminate the read.
	 */
	write_byte((chip << 1) | 1);	/* read cycle */
	while(len-- > 0) {
		*buffer++ = read_byte(len == 0);
	}
	send_stop();
	return(0);
}

/*-----------------------------------------------------------------------
 * Write bytes
 */
static int  soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
			int alen, uchar *buffer, int len)
{
	int shift, failures = 0;

	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
		chip, addr, alen, buffer, len);

	send_start();
	if(write_byte(chip << 1)) {	/* write cycle */
		send_stop();
		PRINTD("i2c_write, no chip responded %02X\n", chip);
		return(1);
	}
	shift = (alen-1) * 8;
	while(alen-- > 0) {
		if(write_byte(addr >> shift)) {
			PRINTD("i2c_write, address not <ACK>ed\n");
			return(1);
		}
		shift -= 8;
	}

	while(len-- > 0) {
		if(write_byte(*buffer++)) {
			failures++;
		}
	}
	send_stop();
	return(failures);
}

/*
 * Register soft i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
			 0)
#if defined(I2C_SOFT_DECLARATIONS2)
U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_2,
			 CONFIG_SYS_I2C_SOFT_SLAVE_2,
			 1)
#endif
#if defined(I2C_SOFT_DECLARATIONS3)
U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_3,
			 CONFIG_SYS_I2C_SOFT_SLAVE_3,
			 2)
#endif
#if defined(I2C_SOFT_DECLARATIONS4)
U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_4,
			 CONFIG_SYS_I2C_SOFT_SLAVE_4,
			 3)
#endif
#if defined(I2C_SOFT_DECLARATIONS5)
U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_5,
			 CONFIG_SYS_I2C_SOFT_SLAVE_5,
			 4)
#endif
#if defined(I2C_SOFT_DECLARATIONS6)
U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_6,
			 CONFIG_SYS_I2C_SOFT_SLAVE_6,
			 5)
#endif
#if defined(I2C_SOFT_DECLARATIONS7)
U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_7,
			 CONFIG_SYS_I2C_SOFT_SLAVE_7,
			 6)
#endif
#if defined(I2C_SOFT_DECLARATIONS8)
U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_8,
			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
			 7)
#endif
#if defined(I2C_SOFT_DECLARATIONS9)
U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_9,
			 CONFIG_SYS_I2C_SOFT_SLAVE_9,
			 8)
#endif
#if defined(I2C_SOFT_DECLARATIONS10)
U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_10,
			 CONFIG_SYS_I2C_SOFT_SLAVE_10,
			 9)
#endif
#if defined(I2C_SOFT_DECLARATIONS11)
U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_11,
			 CONFIG_SYS_I2C_SOFT_SLAVE_11,
			 10)
#endif
#if defined(I2C_SOFT_DECLARATIONS12)
U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
			 soft_i2c_read, soft_i2c_write, NULL,
			 CONFIG_SYS_I2C_SOFT_SPEED_12,
			 CONFIG_SYS_I2C_SOFT_SLAVE_12,
			 11)
#endif
Commit	Line	Data
c609719b	1	/*
ea818dbb HS	2	* (C) Copyright 2009
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	* Changes for multibus/multiadapter I2C support.
	5	*
c609719b WD	6	* (C) Copyright 2001, 2002
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	10	*
	11	* This has been changed substantially by Gerald Van Baren, Custom IDEAS,
	12	* vanbaren@cideas.com. It was heavily influenced by LiMon, written by
	13	* Neil Russell.
28527096 SG	14	*
	15	* NOTE: This driver should be converted to driver model before June 2017.
	16	* Please see doc/driver-model/i2c-howto.txt for instructions.
c609719b WD	17	*/
	18
	19	#include <common.h>
daab59ac AS	20	#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
	21	#include <ioports.h>
	22	#include <asm/io.h>
eabd5d8d	23	#endif
f3100ff7	24	#if defined(CONFIG_AT91FAMILY)
9d5028c2 WD	25	#include <asm/io.h>
9d5028c2 WD	26	#include <asm/arch/hardware.h>
0cf0b931	27	#include <asm/arch/at91_pio.h>
cb96a0a4	28	#ifdef CONFIG_ATMEL_LEGACY
4e574c4e	29	#include <asm/arch/gpio.h>
0cf0b931	30	#endif
4e574c4e	31	#endif
b1e41d1c	32	#if defined(CONFIG_8xx)
a21ca95f HS	33	#include <asm/io.h>
a21ca95f HS	34	#endif
c609719b WD	35	#include <i2c.h>
c609719b WD	36
793b5726 MF	37	#if defined(CONFIG_SOFT_I2C_GPIO_SCL)
	38	# include <asm/gpio.h>
	39
	40	# ifndef I2C_GPIO_SYNC
	41	# define I2C_GPIO_SYNC
	42	# endif
	43
	44	# ifndef I2C_INIT
	45	# define I2C_INIT \
	46	do { \
	47	gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \
	48	gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \
	49	} while (0)
	50	# endif
	51
	52	# ifndef I2C_ACTIVE
	53	# define I2C_ACTIVE do { } while (0)
	54	# endif
	55
	56	# ifndef I2C_TRISTATE
	57	# define I2C_TRISTATE do { } while (0)
	58	# endif
	59
	60	# ifndef I2C_READ
	61	# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA)
	62	# endif
	63
	64	# ifndef I2C_SDA
	65	# define I2C_SDA(bit) \
	66	do { \
	67	if (bit) \
	68	gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \
	69	else \
	70	gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \
	71	I2C_GPIO_SYNC; \
	72	} while (0)
	73	# endif
	74
	75	# ifndef I2C_SCL
	76	# define I2C_SCL(bit) \
	77	do { \
	78	gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \
	79	I2C_GPIO_SYNC; \
	80	} while (0)
	81	# endif
	82
	83	# ifndef I2C_DELAY
	84	# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	85	# endif
	86
	87	#endif
	88
c609719b WD	89	/* #define DEBUG_I2C */
c609719b WD	90
d87080b7	91	DECLARE_GLOBAL_DATA_PTR;
ea818dbb HS	92
ea818dbb HS	93	#ifndef I2C_SOFT_DECLARATIONS
ea818dbb	94	# define I2C_SOFT_DECLARATIONS
ea818dbb HS	95	#endif
ea818dbb HS	96
90f002a9 MV	97	#if !defined(CONFIG_SYS_I2C_SOFT_SPEED)
90f002a9 MV	98	#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
ea818dbb	99	#endif
90f002a9 MV	100	#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE)
90f002a9 MV	101	#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
d87080b7 WD	102	#endif
d87080b7 WD	103
c609719b WD	104	/*-----------------------------------------------------------------------
	105	* Definitions
	106	*/
c609719b WD	107	#define RETRIES 0
c609719b WD	108
c609719b WD	109	#define I2C_ACK 0 /* PD_SDA level to ack a byte */
	110	#define I2C_NOACK 1 /* PD_SDA level to noack a byte */
	111
	112
	113	#ifdef DEBUG_I2C
	114	#define PRINTD(fmt,args...) do { \
c609719b WD	115	printf (fmt ,##args); \
	116	} while (0)
	117	#else
	118	#define PRINTD(fmt,args...)
	119	#endif
	120
	121	/*-----------------------------------------------------------------------
	122	* Local functions
	123	*/
6d0f6bcf	124	#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
c609719b	125	static void send_reset (void);
4ca107ef	126	#endif
c609719b WD	127	static void send_start (void);
	128	static void send_stop (void);
	129	static void send_ack (int);
	130	static int write_byte (uchar byte);
	131	static uchar read_byte (int);
	132
6d0f6bcf	133	#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
c609719b WD	134	/*-----------------------------------------------------------------------
	135	* Send a reset sequence consisting of 9 clocks with the data signal high
	136	* to clock any confused device back into an idle state. Also send a
	137	* <stop> at the end of the sequence for belts & suspenders.
	138	*/
	139	static void send_reset(void)
	140	{
98aed379	141	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b WD	142	int j;
c609719b WD	143
60fbe254	144	I2C_SCL(1);
c609719b	145	I2C_SDA(1);
60fbe254 WD	146	#ifdef I2C_INIT
	147	I2C_INIT;
	148	#endif
	149	I2C_TRISTATE;
c609719b WD	150	for(j = 0; j < 9; j++) {
	151	I2C_SCL(0);
	152	I2C_DELAY;
	153	I2C_DELAY;
	154	I2C_SCL(1);
	155	I2C_DELAY;
	156	I2C_DELAY;
	157	}
	158	send_stop();
	159	I2C_TRISTATE;
	160	}
4ca107ef	161	#endif
c609719b WD	162
	163	/*-----------------------------------------------------------------------
	164	* START: High -> Low on SDA while SCL is High
	165	*/
	166	static void send_start(void)
	167	{
98aed379	168	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b WD	169
	170	I2C_DELAY;
	171	I2C_SDA(1);
	172	I2C_ACTIVE;
	173	I2C_DELAY;
	174	I2C_SCL(1);
	175	I2C_DELAY;
	176	I2C_SDA(0);
	177	I2C_DELAY;
	178	}
	179
	180	/*-----------------------------------------------------------------------
	181	* STOP: Low -> High on SDA while SCL is High
	182	*/
	183	static void send_stop(void)
	184	{
98aed379	185	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b WD	186
	187	I2C_SCL(0);
	188	I2C_DELAY;
	189	I2C_SDA(0);
	190	I2C_ACTIVE;
	191	I2C_DELAY;
	192	I2C_SCL(1);
	193	I2C_DELAY;
	194	I2C_SDA(1);
	195	I2C_DELAY;
	196	I2C_TRISTATE;
	197	}
	198
c609719b WD	199	/*-----------------------------------------------------------------------
	200	* ack should be I2C_ACK or I2C_NOACK
	201	*/
	202	static void send_ack(int ack)
	203	{
98aed379	204	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b	205
c609719b WD	206	I2C_SCL(0);
c609719b WD	207	I2C_DELAY;
c609719b	208	I2C_ACTIVE;
c15f80ea	209	I2C_SDA(ack);
c609719b WD	210	I2C_DELAY;
	211	I2C_SCL(1);
	212	I2C_DELAY;
	213	I2C_DELAY;
	214	I2C_SCL(0);
	215	I2C_DELAY;
	216	}
	217
c609719b WD	218	/*-----------------------------------------------------------------------
	219	* Send 8 bits and look for an acknowledgement.
	220	*/
	221	static int write_byte(uchar data)
	222	{
98aed379	223	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b WD	224	int j;
	225	int nack;
	226
	227	I2C_ACTIVE;
	228	for(j = 0; j < 8; j++) {
	229	I2C_SCL(0);
	230	I2C_DELAY;
	231	I2C_SDA(data & 0x80);
	232	I2C_DELAY;
	233	I2C_SCL(1);
	234	I2C_DELAY;
	235	I2C_DELAY;
	236
	237	data <<= 1;
	238	}
	239
	240	/*
	241	* Look for an <ACK>(negative logic) and return it.
	242	*/
	243	I2C_SCL(0);
	244	I2C_DELAY;
	245	I2C_SDA(1);
	246	I2C_TRISTATE;
	247	I2C_DELAY;
	248	I2C_SCL(1);
	249	I2C_DELAY;
	250	I2C_DELAY;
	251	nack = I2C_READ;
	252	I2C_SCL(0);
	253	I2C_DELAY;
	254	I2C_ACTIVE;
	255
	256	return(nack); /* not a nack is an ack */
	257	}
	258
c609719b WD	259	/*-----------------------------------------------------------------------
	260	* if ack == I2C_ACK, ACK the byte so can continue reading, else
	261	* send I2C_NOACK to end the read.
	262	*/
	263	static uchar read_byte(int ack)
	264	{
98aed379	265	I2C_SOFT_DECLARATIONS /* intentional without ';' */
c609719b WD	266	int data;
	267	int j;
	268
	269	/*
	270	* Read 8 bits, MSB first.
	271	*/
	272	I2C_TRISTATE;
110e006f	273	I2C_SDA(1);
c609719b WD	274	data = 0;
	275	for(j = 0; j < 8; j++) {
	276	I2C_SCL(0);
	277	I2C_DELAY;
	278	I2C_SCL(1);
	279	I2C_DELAY;
	280	data <<= 1;
	281	data \|= I2C_READ;
	282	I2C_DELAY;
	283	}
	284	send_ack(ack);
	285
	286	return(data);
	287	}
	288
c609719b WD	289	/*-----------------------------------------------------------------------
	290	* Initialization
	291	*/
ea818dbb	292	static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
c609719b	293	{
6d0f6bcf	294	#if defined(CONFIG_SYS_I2C_INIT_BOARD)
4ca107ef HS	295	/* call board specific i2c bus reset routine before accessing the */
	296	/* environment, which might be in a chip on that bus. For details */
	297	/* about this problem see doc/I2C_Edge_Conditions. */
	298	i2c_init_board();
	299	#else
c609719b	300	/*
8bde7f77 WD	301	* WARNING: Do NOT save speed in a static variable: if the
	302	* I2C routines are called before RAM is initialized (to read
	303	* the DIMM SPD, for instance), RAM won't be usable and your
	304	* system will crash.
c609719b WD	305	*/
c609719b WD	306	send_reset ();
4ca107ef	307	#endif
c609719b WD	308	}
	309
	310	/*-----------------------------------------------------------------------
	311	* Probe to see if a chip is present. Also good for checking for the
	312	* completion of EEPROM writes since the chip stops responding until
	313	* the write completes (typically 10mSec).
	314	*/
ea818dbb	315	static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr)
c609719b WD	316	{
	317	int rc;
	318
82d716fd	319	/*
8e7b703a	320	* perform 1 byte write transaction with just address byte
82d716fd WD	321	* (fake write)
82d716fd WD	322	*/
c609719b	323	send_start();
6aff3115	324	rc = write_byte ((addr << 1) \| 0);
c609719b WD	325	send_stop();
	326
	327	return (rc ? 1 : 0);
	328	}
	329
	330	/*-----------------------------------------------------------------------
	331	* Read bytes
	332	*/
ea818dbb HS	333	static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
ea818dbb HS	334	int alen, uchar *buffer, int len)
c609719b WD	335	{
	336	int shift;
	337	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
	338	chip, addr, alen, buffer, len);
	339
6d0f6bcf	340	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
c609719b WD	341	/*
	342	* EEPROM chips that implement "address overflow" are ones
	343	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	344	* address and the extra bits end up in the "chip address"
	345	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	346	* four 256 byte chips.
	347	*
	348	* Note that we consider the length of the address field to
	349	* still be one byte because the extra address bits are
	350	* hidden in the chip address.
	351	*/
6d0f6bcf	352	chip \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
c609719b WD	353
	354	PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
	355	chip, addr);
	356	#endif
	357
	358	/*
	359	* Do the addressing portion of a write cycle to set the
	360	* chip's address pointer. If the address length is zero,
	361	* don't do the normal write cycle to set the address pointer,
	362	* there is no address pointer in this chip.
	363	*/
	364	send_start();
	365	if(alen > 0) {
	366	if(write_byte(chip << 1)) { /* write cycle */
	367	send_stop();
	368	PRINTD("i2c_read, no chip responded %02X\n", chip);
	369	return(1);
	370	}
	371	shift = (alen-1) * 8;
	372	while(alen-- > 0) {
	373	if(write_byte(addr >> shift)) {
	374	PRINTD("i2c_read, address not <ACK>ed\n");
	375	return(1);
	376	}
	377	shift -= 8;
	378	}
2ac6985a AD	379
	380	/* Some I2C chips need a stop/start sequence here,
	381	* other chips don't work with a full stop and need
	382	* only a start. Default behaviour is to send the
	383	* stop/start sequence.
	384	*/
	385	#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
	386	send_start();
	387	#else
	388	send_stop();
c609719b	389	send_start();
2ac6985a	390	#endif
c609719b WD	391	}
	392	/*
	393	* Send the chip address again, this time for a read cycle.
	394	* Then read the data. On the last byte, we do a NACK instead
	395	* of an ACK(len == 0) to terminate the read.
	396	*/
	397	write_byte((chip << 1) \| 1); /* read cycle */
	398	while(len-- > 0) {
	399	*buffer++ = read_byte(len == 0);
	400	}
	401	send_stop();
	402	return(0);
	403	}
	404
	405	/*-----------------------------------------------------------------------
	406	* Write bytes
	407	*/
ea818dbb HS	408	static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
ea818dbb HS	409	int alen, uchar *buffer, int len)
c609719b WD	410	{
	411	int shift, failures = 0;
	412
	413	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
	414	chip, addr, alen, buffer, len);
	415
	416	send_start();
	417	if(write_byte(chip << 1)) { /* write cycle */
	418	send_stop();
	419	PRINTD("i2c_write, no chip responded %02X\n", chip);
	420	return(1);
	421	}
	422	shift = (alen-1) * 8;
	423	while(alen-- > 0) {
	424	if(write_byte(addr >> shift)) {
	425	PRINTD("i2c_write, address not <ACK>ed\n");
	426	return(1);
	427	}
	428	shift -= 8;
	429	}
	430
	431	while(len-- > 0) {
	432	if(write_byte(*buffer++)) {
	433	failures++;
	434	}
	435	}
	436	send_stop();
	437	return(failures);
	438	}
ea818dbb HS	439
	440	/*
	441	* Register soft i2c adapters
	442	*/
37b33254	443	U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe,
ea818dbb HS	444	soft_i2c_read, soft_i2c_write, NULL,
	445	CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE,
	446	0)
	447	#if defined(I2C_SOFT_DECLARATIONS2)
37b33254	448	U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe,
ea818dbb HS	449	soft_i2c_read, soft_i2c_write, NULL,
	450	CONFIG_SYS_I2C_SOFT_SPEED_2,
	451	CONFIG_SYS_I2C_SOFT_SLAVE_2,
	452	1)
	453	#endif
	454	#if defined(I2C_SOFT_DECLARATIONS3)
37b33254	455	U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe,
ea818dbb HS	456	soft_i2c_read, soft_i2c_write, NULL,
	457	CONFIG_SYS_I2C_SOFT_SPEED_3,
	458	CONFIG_SYS_I2C_SOFT_SLAVE_3,
	459	2)
	460	#endif
	461	#if defined(I2C_SOFT_DECLARATIONS4)
37b33254	462	U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe,
ea818dbb HS	463	soft_i2c_read, soft_i2c_write, NULL,
	464	CONFIG_SYS_I2C_SOFT_SPEED_4,
	465	CONFIG_SYS_I2C_SOFT_SLAVE_4,
	466	3)
	467	#endif
7ed45d3d	468	#if defined(I2C_SOFT_DECLARATIONS5)
37b33254	469	U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe,
7ed45d3d DE	470	soft_i2c_read, soft_i2c_write, NULL,
	471	CONFIG_SYS_I2C_SOFT_SPEED_5,
	472	CONFIG_SYS_I2C_SOFT_SLAVE_5,
	473	4)
	474	#endif
	475	#if defined(I2C_SOFT_DECLARATIONS6)
37b33254	476	U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe,
7ed45d3d DE	477	soft_i2c_read, soft_i2c_write, NULL,
	478	CONFIG_SYS_I2C_SOFT_SPEED_6,
	479	CONFIG_SYS_I2C_SOFT_SLAVE_6,
	480	5)
	481	#endif
	482	#if defined(I2C_SOFT_DECLARATIONS7)
37b33254	483	U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe,
7ed45d3d DE	484	soft_i2c_read, soft_i2c_write, NULL,
	485	CONFIG_SYS_I2C_SOFT_SPEED_7,
	486	CONFIG_SYS_I2C_SOFT_SLAVE_7,
	487	6)
	488	#endif
	489	#if defined(I2C_SOFT_DECLARATIONS8)
37b33254	490	U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe,
7ed45d3d DE	491	soft_i2c_read, soft_i2c_write, NULL,
	492	CONFIG_SYS_I2C_SOFT_SPEED_8,
	493	CONFIG_SYS_I2C_SOFT_SLAVE_8,
	494	7)
	495	#endif
5c3b6dc1	496	#if defined(I2C_SOFT_DECLARATIONS9)
37b33254	497	U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe,
5c3b6dc1 DE	498	soft_i2c_read, soft_i2c_write, NULL,
	499	CONFIG_SYS_I2C_SOFT_SPEED_9,
	500	CONFIG_SYS_I2C_SOFT_SLAVE_9,
	501	8)
	502	#endif
	503	#if defined(I2C_SOFT_DECLARATIONS10)
37b33254	504	U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe,
5c3b6dc1 DE	505	soft_i2c_read, soft_i2c_write, NULL,
	506	CONFIG_SYS_I2C_SOFT_SPEED_10,
	507	CONFIG_SYS_I2C_SOFT_SLAVE_10,
	508	9)
	509	#endif
	510	#if defined(I2C_SOFT_DECLARATIONS11)
	511	U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
	512	soft_i2c_read, soft_i2c_write, NULL,
	513	CONFIG_SYS_I2C_SOFT_SPEED_11,
	514	CONFIG_SYS_I2C_SOFT_SLAVE_11,
	515	10)
	516	#endif
	517	#if defined(I2C_SOFT_DECLARATIONS12)
	518	U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
	519	soft_i2c_read, soft_i2c_write, NULL,
	520	CONFIG_SYS_I2C_SOFT_SPEED_12,
	521	CONFIG_SYS_I2C_SOFT_SLAVE_12,
	522	11)
	523	#endif