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d3d6427a MB |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2009 | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
d3d6427a MB |
5 | */ |
6 | ||
7 | #ifndef _U8500_I2C_H_ | |
8 | #define _U8500_I2C_H_ | |
9 | ||
10 | #include <asm/types.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/errno.h> | |
13 | #include <asm/arch/u8500.h> | |
14 | ||
15 | struct u8500_i2c_regs { | |
16 | u32 cr; /* Control Register 0x00 */ | |
17 | u32 scr; /* Slave Address Register 0x04 */ | |
18 | u32 hsmcr; /* HS Master code Register 0x08 */ | |
19 | u32 mcr; /* Master Control Register 0x0C */ | |
20 | u32 tfr; /* Transmit Fifo Register 0x10 */ | |
21 | u32 sr; /* Status Register 0x14 */ | |
22 | u32 rfr; /* Receiver Fifo Register 0x18 */ | |
23 | u32 tftr; /* Transmit Fifo Threshold Register 0x1C */ | |
24 | u32 rftr; /* Receiver Fifo Threshold Register 0x20 */ | |
25 | u32 dmar; /* DMA register 0x24 */ | |
26 | u32 brcr; /* Baud Rate Counter Register 0x28 */ | |
27 | u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */ | |
28 | u32 risr; /* Raw interrupt status register 0x30 */ | |
29 | u32 misr; /* Masked interrupt status register 0x34 */ | |
30 | u32 icr; /* Interrupt Set and Clear Register 0x38 */ | |
31 | u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */ | |
32 | u32 periph_id_0; /* peripheral ID 0 0xFE0 */ | |
33 | u32 periph_id_1; /* peripheral ID 1 0xFE4 */ | |
34 | u32 periph_id_2; /* peripheral ID 2 0xFE8 */ | |
35 | u32 periph_id_3; /* peripheral ID 3 0xFEC */ | |
36 | u32 cell_id_0; /* I2C cell ID 0 0xFF0 */ | |
37 | u32 cell_id_1; /* I2C cell ID 1 0xFF4 */ | |
38 | u32 cell_id_2; /* I2C cell ID 2 0xFF8 */ | |
39 | u32 cell_id_3; /* I2C cell ID 3 0xFFC */ | |
40 | }; | |
41 | ||
42 | ||
43 | /* Control Register */ | |
44 | ||
45 | /* Mask values for control register mask */ | |
46 | #define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */ | |
47 | #define U8500_I2C_CR_OM 0x0006 /* Operation mode */ | |
48 | #define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */ | |
49 | #define U8500_I2C_CR_SM 0x0030 /* Speed mode */ | |
50 | #define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */ | |
51 | #define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */ | |
52 | #define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */ | |
53 | #define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */ | |
54 | #define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */ | |
55 | #define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */ | |
56 | #define U8500_I2C_CR_LM 0x1000 /* Loop back mode */ | |
57 | #define U8500_I2C_CR_FON 0x6000 /* Filtering On */ | |
58 | ||
59 | /* shift valus for control register bit fields */ | |
60 | #define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */ | |
61 | #define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */ | |
62 | #define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */ | |
63 | #define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */ | |
64 | #define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */ | |
65 | #define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */ | |
66 | #define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */ | |
67 | #define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */ | |
68 | #define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */ | |
69 | #define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */ | |
70 | #define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */ | |
71 | #define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */ | |
72 | ||
73 | /* bus operation modes */ | |
74 | #define U8500_I2C_BUS_SLAVE_MODE 0 | |
75 | #define U8500_I2C_BUS_MASTER_MODE 1 | |
76 | #define U8500_I2C_BUS_MASTER_SLAVE_MODE 2 | |
77 | ||
78 | ||
79 | /* Slave control register*/ | |
80 | ||
81 | /* Mask values slave control register */ | |
82 | #define U8500_I2C_SCR_ADDR 0x3FF | |
83 | #define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000 | |
84 | ||
85 | /* Shift values for Slave control register */ | |
86 | #define U8500_I2C_SCR_SHIFT_ADDR 0 | |
87 | #define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16 | |
88 | ||
89 | ||
90 | /* Master Control Register */ | |
91 | ||
92 | /* Mask values for Master control register */ | |
93 | #define U8500_I2C_MCR_OP 0x00000001 /* Operation */ | |
94 | #define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */ | |
95 | #define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */ | |
96 | #define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */ | |
97 | #define U8500_I2C_MCR_AM 0x00003000 /* Address type */ | |
98 | #define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */ | |
99 | #define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */ | |
100 | #define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */ | |
101 | /* mask for length field,stop and operation */ | |
102 | #define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001 | |
103 | ||
104 | /* Shift values for Master control values */ | |
105 | #define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */ | |
106 | #define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */ | |
107 | #define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */ | |
108 | #define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */ | |
109 | #define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */ | |
110 | #define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */ | |
111 | #define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */ | |
112 | #define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */ | |
113 | ||
114 | #define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0 | |
115 | ||
116 | ||
117 | /* Status Register */ | |
118 | ||
119 | /* Mask values for Status register */ | |
120 | #define U8500_I2C_SR_OP 0x00000003 /* Operation */ | |
121 | #define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */ | |
122 | #define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */ | |
123 | #define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */ | |
124 | #define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */ | |
125 | ||
126 | /* Shift values for Status register */ | |
127 | #define U8500_I2C_SR_SHIFT_OP 0 /* Operation */ | |
128 | #define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */ | |
129 | #define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */ | |
130 | #define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */ | |
131 | #define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */ | |
132 | ||
133 | /* abort cause */ | |
134 | #define U8500_I2C_NACK_ADDR 0 | |
135 | #define U8500_I2C_NACK_DATA 1 | |
136 | #define U8500_I2C_ACK_MCODE 2 | |
137 | #define U8500_I2C_ARB_LOST 3 | |
138 | #define U8500_I2C_BERR_START 4 | |
139 | #define U8500_I2C_BERR_STOP 5 | |
140 | #define U8500_I2C_OVFL 6 | |
141 | ||
142 | ||
143 | /* Baud rate counter registers */ | |
144 | ||
145 | /* Mask values for Baud rate counter register */ | |
146 | #define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */ | |
147 | #define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */ | |
148 | ||
149 | /* Shift values for the Baud rate counter register */ | |
150 | #define U8500_I2C_BRCR_SHIFT_BRCNT2 0 | |
151 | #define U8500_I2C_BRCR_SHIFT_BRCNT1 16 | |
152 | ||
153 | ||
154 | /* Interrupt Register */ | |
155 | ||
156 | /* Mask values for Interrupt registers */ | |
157 | #define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */ | |
158 | #define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */ | |
159 | #define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */ | |
160 | #define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */ | |
161 | #define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */ | |
162 | #define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */ | |
163 | #define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */ | |
164 | #define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */ | |
165 | #define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */ | |
166 | #define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */ | |
167 | #define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/ | |
168 | #define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */ | |
169 | #define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */ | |
170 | #define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */ | |
171 | #define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */ | |
172 | ||
173 | /* Max clocks (Hz) */ | |
174 | #define U8500_I2C_MAX_STANDARD_SCL 100000 | |
175 | #define U8500_I2C_MAX_FAST_SCL 400000 | |
176 | #define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000 | |
177 | ||
178 | #endif /* _U8500_I2C_H_ */ |