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22b46c45 SP |
1 | /* |
2 | * BMG160 Gyro Sensor driver | |
3 | * Copyright (c) 2014, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/acpi.h> | |
21 | #include <linux/gpio/consumer.h> | |
22 | #include <linux/pm.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/iio/iio.h> | |
25 | #include <linux/iio/sysfs.h> | |
26 | #include <linux/iio/buffer.h> | |
27 | #include <linux/iio/trigger.h> | |
28 | #include <linux/iio/events.h> | |
29 | #include <linux/iio/trigger_consumer.h> | |
30 | #include <linux/iio/triggered_buffer.h> | |
c6c9e995 | 31 | #include <linux/regmap.h> |
22b46c45 SP |
32 | |
33 | #define BMG160_DRV_NAME "bmg160" | |
34 | #define BMG160_IRQ_NAME "bmg160_event" | |
35 | #define BMG160_GPIO_NAME "gpio_int" | |
36 | ||
37 | #define BMG160_REG_CHIP_ID 0x00 | |
38 | #define BMG160_CHIP_ID_VAL 0x0F | |
39 | ||
40 | #define BMG160_REG_PMU_LPW 0x11 | |
41 | #define BMG160_MODE_NORMAL 0x00 | |
42 | #define BMG160_MODE_DEEP_SUSPEND 0x20 | |
43 | #define BMG160_MODE_SUSPEND 0x80 | |
44 | ||
45 | #define BMG160_REG_RANGE 0x0F | |
46 | ||
47 | #define BMG160_RANGE_2000DPS 0 | |
48 | #define BMG160_RANGE_1000DPS 1 | |
49 | #define BMG160_RANGE_500DPS 2 | |
50 | #define BMG160_RANGE_250DPS 3 | |
51 | #define BMG160_RANGE_125DPS 4 | |
52 | ||
53 | #define BMG160_REG_PMU_BW 0x10 | |
54 | #define BMG160_NO_FILTER 0 | |
55 | #define BMG160_DEF_BW 100 | |
56 | ||
57 | #define BMG160_REG_INT_MAP_0 0x17 | |
58 | #define BMG160_INT_MAP_0_BIT_ANY BIT(1) | |
59 | ||
60 | #define BMG160_REG_INT_MAP_1 0x18 | |
61 | #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0) | |
62 | ||
63 | #define BMG160_REG_INT_RST_LATCH 0x21 | |
64 | #define BMG160_INT_MODE_LATCH_RESET 0x80 | |
65 | #define BMG160_INT_MODE_LATCH_INT 0x0F | |
66 | #define BMG160_INT_MODE_NON_LATCH_INT 0x00 | |
67 | ||
68 | #define BMG160_REG_INT_EN_0 0x15 | |
69 | #define BMG160_DATA_ENABLE_INT BIT(7) | |
70 | ||
5af6b307 SP |
71 | #define BMG160_REG_INT_EN_1 0x16 |
72 | #define BMG160_INT1_BIT_OD BIT(1) | |
73 | ||
22b46c45 SP |
74 | #define BMG160_REG_XOUT_L 0x02 |
75 | #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2)) | |
76 | ||
77 | #define BMG160_REG_SLOPE_THRES 0x1B | |
78 | #define BMG160_SLOPE_THRES_MASK 0x0F | |
79 | ||
80 | #define BMG160_REG_MOTION_INTR 0x1C | |
81 | #define BMG160_INT_MOTION_X BIT(0) | |
82 | #define BMG160_INT_MOTION_Y BIT(1) | |
83 | #define BMG160_INT_MOTION_Z BIT(2) | |
84 | #define BMG160_ANY_DUR_MASK 0x30 | |
85 | #define BMG160_ANY_DUR_SHIFT 4 | |
86 | ||
87 | #define BMG160_REG_INT_STATUS_2 0x0B | |
88 | #define BMG160_ANY_MOTION_MASK 0x07 | |
cb80f6a3 SP |
89 | #define BMG160_ANY_MOTION_BIT_X BIT(0) |
90 | #define BMG160_ANY_MOTION_BIT_Y BIT(1) | |
91 | #define BMG160_ANY_MOTION_BIT_Z BIT(2) | |
22b46c45 SP |
92 | |
93 | #define BMG160_REG_TEMP 0x08 | |
94 | #define BMG160_TEMP_CENTER_VAL 23 | |
95 | ||
96 | #define BMG160_MAX_STARTUP_TIME_MS 80 | |
97 | ||
98 | #define BMG160_AUTO_SUSPEND_DELAY_MS 2000 | |
99 | ||
100 | struct bmg160_data { | |
74e04345 | 101 | struct device *dev; |
c6c9e995 | 102 | struct regmap *regmap; |
22b46c45 SP |
103 | struct iio_trigger *dready_trig; |
104 | struct iio_trigger *motion_trig; | |
105 | struct mutex mutex; | |
106 | s16 buffer[8]; | |
107 | u8 bw_bits; | |
108 | u32 dps_range; | |
109 | int ev_enable_state; | |
110 | int slope_thres; | |
111 | bool dready_trigger_on; | |
112 | bool motion_trigger_on; | |
5d889abb | 113 | int irq; |
22b46c45 SP |
114 | }; |
115 | ||
116 | enum bmg160_axis { | |
117 | AXIS_X, | |
118 | AXIS_Y, | |
119 | AXIS_Z, | |
120 | }; | |
121 | ||
122 | static const struct { | |
123 | int val; | |
124 | int bw_bits; | |
125 | } bmg160_samp_freq_table[] = { {100, 0x07}, | |
126 | {200, 0x06}, | |
127 | {400, 0x03}, | |
128 | {1000, 0x02}, | |
129 | {2000, 0x01} }; | |
130 | ||
131 | static const struct { | |
132 | int scale; | |
133 | int dps_range; | |
134 | } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS}, | |
135 | { 532, BMG160_RANGE_1000DPS}, | |
136 | { 266, BMG160_RANGE_500DPS}, | |
137 | { 133, BMG160_RANGE_250DPS}, | |
138 | { 66, BMG160_RANGE_125DPS} }; | |
139 | ||
c6c9e995 MSP |
140 | static struct regmap_config bmg160_regmap_i2c_conf = { |
141 | .reg_bits = 8, | |
142 | .val_bits = 8, | |
143 | .max_register = 0x3f | |
144 | }; | |
145 | ||
22b46c45 SP |
146 | static int bmg160_set_mode(struct bmg160_data *data, u8 mode) |
147 | { | |
148 | int ret; | |
149 | ||
c6c9e995 | 150 | ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode); |
22b46c45 | 151 | if (ret < 0) { |
74e04345 | 152 | dev_err(data->dev, "Error writing reg_pmu_lpw\n"); |
22b46c45 SP |
153 | return ret; |
154 | } | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
159 | static int bmg160_convert_freq_to_bit(int val) | |
160 | { | |
161 | int i; | |
162 | ||
163 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
164 | if (bmg160_samp_freq_table[i].val == val) | |
165 | return bmg160_samp_freq_table[i].bw_bits; | |
166 | } | |
167 | ||
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | static int bmg160_set_bw(struct bmg160_data *data, int val) | |
172 | { | |
173 | int ret; | |
174 | int bw_bits; | |
175 | ||
176 | bw_bits = bmg160_convert_freq_to_bit(val); | |
177 | if (bw_bits < 0) | |
178 | return bw_bits; | |
179 | ||
c6c9e995 | 180 | ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits); |
22b46c45 | 181 | if (ret < 0) { |
74e04345 | 182 | dev_err(data->dev, "Error writing reg_pmu_bw\n"); |
22b46c45 SP |
183 | return ret; |
184 | } | |
185 | ||
186 | data->bw_bits = bw_bits; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static int bmg160_chip_init(struct bmg160_data *data) | |
192 | { | |
193 | int ret; | |
c6c9e995 | 194 | unsigned int val; |
22b46c45 | 195 | |
c6c9e995 | 196 | ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val); |
22b46c45 | 197 | if (ret < 0) { |
74e04345 | 198 | dev_err(data->dev, "Error reading reg_chip_id\n"); |
22b46c45 SP |
199 | return ret; |
200 | } | |
201 | ||
74e04345 | 202 | dev_dbg(data->dev, "Chip Id %x\n", val); |
c6c9e995 | 203 | if (val != BMG160_CHIP_ID_VAL) { |
74e04345 | 204 | dev_err(data->dev, "invalid chip %x\n", val); |
22b46c45 SP |
205 | return -ENODEV; |
206 | } | |
207 | ||
208 | ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
209 | if (ret < 0) | |
210 | return ret; | |
211 | ||
212 | /* Wait upto 500 ms to be ready after changing mode */ | |
213 | usleep_range(500, 1000); | |
214 | ||
215 | /* Set Bandwidth */ | |
216 | ret = bmg160_set_bw(data, BMG160_DEF_BW); | |
217 | if (ret < 0) | |
218 | return ret; | |
219 | ||
220 | /* Set Default Range */ | |
c6c9e995 | 221 | ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS); |
22b46c45 | 222 | if (ret < 0) { |
74e04345 | 223 | dev_err(data->dev, "Error writing reg_range\n"); |
22b46c45 SP |
224 | return ret; |
225 | } | |
226 | data->dps_range = BMG160_RANGE_500DPS; | |
227 | ||
c6c9e995 | 228 | ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val); |
22b46c45 | 229 | if (ret < 0) { |
74e04345 | 230 | dev_err(data->dev, "Error reading reg_slope_thres\n"); |
22b46c45 SP |
231 | return ret; |
232 | } | |
c6c9e995 | 233 | data->slope_thres = val; |
22b46c45 SP |
234 | |
235 | /* Set default interrupt mode */ | |
c6c9e995 MSP |
236 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1, |
237 | BMG160_INT1_BIT_OD, 0); | |
5af6b307 | 238 | if (ret < 0) { |
74e04345 | 239 | dev_err(data->dev, "Error updating bits in reg_int_en_1\n"); |
5af6b307 SP |
240 | return ret; |
241 | } | |
242 | ||
c6c9e995 MSP |
243 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
244 | BMG160_INT_MODE_LATCH_INT | | |
245 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 246 | if (ret < 0) { |
74e04345 | 247 | dev_err(data->dev, |
22b46c45 SP |
248 | "Error writing reg_motion_intr\n"); |
249 | return ret; | |
250 | } | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | static int bmg160_set_power_state(struct bmg160_data *data, bool on) | |
256 | { | |
6f0a13f2 | 257 | #ifdef CONFIG_PM |
22b46c45 SP |
258 | int ret; |
259 | ||
260 | if (on) | |
74e04345 | 261 | ret = pm_runtime_get_sync(data->dev); |
22b46c45 | 262 | else { |
74e04345 MSP |
263 | pm_runtime_mark_last_busy(data->dev); |
264 | ret = pm_runtime_put_autosuspend(data->dev); | |
22b46c45 SP |
265 | } |
266 | ||
267 | if (ret < 0) { | |
74e04345 | 268 | dev_err(data->dev, |
22b46c45 | 269 | "Failed: bmg160_set_power_state for %d\n", on); |
10bef289 | 270 | if (on) |
74e04345 | 271 | pm_runtime_put_noidle(data->dev); |
10bef289 | 272 | |
22b46c45 SP |
273 | return ret; |
274 | } | |
ef1c6b23 | 275 | #endif |
22b46c45 SP |
276 | |
277 | return 0; | |
278 | } | |
279 | ||
280 | static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data, | |
281 | bool status) | |
282 | { | |
283 | int ret; | |
284 | ||
285 | /* Enable/Disable INT_MAP0 mapping */ | |
c6c9e995 MSP |
286 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0, |
287 | BMG160_INT_MAP_0_BIT_ANY, | |
288 | (status ? BMG160_INT_MAP_0_BIT_ANY : 0)); | |
22b46c45 | 289 | if (ret < 0) { |
74e04345 | 290 | dev_err(data->dev, "Error updating bits reg_int_map0\n"); |
22b46c45 SP |
291 | return ret; |
292 | } | |
293 | ||
294 | /* Enable/Disable slope interrupts */ | |
295 | if (status) { | |
296 | /* Update slope thres */ | |
c6c9e995 MSP |
297 | ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES, |
298 | data->slope_thres); | |
22b46c45 | 299 | if (ret < 0) { |
74e04345 | 300 | dev_err(data->dev, |
22b46c45 SP |
301 | "Error writing reg_slope_thres\n"); |
302 | return ret; | |
303 | } | |
304 | ||
c6c9e995 MSP |
305 | ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR, |
306 | BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y | | |
307 | BMG160_INT_MOTION_Z); | |
22b46c45 | 308 | if (ret < 0) { |
74e04345 | 309 | dev_err(data->dev, |
22b46c45 SP |
310 | "Error writing reg_motion_intr\n"); |
311 | return ret; | |
312 | } | |
313 | ||
314 | /* | |
315 | * New data interrupt is always non-latched, | |
316 | * which will have higher priority, so no need | |
317 | * to set latched mode, we will be flooded anyway with INTR | |
318 | */ | |
319 | if (!data->dready_trigger_on) { | |
c6c9e995 MSP |
320 | ret = regmap_write(data->regmap, |
321 | BMG160_REG_INT_RST_LATCH, | |
322 | BMG160_INT_MODE_LATCH_INT | | |
323 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 324 | if (ret < 0) { |
74e04345 | 325 | dev_err(data->dev, |
22b46c45 SP |
326 | "Error writing reg_rst_latch\n"); |
327 | return ret; | |
328 | } | |
329 | } | |
330 | ||
c6c9e995 MSP |
331 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, |
332 | BMG160_DATA_ENABLE_INT); | |
22b46c45 | 333 | |
c6c9e995 MSP |
334 | } else { |
335 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); | |
336 | } | |
22b46c45 SP |
337 | |
338 | if (ret < 0) { | |
74e04345 | 339 | dev_err(data->dev, "Error writing reg_int_en0\n"); |
22b46c45 SP |
340 | return ret; |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int bmg160_setup_new_data_interrupt(struct bmg160_data *data, | |
347 | bool status) | |
348 | { | |
349 | int ret; | |
350 | ||
351 | /* Enable/Disable INT_MAP1 mapping */ | |
c6c9e995 MSP |
352 | ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1, |
353 | BMG160_INT_MAP_1_BIT_NEW_DATA, | |
354 | (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0)); | |
22b46c45 | 355 | if (ret < 0) { |
74e04345 | 356 | dev_err(data->dev, "Error updating bits in reg_int_map1\n"); |
22b46c45 SP |
357 | return ret; |
358 | } | |
359 | ||
360 | if (status) { | |
c6c9e995 MSP |
361 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
362 | BMG160_INT_MODE_NON_LATCH_INT | | |
363 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 364 | if (ret < 0) { |
74e04345 | 365 | dev_err(data->dev, |
22b46c45 SP |
366 | "Error writing reg_rst_latch\n"); |
367 | return ret; | |
368 | } | |
369 | ||
c6c9e995 MSP |
370 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, |
371 | BMG160_DATA_ENABLE_INT); | |
22b46c45 SP |
372 | |
373 | } else { | |
374 | /* Restore interrupt mode */ | |
c6c9e995 MSP |
375 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
376 | BMG160_INT_MODE_LATCH_INT | | |
377 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 378 | if (ret < 0) { |
74e04345 | 379 | dev_err(data->dev, |
22b46c45 SP |
380 | "Error writing reg_rst_latch\n"); |
381 | return ret; | |
382 | } | |
383 | ||
c6c9e995 | 384 | ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0); |
22b46c45 SP |
385 | } |
386 | ||
387 | if (ret < 0) { | |
74e04345 | 388 | dev_err(data->dev, "Error writing reg_int_en0\n"); |
22b46c45 SP |
389 | return ret; |
390 | } | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static int bmg160_get_bw(struct bmg160_data *data, int *val) | |
396 | { | |
397 | int i; | |
398 | ||
399 | for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) { | |
400 | if (bmg160_samp_freq_table[i].bw_bits == data->bw_bits) { | |
401 | *val = bmg160_samp_freq_table[i].val; | |
402 | return IIO_VAL_INT; | |
403 | } | |
404 | } | |
405 | ||
406 | return -EINVAL; | |
407 | } | |
408 | ||
409 | static int bmg160_set_scale(struct bmg160_data *data, int val) | |
410 | { | |
411 | int ret, i; | |
412 | ||
413 | for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { | |
414 | if (bmg160_scale_table[i].scale == val) { | |
c6c9e995 MSP |
415 | ret = regmap_write(data->regmap, BMG160_REG_RANGE, |
416 | bmg160_scale_table[i].dps_range); | |
22b46c45 | 417 | if (ret < 0) { |
74e04345 | 418 | dev_err(data->dev, |
22b46c45 SP |
419 | "Error writing reg_range\n"); |
420 | return ret; | |
421 | } | |
422 | data->dps_range = bmg160_scale_table[i].dps_range; | |
423 | return 0; | |
424 | } | |
425 | } | |
426 | ||
427 | return -EINVAL; | |
428 | } | |
429 | ||
430 | static int bmg160_get_temp(struct bmg160_data *data, int *val) | |
431 | { | |
432 | int ret; | |
c6c9e995 | 433 | unsigned int raw_val; |
22b46c45 SP |
434 | |
435 | mutex_lock(&data->mutex); | |
436 | ret = bmg160_set_power_state(data, true); | |
437 | if (ret < 0) { | |
438 | mutex_unlock(&data->mutex); | |
439 | return ret; | |
440 | } | |
441 | ||
c6c9e995 | 442 | ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val); |
22b46c45 | 443 | if (ret < 0) { |
74e04345 | 444 | dev_err(data->dev, "Error reading reg_temp\n"); |
22b46c45 SP |
445 | bmg160_set_power_state(data, false); |
446 | mutex_unlock(&data->mutex); | |
447 | return ret; | |
448 | } | |
449 | ||
c6c9e995 | 450 | *val = sign_extend32(raw_val, 7); |
22b46c45 SP |
451 | ret = bmg160_set_power_state(data, false); |
452 | mutex_unlock(&data->mutex); | |
453 | if (ret < 0) | |
454 | return ret; | |
455 | ||
456 | return IIO_VAL_INT; | |
457 | } | |
458 | ||
459 | static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val) | |
460 | { | |
461 | int ret; | |
c6c9e995 | 462 | unsigned int raw_val; |
22b46c45 SP |
463 | |
464 | mutex_lock(&data->mutex); | |
465 | ret = bmg160_set_power_state(data, true); | |
466 | if (ret < 0) { | |
467 | mutex_unlock(&data->mutex); | |
468 | return ret; | |
469 | } | |
470 | ||
c6c9e995 MSP |
471 | ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val, |
472 | 2); | |
22b46c45 | 473 | if (ret < 0) { |
74e04345 | 474 | dev_err(data->dev, "Error reading axis %d\n", axis); |
22b46c45 SP |
475 | bmg160_set_power_state(data, false); |
476 | mutex_unlock(&data->mutex); | |
477 | return ret; | |
478 | } | |
479 | ||
c6c9e995 | 480 | *val = sign_extend32(raw_val, 15); |
22b46c45 SP |
481 | ret = bmg160_set_power_state(data, false); |
482 | mutex_unlock(&data->mutex); | |
483 | if (ret < 0) | |
484 | return ret; | |
485 | ||
486 | return IIO_VAL_INT; | |
487 | } | |
488 | ||
489 | static int bmg160_read_raw(struct iio_dev *indio_dev, | |
490 | struct iio_chan_spec const *chan, | |
491 | int *val, int *val2, long mask) | |
492 | { | |
493 | struct bmg160_data *data = iio_priv(indio_dev); | |
494 | int ret; | |
495 | ||
496 | switch (mask) { | |
497 | case IIO_CHAN_INFO_RAW: | |
498 | switch (chan->type) { | |
499 | case IIO_TEMP: | |
500 | return bmg160_get_temp(data, val); | |
501 | case IIO_ANGL_VEL: | |
502 | if (iio_buffer_enabled(indio_dev)) | |
503 | return -EBUSY; | |
504 | else | |
505 | return bmg160_get_axis(data, chan->scan_index, | |
506 | val); | |
507 | default: | |
508 | return -EINVAL; | |
509 | } | |
510 | case IIO_CHAN_INFO_OFFSET: | |
511 | if (chan->type == IIO_TEMP) { | |
512 | *val = BMG160_TEMP_CENTER_VAL; | |
513 | return IIO_VAL_INT; | |
514 | } else | |
515 | return -EINVAL; | |
516 | case IIO_CHAN_INFO_SCALE: | |
517 | *val = 0; | |
518 | switch (chan->type) { | |
519 | case IIO_TEMP: | |
520 | *val2 = 500000; | |
521 | return IIO_VAL_INT_PLUS_MICRO; | |
522 | case IIO_ANGL_VEL: | |
523 | { | |
524 | int i; | |
525 | ||
526 | for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) { | |
527 | if (bmg160_scale_table[i].dps_range == | |
528 | data->dps_range) { | |
529 | *val2 = bmg160_scale_table[i].scale; | |
530 | return IIO_VAL_INT_PLUS_MICRO; | |
531 | } | |
532 | } | |
533 | return -EINVAL; | |
534 | } | |
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
538 | case IIO_CHAN_INFO_SAMP_FREQ: | |
539 | *val2 = 0; | |
540 | mutex_lock(&data->mutex); | |
541 | ret = bmg160_get_bw(data, val); | |
542 | mutex_unlock(&data->mutex); | |
543 | return ret; | |
544 | default: | |
545 | return -EINVAL; | |
546 | } | |
547 | } | |
548 | ||
549 | static int bmg160_write_raw(struct iio_dev *indio_dev, | |
550 | struct iio_chan_spec const *chan, | |
551 | int val, int val2, long mask) | |
552 | { | |
553 | struct bmg160_data *data = iio_priv(indio_dev); | |
554 | int ret; | |
555 | ||
556 | switch (mask) { | |
557 | case IIO_CHAN_INFO_SAMP_FREQ: | |
558 | mutex_lock(&data->mutex); | |
559 | /* | |
560 | * Section 4.2 of spec | |
561 | * In suspend mode, the only supported operations are reading | |
562 | * registers as well as writing to the (0x14) softreset | |
563 | * register. Since we will be in suspend mode by default, change | |
564 | * mode to power on for other writes. | |
565 | */ | |
566 | ret = bmg160_set_power_state(data, true); | |
567 | if (ret < 0) { | |
568 | mutex_unlock(&data->mutex); | |
569 | return ret; | |
570 | } | |
571 | ret = bmg160_set_bw(data, val); | |
572 | if (ret < 0) { | |
573 | bmg160_set_power_state(data, false); | |
574 | mutex_unlock(&data->mutex); | |
575 | return ret; | |
576 | } | |
577 | ret = bmg160_set_power_state(data, false); | |
578 | mutex_unlock(&data->mutex); | |
579 | return ret; | |
580 | case IIO_CHAN_INFO_SCALE: | |
581 | if (val) | |
582 | return -EINVAL; | |
583 | ||
584 | mutex_lock(&data->mutex); | |
585 | /* Refer to comments above for the suspend mode ops */ | |
586 | ret = bmg160_set_power_state(data, true); | |
587 | if (ret < 0) { | |
588 | mutex_unlock(&data->mutex); | |
589 | return ret; | |
590 | } | |
591 | ret = bmg160_set_scale(data, val2); | |
592 | if (ret < 0) { | |
593 | bmg160_set_power_state(data, false); | |
594 | mutex_unlock(&data->mutex); | |
595 | return ret; | |
596 | } | |
597 | ret = bmg160_set_power_state(data, false); | |
598 | mutex_unlock(&data->mutex); | |
599 | return ret; | |
600 | default: | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | return -EINVAL; | |
605 | } | |
606 | ||
607 | static int bmg160_read_event(struct iio_dev *indio_dev, | |
608 | const struct iio_chan_spec *chan, | |
609 | enum iio_event_type type, | |
610 | enum iio_event_direction dir, | |
611 | enum iio_event_info info, | |
612 | int *val, int *val2) | |
613 | { | |
614 | struct bmg160_data *data = iio_priv(indio_dev); | |
615 | ||
616 | *val2 = 0; | |
617 | switch (info) { | |
618 | case IIO_EV_INFO_VALUE: | |
619 | *val = data->slope_thres & BMG160_SLOPE_THRES_MASK; | |
620 | break; | |
621 | default: | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
625 | return IIO_VAL_INT; | |
626 | } | |
627 | ||
628 | static int bmg160_write_event(struct iio_dev *indio_dev, | |
629 | const struct iio_chan_spec *chan, | |
630 | enum iio_event_type type, | |
631 | enum iio_event_direction dir, | |
632 | enum iio_event_info info, | |
633 | int val, int val2) | |
634 | { | |
635 | struct bmg160_data *data = iio_priv(indio_dev); | |
636 | ||
637 | switch (info) { | |
638 | case IIO_EV_INFO_VALUE: | |
639 | if (data->ev_enable_state) | |
640 | return -EBUSY; | |
641 | data->slope_thres &= ~BMG160_SLOPE_THRES_MASK; | |
642 | data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK); | |
643 | break; | |
644 | default: | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static int bmg160_read_event_config(struct iio_dev *indio_dev, | |
652 | const struct iio_chan_spec *chan, | |
653 | enum iio_event_type type, | |
654 | enum iio_event_direction dir) | |
655 | { | |
656 | ||
657 | struct bmg160_data *data = iio_priv(indio_dev); | |
658 | ||
659 | return data->ev_enable_state; | |
660 | } | |
661 | ||
662 | static int bmg160_write_event_config(struct iio_dev *indio_dev, | |
663 | const struct iio_chan_spec *chan, | |
664 | enum iio_event_type type, | |
665 | enum iio_event_direction dir, | |
666 | int state) | |
667 | { | |
668 | struct bmg160_data *data = iio_priv(indio_dev); | |
669 | int ret; | |
670 | ||
671 | if (state && data->ev_enable_state) | |
672 | return 0; | |
673 | ||
674 | mutex_lock(&data->mutex); | |
675 | ||
676 | if (!state && data->motion_trigger_on) { | |
677 | data->ev_enable_state = 0; | |
678 | mutex_unlock(&data->mutex); | |
679 | return 0; | |
680 | } | |
681 | /* | |
682 | * We will expect the enable and disable to do operation in | |
683 | * in reverse order. This will happen here anyway as our | |
684 | * resume operation uses sync mode runtime pm calls, the | |
685 | * suspend operation will be delayed by autosuspend delay | |
686 | * So the disable operation will still happen in reverse of | |
687 | * enable operation. When runtime pm is disabled the mode | |
688 | * is always on so sequence doesn't matter | |
689 | */ | |
690 | ret = bmg160_set_power_state(data, state); | |
691 | if (ret < 0) { | |
692 | mutex_unlock(&data->mutex); | |
693 | return ret; | |
694 | } | |
695 | ||
696 | ret = bmg160_setup_any_motion_interrupt(data, state); | |
697 | if (ret < 0) { | |
10bef289 | 698 | bmg160_set_power_state(data, false); |
22b46c45 SP |
699 | mutex_unlock(&data->mutex); |
700 | return ret; | |
701 | } | |
702 | ||
703 | data->ev_enable_state = state; | |
704 | mutex_unlock(&data->mutex); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
22b46c45 SP |
709 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000"); |
710 | ||
711 | static IIO_CONST_ATTR(in_anglvel_scale_available, | |
712 | "0.001065 0.000532 0.000266 0.000133 0.000066"); | |
713 | ||
714 | static struct attribute *bmg160_attributes[] = { | |
715 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
716 | &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, | |
717 | NULL, | |
718 | }; | |
719 | ||
720 | static const struct attribute_group bmg160_attrs_group = { | |
721 | .attrs = bmg160_attributes, | |
722 | }; | |
723 | ||
724 | static const struct iio_event_spec bmg160_event = { | |
725 | .type = IIO_EV_TYPE_ROC, | |
6896ab3a | 726 | .dir = IIO_EV_DIR_EITHER, |
22b46c45 SP |
727 | .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | |
728 | BIT(IIO_EV_INFO_ENABLE) | |
729 | }; | |
730 | ||
731 | #define BMG160_CHANNEL(_axis) { \ | |
732 | .type = IIO_ANGL_VEL, \ | |
733 | .modified = 1, \ | |
734 | .channel2 = IIO_MOD_##_axis, \ | |
735 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
736 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ | |
737 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
738 | .scan_index = AXIS_##_axis, \ | |
739 | .scan_type = { \ | |
740 | .sign = 's', \ | |
741 | .realbits = 16, \ | |
742 | .storagebits = 16, \ | |
743 | }, \ | |
744 | .event_spec = &bmg160_event, \ | |
745 | .num_event_specs = 1 \ | |
746 | } | |
747 | ||
748 | static const struct iio_chan_spec bmg160_channels[] = { | |
749 | { | |
750 | .type = IIO_TEMP, | |
751 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
752 | BIT(IIO_CHAN_INFO_SCALE) | | |
753 | BIT(IIO_CHAN_INFO_OFFSET), | |
754 | .scan_index = -1, | |
755 | }, | |
756 | BMG160_CHANNEL(X), | |
757 | BMG160_CHANNEL(Y), | |
758 | BMG160_CHANNEL(Z), | |
759 | IIO_CHAN_SOFT_TIMESTAMP(3), | |
760 | }; | |
761 | ||
762 | static const struct iio_info bmg160_info = { | |
763 | .attrs = &bmg160_attrs_group, | |
764 | .read_raw = bmg160_read_raw, | |
765 | .write_raw = bmg160_write_raw, | |
766 | .read_event_value = bmg160_read_event, | |
767 | .write_event_value = bmg160_write_event, | |
768 | .write_event_config = bmg160_write_event_config, | |
769 | .read_event_config = bmg160_read_event_config, | |
22b46c45 SP |
770 | .driver_module = THIS_MODULE, |
771 | }; | |
772 | ||
773 | static irqreturn_t bmg160_trigger_handler(int irq, void *p) | |
774 | { | |
775 | struct iio_poll_func *pf = p; | |
776 | struct iio_dev *indio_dev = pf->indio_dev; | |
777 | struct bmg160_data *data = iio_priv(indio_dev); | |
778 | int bit, ret, i = 0; | |
c6c9e995 | 779 | unsigned int val; |
22b46c45 SP |
780 | |
781 | mutex_lock(&data->mutex); | |
70dddeee | 782 | for_each_set_bit(bit, indio_dev->active_scan_mask, |
22b46c45 | 783 | indio_dev->masklength) { |
c6c9e995 MSP |
784 | ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(bit), |
785 | &val, 2); | |
22b46c45 SP |
786 | if (ret < 0) { |
787 | mutex_unlock(&data->mutex); | |
788 | goto err; | |
789 | } | |
790 | data->buffer[i++] = ret; | |
791 | } | |
792 | mutex_unlock(&data->mutex); | |
793 | ||
794 | iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, | |
eb219101 | 795 | pf->timestamp); |
22b46c45 SP |
796 | err: |
797 | iio_trigger_notify_done(indio_dev->trig); | |
798 | ||
799 | return IRQ_HANDLED; | |
800 | } | |
801 | ||
802 | static int bmg160_trig_try_reen(struct iio_trigger *trig) | |
803 | { | |
804 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
805 | struct bmg160_data *data = iio_priv(indio_dev); | |
806 | int ret; | |
807 | ||
808 | /* new data interrupts don't need ack */ | |
809 | if (data->dready_trigger_on) | |
810 | return 0; | |
811 | ||
812 | /* Set latched mode interrupt and clear any latched interrupt */ | |
c6c9e995 MSP |
813 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
814 | BMG160_INT_MODE_LATCH_INT | | |
815 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 816 | if (ret < 0) { |
74e04345 | 817 | dev_err(data->dev, "Error writing reg_rst_latch\n"); |
22b46c45 SP |
818 | return ret; |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig, | |
825 | bool state) | |
826 | { | |
827 | struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); | |
828 | struct bmg160_data *data = iio_priv(indio_dev); | |
829 | int ret; | |
830 | ||
831 | mutex_lock(&data->mutex); | |
832 | ||
833 | if (!state && data->ev_enable_state && data->motion_trigger_on) { | |
834 | data->motion_trigger_on = false; | |
835 | mutex_unlock(&data->mutex); | |
836 | return 0; | |
837 | } | |
838 | ||
839 | /* | |
840 | * Refer to comment in bmg160_write_event_config for | |
841 | * enable/disable operation order | |
842 | */ | |
843 | ret = bmg160_set_power_state(data, state); | |
844 | if (ret < 0) { | |
845 | mutex_unlock(&data->mutex); | |
846 | return ret; | |
847 | } | |
848 | if (data->motion_trig == trig) | |
849 | ret = bmg160_setup_any_motion_interrupt(data, state); | |
850 | else | |
851 | ret = bmg160_setup_new_data_interrupt(data, state); | |
852 | if (ret < 0) { | |
10bef289 | 853 | bmg160_set_power_state(data, false); |
22b46c45 SP |
854 | mutex_unlock(&data->mutex); |
855 | return ret; | |
856 | } | |
857 | if (data->motion_trig == trig) | |
858 | data->motion_trigger_on = state; | |
859 | else | |
860 | data->dready_trigger_on = state; | |
861 | ||
862 | mutex_unlock(&data->mutex); | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
867 | static const struct iio_trigger_ops bmg160_trigger_ops = { | |
868 | .set_trigger_state = bmg160_data_rdy_trigger_set_state, | |
869 | .try_reenable = bmg160_trig_try_reen, | |
870 | .owner = THIS_MODULE, | |
871 | }; | |
872 | ||
873 | static irqreturn_t bmg160_event_handler(int irq, void *private) | |
874 | { | |
875 | struct iio_dev *indio_dev = private; | |
876 | struct bmg160_data *data = iio_priv(indio_dev); | |
877 | int ret; | |
878 | int dir; | |
c6c9e995 | 879 | unsigned int val; |
22b46c45 | 880 | |
c6c9e995 | 881 | ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val); |
22b46c45 | 882 | if (ret < 0) { |
74e04345 | 883 | dev_err(data->dev, "Error reading reg_int_status2\n"); |
22b46c45 SP |
884 | goto ack_intr_status; |
885 | } | |
886 | ||
c6c9e995 | 887 | if (val & 0x08) |
22b46c45 SP |
888 | dir = IIO_EV_DIR_RISING; |
889 | else | |
890 | dir = IIO_EV_DIR_FALLING; | |
891 | ||
c6c9e995 | 892 | if (val & BMG160_ANY_MOTION_BIT_X) |
22b46c45 SP |
893 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
894 | 0, | |
cb80f6a3 SP |
895 | IIO_MOD_X, |
896 | IIO_EV_TYPE_ROC, | |
897 | dir), | |
eb219101 | 898 | iio_get_time_ns()); |
c6c9e995 | 899 | if (val & BMG160_ANY_MOTION_BIT_Y) |
cb80f6a3 SP |
900 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
901 | 0, | |
902 | IIO_MOD_Y, | |
903 | IIO_EV_TYPE_ROC, | |
904 | dir), | |
eb219101 | 905 | iio_get_time_ns()); |
c6c9e995 | 906 | if (val & BMG160_ANY_MOTION_BIT_Z) |
cb80f6a3 SP |
907 | iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL, |
908 | 0, | |
909 | IIO_MOD_Z, | |
22b46c45 SP |
910 | IIO_EV_TYPE_ROC, |
911 | dir), | |
eb219101 | 912 | iio_get_time_ns()); |
22b46c45 SP |
913 | |
914 | ack_intr_status: | |
915 | if (!data->dready_trigger_on) { | |
c6c9e995 MSP |
916 | ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH, |
917 | BMG160_INT_MODE_LATCH_INT | | |
918 | BMG160_INT_MODE_LATCH_RESET); | |
22b46c45 | 919 | if (ret < 0) |
74e04345 | 920 | dev_err(data->dev, |
22b46c45 SP |
921 | "Error writing reg_rst_latch\n"); |
922 | } | |
923 | ||
924 | return IRQ_HANDLED; | |
925 | } | |
926 | ||
927 | static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private) | |
928 | { | |
929 | struct iio_dev *indio_dev = private; | |
930 | struct bmg160_data *data = iio_priv(indio_dev); | |
931 | ||
22b46c45 SP |
932 | if (data->dready_trigger_on) |
933 | iio_trigger_poll(data->dready_trig); | |
934 | else if (data->motion_trigger_on) | |
935 | iio_trigger_poll(data->motion_trig); | |
936 | ||
937 | if (data->ev_enable_state) | |
938 | return IRQ_WAKE_THREAD; | |
939 | else | |
940 | return IRQ_HANDLED; | |
941 | ||
942 | } | |
943 | ||
00e0c8e8 VD |
944 | static int bmg160_buffer_preenable(struct iio_dev *indio_dev) |
945 | { | |
946 | struct bmg160_data *data = iio_priv(indio_dev); | |
947 | ||
948 | return bmg160_set_power_state(data, true); | |
949 | } | |
950 | ||
951 | static int bmg160_buffer_postdisable(struct iio_dev *indio_dev) | |
952 | { | |
953 | struct bmg160_data *data = iio_priv(indio_dev); | |
954 | ||
955 | return bmg160_set_power_state(data, false); | |
956 | } | |
957 | ||
958 | static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = { | |
959 | .preenable = bmg160_buffer_preenable, | |
960 | .postenable = iio_triggered_buffer_postenable, | |
961 | .predisable = iio_triggered_buffer_predisable, | |
962 | .postdisable = bmg160_buffer_postdisable, | |
963 | }; | |
964 | ||
5d889abb | 965 | static int bmg160_gpio_probe(struct bmg160_data *data) |
3a0888ed | 966 | |
22b46c45 | 967 | { |
22b46c45 SP |
968 | struct device *dev; |
969 | struct gpio_desc *gpio; | |
22b46c45 | 970 | |
5d889abb | 971 | dev = data->dev; |
22b46c45 SP |
972 | |
973 | /* data ready gpio interrupt pin */ | |
b457f53a | 974 | gpio = devm_gpiod_get_index(dev, BMG160_GPIO_NAME, 0, GPIOD_IN); |
22b46c45 SP |
975 | if (IS_ERR(gpio)) { |
976 | dev_err(dev, "acpi gpio get index failed\n"); | |
977 | return PTR_ERR(gpio); | |
978 | } | |
979 | ||
5d889abb | 980 | data->irq = gpiod_to_irq(gpio); |
22b46c45 | 981 | |
5d889abb MSP |
982 | dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), |
983 | data->irq); | |
22b46c45 | 984 | |
5d889abb | 985 | return 0; |
22b46c45 SP |
986 | } |
987 | ||
3a0888ed IT |
988 | static const char *bmg160_match_acpi_device(struct device *dev) |
989 | { | |
990 | const struct acpi_device_id *id; | |
991 | ||
992 | id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
993 | if (!id) | |
994 | return NULL; | |
995 | ||
996 | return dev_name(dev); | |
997 | } | |
998 | ||
22b46c45 SP |
999 | static int bmg160_probe(struct i2c_client *client, |
1000 | const struct i2c_device_id *id) | |
1001 | { | |
1002 | struct bmg160_data *data; | |
1003 | struct iio_dev *indio_dev; | |
1004 | int ret; | |
3a0888ed | 1005 | const char *name = NULL; |
c6c9e995 | 1006 | struct regmap *regmap; |
5d889abb | 1007 | struct device *dev = &client->dev; |
c6c9e995 MSP |
1008 | |
1009 | regmap = devm_regmap_init_i2c(client, &bmg160_regmap_i2c_conf); | |
1010 | if (IS_ERR(regmap)) { | |
1011 | dev_err(&client->dev, "Failed to register i2c regmap %d\n", | |
1012 | (int)PTR_ERR(regmap)); | |
1013 | return PTR_ERR(regmap); | |
1014 | } | |
22b46c45 SP |
1015 | |
1016 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); | |
1017 | if (!indio_dev) | |
1018 | return -ENOMEM; | |
1019 | ||
1020 | data = iio_priv(indio_dev); | |
5d889abb MSP |
1021 | dev_set_drvdata(dev, indio_dev); |
1022 | data->dev = dev; | |
1023 | data->irq = client->irq; | |
22b46c45 SP |
1024 | |
1025 | ret = bmg160_chip_init(data); | |
1026 | if (ret < 0) | |
1027 | return ret; | |
1028 | ||
1029 | mutex_init(&data->mutex); | |
1030 | ||
3a0888ed IT |
1031 | if (id) |
1032 | name = id->name; | |
1033 | ||
5d889abb MSP |
1034 | if (ACPI_HANDLE(dev)) |
1035 | name = bmg160_match_acpi_device(dev); | |
3a0888ed | 1036 | |
5d889abb | 1037 | indio_dev->dev.parent = dev; |
22b46c45 SP |
1038 | indio_dev->channels = bmg160_channels; |
1039 | indio_dev->num_channels = ARRAY_SIZE(bmg160_channels); | |
3a0888ed | 1040 | indio_dev->name = name; |
22b46c45 SP |
1041 | indio_dev->modes = INDIO_DIRECT_MODE; |
1042 | indio_dev->info = &bmg160_info; | |
1043 | ||
5d889abb MSP |
1044 | if (data->irq <= 0) |
1045 | bmg160_gpio_probe(data); | |
22b46c45 | 1046 | |
5d889abb MSP |
1047 | if (data->irq > 0) { |
1048 | ret = devm_request_threaded_irq(dev, | |
1049 | data->irq, | |
22b46c45 SP |
1050 | bmg160_data_rdy_trig_poll, |
1051 | bmg160_event_handler, | |
1052 | IRQF_TRIGGER_RISING, | |
1053 | BMG160_IRQ_NAME, | |
1054 | indio_dev); | |
1055 | if (ret) | |
1056 | return ret; | |
1057 | ||
5d889abb | 1058 | data->dready_trig = devm_iio_trigger_alloc(dev, |
22b46c45 SP |
1059 | "%s-dev%d", |
1060 | indio_dev->name, | |
1061 | indio_dev->id); | |
1062 | if (!data->dready_trig) | |
1063 | return -ENOMEM; | |
1064 | ||
5d889abb | 1065 | data->motion_trig = devm_iio_trigger_alloc(dev, |
22b46c45 SP |
1066 | "%s-any-motion-dev%d", |
1067 | indio_dev->name, | |
1068 | indio_dev->id); | |
1069 | if (!data->motion_trig) | |
1070 | return -ENOMEM; | |
1071 | ||
5d889abb | 1072 | data->dready_trig->dev.parent = dev; |
22b46c45 SP |
1073 | data->dready_trig->ops = &bmg160_trigger_ops; |
1074 | iio_trigger_set_drvdata(data->dready_trig, indio_dev); | |
1075 | ret = iio_trigger_register(data->dready_trig); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
5d889abb | 1079 | data->motion_trig->dev.parent = dev; |
22b46c45 SP |
1080 | data->motion_trig->ops = &bmg160_trigger_ops; |
1081 | iio_trigger_set_drvdata(data->motion_trig, indio_dev); | |
1082 | ret = iio_trigger_register(data->motion_trig); | |
1083 | if (ret) { | |
1084 | data->motion_trig = NULL; | |
1085 | goto err_trigger_unregister; | |
1086 | } | |
00e0c8e8 | 1087 | } |
22b46c45 | 1088 | |
00e0c8e8 VD |
1089 | ret = iio_triggered_buffer_setup(indio_dev, |
1090 | iio_pollfunc_store_time, | |
1091 | bmg160_trigger_handler, | |
1092 | &bmg160_buffer_setup_ops); | |
1093 | if (ret < 0) { | |
5d889abb | 1094 | dev_err(dev, |
00e0c8e8 VD |
1095 | "iio triggered buffer setup failed\n"); |
1096 | goto err_trigger_unregister; | |
22b46c45 SP |
1097 | } |
1098 | ||
1099 | ret = iio_device_register(indio_dev); | |
1100 | if (ret < 0) { | |
5d889abb | 1101 | dev_err(dev, "unable to register iio device\n"); |
22b46c45 SP |
1102 | goto err_buffer_cleanup; |
1103 | } | |
1104 | ||
5d889abb | 1105 | ret = pm_runtime_set_active(dev); |
22b46c45 SP |
1106 | if (ret) |
1107 | goto err_iio_unregister; | |
1108 | ||
5d889abb MSP |
1109 | pm_runtime_enable(dev); |
1110 | pm_runtime_set_autosuspend_delay(dev, | |
22b46c45 | 1111 | BMG160_AUTO_SUSPEND_DELAY_MS); |
5d889abb | 1112 | pm_runtime_use_autosuspend(dev); |
22b46c45 SP |
1113 | |
1114 | return 0; | |
1115 | ||
1116 | err_iio_unregister: | |
1117 | iio_device_unregister(indio_dev); | |
1118 | err_buffer_cleanup: | |
00e0c8e8 | 1119 | iio_triggered_buffer_cleanup(indio_dev); |
22b46c45 SP |
1120 | err_trigger_unregister: |
1121 | if (data->dready_trig) | |
1122 | iio_trigger_unregister(data->dready_trig); | |
1123 | if (data->motion_trig) | |
1124 | iio_trigger_unregister(data->motion_trig); | |
1125 | ||
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | static int bmg160_remove(struct i2c_client *client) | |
1130 | { | |
1131 | struct iio_dev *indio_dev = i2c_get_clientdata(client); | |
1132 | struct bmg160_data *data = iio_priv(indio_dev); | |
1133 | ||
1134 | pm_runtime_disable(&client->dev); | |
1135 | pm_runtime_set_suspended(&client->dev); | |
1136 | pm_runtime_put_noidle(&client->dev); | |
1137 | ||
1138 | iio_device_unregister(indio_dev); | |
00e0c8e8 | 1139 | iio_triggered_buffer_cleanup(indio_dev); |
22b46c45 SP |
1140 | |
1141 | if (data->dready_trig) { | |
22b46c45 SP |
1142 | iio_trigger_unregister(data->dready_trig); |
1143 | iio_trigger_unregister(data->motion_trig); | |
1144 | } | |
1145 | ||
1146 | mutex_lock(&data->mutex); | |
1147 | bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND); | |
1148 | mutex_unlock(&data->mutex); | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | #ifdef CONFIG_PM_SLEEP | |
1154 | static int bmg160_suspend(struct device *dev) | |
1155 | { | |
ebc6eb59 | 1156 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1157 | struct bmg160_data *data = iio_priv(indio_dev); |
1158 | ||
1159 | mutex_lock(&data->mutex); | |
1160 | bmg160_set_mode(data, BMG160_MODE_SUSPEND); | |
1161 | mutex_unlock(&data->mutex); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static int bmg160_resume(struct device *dev) | |
1167 | { | |
ebc6eb59 | 1168 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1169 | struct bmg160_data *data = iio_priv(indio_dev); |
1170 | ||
1171 | mutex_lock(&data->mutex); | |
1172 | if (data->dready_trigger_on || data->motion_trigger_on || | |
1173 | data->ev_enable_state) | |
1174 | bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
1175 | mutex_unlock(&data->mutex); | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | #endif | |
1180 | ||
6f0a13f2 | 1181 | #ifdef CONFIG_PM |
22b46c45 SP |
1182 | static int bmg160_runtime_suspend(struct device *dev) |
1183 | { | |
ebc6eb59 | 1184 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 | 1185 | struct bmg160_data *data = iio_priv(indio_dev); |
10bef289 | 1186 | int ret; |
22b46c45 | 1187 | |
10bef289 SP |
1188 | ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND); |
1189 | if (ret < 0) { | |
74e04345 | 1190 | dev_err(data->dev, "set mode failed\n"); |
10bef289 SP |
1191 | return -EAGAIN; |
1192 | } | |
1193 | ||
1194 | return 0; | |
22b46c45 SP |
1195 | } |
1196 | ||
1197 | static int bmg160_runtime_resume(struct device *dev) | |
1198 | { | |
ebc6eb59 | 1199 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
22b46c45 SP |
1200 | struct bmg160_data *data = iio_priv(indio_dev); |
1201 | int ret; | |
1202 | ||
1203 | ret = bmg160_set_mode(data, BMG160_MODE_NORMAL); | |
1204 | if (ret < 0) | |
1205 | return ret; | |
1206 | ||
1207 | msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS); | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | #endif | |
1212 | ||
1213 | static const struct dev_pm_ops bmg160_pm_ops = { | |
1214 | SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume) | |
1215 | SET_RUNTIME_PM_OPS(bmg160_runtime_suspend, | |
1216 | bmg160_runtime_resume, NULL) | |
1217 | }; | |
1218 | ||
1219 | static const struct acpi_device_id bmg160_acpi_match[] = { | |
1220 | {"BMG0160", 0}, | |
3a0888ed IT |
1221 | {"BMI055B", 0}, |
1222 | {}, | |
22b46c45 | 1223 | }; |
3a0888ed | 1224 | |
22b46c45 SP |
1225 | MODULE_DEVICE_TABLE(acpi, bmg160_acpi_match); |
1226 | ||
1227 | static const struct i2c_device_id bmg160_id[] = { | |
1228 | {"bmg160", 0}, | |
3a0888ed | 1229 | {"bmi055_gyro", 0}, |
22b46c45 SP |
1230 | {} |
1231 | }; | |
1232 | ||
1233 | MODULE_DEVICE_TABLE(i2c, bmg160_id); | |
1234 | ||
1235 | static struct i2c_driver bmg160_driver = { | |
1236 | .driver = { | |
1237 | .name = BMG160_DRV_NAME, | |
1238 | .acpi_match_table = ACPI_PTR(bmg160_acpi_match), | |
1239 | .pm = &bmg160_pm_ops, | |
1240 | }, | |
1241 | .probe = bmg160_probe, | |
1242 | .remove = bmg160_remove, | |
1243 | .id_table = bmg160_id, | |
1244 | }; | |
1245 | module_i2c_driver(bmg160_driver); | |
1246 | ||
1247 | MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); | |
1248 | MODULE_LICENSE("GPL v2"); | |
1249 | MODULE_DESCRIPTION("BMG160 Gyro driver"); |