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IB/mlx5: Add tunneling offloads support
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
78984898 59#include <linux/mlx5/vport.h>
e126ba97 60#include "mlx5_ib.h"
e1f24a79 61#include "cmd.h"
c85023e1 62#include <linux/mlx5/vport.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fd65f1b8
MS		 101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
fc24fc5e
AS		 115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
5ec8c83e
AH		 122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
fc24fc5e 131
fd65f1b8 132 case NETDEV_CHANGE:
5ec8c83e 133 case NETDEV_UP:
88621dfe
AH		 134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
626bc02d 145 struct ib_event ibev = { };
fd65f1b8 146 enum ib_port_state port_state;
5ec8c83e 147
fd65f1b8
MS		 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
5ec8c83e 155 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
5ec8c83e
AH		 163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
88621dfe 167 }
fc24fc5e 168
5ec8c83e
AH		 169 default:
170 break;
171 }
fc24fc5e
AS		 172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
88621dfe
AH		 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
fc24fc5e
AS		 186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
f1b65df5
NO		 197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
095b0927
IT		 255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
3f89a643
AS		 257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 259 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 260 struct net_device *ndev, *upper;
3f89a643 261 enum ib_mtu ndev_ib_mtu;
c876a1b7 262 u16 qkey_viol_cntr;
f1b65df5 263 u32 eth_prot_oper;
095b0927 264 int err;
3f89a643 265
f1b65df5
NO		 266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
50f22fd8 268 */
095b0927
IT		 269 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
270 if (err)
271 return err;
f1b65df5
NO		 272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
3f89a643
AS		 275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
c876a1b7
LR		 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
095b0927 292 return 0;
3f89a643 293
88621dfe
AH		 294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
3f89a643
AS		 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 315 return 0;
3f89a643
AS		 316}
317
095b0927
IT		 318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
3cca2606 321{
095b0927
IT		 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
3cca2606
AS		 337 }
338
095b0927 339 switch (gid_type) {
3cca2606 340 case IB_GID_TYPE_IB:
095b0927 341 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 349 break;
350
351 default:
095b0927 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 353 }
354
095b0927
IT		 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
3cca2606
AS		 358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
095b0927 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
095b0927 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 372}
373
2811ba51
AS		 374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
ed88451e
MD		 394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
1b5daf11
MD		 415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
7fae6655
NO		 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
1b5daf11
MD		 420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
ebd61f68 433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
da7525d2
EBE		 440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
bd10838a 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 448
449 /* Check if HW supports 8 bytes standard atomic operations and capable
450 * of host endianness respond
451 */
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
1b5daf11
MD		 462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
1b5daf11
MD		 482
483 default:
484 return -EINVAL;
485 }
3f89a643
AS		 486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
1b5daf11
MD		 492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
1b5daf11
MD		 550
551 default:
552 return -EINVAL;
553 }
3f89a643
AS		 554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
1b5daf11
MD		 559}
560
561struct mlx5_reg_node_desc {
bd99fdea 562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
e126ba97 579static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
e126ba97
EC		 582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 584 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 585 int err = -ENOMEM;
288c01b7 586 int max_sq_desc;
e126ba97
EC		 587 int max_rq_sg;
588 int max_sq_sg;
e0238a6a 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
e126ba97 593
402ca536
BW		 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 601 return -EINVAL;
602
1b5daf11
MD		 603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
e126ba97 608
1b5daf11 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 610 if (err)
1b5daf11 611 return err;
e126ba97 612
1b5daf11
MD		 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
e126ba97 616
9603b61d
JM		 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
e126ba97
EC		 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 623 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 624
625 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 629 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 631 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 632 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 637 /* We support 'Gappy' memory registration too */
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 639 }
e126ba97 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 641 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643 /* At this stage no support for signature handover */
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
938fe83c 650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 652
402ca536 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655 /* Legacy bit to support old userspace libraries */
88115fe7 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 663
402ca536
BW		 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
31f69a82
YH		 673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 693 }
694
f0313965
ES		 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
03404e8a
MG		 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
1d54f890
YH		 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
cff5a0f3 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710 /* Legacy bit to support old userspace libraries */
cff5a0f3 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
cff5a0f3 714
da6d6ba3
MG		 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
1b5daf11
MD		 718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 720
721 props->max_mr_size = ~0ull;
e0238a6a 722 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
e126ba97 731 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 732 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 743 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 746 get_atomic_caps(dev, props);
81bea28f 747 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 753 props->max_ah = INT_MAX;
7c60bcbb
MB		 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 756
8cdd312c 757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 758 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
051f2630
LR		 763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
eff901d3
EC		 766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
31f69a82
YH		 769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
eb761894 780 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 781 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
782 props->tm_caps.max_num_tags =
eb761894 783 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 784 props->tm_caps.flags = IB_TM_CAP_RC;
785 props->tm_caps.max_ops =
eb761894 786 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 787 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 788 }
789
7e43a2a5
BW		 790 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
791 resp.cqe_comp_caps.max_num =
792 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
793 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
794 resp.cqe_comp_caps.supported_format =
795 MLX5_IB_CQE_RES_FORMAT_HASH |
796 MLX5_IB_CQE_RES_FORMAT_CSUM;
797 resp.response_length += sizeof(resp.cqe_comp_caps);
798 }
799
d949167d
BW		 800 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
801 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
802 MLX5_CAP_GEN(mdev, qos)) {
803 resp.packet_pacing_caps.qp_rate_limit_max =
804 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
805 resp.packet_pacing_caps.qp_rate_limit_min =
806 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
807 resp.packet_pacing_caps.supported_qpts |=
808 1 << IB_QPT_RAW_PACKET;
809 }
810 resp.response_length += sizeof(resp.packet_pacing_caps);
811 }
812
9f885201
LR		 813 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
814 uhw->outlen)) {
795b609c
BW		 815 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
816 resp.mlx5_ib_support_multi_pkt_send_wqes =
817 MLX5_IB_ALLOW_MPW;
050da902
BW		 818
819 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
820 resp.mlx5_ib_support_multi_pkt_send_wqes |=
821 MLX5_IB_SUPPORT_EMPW;
822
9f885201
LR		 823 resp.response_length +=
824 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
825 }
826
de57f2ad
GL		 827 if (field_avail(typeof(resp), flags, uhw->outlen)) {
828 resp.response_length += sizeof(resp.flags);
7a0c8f42 829
de57f2ad
GL		 830 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
831 resp.flags |=
832 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 833
834 if (MLX5_CAP_GEN(mdev, cqe_128_always))
835 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 836 }
9f885201 837
96dc3fc5
NO		 838 if (field_avail(typeof(resp), sw_parsing_caps,
839 uhw->outlen)) {
840 resp.response_length += sizeof(resp.sw_parsing_caps);
841 if (MLX5_CAP_ETH(mdev, swp)) {
842 resp.sw_parsing_caps.sw_parsing_offloads |=
843 MLX5_IB_SW_PARSING;
844
845 if (MLX5_CAP_ETH(mdev, swp_csum))
846 resp.sw_parsing_caps.sw_parsing_offloads |=
847 MLX5_IB_SW_PARSING_CSUM;
848
849 if (MLX5_CAP_ETH(mdev, swp_lso))
850 resp.sw_parsing_caps.sw_parsing_offloads |=
851 MLX5_IB_SW_PARSING_LSO;
852
853 if (resp.sw_parsing_caps.sw_parsing_offloads)
854 resp.sw_parsing_caps.supported_qpts =
855 BIT(IB_QPT_RAW_PACKET);
856 }
857 }
858
b4f34597
NO		 859 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
860 resp.response_length += sizeof(resp.striding_rq_caps);
861 if (MLX5_CAP_GEN(mdev, striding_rq)) {
862 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
863 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
864 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
865 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
866 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
867 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
868 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
869 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
870 resp.striding_rq_caps.supported_qpts =
871 BIT(IB_QPT_RAW_PACKET);
872 }
873 }
874
f95ef6cb
MG		 875 if (field_avail(typeof(resp), tunnel_offloads_caps,
876 uhw->outlen)) {
877 resp.response_length += sizeof(resp.tunnel_offloads_caps);
878 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
879 resp.tunnel_offloads_caps |=
880 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
881 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
882 resp.tunnel_offloads_caps |=
883 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
884 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
885 resp.tunnel_offloads_caps |=
886 MLX5_IB_TUNNELED_OFFLOADS_GRE;
887 }
888
402ca536
BW		 889 if (uhw->outlen) {
890 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
891
892 if (err)
893 return err;
894 }
895
1b5daf11 896 return 0;
e126ba97
EC		 897}
898
1b5daf11
MD		 899enum mlx5_ib_width {
900 MLX5_IB_WIDTH_1X = 1 << 0,
901 MLX5_IB_WIDTH_2X = 1 << 1,
902 MLX5_IB_WIDTH_4X = 1 << 2,
903 MLX5_IB_WIDTH_8X = 1 << 3,
904 MLX5_IB_WIDTH_12X = 1 << 4
905};
906
907static int translate_active_width(struct ib_device *ibdev, u8 active_width,
908 u8 *ib_width)
e126ba97
EC		 909{
910 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 911 int err = 0;
912
913 if (active_width & MLX5_IB_WIDTH_1X) {
914 *ib_width = IB_WIDTH_1X;
915 } else if (active_width & MLX5_IB_WIDTH_2X) {
916 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
917 (int)active_width);
918 err = -EINVAL;
919 } else if (active_width & MLX5_IB_WIDTH_4X) {
920 *ib_width = IB_WIDTH_4X;
921 } else if (active_width & MLX5_IB_WIDTH_8X) {
922 *ib_width = IB_WIDTH_8X;
923 } else if (active_width & MLX5_IB_WIDTH_12X) {
924 *ib_width = IB_WIDTH_12X;
925 } else {
926 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
927 (int)active_width);
928 err = -EINVAL;
e126ba97
EC		 929 }
930
1b5daf11
MD		 931 return err;
932}
e126ba97 933
1b5daf11
MD		 934static int mlx5_mtu_to_ib_mtu(int mtu)
935{
936 switch (mtu) {
937 case 256: return 1;
938 case 512: return 2;
939 case 1024: return 3;
940 case 2048: return 4;
941 case 4096: return 5;
942 default:
943 pr_warn("invalid mtu\n");
944 return -1;
e126ba97 945 }
1b5daf11 946}
e126ba97 947
1b5daf11
MD		 948enum ib_max_vl_num {
949 __IB_MAX_VL_0 = 1,
950 __IB_MAX_VL_0_1 = 2,
951 __IB_MAX_VL_0_3 = 3,
952 __IB_MAX_VL_0_7 = 4,
953 __IB_MAX_VL_0_14 = 5,
954};
e126ba97 955
1b5daf11
MD		 956enum mlx5_vl_hw_cap {
957 MLX5_VL_HW_0 = 1,
958 MLX5_VL_HW_0_1 = 2,
959 MLX5_VL_HW_0_2 = 3,
960 MLX5_VL_HW_0_3 = 4,
961 MLX5_VL_HW_0_4 = 5,
962 MLX5_VL_HW_0_5 = 6,
963 MLX5_VL_HW_0_6 = 7,
964 MLX5_VL_HW_0_7 = 8,
965 MLX5_VL_HW_0_14 = 15
966};
e126ba97 967
1b5daf11
MD		 968static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
969 u8 *max_vl_num)
970{
971 switch (vl_hw_cap) {
972 case MLX5_VL_HW_0:
973 *max_vl_num = __IB_MAX_VL_0;
974 break;
975 case MLX5_VL_HW_0_1:
976 *max_vl_num = __IB_MAX_VL_0_1;
977 break;
978 case MLX5_VL_HW_0_3:
979 *max_vl_num = __IB_MAX_VL_0_3;
980 break;
981 case MLX5_VL_HW_0_7:
982 *max_vl_num = __IB_MAX_VL_0_7;
983 break;
984 case MLX5_VL_HW_0_14:
985 *max_vl_num = __IB_MAX_VL_0_14;
986 break;
e126ba97 987
1b5daf11
MD		 988 default:
989 return -EINVAL;
e126ba97 990 }
e126ba97 991
1b5daf11 992 return 0;
e126ba97
EC		 993}
994
1b5daf11
MD		 995static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
996 struct ib_port_attr *props)
e126ba97 997{
1b5daf11
MD		 998 struct mlx5_ib_dev *dev = to_mdev(ibdev);
999 struct mlx5_core_dev *mdev = dev->mdev;
1000 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1001 u16 max_mtu;
1002 u16 oper_mtu;
1b5daf11
MD		 1003 int err;
1004 u8 ib_link_width_oper;
1005 u8 vl_hw_cap;
e126ba97 1006
1b5daf11
MD		 1007 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1008 if (!rep) {
1009 err = -ENOMEM;
e126ba97 1010 goto out;
e126ba97 1011 }
e126ba97 1012
c4550c63 1013 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1014
1b5daf11 1015 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1016 if (err)
1017 goto out;
1018
1b5daf11
MD		 1019 props->lid = rep->lid;
1020 props->lmc = rep->lmc;
1021 props->sm_lid = rep->sm_lid;
1022 props->sm_sl = rep->sm_sl;
1023 props->state = rep->vport_state;
1024 props->phys_state = rep->port_physical_state;
1025 props->port_cap_flags = rep->cap_mask1;
1026 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1027 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1028 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1029 props->bad_pkey_cntr = rep->pkey_violation_counter;
1030 props->qkey_viol_cntr = rep->qkey_violation_counter;
1031 props->subnet_timeout = rep->subnet_timeout;
1032 props->init_type_reply = rep->init_type_reply;
eff901d3 1033 props->grh_required = rep->grh_required;
e126ba97 1034
1b5daf11
MD		 1035 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1036 if (err)
e126ba97 1037 goto out;
e126ba97 1038
1b5daf11
MD		 1039 err = translate_active_width(ibdev, ib_link_width_oper,
1040 &props->active_width);
1041 if (err)
1042 goto out;
d5beb7f2 1043 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1044 if (err)
1045 goto out;
1046
facc9699 1047 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1048
1b5daf11 1049 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1050
facc9699 1051 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1052
1b5daf11 1053 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1054
1b5daf11
MD		 1055 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1056 if (err)
1057 goto out;
e126ba97 1058
1b5daf11
MD		 1059 err = translate_max_vl_num(ibdev, vl_hw_cap,
1060 &props->max_vl_num);
e126ba97 1061out:
1b5daf11 1062 kfree(rep);
e126ba97
EC		 1063 return err;
1064}
1065
1b5daf11
MD		 1066int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1067 struct ib_port_attr *props)
e126ba97 1068{
095b0927
IT		 1069 unsigned int count;
1070 int ret;
1071
1b5daf11
MD		 1072 switch (mlx5_get_vport_access_method(ibdev)) {
1073 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1074 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1075 break;
e126ba97 1076
1b5daf11 1077 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1078 ret = mlx5_query_hca_port(ibdev, port, props);
1079 break;
e126ba97 1080
3f89a643 1081 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1082 ret = mlx5_query_port_roce(ibdev, port, props);
1083 break;
3f89a643 1084
1b5daf11 1085 default:
095b0927
IT		 1086 ret = -EINVAL;
1087 }
1088
1089 if (!ret && props) {
1090 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1091 props->gid_tbl_len -= count;
1b5daf11 1092 }
095b0927 1093 return ret;
1b5daf11 1094}
e126ba97 1095
1b5daf11
MD		 1096static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1097 union ib_gid *gid)
1098{
1099 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1100 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1101
1b5daf11
MD		 1102 switch (mlx5_get_vport_access_method(ibdev)) {
1103 case MLX5_VPORT_ACCESS_METHOD_MAD:
1104 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1105
1b5daf11
MD		 1106 case MLX5_VPORT_ACCESS_METHOD_HCA:
1107 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1108
1109 default:
1110 return -EINVAL;
1111 }
e126ba97 1112
e126ba97
EC		 1113}
1114
1b5daf11
MD		 1115static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1116 u16 *pkey)
1117{
1118 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1119 struct mlx5_core_dev *mdev = dev->mdev;
1120
1121 switch (mlx5_get_vport_access_method(ibdev)) {
1122 case MLX5_VPORT_ACCESS_METHOD_MAD:
1123 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1124
1125 case MLX5_VPORT_ACCESS_METHOD_HCA:
1126 case MLX5_VPORT_ACCESS_METHOD_NIC:
1127 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1128 pkey);
1129 default:
1130 return -EINVAL;
1131 }
1132}
e126ba97
EC		 1133
1134static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1135 struct ib_device_modify *props)
1136{
1137 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1138 struct mlx5_reg_node_desc in;
1139 struct mlx5_reg_node_desc out;
1140 int err;
1141
1142 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1143 return -EOPNOTSUPP;
1144
1145 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1146 return 0;
1147
1148 /*
1149 * If possible, pass node desc to FW, so it can generate
1150 * a 144 trap. If cmd fails, just ignore.
1151 */
bd99fdea 1152 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1153 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1154 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1155 if (err)
1156 return err;
1157
bd99fdea 1158 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1159
1160 return err;
1161}
1162
cdbe33d0
EC		 1163static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1164 u32 value)
1165{
1166 struct mlx5_hca_vport_context ctx = {};
1167 int err;
1168
1169 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1170 port_num, 0, &ctx);
1171 if (err)
1172 return err;
1173
1174 if (~ctx.cap_mask1_perm & mask) {
1175 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1176 mask, ctx.cap_mask1_perm);
1177 return -EINVAL;
1178 }
1179
1180 ctx.cap_mask1 = value;
1181 ctx.cap_mask1_perm = mask;
1182 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1183 port_num, 0, &ctx);
1184
1185 return err;
1186}
1187
e126ba97
EC		 1188static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1189 struct ib_port_modify *props)
1190{
1191 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1192 struct ib_port_attr attr;
1193 u32 tmp;
1194 int err;
cdbe33d0
EC		 1195 u32 change_mask;
1196 u32 value;
1197 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1198 IB_LINK_LAYER_INFINIBAND);
1199
ec255879
MD		 1200 /* CM layer calls ib_modify_port() regardless of the link layer. For
1201 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1202 */
1203 if (!is_ib)
1204 return 0;
1205
cdbe33d0
EC		 1206 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1207 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1208 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1209 return set_port_caps_atomic(dev, port, change_mask, value);
1210 }
e126ba97
EC		 1211
1212 mutex_lock(&dev->cap_mask_mutex);
1213
c4550c63 1214 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1215 if (err)
1216 goto out;
1217
1218 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1219 ~props->clr_port_cap_mask;
1220
9603b61d 1221 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1222
1223out:
1224 mutex_unlock(&dev->cap_mask_mutex);
1225 return err;
1226}
1227
30aa60b3
EC		 1228static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1229{
1230 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1231 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1232}
1233
b037c29a
EC		 1234static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1235 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1236 u32 *num_sys_pages)
1237{
1238 int uars_per_sys_page;
1239 int bfregs_per_sys_page;
1240 int ref_bfregs = req->total_num_bfregs;
1241
1242 if (req->total_num_bfregs == 0)
1243 return -EINVAL;
1244
1245 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1246 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1247
1248 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1249 return -ENOMEM;
1250
1251 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1252 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1253 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1254 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1255
1256 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1257 return -EINVAL;
1258
9c2d33d4 1259 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1260 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1261 lib_uar_4k ? "yes" : "no", ref_bfregs,
1262 req->total_num_bfregs, *num_sys_pages);
1263
1264 return 0;
1265}
1266
1267static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1268{
1269 struct mlx5_bfreg_info *bfregi;
1270 int err;
1271 int i;
1272
1273 bfregi = &context->bfregi;
1274 for (i = 0; i < bfregi->num_sys_pages; i++) {
1275 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1276 if (err)
1277 goto error;
1278
1279 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1280 }
1281 return 0;
1282
1283error:
1284 for (--i; i >= 0; i--)
1285 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1286 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1287
1288 return err;
1289}
1290
1291static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1292{
1293 struct mlx5_bfreg_info *bfregi;
1294 int err;
1295 int i;
1296
1297 bfregi = &context->bfregi;
1298 for (i = 0; i < bfregi->num_sys_pages; i++) {
1299 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1300 if (err) {
1301 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1302 return err;
1303 }
1304 }
1305 return 0;
1306}
1307
c85023e1
HN		 1308static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1309{
1310 int err;
1311
1312 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1313 if (err)
1314 return err;
1315
1316 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1317 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1318 return err;
1319
1320 mutex_lock(&dev->lb_mutex);
1321 dev->user_td++;
1322
1323 if (dev->user_td == 2)
1324 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1325
1326 mutex_unlock(&dev->lb_mutex);
1327 return err;
1328}
1329
1330static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1331{
1332 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1333
1334 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1335 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1336 return;
1337
1338 mutex_lock(&dev->lb_mutex);
1339 dev->user_td--;
1340
1341 if (dev->user_td < 2)
1342 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1343
1344 mutex_unlock(&dev->lb_mutex);
1345}
1346
e126ba97
EC		 1347static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1348 struct ib_udata *udata)
1349{
1350 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1351 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1352 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1353 struct mlx5_ib_ucontext *context;
2f5ff264 1354 struct mlx5_bfreg_info *bfregi;
78c0f98c 1355 int ver;
e126ba97 1356 int err;
a168a41c
MD		 1357 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1358 max_cqe_version);
b037c29a 1359 bool lib_uar_4k;
e126ba97
EC		 1360
1361 if (!dev->ib_active)
1362 return ERR_PTR(-EAGAIN);
1363
e093111d 1364 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1365 ver = 0;
e093111d 1366 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1367 ver = 2;
1368 else
1369 return ERR_PTR(-EINVAL);
1370
e093111d 1371 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1372 if (err)
1373 return ERR_PTR(err);
1374
b368d7cb 1375 if (req.flags)
78c0f98c
EC		 1376 return ERR_PTR(-EINVAL);
1377
f72300c5 1378 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1379 return ERR_PTR(-EOPNOTSUPP);
1380
2f5ff264
EC		 1381 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1382 MLX5_NON_FP_BFREGS_PER_UAR);
1383 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1384 return ERR_PTR(-EINVAL);
1385
938fe83c 1386 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1387 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1388 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1389 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1390 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1391 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1392 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1393 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1394 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1395 resp.cqe_version = min_t(__u8,
1396 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1397 req.max_cqe_version);
30aa60b3
EC		 1398 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1399 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1400 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1401 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1402 resp.response_length = min(offsetof(typeof(resp), response_length) +
1403 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1404
1405 context = kzalloc(sizeof(*context), GFP_KERNEL);
1406 if (!context)
1407 return ERR_PTR(-ENOMEM);
1408
30aa60b3 1409 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1410 bfregi = &context->bfregi;
b037c29a
EC		 1411
1412 /* updates req->total_num_bfregs */
1413 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1414 if (err)
e126ba97 1415 goto out_ctx;
e126ba97 1416
b037c29a
EC		 1417 mutex_init(&bfregi->lock);
1418 bfregi->lib_uar_4k = lib_uar_4k;
1419 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1420 GFP_KERNEL);
b037c29a 1421 if (!bfregi->count) {
e126ba97 1422 err = -ENOMEM;
b037c29a 1423 goto out_ctx;
e126ba97
EC		 1424 }
1425
b037c29a
EC		 1426 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1427 sizeof(*bfregi->sys_pages),
1428 GFP_KERNEL);
1429 if (!bfregi->sys_pages) {
e126ba97 1430 err = -ENOMEM;
b037c29a 1431 goto out_count;
e126ba97
EC		 1432 }
1433
b037c29a
EC		 1434 err = allocate_uars(dev, context);
1435 if (err)
1436 goto out_sys_pages;
e126ba97 1437
b4cfe447
HE		 1438#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1439 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1440#endif
1441
7d0cc6ed
AK		 1442 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1443 if (!context->upd_xlt_page) {
1444 err = -ENOMEM;
1445 goto out_uars;
1446 }
1447 mutex_init(&context->upd_xlt_page_mutex);
1448
146d2f1a 1449 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1450 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1451 if (err)
7d0cc6ed 1452 goto out_page;
146d2f1a 1453 }
1454
7c2344c3 1455 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1456 INIT_LIST_HEAD(&context->db_page_list);
1457 mutex_init(&context->db_page_mutex);
1458
2f5ff264 1459 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1460 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1461
f72300c5
HA		 1462 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1463 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1464
402ca536 1465 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1466 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1467 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1468 resp.response_length += sizeof(resp.cmds_supp_uhw);
1469 }
1470
78984898
OG		 1471 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1472 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1473 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1474 resp.eth_min_inline++;
1475 }
1476 resp.response_length += sizeof(resp.eth_min_inline);
1477 }
1478
bc5c6eed
NO		 1479 /*
1480 * We don't want to expose information from the PCI bar that is located
1481 * after 4096 bytes, so if the arch only supports larger pages, let's
1482 * pretend we don't support reading the HCA's core clock. This is also
1483 * forced by mmap function.
1484 */
de8d6e02
EC		 1485 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1486 if (PAGE_SIZE <= 4096) {
1487 resp.comp_mask |=
1488 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1489 resp.hca_core_clock_offset =
1490 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1491 }
f72300c5 1492 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1493 sizeof(resp.reserved2);
b368d7cb
MB		 1494 }
1495
30aa60b3
EC		 1496 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1497 resp.response_length += sizeof(resp.log_uar_size);
1498
1499 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1500 resp.response_length += sizeof(resp.num_uars_per_page);
1501
b368d7cb 1502 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1503 if (err)
146d2f1a 1504 goto out_td;
e126ba97 1505
2f5ff264
EC		 1506 bfregi->ver = ver;
1507 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1508 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1509 context->lib_caps = req.lib_caps;
1510 print_lib_caps(dev, context->lib_caps);
f72300c5 1511
e126ba97
EC		 1512 return &context->ibucontext;
1513
146d2f1a 1514out_td:
1515 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1516 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1517
7d0cc6ed
AK		 1518out_page:
1519 free_page(context->upd_xlt_page);
1520
e126ba97 1521out_uars:
b037c29a 1522 deallocate_uars(dev, context);
e126ba97 1523
b037c29a
EC		 1524out_sys_pages:
1525 kfree(bfregi->sys_pages);
e126ba97 1526
b037c29a
EC		 1527out_count:
1528 kfree(bfregi->count);
e126ba97
EC		 1529
1530out_ctx:
1531 kfree(context);
b037c29a 1532
e126ba97
EC		 1533 return ERR_PTR(err);
1534}
1535
1536static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1537{
1538 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1539 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1540 struct mlx5_bfreg_info *bfregi;
e126ba97 1541
b037c29a 1542 bfregi = &context->bfregi;
146d2f1a 1543 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1544 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1545
7d0cc6ed 1546 free_page(context->upd_xlt_page);
b037c29a
EC		 1547 deallocate_uars(dev, context);
1548 kfree(bfregi->sys_pages);
2f5ff264 1549 kfree(bfregi->count);
e126ba97
EC		 1550 kfree(context);
1551
1552 return 0;
1553}
1554
b037c29a
EC		 1555static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1556 struct mlx5_bfreg_info *bfregi,
1557 int idx)
e126ba97 1558{
b037c29a
EC		 1559 int fw_uars_per_page;
1560
1561 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1562
1563 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1564 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1565}
1566
1567static int get_command(unsigned long offset)
1568{
1569 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1570}
1571
1572static int get_arg(unsigned long offset)
1573{
1574 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1575}
1576
1577static int get_index(unsigned long offset)
1578{
1579 return get_arg(offset);
1580}
1581
7c2344c3
MG		 1582static void mlx5_ib_vma_open(struct vm_area_struct *area)
1583{
1584 /* vma_open is called when a new VMA is created on top of our VMA. This
1585 * is done through either mremap flow or split_vma (usually due to
1586 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1587 * as this VMA is strongly hardware related. Therefore we set the
1588 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1589 * calling us again and trying to do incorrect actions. We assume that
1590 * the original VMA size is exactly a single page, and therefore all
1591 * "splitting" operation will not happen to it.
1592 */
1593 area->vm_ops = NULL;
1594}
1595
1596static void mlx5_ib_vma_close(struct vm_area_struct *area)
1597{
1598 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1599
1600 /* It's guaranteed that all VMAs opened on a FD are closed before the
1601 * file itself is closed, therefore no sync is needed with the regular
1602 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1603 * However need a sync with accessing the vma as part of
1604 * mlx5_ib_disassociate_ucontext.
1605 * The close operation is usually called under mm->mmap_sem except when
1606 * process is exiting.
1607 * The exiting case is handled explicitly as part of
1608 * mlx5_ib_disassociate_ucontext.
1609 */
1610 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1611
1612 /* setting the vma context pointer to null in the mlx5_ib driver's
1613 * private data, to protect a race condition in
1614 * mlx5_ib_disassociate_ucontext().
1615 */
1616 mlx5_ib_vma_priv_data->vma = NULL;
1617 list_del(&mlx5_ib_vma_priv_data->list);
1618 kfree(mlx5_ib_vma_priv_data);
1619}
1620
1621static const struct vm_operations_struct mlx5_ib_vm_ops = {
1622 .open = mlx5_ib_vma_open,
1623 .close = mlx5_ib_vma_close
1624};
1625
1626static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1627 struct mlx5_ib_ucontext *ctx)
1628{
1629 struct mlx5_ib_vma_private_data *vma_prv;
1630 struct list_head *vma_head = &ctx->vma_private_list;
1631
1632 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1633 if (!vma_prv)
1634 return -ENOMEM;
1635
1636 vma_prv->vma = vma;
1637 vma->vm_private_data = vma_prv;
1638 vma->vm_ops = &mlx5_ib_vm_ops;
1639
1640 list_add(&vma_prv->list, vma_head);
1641
1642 return 0;
1643}
1644
1645static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1646{
1647 int ret;
1648 struct vm_area_struct *vma;
1649 struct mlx5_ib_vma_private_data *vma_private, *n;
1650 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1651 struct task_struct *owning_process = NULL;
1652 struct mm_struct *owning_mm = NULL;
1653
1654 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1655 if (!owning_process)
1656 return;
1657
1658 owning_mm = get_task_mm(owning_process);
1659 if (!owning_mm) {
1660 pr_info("no mm, disassociate ucontext is pending task termination\n");
1661 while (1) {
1662 put_task_struct(owning_process);
1663 usleep_range(1000, 2000);
1664 owning_process = get_pid_task(ibcontext->tgid,
1665 PIDTYPE_PID);
1666 if (!owning_process ||
1667 owning_process->state == TASK_DEAD) {
1668 pr_info("disassociate ucontext done, task was terminated\n");
1669 /* in case task was dead need to release the
1670 * task struct.
1671 */
1672 if (owning_process)
1673 put_task_struct(owning_process);
1674 return;
1675 }
1676 }
1677 }
1678
1679 /* need to protect from a race on closing the vma as part of
1680 * mlx5_ib_vma_close.
1681 */
ecc7d83b 1682 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1683 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1684 list) {
1685 vma = vma_private->vma;
1686 ret = zap_vma_ptes(vma, vma->vm_start,
1687 PAGE_SIZE);
1688 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1689 /* context going to be destroyed, should
1690 * not access ops any more.
1691 */
13776612 1692 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1693 vma->vm_ops = NULL;
1694 list_del(&vma_private->list);
1695 kfree(vma_private);
1696 }
ecc7d83b 1697 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1698 mmput(owning_mm);
1699 put_task_struct(owning_process);
1700}
1701
37aa5c36
GL		 1702static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1703{
1704 switch (cmd) {
1705 case MLX5_IB_MMAP_WC_PAGE:
1706 return "WC";
1707 case MLX5_IB_MMAP_REGULAR_PAGE:
1708 return "best effort WC";
1709 case MLX5_IB_MMAP_NC_PAGE:
1710 return "NC";
1711 default:
1712 return NULL;
1713 }
1714}
1715
1716static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1717 struct vm_area_struct *vma,
1718 struct mlx5_ib_ucontext *context)
37aa5c36 1719{
2f5ff264 1720 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1721 int err;
1722 unsigned long idx;
1723 phys_addr_t pfn, pa;
1724 pgprot_t prot;
b037c29a
EC		 1725 int uars_per_page;
1726
1727 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1728 return -EINVAL;
1729
1730 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1731 idx = get_index(vma->vm_pgoff);
1732 if (idx % uars_per_page ||
1733 idx * uars_per_page >= bfregi->num_sys_pages) {
1734 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1735 return -EINVAL;
1736 }
37aa5c36
GL		 1737
1738 switch (cmd) {
1739 case MLX5_IB_MMAP_WC_PAGE:
1740/* Some architectures don't support WC memory */
1741#if defined(CONFIG_X86)
1742 if (!pat_enabled())
1743 return -EPERM;
1744#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1745 return -EPERM;
1746#endif
1747 /* fall through */
1748 case MLX5_IB_MMAP_REGULAR_PAGE:
1749 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1750 prot = pgprot_writecombine(vma->vm_page_prot);
1751 break;
1752 case MLX5_IB_MMAP_NC_PAGE:
1753 prot = pgprot_noncached(vma->vm_page_prot);
1754 break;
1755 default:
1756 return -EINVAL;
1757 }
1758
b037c29a 1759 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1760 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1761
1762 vma->vm_page_prot = prot;
1763 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1764 PAGE_SIZE, vma->vm_page_prot);
1765 if (err) {
1766 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1767 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1768 return -EAGAIN;
1769 }
1770
1771 pa = pfn << PAGE_SHIFT;
1772 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1773 vma->vm_start, &pa);
1774
7c2344c3 1775 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1776}
1777
e126ba97
EC		 1778static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1779{
1780 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1781 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1782 unsigned long command;
e126ba97
EC		 1783 phys_addr_t pfn;
1784
1785 command = get_command(vma->vm_pgoff);
1786 switch (command) {
37aa5c36
GL		 1787 case MLX5_IB_MMAP_WC_PAGE:
1788 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1789 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1790 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1791
1792 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1793 return -ENOSYS;
1794
d69e3bcf 1795 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1796 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1797 return -EINVAL;
1798
6cbac1e4 1799 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1800 return -EPERM;
1801
1802 /* Don't expose to user-space information it shouldn't have */
1803 if (PAGE_SIZE > 4096)
1804 return -EOPNOTSUPP;
1805
1806 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1807 pfn = (dev->mdev->iseg_base +
1808 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1809 PAGE_SHIFT;
1810 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1811 PAGE_SIZE, vma->vm_page_prot))
1812 return -EAGAIN;
1813
1814 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1815 vma->vm_start,
1816 (unsigned long long)pfn << PAGE_SHIFT);
1817 break;
d69e3bcf 1818
e126ba97
EC		 1819 default:
1820 return -EINVAL;
1821 }
1822
1823 return 0;
1824}
1825
e126ba97
EC		 1826static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1827 struct ib_ucontext *context,
1828 struct ib_udata *udata)
1829{
1830 struct mlx5_ib_alloc_pd_resp resp;
1831 struct mlx5_ib_pd *pd;
1832 int err;
1833
1834 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1835 if (!pd)
1836 return ERR_PTR(-ENOMEM);
1837
9603b61d 1838 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1839 if (err) {
1840 kfree(pd);
1841 return ERR_PTR(err);
1842 }
1843
1844 if (context) {
1845 resp.pdn = pd->pdn;
1846 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1847 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1848 kfree(pd);
1849 return ERR_PTR(-EFAULT);
1850 }
e126ba97
EC		 1851 }
1852
1853 return &pd->ibpd;
1854}
1855
1856static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1857{
1858 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1859 struct mlx5_ib_pd *mpd = to_mpd(pd);
1860
9603b61d 1861 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1862 kfree(mpd);
1863
1864 return 0;
1865}
1866
466fa6d2
MG		 1867enum {
1868 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1869 MATCH_CRITERIA_ENABLE_MISC_BIT,
1870 MATCH_CRITERIA_ENABLE_INNER_BIT
1871};
1872
1873#define HEADER_IS_ZERO(match_criteria, headers) \
1874 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1875 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1876
466fa6d2 1877static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1878{
466fa6d2 1879 u8 match_criteria_enable;
038d2ef8 1880
466fa6d2
MG		 1881 match_criteria_enable =
1882 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1883 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1884 match_criteria_enable |=
1885 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1886 MATCH_CRITERIA_ENABLE_MISC_BIT;
1887 match_criteria_enable |=
1888 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1889 MATCH_CRITERIA_ENABLE_INNER_BIT;
1890
1891 return match_criteria_enable;
038d2ef8
MG		 1892}
1893
ca0d4753
MG		 1894static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1895{
1896 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1897 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1898}
1899
2d1e697e
MR		 1900static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1901 bool inner)
1902{
1903 if (inner) {
1904 MLX5_SET(fte_match_set_misc,
1905 misc_c, inner_ipv6_flow_label, mask);
1906 MLX5_SET(fte_match_set_misc,
1907 misc_v, inner_ipv6_flow_label, val);
1908 } else {
1909 MLX5_SET(fte_match_set_misc,
1910 misc_c, outer_ipv6_flow_label, mask);
1911 MLX5_SET(fte_match_set_misc,
1912 misc_v, outer_ipv6_flow_label, val);
1913 }
1914}
1915
ca0d4753
MG		 1916static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1917{
1918 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1919 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1920 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1921 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1922}
1923
c47ac6ae
MG		 1924#define LAST_ETH_FIELD vlan_tag
1925#define LAST_IB_FIELD sl
ca0d4753 1926#define LAST_IPV4_FIELD tos
466fa6d2 1927#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1928#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1929#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1930#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1931#define LAST_DROP_FIELD size
c47ac6ae
MG		 1932
1933/* Field is the last supported field */
1934#define FIELDS_NOT_SUPPORTED(filter, field)\
1935 memchr_inv((void *)&filter.field +\
1936 sizeof(filter.field), 0,\
1937 sizeof(filter) -\
1938 offsetof(typeof(filter), field) -\
1939 sizeof(filter.field))
1940
19cc7524
AL		 1941#define IPV4_VERSION 4
1942#define IPV6_VERSION 6
1943static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1944 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1945 u32 *tag_id, bool *is_drop)
038d2ef8 1946{
466fa6d2
MG		 1947 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1948 misc_parameters);
1949 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1950 misc_parameters);
2d1e697e
MR		 1951 void *headers_c;
1952 void *headers_v;
19cc7524 1953 int match_ipv;
2d1e697e
MR		 1954
1955 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1956 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1957 inner_headers);
1958 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1959 inner_headers);
19cc7524
AL		 1960 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1961 ft_field_support.inner_ip_version);
2d1e697e
MR		 1962 } else {
1963 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1964 outer_headers);
1965 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1966 outer_headers);
19cc7524
AL		 1967 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1968 ft_field_support.outer_ip_version);
2d1e697e 1969 }
466fa6d2 1970
2d1e697e 1971 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1972 case IB_FLOW_SPEC_ETH:
c47ac6ae 1973 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1974 return -EOPNOTSUPP;
038d2ef8 1975
2d1e697e 1976 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1977 dmac_47_16),
1978 ib_spec->eth.mask.dst_mac);
2d1e697e 1979 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1980 dmac_47_16),
1981 ib_spec->eth.val.dst_mac);
1982
2d1e697e 1983 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1984 smac_47_16),
1985 ib_spec->eth.mask.src_mac);
2d1e697e 1986 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1987 smac_47_16),
1988 ib_spec->eth.val.src_mac);
1989
038d2ef8 1990 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1991 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1992 cvlan_tag, 1);
2d1e697e 1993 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1994 cvlan_tag, 1);
038d2ef8 1995
2d1e697e 1996 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1997 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1998 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1999 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2000
2d1e697e 2001 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2002 first_cfi,
2003 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2004 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2005 first_cfi,
2006 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2007
2d1e697e 2008 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2009 first_prio,
2010 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2011 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2012 first_prio,
2013 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2014 }
2d1e697e 2015 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2016 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2017 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2018 ethertype, ntohs(ib_spec->eth.val.ether_type));
2019 break;
2020 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2021 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2022 return -EOPNOTSUPP;
038d2ef8 2023
19cc7524
AL		 2024 if (match_ipv) {
2025 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2026 ip_version, 0xf);
2027 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2028 ip_version, IPV4_VERSION);
2029 } else {
2030 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2031 ethertype, 0xffff);
2032 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2033 ethertype, ETH_P_IP);
2034 }
038d2ef8 2035
2d1e697e 2036 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2037 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2038 &ib_spec->ipv4.mask.src_ip,
2039 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2040 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2041 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2042 &ib_spec->ipv4.val.src_ip,
2043 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2044 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2045 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2046 &ib_spec->ipv4.mask.dst_ip,
2047 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2048 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2049 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2050 &ib_spec->ipv4.val.dst_ip,
2051 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2052
2d1e697e 2053 set_tos(headers_c, headers_v,
ca0d4753
MG		 2054 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2055
2d1e697e 2056 set_proto(headers_c, headers_v,
ca0d4753 2057 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2058 break;
026bae0c 2059 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2060 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2061 return -EOPNOTSUPP;
026bae0c 2062
19cc7524
AL		 2063 if (match_ipv) {
2064 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2065 ip_version, 0xf);
2066 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2067 ip_version, IPV6_VERSION);
2068 } else {
2069 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2070 ethertype, 0xffff);
2071 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2072 ethertype, ETH_P_IPV6);
2073 }
026bae0c 2074
2d1e697e 2075 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2076 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2077 &ib_spec->ipv6.mask.src_ip,
2078 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2079 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2080 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2081 &ib_spec->ipv6.val.src_ip,
2082 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2083 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2084 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2085 &ib_spec->ipv6.mask.dst_ip,
2086 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2087 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2088 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2089 &ib_spec->ipv6.val.dst_ip,
2090 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2091
2d1e697e 2092 set_tos(headers_c, headers_v,
466fa6d2
MG		 2093 ib_spec->ipv6.mask.traffic_class,
2094 ib_spec->ipv6.val.traffic_class);
2095
2d1e697e 2096 set_proto(headers_c, headers_v,
466fa6d2
MG		 2097 ib_spec->ipv6.mask.next_hdr,
2098 ib_spec->ipv6.val.next_hdr);
2099
2d1e697e
MR		 2100 set_flow_label(misc_params_c, misc_params_v,
2101 ntohl(ib_spec->ipv6.mask.flow_label),
2102 ntohl(ib_spec->ipv6.val.flow_label),
2103 ib_spec->type & IB_FLOW_SPEC_INNER);
2104
026bae0c 2105 break;
038d2ef8 2106 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2107 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2108 LAST_TCP_UDP_FIELD))
1ffd3a26 2109 return -EOPNOTSUPP;
038d2ef8 2110
2d1e697e 2111 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2112 0xff);
2d1e697e 2113 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2114 IPPROTO_TCP);
2115
2d1e697e 2116 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2117 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2118 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2119 ntohs(ib_spec->tcp_udp.val.src_port));
2120
2d1e697e 2121 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2122 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2123 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2124 ntohs(ib_spec->tcp_udp.val.dst_port));
2125 break;
2126 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2127 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2128 LAST_TCP_UDP_FIELD))
1ffd3a26 2129 return -EOPNOTSUPP;
038d2ef8 2130
2d1e697e 2131 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2132 0xff);
2d1e697e 2133 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2134 IPPROTO_UDP);
2135
2d1e697e 2136 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2137 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2139 ntohs(ib_spec->tcp_udp.val.src_port));
2140
2d1e697e 2141 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2142 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2143 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2144 ntohs(ib_spec->tcp_udp.val.dst_port));
2145 break;
ffb30d8f
MR		 2146 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2147 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2148 LAST_TUNNEL_FIELD))
1ffd3a26 2149 return -EOPNOTSUPP;
ffb30d8f
MR		 2150
2151 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2152 ntohl(ib_spec->tunnel.mask.tunnel_id));
2153 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2154 ntohl(ib_spec->tunnel.val.tunnel_id));
2155 break;
2ac693f9
MR		 2156 case IB_FLOW_SPEC_ACTION_TAG:
2157 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2158 LAST_FLOW_TAG_FIELD))
2159 return -EOPNOTSUPP;
2160 if (ib_spec->flow_tag.tag_id >= BIT(24))
2161 return -EINVAL;
2162
2163 *tag_id = ib_spec->flow_tag.tag_id;
2164 break;
a22ed86c
SS		 2165 case IB_FLOW_SPEC_ACTION_DROP:
2166 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2167 LAST_DROP_FIELD))
2168 return -EOPNOTSUPP;
2169 *is_drop = true;
2170 break;
038d2ef8
MG		 2171 default:
2172 return -EINVAL;
2173 }
2174
2175 return 0;
2176}
2177
2178/* If a flow could catch both multicast and unicast packets,
2179 * it won't fall into the multicast flow steering table and this rule
2180 * could steal other multicast packets.
2181 */
a550ddfc 2182static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2183{
81e30880 2184 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2185
2186 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2187 ib_attr->num_of_specs < 1)
2188 return false;
2189
81e30880
YH		 2190 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2191 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2192 struct ib_flow_spec_ipv4 *ipv4_spec;
2193
2194 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2195 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2196 return true;
2197
038d2ef8 2198 return false;
81e30880
YH		 2199 }
2200
2201 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2202 struct ib_flow_spec_eth *eth_spec;
2203
2204 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2205 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2206 is_multicast_ether_addr(eth_spec->val.dst_mac);
2207 }
038d2ef8 2208
81e30880 2209 return false;
038d2ef8
MG		 2210}
2211
19cc7524
AL		 2212static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2213 const struct ib_flow_attr *flow_attr,
0f750966 2214 bool check_inner)
038d2ef8
MG		 2215{
2216 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2217 int match_ipv = check_inner ?
2218 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2219 ft_field_support.inner_ip_version) :
2220 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2221 ft_field_support.outer_ip_version);
0f750966
AL		 2222 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2223 bool ipv4_spec_valid, ipv6_spec_valid;
2224 unsigned int ip_spec_type = 0;
2225 bool has_ethertype = false;
038d2ef8 2226 unsigned int spec_index;
0f750966
AL		 2227 bool mask_valid = true;
2228 u16 eth_type = 0;
2229 bool type_valid;
038d2ef8
MG		 2230
2231 /* Validate that ethertype is correct */
2232 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2233 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2234 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2235 mask_valid = (ib_spec->eth.mask.ether_type ==
2236 htons(0xffff));
2237 has_ethertype = true;
2238 eth_type = ntohs(ib_spec->eth.val.ether_type);
2239 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2240 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2241 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2242 }
2243 ib_spec = (void *)ib_spec + ib_spec->size;
2244 }
0f750966
AL		 2245
2246 type_valid = (!has_ethertype) || (!ip_spec_type);
2247 if (!type_valid && mask_valid) {
2248 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2249 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2250 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2251 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2252
2253 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2254 (((eth_type == ETH_P_MPLS_UC) ||
2255 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2256 }
2257
2258 return type_valid;
2259}
2260
19cc7524
AL		 2261static bool is_valid_attr(struct mlx5_core_dev *mdev,
2262 const struct ib_flow_attr *flow_attr)
0f750966 2263{
19cc7524
AL		 2264 return is_valid_ethertype(mdev, flow_attr, false) &&
2265 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2266}
2267
2268static void put_flow_table(struct mlx5_ib_dev *dev,
2269 struct mlx5_ib_flow_prio *prio, bool ft_added)
2270{
2271 prio->refcount -= !!ft_added;
2272 if (!prio->refcount) {
2273 mlx5_destroy_flow_table(prio->flow_table);
2274 prio->flow_table = NULL;
2275 }
2276}
2277
2278static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2279{
2280 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2281 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2282 struct mlx5_ib_flow_handler,
2283 ibflow);
2284 struct mlx5_ib_flow_handler *iter, *tmp;
2285
2286 mutex_lock(&dev->flow_db.lock);
2287
2288 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2289 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2290 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2291 list_del(&iter->list);
2292 kfree(iter);
2293 }
2294
74491de9 2295 mlx5_del_flow_rules(handler->rule);
5497adc6 2296 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2297 mutex_unlock(&dev->flow_db.lock);
2298
2299 kfree(handler);
2300
2301 return 0;
2302}
2303
35d19011
MG		 2304static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2305{
2306 priority *= 2;
2307 if (!dont_trap)
2308 priority++;
2309 return priority;
2310}
2311
cc0e5d42
MG		 2312enum flow_table_type {
2313 MLX5_IB_FT_RX,
2314 MLX5_IB_FT_TX
2315};
2316
00b7c2ab
MG		 2317#define MLX5_FS_MAX_TYPES 6
2318#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2319static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2320 struct ib_flow_attr *flow_attr,
2321 enum flow_table_type ft_type)
038d2ef8 2322{
35d19011 2323 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2324 struct mlx5_flow_namespace *ns = NULL;
2325 struct mlx5_ib_flow_prio *prio;
2326 struct mlx5_flow_table *ft;
dac388ef 2327 int max_table_size;
038d2ef8
MG		 2328 int num_entries;
2329 int num_groups;
2330 int priority;
2331 int err = 0;
2332
dac388ef
MG		 2333 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2334 log_max_ft_size));
038d2ef8 2335 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2336 if (flow_is_multicast_only(flow_attr) &&
2337 !dont_trap)
038d2ef8
MG		 2338 priority = MLX5_IB_FLOW_MCAST_PRIO;
2339 else
35d19011
MG		 2340 priority = ib_prio_to_core_prio(flow_attr->priority,
2341 dont_trap);
038d2ef8
MG		 2342 ns = mlx5_get_flow_namespace(dev->mdev,
2343 MLX5_FLOW_NAMESPACE_BYPASS);
2344 num_entries = MLX5_FS_MAX_ENTRIES;
2345 num_groups = MLX5_FS_MAX_TYPES;
2346 prio = &dev->flow_db.prios[priority];
2347 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2348 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2349 ns = mlx5_get_flow_namespace(dev->mdev,
2350 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2351 build_leftovers_ft_param(&priority,
2352 &num_entries,
2353 &num_groups);
2354 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2355 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2356 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2357 allow_sniffer_and_nic_rx_shared_tir))
2358 return ERR_PTR(-ENOTSUPP);
2359
2360 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2361 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2362 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2363
2364 prio = &dev->flow_db.sniffer[ft_type];
2365 priority = 0;
2366 num_entries = 1;
2367 num_groups = 1;
038d2ef8
MG		 2368 }
2369
2370 if (!ns)
2371 return ERR_PTR(-ENOTSUPP);
2372
dac388ef
MG		 2373 if (num_entries > max_table_size)
2374 return ERR_PTR(-ENOMEM);
2375
038d2ef8
MG		 2376 ft = prio->flow_table;
2377 if (!ft) {
2378 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2379 num_entries,
d63cd286 2380 num_groups,
c9f1b073 2381 0, 0);
038d2ef8
MG		 2382
2383 if (!IS_ERR(ft)) {
2384 prio->refcount = 0;
2385 prio->flow_table = ft;
2386 } else {
2387 err = PTR_ERR(ft);
2388 }
2389 }
2390
2391 return err ? ERR_PTR(err) : prio;
2392}
2393
a550ddfc
YH		 2394static void set_underlay_qp(struct mlx5_ib_dev *dev,
2395 struct mlx5_flow_spec *spec,
2396 u32 underlay_qpn)
2397{
2398 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2399 spec->match_criteria,
2400 misc_parameters);
2401 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2402 misc_parameters);
2403
2404 if (underlay_qpn &&
2405 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2406 ft_field_support.bth_dst_qp)) {
2407 MLX5_SET(fte_match_set_misc,
2408 misc_params_v, bth_dst_qp, underlay_qpn);
2409 MLX5_SET(fte_match_set_misc,
2410 misc_params_c, bth_dst_qp, 0xffffff);
2411 }
2412}
2413
2414static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2415 struct mlx5_ib_flow_prio *ft_prio,
2416 const struct ib_flow_attr *flow_attr,
2417 struct mlx5_flow_destination *dst,
2418 u32 underlay_qpn)
038d2ef8
MG		 2419{
2420 struct mlx5_flow_table *ft = ft_prio->flow_table;
2421 struct mlx5_ib_flow_handler *handler;
66958ed9 2422 struct mlx5_flow_act flow_act = {0};
c5bb1730 2423 struct mlx5_flow_spec *spec;
a22ed86c 2424 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2425 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2426 unsigned int spec_index;
2ac693f9 2427 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2428 bool is_drop = false;
038d2ef8 2429 int err = 0;
a22ed86c 2430 int dest_num = 1;
038d2ef8 2431
19cc7524 2432 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2433 return ERR_PTR(-EINVAL);
2434
1b9a07ee 2435 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2436 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2437 if (!handler || !spec) {
038d2ef8
MG		 2438 err = -ENOMEM;
2439 goto free;
2440 }
2441
2442 INIT_LIST_HEAD(&handler->list);
2443
2444 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2445 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2446 spec->match_value,
2447 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2448 if (err < 0)
2449 goto free;
2450
2451 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2452 }
2453
a550ddfc
YH		 2454 if (!flow_is_multicast_only(flow_attr))
2455 set_underlay_qp(dev, spec, underlay_qpn);
2456
466fa6d2 2457 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2458 if (is_drop) {
2459 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2460 rule_dst = NULL;
2461 dest_num = 0;
2462 } else {
2463 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2464 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2465 }
2ac693f9
MR		 2466
2467 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2468 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2469 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2470 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2471 flow_tag, flow_attr->type);
2472 err = -EINVAL;
2473 goto free;
2474 }
2475 flow_act.flow_tag = flow_tag;
74491de9 2476 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2477 &flow_act,
a22ed86c 2478 rule_dst, dest_num);
038d2ef8
MG		 2479
2480 if (IS_ERR(handler->rule)) {
2481 err = PTR_ERR(handler->rule);
2482 goto free;
2483 }
2484
d9d4980a 2485 ft_prio->refcount++;
5497adc6 2486 handler->prio = ft_prio;
038d2ef8
MG		 2487
2488 ft_prio->flow_table = ft;
2489free:
2490 if (err)
2491 kfree(handler);
c5bb1730 2492 kvfree(spec);
038d2ef8
MG		 2493 return err ? ERR_PTR(err) : handler;
2494}
2495
a550ddfc
YH		 2496static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2497 struct mlx5_ib_flow_prio *ft_prio,
2498 const struct ib_flow_attr *flow_attr,
2499 struct mlx5_flow_destination *dst)
2500{
2501 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2502}
2503
35d19011
MG		 2504static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2505 struct mlx5_ib_flow_prio *ft_prio,
2506 struct ib_flow_attr *flow_attr,
2507 struct mlx5_flow_destination *dst)
2508{
2509 struct mlx5_ib_flow_handler *handler_dst = NULL;
2510 struct mlx5_ib_flow_handler *handler = NULL;
2511
2512 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2513 if (!IS_ERR(handler)) {
2514 handler_dst = create_flow_rule(dev, ft_prio,
2515 flow_attr, dst);
2516 if (IS_ERR(handler_dst)) {
74491de9 2517 mlx5_del_flow_rules(handler->rule);
d9d4980a 2518 ft_prio->refcount--;
35d19011
MG		 2519 kfree(handler);
2520 handler = handler_dst;
2521 } else {
2522 list_add(&handler_dst->list, &handler->list);
2523 }
2524 }
2525
2526 return handler;
2527}
038d2ef8
MG		 2528enum {
2529 LEFTOVERS_MC,
2530 LEFTOVERS_UC,
2531};
2532
2533static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2534 struct mlx5_ib_flow_prio *ft_prio,
2535 struct ib_flow_attr *flow_attr,
2536 struct mlx5_flow_destination *dst)
2537{
2538 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2539 struct mlx5_ib_flow_handler *handler = NULL;
2540
2541 static struct {
2542 struct ib_flow_attr flow_attr;
2543 struct ib_flow_spec_eth eth_flow;
2544 } leftovers_specs[] = {
2545 [LEFTOVERS_MC] = {
2546 .flow_attr = {
2547 .num_of_specs = 1,
2548 .size = sizeof(leftovers_specs[0])
2549 },
2550 .eth_flow = {
2551 .type = IB_FLOW_SPEC_ETH,
2552 .size = sizeof(struct ib_flow_spec_eth),
2553 .mask = {.dst_mac = {0x1} },
2554 .val = {.dst_mac = {0x1} }
2555 }
2556 },
2557 [LEFTOVERS_UC] = {
2558 .flow_attr = {
2559 .num_of_specs = 1,
2560 .size = sizeof(leftovers_specs[0])
2561 },
2562 .eth_flow = {
2563 .type = IB_FLOW_SPEC_ETH,
2564 .size = sizeof(struct ib_flow_spec_eth),
2565 .mask = {.dst_mac = {0x1} },
2566 .val = {.dst_mac = {} }
2567 }
2568 }
2569 };
2570
2571 handler = create_flow_rule(dev, ft_prio,
2572 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2573 dst);
2574 if (!IS_ERR(handler) &&
2575 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2576 handler_ucast = create_flow_rule(dev, ft_prio,
2577 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2578 dst);
2579 if (IS_ERR(handler_ucast)) {
74491de9 2580 mlx5_del_flow_rules(handler->rule);
d9d4980a 2581 ft_prio->refcount--;
038d2ef8
MG		 2582 kfree(handler);
2583 handler = handler_ucast;
2584 } else {
2585 list_add(&handler_ucast->list, &handler->list);
2586 }
2587 }
2588
2589 return handler;
2590}
2591
cc0e5d42
MG		 2592static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2593 struct mlx5_ib_flow_prio *ft_rx,
2594 struct mlx5_ib_flow_prio *ft_tx,
2595 struct mlx5_flow_destination *dst)
2596{
2597 struct mlx5_ib_flow_handler *handler_rx;
2598 struct mlx5_ib_flow_handler *handler_tx;
2599 int err;
2600 static const struct ib_flow_attr flow_attr = {
2601 .num_of_specs = 0,
2602 .size = sizeof(flow_attr)
2603 };
2604
2605 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2606 if (IS_ERR(handler_rx)) {
2607 err = PTR_ERR(handler_rx);
2608 goto err;
2609 }
2610
2611 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2612 if (IS_ERR(handler_tx)) {
2613 err = PTR_ERR(handler_tx);
2614 goto err_tx;
2615 }
2616
2617 list_add(&handler_tx->list, &handler_rx->list);
2618
2619 return handler_rx;
2620
2621err_tx:
74491de9 2622 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2623 ft_rx->refcount--;
2624 kfree(handler_rx);
2625err:
2626 return ERR_PTR(err);
2627}
2628
038d2ef8
MG		 2629static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2630 struct ib_flow_attr *flow_attr,
2631 int domain)
2632{
2633 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2634 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2635 struct mlx5_ib_flow_handler *handler = NULL;
2636 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2637 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2638 struct mlx5_ib_flow_prio *ft_prio;
2639 int err;
a550ddfc 2640 int underlay_qpn;
038d2ef8
MG		 2641
2642 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2643 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2644
2645 if (domain != IB_FLOW_DOMAIN_USER ||
2646 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2647 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2648 return ERR_PTR(-EINVAL);
2649
2650 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2651 if (!dst)
2652 return ERR_PTR(-ENOMEM);
2653
2654 mutex_lock(&dev->flow_db.lock);
2655
cc0e5d42 2656 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2657 if (IS_ERR(ft_prio)) {
2658 err = PTR_ERR(ft_prio);
2659 goto unlock;
2660 }
cc0e5d42
MG		 2661 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2662 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2663 if (IS_ERR(ft_prio_tx)) {
2664 err = PTR_ERR(ft_prio_tx);
2665 ft_prio_tx = NULL;
2666 goto destroy_ft;
2667 }
2668 }
038d2ef8
MG		 2669
2670 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2671 if (mqp->flags & MLX5_IB_QP_RSS)
2672 dst->tir_num = mqp->rss_qp.tirn;
2673 else
2674 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2675
2676 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2677 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2678 handler = create_dont_trap_rule(dev, ft_prio,
2679 flow_attr, dst);
2680 } else {
a550ddfc
YH		 2681 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2682 mqp->underlay_qpn : 0;
2683 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2684 dst, underlay_qpn);
35d19011 2685 }
038d2ef8
MG		 2686 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2687 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2688 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2689 dst);
cc0e5d42
MG		 2690 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2691 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2692 } else {
2693 err = -EINVAL;
2694 goto destroy_ft;
2695 }
2696
2697 if (IS_ERR(handler)) {
2698 err = PTR_ERR(handler);
2699 handler = NULL;
2700 goto destroy_ft;
2701 }
2702
038d2ef8
MG		 2703 mutex_unlock(&dev->flow_db.lock);
2704 kfree(dst);
2705
2706 return &handler->ibflow;
2707
2708destroy_ft:
2709 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2710 if (ft_prio_tx)
2711 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2712unlock:
2713 mutex_unlock(&dev->flow_db.lock);
2714 kfree(dst);
2715 kfree(handler);
2716 return ERR_PTR(err);
2717}
2718
e126ba97
EC		 2719static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2720{
2721 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2722 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2723 int err;
2724
81e30880
YH		 2725 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2726 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2727 return -EOPNOTSUPP;
2728 }
2729
9603b61d 2730 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2731 if (err)
2732 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2733 ibqp->qp_num, gid->raw);
2734
2735 return err;
2736}
2737
2738static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2739{
2740 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2741 int err;
2742
9603b61d 2743 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2744 if (err)
2745 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2746 ibqp->qp_num, gid->raw);
2747
2748 return err;
2749}
2750
2751static int init_node_data(struct mlx5_ib_dev *dev)
2752{
1b5daf11 2753 int err;
e126ba97 2754
1b5daf11 2755 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2756 if (err)
1b5daf11 2757 return err;
e126ba97 2758
1b5daf11 2759 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2760
1b5daf11 2761 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2762}
2763
2764static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2765 char *buf)
2766{
2767 struct mlx5_ib_dev *dev =
2768 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2769
9603b61d 2770 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2771}
2772
2773static ssize_t show_reg_pages(struct device *device,
2774 struct device_attribute *attr, char *buf)
2775{
2776 struct mlx5_ib_dev *dev =
2777 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2778
6aec21f6 2779 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2780}
2781
2782static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2783 char *buf)
2784{
2785 struct mlx5_ib_dev *dev =
2786 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2787 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2788}
2789
e126ba97
EC		 2790static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2791 char *buf)
2792{
2793 struct mlx5_ib_dev *dev =
2794 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2795 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2796}
2797
2798static ssize_t show_board(struct device *device, struct device_attribute *attr,
2799 char *buf)
2800{
2801 struct mlx5_ib_dev *dev =
2802 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2803 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2804 dev->mdev->board_id);
e126ba97
EC		 2805}
2806
2807static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2808static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2809static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2810static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2811static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2812
2813static struct device_attribute *mlx5_class_attributes[] = {
2814 &dev_attr_hw_rev,
e126ba97
EC		 2815 &dev_attr_hca_type,
2816 &dev_attr_board_id,
2817 &dev_attr_fw_pages,
2818 &dev_attr_reg_pages,
2819};
2820
7722f47e
HE		 2821static void pkey_change_handler(struct work_struct *work)
2822{
2823 struct mlx5_ib_port_resources *ports =
2824 container_of(work, struct mlx5_ib_port_resources,
2825 pkey_change_work);
2826
2827 mutex_lock(&ports->devr->mutex);
2828 mlx5_ib_gsi_pkey_change(ports->gsi);
2829 mutex_unlock(&ports->devr->mutex);
2830}
2831
89ea94a7
MG		 2832static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2833{
2834 struct mlx5_ib_qp *mqp;
2835 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2836 struct mlx5_core_cq *mcq;
2837 struct list_head cq_armed_list;
2838 unsigned long flags_qp;
2839 unsigned long flags_cq;
2840 unsigned long flags;
2841
2842 INIT_LIST_HEAD(&cq_armed_list);
2843
2844 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2845 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2846 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2847 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2848 if (mqp->sq.tail != mqp->sq.head) {
2849 send_mcq = to_mcq(mqp->ibqp.send_cq);
2850 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2851 if (send_mcq->mcq.comp &&
2852 mqp->ibqp.send_cq->comp_handler) {
2853 if (!send_mcq->mcq.reset_notify_added) {
2854 send_mcq->mcq.reset_notify_added = 1;
2855 list_add_tail(&send_mcq->mcq.reset_notify,
2856 &cq_armed_list);
2857 }
2858 }
2859 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2860 }
2861 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2862 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2863 /* no handling is needed for SRQ */
2864 if (!mqp->ibqp.srq) {
2865 if (mqp->rq.tail != mqp->rq.head) {
2866 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2867 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2868 if (recv_mcq->mcq.comp &&
2869 mqp->ibqp.recv_cq->comp_handler) {
2870 if (!recv_mcq->mcq.reset_notify_added) {
2871 recv_mcq->mcq.reset_notify_added = 1;
2872 list_add_tail(&recv_mcq->mcq.reset_notify,
2873 &cq_armed_list);
2874 }
2875 }
2876 spin_unlock_irqrestore(&recv_mcq->lock,
2877 flags_cq);
2878 }
2879 }
2880 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2881 }
2882 /*At that point all inflight post send were put to be executed as of we
2883 * lock/unlock above locks Now need to arm all involved CQs.
2884 */
2885 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2886 mcq->comp(mcq);
2887 }
2888 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2889}
2890
03404e8a
MG		 2891static void delay_drop_handler(struct work_struct *work)
2892{
2893 int err;
2894 struct mlx5_ib_delay_drop *delay_drop =
2895 container_of(work, struct mlx5_ib_delay_drop,
2896 delay_drop_work);
2897
fe248c3a
MG		 2898 atomic_inc(&delay_drop->events_cnt);
2899
03404e8a
MG		 2900 mutex_lock(&delay_drop->lock);
2901 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2902 delay_drop->timeout);
2903 if (err) {
2904 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2905 delay_drop->timeout);
2906 delay_drop->activate = false;
2907 }
2908 mutex_unlock(&delay_drop->lock);
2909}
2910
9603b61d 2911static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2912 enum mlx5_dev_event event, unsigned long param)
e126ba97 2913{
9603b61d 2914 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2915 struct ib_event ibev;
dbaaff2a 2916 bool fatal = false;
e126ba97
EC		 2917 u8 port = 0;
2918
2919 switch (event) {
2920 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2921 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2922 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2923 fatal = true;
e126ba97
EC		 2924 break;
2925
2926 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2927 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2928 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2929 port = (u8)param;
5ec8c83e
AH		 2930
2931 /* In RoCE, port up/down events are handled in
2932 * mlx5_netdev_event().
2933 */
2934 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2935 IB_LINK_LAYER_ETHERNET)
2936 return;
2937
2938 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2939 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2940 break;
2941
e126ba97
EC		 2942 case MLX5_DEV_EVENT_LID_CHANGE:
2943 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2944 port = (u8)param;
e126ba97
EC		 2945 break;
2946
2947 case MLX5_DEV_EVENT_PKEY_CHANGE:
2948 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2949 port = (u8)param;
7722f47e
HE		 2950
2951 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2952 break;
2953
2954 case MLX5_DEV_EVENT_GUID_CHANGE:
2955 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2956 port = (u8)param;
e126ba97
EC		 2957 break;
2958
2959 case MLX5_DEV_EVENT_CLIENT_REREG:
2960 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2961 port = (u8)param;
e126ba97 2962 break;
03404e8a
MG		 2963 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2964 schedule_work(&ibdev->delay_drop.delay_drop_work);
2965 goto out;
bdc37924 2966 default:
03404e8a 2967 goto out;
e126ba97
EC		 2968 }
2969
2970 ibev.device = &ibdev->ib_dev;
2971 ibev.element.port_num = port;
2972
a0c84c32
EC		 2973 if (port < 1 || port > ibdev->num_ports) {
2974 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2975 goto out;
a0c84c32
EC		 2976 }
2977
e126ba97
EC		 2978 if (ibdev->ib_active)
2979 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2980
2981 if (fatal)
2982 ibdev->ib_active = false;
03404e8a
MG		 2983
2984out:
2985 return;
e126ba97
EC		 2986}
2987
c43f1112
MG		 2988static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2989{
2990 struct mlx5_hca_vport_context vport_ctx;
2991 int err;
2992 int port;
2993
2994 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2995 dev->mdev->port_caps[port - 1].has_smi = false;
2996 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2997 MLX5_CAP_PORT_TYPE_IB) {
2998 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2999 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3000 port, 0,
3001 &vport_ctx);
3002 if (err) {
3003 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3004 port, err);
3005 return err;
3006 }
3007 dev->mdev->port_caps[port - 1].has_smi =
3008 vport_ctx.has_smi;
3009 } else {
3010 dev->mdev->port_caps[port - 1].has_smi = true;
3011 }
3012 }
3013 }
3014 return 0;
3015}
3016
e126ba97
EC		 3017static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3018{
3019 int port;
3020
938fe83c 3021 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 3022 mlx5_query_ext_port_caps(dev, port);
3023}
3024
3025static int get_port_caps(struct mlx5_ib_dev *dev)
3026{
3027 struct ib_device_attr *dprops = NULL;
3028 struct ib_port_attr *pprops = NULL;
f614fc15 3029 int err = -ENOMEM;
e126ba97 3030 int port;
2528e33e 3031 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3032
3033 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3034 if (!pprops)
3035 goto out;
3036
3037 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3038 if (!dprops)
3039 goto out;
3040
c43f1112
MG		 3041 err = set_has_smi_cap(dev);
3042 if (err)
3043 goto out;
3044
2528e33e 3045 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3046 if (err) {
3047 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3048 goto out;
3049 }
3050
938fe83c 3051 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 3052 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 3053 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3054 if (err) {
938fe83c
SM		 3055 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3056 port, err);
e126ba97
EC		 3057 break;
3058 }
938fe83c
SM		 3059 dev->mdev->port_caps[port - 1].pkey_table_len =
3060 dprops->max_pkeys;
3061 dev->mdev->port_caps[port - 1].gid_table_len =
3062 pprops->gid_tbl_len;
e126ba97
EC		 3063 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3064 dprops->max_pkeys, pprops->gid_tbl_len);
3065 }
3066
3067out:
3068 kfree(pprops);
3069 kfree(dprops);
3070
3071 return err;
3072}
3073
3074static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3075{
3076 int err;
3077
3078 err = mlx5_mr_cache_cleanup(dev);
3079 if (err)
3080 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3081
3082 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3083 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3084 ib_dealloc_pd(dev->umrc.pd);
3085}
3086
3087enum {
3088 MAX_UMR_WR = 128,
3089};
3090
3091static int create_umr_res(struct mlx5_ib_dev *dev)
3092{
3093 struct ib_qp_init_attr *init_attr = NULL;
3094 struct ib_qp_attr *attr = NULL;
3095 struct ib_pd *pd;
3096 struct ib_cq *cq;
3097 struct ib_qp *qp;
e126ba97
EC		 3098 int ret;
3099
3100 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3101 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3102 if (!attr || !init_attr) {
3103 ret = -ENOMEM;
3104 goto error_0;
3105 }
3106
ed082d36 3107 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3108 if (IS_ERR(pd)) {
3109 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3110 ret = PTR_ERR(pd);
3111 goto error_0;
3112 }
3113
add08d76 3114 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3115 if (IS_ERR(cq)) {
3116 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3117 ret = PTR_ERR(cq);
3118 goto error_2;
3119 }
e126ba97
EC		 3120
3121 init_attr->send_cq = cq;
3122 init_attr->recv_cq = cq;
3123 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3124 init_attr->cap.max_send_wr = MAX_UMR_WR;
3125 init_attr->cap.max_send_sge = 1;
3126 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3127 init_attr->port_num = 1;
3128 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3129 if (IS_ERR(qp)) {
3130 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3131 ret = PTR_ERR(qp);
3132 goto error_3;
3133 }
3134 qp->device = &dev->ib_dev;
3135 qp->real_qp = qp;
3136 qp->uobject = NULL;
3137 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3138
3139 attr->qp_state = IB_QPS_INIT;
3140 attr->port_num = 1;
3141 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3142 IB_QP_PORT, NULL);
3143 if (ret) {
3144 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3145 goto error_4;
3146 }
3147
3148 memset(attr, 0, sizeof(*attr));
3149 attr->qp_state = IB_QPS_RTR;
3150 attr->path_mtu = IB_MTU_256;
3151
3152 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3153 if (ret) {
3154 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3155 goto error_4;
3156 }
3157
3158 memset(attr, 0, sizeof(*attr));
3159 attr->qp_state = IB_QPS_RTS;
3160 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3161 if (ret) {
3162 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3163 goto error_4;
3164 }
3165
3166 dev->umrc.qp = qp;
3167 dev->umrc.cq = cq;
e126ba97
EC		 3168 dev->umrc.pd = pd;
3169
3170 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3171 ret = mlx5_mr_cache_init(dev);
3172 if (ret) {
3173 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3174 goto error_4;
3175 }
3176
3177 kfree(attr);
3178 kfree(init_attr);
3179
3180 return 0;
3181
3182error_4:
3183 mlx5_ib_destroy_qp(qp);
3184
3185error_3:
add08d76 3186 ib_free_cq(cq);
e126ba97
EC		 3187
3188error_2:
e126ba97
EC		 3189 ib_dealloc_pd(pd);
3190
3191error_0:
3192 kfree(attr);
3193 kfree(init_attr);
3194 return ret;
3195}
3196
6e8484c5
MG		 3197static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3198{
3199 switch (umr_fence_cap) {
3200 case MLX5_CAP_UMR_FENCE_NONE:
3201 return MLX5_FENCE_MODE_NONE;
3202 case MLX5_CAP_UMR_FENCE_SMALL:
3203 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3204 default:
3205 return MLX5_FENCE_MODE_STRONG_ORDERING;
3206 }
3207}
3208
e126ba97
EC		 3209static int create_dev_resources(struct mlx5_ib_resources *devr)
3210{
3211 struct ib_srq_init_attr attr;
3212 struct mlx5_ib_dev *dev;
bcf4c1ea 3213 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3214 int port;
e126ba97
EC		 3215 int ret = 0;
3216
3217 dev = container_of(devr, struct mlx5_ib_dev, devr);
3218
d16e91da
HE		 3219 mutex_init(&devr->mutex);
3220
e126ba97
EC		 3221 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3222 if (IS_ERR(devr->p0)) {
3223 ret = PTR_ERR(devr->p0);
3224 goto error0;
3225 }
3226 devr->p0->device = &dev->ib_dev;
3227 devr->p0->uobject = NULL;
3228 atomic_set(&devr->p0->usecnt, 0);
3229
bcf4c1ea 3230 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3231 if (IS_ERR(devr->c0)) {
3232 ret = PTR_ERR(devr->c0);
3233 goto error1;
3234 }
3235 devr->c0->device = &dev->ib_dev;
3236 devr->c0->uobject = NULL;
3237 devr->c0->comp_handler = NULL;
3238 devr->c0->event_handler = NULL;
3239 devr->c0->cq_context = NULL;
3240 atomic_set(&devr->c0->usecnt, 0);
3241
3242 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3243 if (IS_ERR(devr->x0)) {
3244 ret = PTR_ERR(devr->x0);
3245 goto error2;
3246 }
3247 devr->x0->device = &dev->ib_dev;
3248 devr->x0->inode = NULL;
3249 atomic_set(&devr->x0->usecnt, 0);
3250 mutex_init(&devr->x0->tgt_qp_mutex);
3251 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3252
3253 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3254 if (IS_ERR(devr->x1)) {
3255 ret = PTR_ERR(devr->x1);
3256 goto error3;
3257 }
3258 devr->x1->device = &dev->ib_dev;
3259 devr->x1->inode = NULL;
3260 atomic_set(&devr->x1->usecnt, 0);
3261 mutex_init(&devr->x1->tgt_qp_mutex);
3262 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3263
3264 memset(&attr, 0, sizeof(attr));
3265 attr.attr.max_sge = 1;
3266 attr.attr.max_wr = 1;
3267 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3268 attr.ext.cq = devr->c0;
e126ba97
EC		 3269 attr.ext.xrc.xrcd = devr->x0;
3270
3271 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3272 if (IS_ERR(devr->s0)) {
3273 ret = PTR_ERR(devr->s0);
3274 goto error4;
3275 }
3276 devr->s0->device = &dev->ib_dev;
3277 devr->s0->pd = devr->p0;
3278 devr->s0->uobject = NULL;
3279 devr->s0->event_handler = NULL;
3280 devr->s0->srq_context = NULL;
3281 devr->s0->srq_type = IB_SRQT_XRC;
3282 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3283 devr->s0->ext.cq = devr->c0;
e126ba97 3284 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3285 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3286 atomic_inc(&devr->p0->usecnt);
3287 atomic_set(&devr->s0->usecnt, 0);
3288
4aa17b28
HA		 3289 memset(&attr, 0, sizeof(attr));
3290 attr.attr.max_sge = 1;
3291 attr.attr.max_wr = 1;
3292 attr.srq_type = IB_SRQT_BASIC;
3293 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3294 if (IS_ERR(devr->s1)) {
3295 ret = PTR_ERR(devr->s1);
3296 goto error5;
3297 }
3298 devr->s1->device = &dev->ib_dev;
3299 devr->s1->pd = devr->p0;
3300 devr->s1->uobject = NULL;
3301 devr->s1->event_handler = NULL;
3302 devr->s1->srq_context = NULL;
3303 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3304 devr->s1->ext.cq = devr->c0;
4aa17b28 3305 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3306 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3307
7722f47e
HE		 3308 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3309 INIT_WORK(&devr->ports[port].pkey_change_work,
3310 pkey_change_handler);
3311 devr->ports[port].devr = devr;
3312 }
3313
e126ba97
EC		 3314 return 0;
3315
4aa17b28
HA		 3316error5:
3317 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3318error4:
3319 mlx5_ib_dealloc_xrcd(devr->x1);
3320error3:
3321 mlx5_ib_dealloc_xrcd(devr->x0);
3322error2:
3323 mlx5_ib_destroy_cq(devr->c0);
3324error1:
3325 mlx5_ib_dealloc_pd(devr->p0);
3326error0:
3327 return ret;
3328}
3329
3330static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3331{
7722f47e
HE		 3332 struct mlx5_ib_dev *dev =
3333 container_of(devr, struct mlx5_ib_dev, devr);
3334 int port;
3335
4aa17b28 3336 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3337 mlx5_ib_destroy_srq(devr->s0);
3338 mlx5_ib_dealloc_xrcd(devr->x0);
3339 mlx5_ib_dealloc_xrcd(devr->x1);
3340 mlx5_ib_destroy_cq(devr->c0);
3341 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3342
3343 /* Make sure no change P_Key work items are still executing */
3344 for (port = 0; port < dev->num_ports; ++port)
3345 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3346}
3347
e53505a8
AS		 3348static u32 get_core_cap_flags(struct ib_device *ibdev)
3349{
3350 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3351 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3352 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3353 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3354 u32 ret = 0;
3355
3356 if (ll == IB_LINK_LAYER_INFINIBAND)
3357 return RDMA_CORE_PORT_IBA_IB;
3358
72cd5717
OG		 3359 ret = RDMA_CORE_PORT_RAW_PACKET;
3360
e53505a8 3361 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3362 return ret;
e53505a8
AS		 3363
3364 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3365 return ret;
e53505a8
AS		 3366
3367 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3368 ret |= RDMA_CORE_PORT_IBA_ROCE;
3369
3370 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3371 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3372
3373 return ret;
3374}
3375
7738613e
IW		 3376static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3377 struct ib_port_immutable *immutable)
3378{
3379 struct ib_port_attr attr;
ca5b91d6
OG		 3380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3381 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3382 int err;
3383
c4550c63
OG		 3384 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3385
3386 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3387 if (err)
3388 return err;
3389
3390 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3391 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3392 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3393 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3394 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3395
3396 return 0;
3397}
3398
9abb0d1b 3399static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3400{
3401 struct mlx5_ib_dev *dev =
3402 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3403 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3404 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3405 fw_rev_sub(dev->mdev));
c7342823
IW		 3406}
3407
45f95acd 3408static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3409{
3410 struct mlx5_core_dev *mdev = dev->mdev;
3411 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3412 MLX5_FLOW_NAMESPACE_LAG);
3413 struct mlx5_flow_table *ft;
3414 int err;
3415
3416 if (!ns || !mlx5_lag_is_active(mdev))
3417 return 0;
3418
3419 err = mlx5_cmd_create_vport_lag(mdev);
3420 if (err)
3421 return err;
3422
3423 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3424 if (IS_ERR(ft)) {
3425 err = PTR_ERR(ft);
3426 goto err_destroy_vport_lag;
3427 }
3428
3429 dev->flow_db.lag_demux_ft = ft;
3430 return 0;
3431
3432err_destroy_vport_lag:
3433 mlx5_cmd_destroy_vport_lag(mdev);
3434 return err;
3435}
3436
45f95acd 3437static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3438{
3439 struct mlx5_core_dev *mdev = dev->mdev;
3440
3441 if (dev->flow_db.lag_demux_ft) {
3442 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3443 dev->flow_db.lag_demux_ft = NULL;
3444
3445 mlx5_cmd_destroy_vport_lag(mdev);
3446 }
3447}
3448
d012f5d6
OG		 3449static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3450{
3451 int err;
3452
3453 dev->roce.nb.notifier_call = mlx5_netdev_event;
3454 err = register_netdevice_notifier(&dev->roce.nb);
3455 if (err) {
3456 dev->roce.nb.notifier_call = NULL;
3457 return err;
3458 }
3459
3460 return 0;
3461}
3462
3463static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3464{
3465 if (dev->roce.nb.notifier_call) {
3466 unregister_netdevice_notifier(&dev->roce.nb);
3467 dev->roce.nb.notifier_call = NULL;
3468 }
3469}
3470
45f95acd 3471static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3472{
e53505a8
AS		 3473 int err;
3474
d012f5d6
OG		 3475 err = mlx5_add_netdev_notifier(dev);
3476 if (err)
e53505a8
AS		 3477 return err;
3478
ca5b91d6
OG		 3479 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3480 err = mlx5_nic_vport_enable_roce(dev->mdev);
3481 if (err)
3482 goto err_unregister_netdevice_notifier;
3483 }
e53505a8 3484
45f95acd 3485 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3486 if (err)
3487 goto err_disable_roce;
3488
e53505a8
AS		 3489 return 0;
3490
9ef9c640 3491err_disable_roce:
ca5b91d6
OG		 3492 if (MLX5_CAP_GEN(dev->mdev, roce))
3493 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3494
e53505a8 3495err_unregister_netdevice_notifier:
d012f5d6 3496 mlx5_remove_netdev_notifier(dev);
e53505a8 3497 return err;
fc24fc5e
AS		 3498}
3499
45f95acd 3500static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3501{
45f95acd 3502 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3503 if (MLX5_CAP_GEN(dev->mdev, roce))
3504 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3505}
3506
e1f24a79 3507struct mlx5_ib_counter {
7c16f477
KH		 3508 const char *name;
3509 size_t offset;
3510};
3511
3512#define INIT_Q_COUNTER(_name) \
3513 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3514
e1f24a79 3515static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3516 INIT_Q_COUNTER(rx_write_requests),
3517 INIT_Q_COUNTER(rx_read_requests),
3518 INIT_Q_COUNTER(rx_atomic_requests),
3519 INIT_Q_COUNTER(out_of_buffer),
3520};
3521
e1f24a79 3522static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3523 INIT_Q_COUNTER(out_of_sequence),
3524};
3525
e1f24a79 3526static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3527 INIT_Q_COUNTER(duplicate_request),
3528 INIT_Q_COUNTER(rnr_nak_retry_err),
3529 INIT_Q_COUNTER(packet_seq_err),
3530 INIT_Q_COUNTER(implied_nak_seq_err),
3531 INIT_Q_COUNTER(local_ack_timeout_err),
3532};
3533
e1f24a79
PP		 3534#define INIT_CONG_COUNTER(_name) \
3535 { .name = #_name, .offset = \
3536 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3537
3538static const struct mlx5_ib_counter cong_cnts[] = {
3539 INIT_CONG_COUNTER(rp_cnp_ignored),
3540 INIT_CONG_COUNTER(rp_cnp_handled),
3541 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3542 INIT_CONG_COUNTER(np_cnp_sent),
3543};
3544
58dcb60a
PP		 3545static const struct mlx5_ib_counter extended_err_cnts[] = {
3546 INIT_Q_COUNTER(resp_local_length_error),
3547 INIT_Q_COUNTER(resp_cqe_error),
3548 INIT_Q_COUNTER(req_cqe_error),
3549 INIT_Q_COUNTER(req_remote_invalid_request),
3550 INIT_Q_COUNTER(req_remote_access_errors),
3551 INIT_Q_COUNTER(resp_remote_access_errors),
3552 INIT_Q_COUNTER(resp_cqe_flush_error),
3553 INIT_Q_COUNTER(req_cqe_flush_error),
3554};
3555
e1f24a79 3556static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3557{
3558 unsigned int i;
3559
7c16f477 3560 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3561 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3562 dev->port[i].cnts.set_id);
3563 kfree(dev->port[i].cnts.names);
3564 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3565 }
3566}
3567
e1f24a79
PP		 3568static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3569 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3570{
3571 u32 num_counters;
3572
3573 num_counters = ARRAY_SIZE(basic_q_cnts);
3574
3575 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3576 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3577
3578 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3579 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3580
3581 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3582 num_counters += ARRAY_SIZE(extended_err_cnts);
3583
e1f24a79 3584 cnts->num_q_counters = num_counters;
7c16f477 3585
e1f24a79
PP		 3586 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3587 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3588 num_counters += ARRAY_SIZE(cong_cnts);
3589 }
3590
3591 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3592 if (!cnts->names)
7c16f477
KH		 3593 return -ENOMEM;
3594
e1f24a79
PP		 3595 cnts->offsets = kcalloc(num_counters,
3596 sizeof(cnts->offsets), GFP_KERNEL);
3597 if (!cnts->offsets)
7c16f477
KH		 3598 goto err_names;
3599
7c16f477
KH		 3600 return 0;
3601
3602err_names:
e1f24a79 3603 kfree(cnts->names);
7c16f477
KH		 3604 return -ENOMEM;
3605}
3606
e1f24a79
PP		 3607static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3608 const char **names,
3609 size_t *offsets)
7c16f477
KH		 3610{
3611 int i;
3612 int j = 0;
3613
3614 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3615 names[j] = basic_q_cnts[i].name;
3616 offsets[j] = basic_q_cnts[i].offset;
3617 }
3618
3619 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3620 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3621 names[j] = out_of_seq_q_cnts[i].name;
3622 offsets[j] = out_of_seq_q_cnts[i].offset;
3623 }
3624 }
3625
3626 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3627 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3628 names[j] = retrans_q_cnts[i].name;
3629 offsets[j] = retrans_q_cnts[i].offset;
3630 }
3631 }
e1f24a79 3632
58dcb60a
PP		 3633 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3634 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3635 names[j] = extended_err_cnts[i].name;
3636 offsets[j] = extended_err_cnts[i].offset;
3637 }
3638 }
3639
e1f24a79
PP		 3640 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3641 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3642 names[j] = cong_cnts[i].name;
3643 offsets[j] = cong_cnts[i].offset;
3644 }
3645 }
0837e86a
MB		 3646}
3647
e1f24a79 3648static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3649{
3650 int i;
3651 int ret;
3652
3653 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3654 struct mlx5_ib_port *port = &dev->port[i];
3655
0837e86a 3656 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3657 &port->cnts.set_id);
0837e86a
MB		 3658 if (ret) {
3659 mlx5_ib_warn(dev,
3660 "couldn't allocate queue counter for port %d, err %d\n",
3661 i + 1, ret);
3662 goto dealloc_counters;
3663 }
7c16f477 3664
e1f24a79 3665 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3666 if (ret)
3667 goto dealloc_counters;
3668
e1f24a79
PP		 3669 mlx5_ib_fill_counters(dev, port->cnts.names,
3670 port->cnts.offsets);
0837e86a
MB		 3671 }
3672
3673 return 0;
3674
3675dealloc_counters:
3676 while (--i >= 0)
3677 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3678 dev->port[i].cnts.set_id);
0837e86a
MB		 3679
3680 return ret;
3681}
3682
0ad17a8f
MB		 3683static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3684 u8 port_num)
3685{
7c16f477
KH		 3686 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3687 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3688
3689 /* We support only per port stats */
3690 if (port_num == 0)
3691 return NULL;
3692
e1f24a79
PP		 3693 return rdma_alloc_hw_stats_struct(port->cnts.names,
3694 port->cnts.num_q_counters +
3695 port->cnts.num_cong_counters,
0ad17a8f
MB		 3696 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3697}
3698
e1f24a79
PP		 3699static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3700 struct mlx5_ib_port *port,
3701 struct rdma_hw_stats *stats)
0ad17a8f 3702{
0ad17a8f
MB		 3703 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3704 void *out;
3705 __be32 val;
e1f24a79 3706 int ret, i;
0ad17a8f 3707
1b9a07ee 3708 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3709 if (!out)
3710 return -ENOMEM;
3711
3712 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3713 port->cnts.set_id, 0,
0ad17a8f
MB		 3714 out, outlen);
3715 if (ret)
3716 goto free;
3717
e1f24a79
PP		 3718 for (i = 0; i < port->cnts.num_q_counters; i++) {
3719 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3720 stats->value[i] = (u64)be32_to_cpu(val);
3721 }
7c16f477 3722
0ad17a8f
MB		 3723free:
3724 kvfree(out);
e1f24a79
PP		 3725 return ret;
3726}
3727
3728static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3729 struct mlx5_ib_port *port,
3730 struct rdma_hw_stats *stats)
3731{
3732 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3733 void *out;
3734 int ret, i;
3735 int offset = port->cnts.num_q_counters;
3736
1b9a07ee 3737 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3738 if (!out)
3739 return -ENOMEM;
3740
3741 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3742 if (ret)
3743 goto free;
3744
3745 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3746 stats->value[i + offset] =
3747 be64_to_cpup((__be64 *)(out +
3748 port->cnts.offsets[i + offset]));
3749 }
3750
3751free:
3752 kvfree(out);
3753 return ret;
3754}
3755
3756static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3757 struct rdma_hw_stats *stats,
3758 u8 port_num, int index)
3759{
3760 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3761 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3762 int ret, num_counters;
3763
3764 if (!stats)
3765 return -EINVAL;
3766
3767 ret = mlx5_ib_query_q_counters(dev, port, stats);
3768 if (ret)
3769 return ret;
3770 num_counters = port->cnts.num_q_counters;
3771
3772 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3773 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3774 if (ret)
3775 return ret;
3776 num_counters += port->cnts.num_cong_counters;
3777 }
3778
3779 return num_counters;
0ad17a8f
MB		 3780}
3781
8e959601
NV		 3782static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3783{
3784 return mlx5_rdma_netdev_free(netdev);
3785}
3786
693dfd5a
ES		 3787static struct net_device*
3788mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3789 u8 port_num,
3790 enum rdma_netdev_t type,
3791 const char *name,
3792 unsigned char name_assign_type,
3793 void (*setup)(struct net_device *))
3794{
8e959601
NV		 3795 struct net_device *netdev;
3796 struct rdma_netdev *rn;
3797
693dfd5a
ES		 3798 if (type != RDMA_NETDEV_IPOIB)
3799 return ERR_PTR(-EOPNOTSUPP);
3800
8e959601
NV		 3801 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3802 name, setup);
3803 if (likely(!IS_ERR_OR_NULL(netdev))) {
3804 rn = netdev_priv(netdev);
3805 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3806 }
3807 return netdev;
693dfd5a
ES		 3808}
3809
fe248c3a
MG		 3810static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3811{
3812 if (!dev->delay_drop.dbg)
3813 return;
3814 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3815 kfree(dev->delay_drop.dbg);
3816 dev->delay_drop.dbg = NULL;
3817}
3818
03404e8a
MG		 3819static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3820{
3821 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3822 return;
3823
3824 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3825 delay_drop_debugfs_cleanup(dev);
3826}
3827
3828static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3829 size_t count, loff_t *pos)
3830{
3831 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3832 char lbuf[20];
3833 int len;
3834
3835 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3836 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3837}
3838
3839static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3840 size_t count, loff_t *pos)
3841{
3842 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3843 u32 timeout;
3844 u32 var;
3845
3846 if (kstrtouint_from_user(buf, count, 0, &var))
3847 return -EFAULT;
3848
3849 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3850 1000);
3851 if (timeout != var)
3852 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3853 timeout);
3854
3855 delay_drop->timeout = timeout;
3856
3857 return count;
3858}
3859
3860static const struct file_operations fops_delay_drop_timeout = {
3861 .owner = THIS_MODULE,
3862 .open = simple_open,
3863 .write = delay_drop_timeout_write,
3864 .read = delay_drop_timeout_read,
3865};
3866
3867static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3868{
3869 struct mlx5_ib_dbg_delay_drop *dbg;
3870
3871 if (!mlx5_debugfs_root)
3872 return 0;
3873
3874 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3875 if (!dbg)
3876 return -ENOMEM;
3877
cbafad87
SM		 3878 dev->delay_drop.dbg = dbg;
3879
fe248c3a
MG		 3880 dbg->dir_debugfs =
3881 debugfs_create_dir("delay_drop",
3882 dev->mdev->priv.dbg_root);
3883 if (!dbg->dir_debugfs)
cbafad87 3884 goto out_debugfs;
fe248c3a
MG		 3885
3886 dbg->events_cnt_debugfs =
3887 debugfs_create_atomic_t("num_timeout_events", 0400,
3888 dbg->dir_debugfs,
3889 &dev->delay_drop.events_cnt);
3890 if (!dbg->events_cnt_debugfs)
3891 goto out_debugfs;
3892
3893 dbg->rqs_cnt_debugfs =
3894 debugfs_create_atomic_t("num_rqs", 0400,
3895 dbg->dir_debugfs,
3896 &dev->delay_drop.rqs_cnt);
3897 if (!dbg->rqs_cnt_debugfs)
3898 goto out_debugfs;
3899
3900 dbg->timeout_debugfs =
3901 debugfs_create_file("timeout", 0600,
3902 dbg->dir_debugfs,
3903 &dev->delay_drop,
3904 &fops_delay_drop_timeout);
3905 if (!dbg->timeout_debugfs)
3906 goto out_debugfs;
3907
3908 return 0;
3909
3910out_debugfs:
3911 delay_drop_debugfs_cleanup(dev);
3912 return -ENOMEM;
03404e8a
MG		 3913}
3914
3915static void init_delay_drop(struct mlx5_ib_dev *dev)
3916{
3917 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3918 return;
3919
3920 mutex_init(&dev->delay_drop.lock);
3921 dev->delay_drop.dev = dev;
3922 dev->delay_drop.activate = false;
3923 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3924 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3925 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3926 atomic_set(&dev->delay_drop.events_cnt, 0);
3927
3928 if (delay_drop_debugfs_init(dev))
3929 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3930}
3931
84305d71
LR		 3932static const struct cpumask *
3933mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 3934{
3935 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3936
3937 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3938}
3939
9603b61d 3940static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3941{
e126ba97 3942 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3943 enum rdma_link_layer ll;
3944 int port_type_cap;
4babcf97 3945 const char *name;
e126ba97
EC		 3946 int err;
3947 int i;
3948
ebd61f68
AS		 3949 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3950 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3951
e126ba97
EC		 3952 printk_once(KERN_INFO "%s", mlx5_version);
3953
3954 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3955 if (!dev)
9603b61d 3956 return NULL;
e126ba97 3957
9603b61d 3958 dev->mdev = mdev;
e126ba97 3959
0837e86a
MB		 3960 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3961 GFP_KERNEL);
3962 if (!dev->port)
3963 goto err_dealloc;
3964
fc24fc5e 3965 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3966 err = get_port_caps(dev);
3967 if (err)
0837e86a 3968 goto err_free_port;
e126ba97 3969
1b5daf11
MD		 3970 if (mlx5_use_mad_ifc(dev))
3971 get_ext_port_caps(dev);
e126ba97 3972
4babcf97
AH		 3973 if (!mlx5_lag_is_active(mdev))
3974 name = "mlx5_%d";
3975 else
3976 name = "mlx5_bond_%d";
3977
3978 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3979 dev->ib_dev.owner = THIS_MODULE;
3980 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3981 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3982 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3983 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3984 dev->ib_dev.num_comp_vectors =
3985 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3986 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3987
3988 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3989 dev->ib_dev.uverbs_cmd_mask =
3990 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3991 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3992 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3993 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3994 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3995 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3996 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3997 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3998 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3999 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4000 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4001 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4002 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4003 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4004 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4005 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4006 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4007 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4008 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4009 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4010 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4011 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4012 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4013 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4014 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4015 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4016 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4017 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4018 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 4019 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
4020 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 4021
4022 dev->ib_dev.query_device = mlx5_ib_query_device;
4023 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4024 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 4025 if (ll == IB_LINK_LAYER_ETHERNET)
4026 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 4027 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4028 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4029 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4030 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4031 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4032 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4033 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4034 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4035 dev->ib_dev.mmap = mlx5_ib_mmap;
4036 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4037 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4038 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4039 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4040 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4041 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4042 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4043 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4044 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4045 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4046 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4047 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4048 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4049 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4050 dev->ib_dev.post_send = mlx5_ib_post_send;
4051 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4052 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4053 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4054 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4055 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4056 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4057 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4058 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4059 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4060 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4061 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4062 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4063 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4064 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4065 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4066 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4067 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4068 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4069 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4070 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4071 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4072 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4073
eff901d3
EC		 4074 if (mlx5_core_is_pf(mdev)) {
4075 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4076 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4077 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4078 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4079 }
e126ba97 4080
7c2344c3
MG		 4081 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4082
938fe83c 4083 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 4084
6e8484c5
MG		 4085 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4086
d2370e0a
MB		 4087 if (MLX5_CAP_GEN(mdev, imaicl)) {
4088 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4089 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4090 dev->ib_dev.uverbs_cmd_mask |=
4091 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4092 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4093 }
4094
7c16f477 4095 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 4096 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4097 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4098 }
4099
938fe83c 4100 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4101 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4102 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4103 dev->ib_dev.uverbs_cmd_mask |=
4104 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4105 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4106 }
4107
81e30880
YH		 4108 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4109 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4110 dev->ib_dev.uverbs_ex_cmd_mask |=
4111 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4112 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4113
048ccca8 4114 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4115 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4116 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4117 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4118 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4119 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4120 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4121 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4122 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4123 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4124 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4125 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4126 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4127 }
e126ba97
EC		 4128 err = init_node_data(dev);
4129 if (err)
90be7c8a 4130 goto err_free_port;
e126ba97 4131
038d2ef8 4132 mutex_init(&dev->flow_db.lock);
e126ba97 4133 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4134 INIT_LIST_HEAD(&dev->qp_list);
4135 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4136
fc24fc5e 4137 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4138 err = mlx5_enable_eth(dev);
fc24fc5e 4139 if (err)
90be7c8a 4140 goto err_free_port;
fd65f1b8 4141 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4142 }
4143
e126ba97
EC		 4144 err = create_dev_resources(&dev->devr);
4145 if (err)
45f95acd 4146 goto err_disable_eth;
e126ba97 4147
6aec21f6 4148 err = mlx5_ib_odp_init_one(dev);
281d1a92 4149 if (err)
e126ba97
EC		 4150 goto err_rsrc;
4151
45bded2c 4152 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4153 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4154 if (err)
4155 goto err_odp;
4156 }
6aec21f6 4157
4a2da0b8
PP		 4158 err = mlx5_ib_init_cong_debugfs(dev);
4159 if (err)
4160 goto err_cnt;
4161
5fe9dec0
EC		 4162 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4163 if (!dev->mdev->priv.uar)
4a2da0b8 4164 goto err_cong;
5fe9dec0
EC		 4165
4166 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4167 if (err)
4168 goto err_uar_page;
4169
4170 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4171 if (err)
4172 goto err_bfreg;
4173
0837e86a
MB		 4174 err = ib_register_device(&dev->ib_dev, NULL);
4175 if (err)
5fe9dec0 4176 goto err_fp_bfreg;
0837e86a 4177
e126ba97
EC		 4178 err = create_umr_res(dev);
4179 if (err)
4180 goto err_dev;
4181
03404e8a
MG		 4182 init_delay_drop(dev);
4183
e126ba97 4184 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4185 err = device_create_file(&dev->ib_dev.dev,
4186 mlx5_class_attributes[i]);
4187 if (err)
03404e8a 4188 goto err_delay_drop;
e126ba97
EC		 4189 }
4190
c85023e1
HN		 4191 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4192 MLX5_CAP_GEN(mdev, disable_local_lb))
4193 mutex_init(&dev->lb_mutex);
4194
e126ba97
EC		 4195 dev->ib_active = true;
4196
9603b61d 4197 return dev;
e126ba97 4198
03404e8a
MG		 4199err_delay_drop:
4200 cancel_delay_drop(dev);
e126ba97
EC		 4201 destroy_umrc_res(dev);
4202
4203err_dev:
4204 ib_unregister_device(&dev->ib_dev);
4205
5fe9dec0
EC		 4206err_fp_bfreg:
4207 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4208
4209err_bfreg:
4210 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4211
4212err_uar_page:
4213 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4214
4a2da0b8 4215err_cong:
e19cd282
PP		 4216 mlx5_ib_cleanup_cong_debugfs(dev);
4217err_cnt:
45bded2c 4218 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4219 mlx5_ib_dealloc_counters(dev);
0837e86a 4220
6aec21f6
HE		 4221err_odp:
4222 mlx5_ib_odp_remove_one(dev);
4223
e126ba97
EC		 4224err_rsrc:
4225 destroy_dev_resources(&dev->devr);
4226
45f95acd 4227err_disable_eth:
5ec8c83e 4228 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4229 mlx5_disable_eth(dev);
d012f5d6 4230 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4231 }
fc24fc5e 4232
0837e86a
MB		 4233err_free_port:
4234 kfree(dev->port);
4235
9603b61d 4236err_dealloc:
e126ba97
EC		 4237 ib_dealloc_device((struct ib_device *)dev);
4238
9603b61d 4239 return NULL;
e126ba97
EC		 4240}
4241
9603b61d 4242static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4243{
9603b61d 4244 struct mlx5_ib_dev *dev = context;
fc24fc5e 4245 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4246
03404e8a 4247 cancel_delay_drop(dev);
d012f5d6 4248 mlx5_remove_netdev_notifier(dev);
e126ba97 4249 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4250 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4251 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4252 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4253 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4254 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4255 mlx5_ib_dealloc_counters(dev);
eefd56e5 4256 destroy_umrc_res(dev);
6aec21f6 4257 mlx5_ib_odp_remove_one(dev);
e126ba97 4258 destroy_dev_resources(&dev->devr);
fc24fc5e 4259 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4260 mlx5_disable_eth(dev);
0837e86a 4261 kfree(dev->port);
e126ba97
EC		 4262 ib_dealloc_device(&dev->ib_dev);
4263}
4264
9603b61d
JM		 4265static struct mlx5_interface mlx5_ib_interface = {
4266 .add = mlx5_ib_add,
4267 .remove = mlx5_ib_remove,
4268 .event = mlx5_ib_event,
d9aaed83
AK		 4269#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4270 .pfault = mlx5_ib_pfault,
4271#endif
64613d94 4272 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4273};
4274
4275static int __init mlx5_ib_init(void)
4276{
6aec21f6
HE		 4277 int err;
4278
81713d37 4279 mlx5_ib_odp_init();
9603b61d 4280
6aec21f6 4281 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4282
6aec21f6 4283 return err;
e126ba97
EC		 4284}
4285
4286static void __exit mlx5_ib_cleanup(void)
4287{
9603b61d 4288 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4289}
4290
4291module_init(mlx5_ib_init);
4292module_exit(mlx5_ib_cleanup);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git