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RDMA/rxe: Remove unused addr_same()
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
443c1cf9 40#include "cmd.h"
e126ba97
EC		 41
42/* not supported currently */
43static int wq_signature;
44
45enum {
46 MLX5_IB_ACK_REQ_FREQ = 8,
47};
48
49enum {
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
54};
55
56enum {
57 MLX5_IB_SQ_STRIDE = 6,
064e5262 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
e126ba97
EC		 59};
60
61static const u32 mlx5_ib_opcode[] = {
62 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 63 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
76};
77
f0313965
ES		 78struct mlx5_wqe_eth_pad {
79 u8 rsvd0[16];
80};
e126ba97 81
eb49ab0c
AV		 82enum raw_qp_set_mask_map {
83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 85};
86
0680efa2
AV		 87struct mlx5_modify_raw_qp_param {
88 u16 operation;
eb49ab0c
AV		 89
90 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 91
92 struct mlx5_rate_limit rl;
93
eb49ab0c 94 u8 rq_q_ctr_id;
0680efa2
AV		 95};
96
89ea94a7
MG		 97static void get_cqs(enum ib_qp_type qp_type,
98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100
e126ba97
EC		 101static int is_qp0(enum ib_qp_type qp_type)
102{
103 return qp_type == IB_QPT_SMI;
104}
105
e126ba97
EC		 106static int is_sqp(enum ib_qp_type qp_type)
107{
108 return is_qp0(qp_type) || is_qp1(qp_type);
109}
110
111static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
112{
113 return mlx5_buf_offset(&qp->buf, offset);
114}
115
116static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
117{
118 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
119}
120
121void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
122{
123 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
124}
125
c1395a2a
HE		 126/**
127 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
128 *
129 * @qp: QP to copy from.
130 * @send: copy from the send queue when non-zero, use the receive queue
131 * otherwise.
132 * @wqe_index: index to start copying from. For send work queues, the
133 * wqe_index is in units of MLX5_SEND_WQE_BB.
134 * For receive work queue, it is the number of work queue
135 * element in the queue.
136 * @buffer: destination buffer.
137 * @length: maximum number of bytes to copy.
138 *
139 * Copies at least a single WQE, but may copy more data.
140 *
141 * Return: the number of bytes copied, or an error code.
142 */
143int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 144 void *buffer, u32 length,
145 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 146{
147 struct ib_device *ibdev = qp->ibqp.device;
148 struct mlx5_ib_dev *dev = to_mdev(ibdev);
149 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
150 size_t offset;
151 size_t wq_end;
19098df2 152 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 153 u32 first_copy_length;
154 int wqe_length;
155 int ret;
156
157 if (wq->wqe_cnt == 0) {
158 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
159 qp->ibqp.qp_type);
160 return -EINVAL;
161 }
162
163 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
164 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
165
166 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
167 return -EINVAL;
168
169 if (offset > umem->length ||
170 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
171 return -EINVAL;
172
173 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
174 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
175 if (ret)
176 return ret;
177
178 if (send) {
179 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
180 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
181
182 wqe_length = ds * MLX5_WQE_DS_UNITS;
183 } else {
184 wqe_length = 1 << wq->wqe_shift;
185 }
186
187 if (wqe_length <= first_copy_length)
188 return first_copy_length;
189
190 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
191 wqe_length - first_copy_length);
192 if (ret)
193 return ret;
194
195 return wqe_length;
196}
197
e126ba97
EC		 198static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
199{
200 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
201 struct ib_event event;
202
19098df2 203 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
204 /* This event is only valid for trans_qps */
205 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
206 }
e126ba97
EC		 207
208 if (ibqp->event_handler) {
209 event.device = ibqp->device;
210 event.element.qp = ibqp;
211 switch (type) {
212 case MLX5_EVENT_TYPE_PATH_MIG:
213 event.event = IB_EVENT_PATH_MIG;
214 break;
215 case MLX5_EVENT_TYPE_COMM_EST:
216 event.event = IB_EVENT_COMM_EST;
217 break;
218 case MLX5_EVENT_TYPE_SQ_DRAINED:
219 event.event = IB_EVENT_SQ_DRAINED;
220 break;
221 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
222 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 break;
224 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
225 event.event = IB_EVENT_QP_FATAL;
226 break;
227 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
228 event.event = IB_EVENT_PATH_MIG_ERR;
229 break;
230 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
231 event.event = IB_EVENT_QP_REQ_ERR;
232 break;
233 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
234 event.event = IB_EVENT_QP_ACCESS_ERR;
235 break;
236 default:
237 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
238 return;
239 }
240
241 ibqp->event_handler(&event, ibqp->qp_context);
242 }
243}
244
245static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
246 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
247{
248 int wqe_size;
249 int wq_size;
250
251 /* Sanity check RQ size before proceeding */
938fe83c 252 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 253 return -EINVAL;
254
255 if (!has_rq) {
256 qp->rq.max_gs = 0;
257 qp->rq.wqe_cnt = 0;
258 qp->rq.wqe_shift = 0;
0540d814
NO		 259 cap->max_recv_wr = 0;
260 cap->max_recv_sge = 0;
e126ba97
EC		 261 } else {
262 if (ucmd) {
263 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 264 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
265 return -EINVAL;
e126ba97 266 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
002bf228
LR		 267 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
268 return -EINVAL;
e126ba97
EC		 269 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
270 qp->rq.max_post = qp->rq.wqe_cnt;
271 } else {
272 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
273 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
274 wqe_size = roundup_pow_of_two(wqe_size);
275 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
276 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
277 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 278 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 279 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
280 wqe_size,
938fe83c
SM		 281 MLX5_CAP_GEN(dev->mdev,
282 max_wqe_sz_rq));
e126ba97
EC		 283 return -EINVAL;
284 }
285 qp->rq.wqe_shift = ilog2(wqe_size);
286 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
287 qp->rq.max_post = qp->rq.wqe_cnt;
288 }
289 }
290
291 return 0;
292}
293
f0313965 294static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 295{
618af384 296 int size = 0;
e126ba97 297
f0313965 298 switch (attr->qp_type) {
e126ba97 299 case IB_QPT_XRC_INI:
b125a54b 300 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 301 /* fall through */
302 case IB_QPT_RC:
303 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 304 max(sizeof(struct mlx5_wqe_atomic_seg) +
305 sizeof(struct mlx5_wqe_raddr_seg),
306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 307 sizeof(struct mlx5_mkey_seg) +
308 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
309 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 310 break;
311
b125a54b
EC		 312 case IB_QPT_XRC_TGT:
313 return 0;
314
e126ba97 315 case IB_QPT_UC:
b125a54b 316 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 317 max(sizeof(struct mlx5_wqe_raddr_seg),
318 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
319 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 320 break;
321
322 case IB_QPT_UD:
f0313965
ES		 323 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
324 size += sizeof(struct mlx5_wqe_eth_pad) +
325 sizeof(struct mlx5_wqe_eth_seg);
326 /* fall through */
e126ba97 327 case IB_QPT_SMI:
d16e91da 328 case MLX5_IB_QPT_HW_GSI:
b125a54b 329 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 330 sizeof(struct mlx5_wqe_datagram_seg);
331 break;
332
333 case MLX5_IB_QPT_REG_UMR:
b125a54b 334 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 335 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
336 sizeof(struct mlx5_mkey_seg);
337 break;
338
339 default:
340 return -EINVAL;
341 }
342
343 return size;
344}
345
346static int calc_send_wqe(struct ib_qp_init_attr *attr)
347{
348 int inl_size = 0;
349 int size;
350
f0313965 351 size = sq_overhead(attr);
e126ba97
EC		 352 if (size < 0)
353 return size;
354
355 if (attr->cap.max_inline_data) {
356 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
357 attr->cap.max_inline_data;
358 }
359
360 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 361 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
362 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
363 return MLX5_SIG_WQE_SIZE;
364 else
365 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 366}
367
288c01b7
EC		 368static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
369{
370 int max_sge;
371
372 if (attr->qp_type == IB_QPT_RC)
373 max_sge = (min_t(int, wqe_size, 512) -
374 sizeof(struct mlx5_wqe_ctrl_seg) -
375 sizeof(struct mlx5_wqe_raddr_seg)) /
376 sizeof(struct mlx5_wqe_data_seg);
377 else if (attr->qp_type == IB_QPT_XRC_INI)
378 max_sge = (min_t(int, wqe_size, 512) -
379 sizeof(struct mlx5_wqe_ctrl_seg) -
380 sizeof(struct mlx5_wqe_xrc_seg) -
381 sizeof(struct mlx5_wqe_raddr_seg)) /
382 sizeof(struct mlx5_wqe_data_seg);
383 else
384 max_sge = (wqe_size - sq_overhead(attr)) /
385 sizeof(struct mlx5_wqe_data_seg);
386
387 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
388 sizeof(struct mlx5_wqe_data_seg));
389}
390
e126ba97
EC		 391static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
392 struct mlx5_ib_qp *qp)
393{
394 int wqe_size;
395 int wq_size;
396
397 if (!attr->cap.max_send_wr)
398 return 0;
399
400 wqe_size = calc_send_wqe(attr);
401 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
402 if (wqe_size < 0)
403 return wqe_size;
404
938fe83c 405 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 406 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 407 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 408 return -EINVAL;
409 }
410
f0313965
ES		 411 qp->max_inline_data = wqe_size - sq_overhead(attr) -
412 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 413 attr->cap.max_inline_data = qp->max_inline_data;
414
e1e66cc2
SG		 415 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
416 qp->signature_en = true;
417
e126ba97
EC		 418 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
419 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 420 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 421 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
422 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 423 qp->sq.wqe_cnt,
424 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 425 return -ENOMEM;
426 }
e126ba97 427 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 428 qp->sq.max_gs = get_send_sge(attr, wqe_size);
429 if (qp->sq.max_gs < attr->cap.max_send_sge)
430 return -ENOMEM;
431
432 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 433 qp->sq.max_post = wq_size / wqe_size;
434 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 435
436 return wq_size;
437}
438
439static int set_user_buf_size(struct mlx5_ib_dev *dev,
440 struct mlx5_ib_qp *qp,
19098df2 441 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 442 struct mlx5_ib_qp_base *base,
443 struct ib_qp_init_attr *attr)
e126ba97
EC		 444{
445 int desc_sz = 1 << qp->sq.wqe_shift;
446
938fe83c 447 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 448 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 449 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 450 return -EINVAL;
451 }
452
453 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
454 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
455 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
456 return -EINVAL;
457 }
458
459 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
460
938fe83c 461 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 462 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 463 qp->sq.wqe_cnt,
464 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 465 return -EINVAL;
466 }
467
c2e53b2c
YH		 468 if (attr->qp_type == IB_QPT_RAW_PACKET ||
469 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 470 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
471 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
472 } else {
473 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
474 (qp->sq.wqe_cnt << 6);
475 }
e126ba97
EC		 476
477 return 0;
478}
479
480static int qp_has_rq(struct ib_qp_init_attr *attr)
481{
482 if (attr->qp_type == IB_QPT_XRC_INI ||
483 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
484 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
485 !attr->cap.max_recv_wr)
486 return 0;
487
488 return 1;
489}
490
0b80c14f
EC		 491enum {
492 /* this is the first blue flame register in the array of bfregs assigned
493 * to a processes. Since we do not use it for blue flame but rather
494 * regular 64 bit doorbells, we do not need a lock for maintaiing
495 * "odd/even" order
496 */
497 NUM_NON_BLUE_FLAME_BFREGS = 1,
498};
499
b037c29a
EC		 500static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
501{
31a78a5a 502 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 503}
504
505static int num_med_bfreg(struct mlx5_ib_dev *dev,
506 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 507{
508 int n;
509
b037c29a
EC		 510 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
511 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 512
513 return n >= 0 ? n : 0;
514}
515
18b0362e
YH		 516static int first_med_bfreg(struct mlx5_ib_dev *dev,
517 struct mlx5_bfreg_info *bfregi)
518{
519 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
520}
521
b037c29a
EC		 522static int first_hi_bfreg(struct mlx5_ib_dev *dev,
523 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 524{
525 int med;
c1be5232 526
b037c29a
EC		 527 med = num_med_bfreg(dev, bfregi);
528 return ++med;
c1be5232
EC		 529}
530
b037c29a
EC		 531static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
532 struct mlx5_bfreg_info *bfregi)
e126ba97 533{
e126ba97
EC		 534 int i;
535
b037c29a
EC		 536 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
537 if (!bfregi->count[i]) {
2f5ff264 538 bfregi->count[i]++;
e126ba97
EC		 539 return i;
540 }
541 }
542
543 return -ENOMEM;
544}
545
b037c29a
EC		 546static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
547 struct mlx5_bfreg_info *bfregi)
e126ba97 548{
18b0362e 549 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 550 int i;
551
18b0362e
YH		 552 if (minidx < 0)
553 return minidx;
554
555 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 556 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 557 minidx = i;
0b80c14f
EC		 558 if (!bfregi->count[minidx])
559 break;
e126ba97
EC		 560 }
561
2f5ff264 562 bfregi->count[minidx]++;
e126ba97
EC		 563 return minidx;
564}
565
b037c29a 566static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 567 struct mlx5_bfreg_info *bfregi)
e126ba97 568{
ffaf58de 569 int bfregn = -ENOMEM;
e126ba97 570
2f5ff264 571 mutex_lock(&bfregi->lock);
ffaf58de
LR		 572 if (bfregi->ver >= 2) {
573 bfregn = alloc_high_class_bfreg(dev, bfregi);
574 if (bfregn < 0)
575 bfregn = alloc_med_class_bfreg(dev, bfregi);
576 }
577
578 if (bfregn < 0) {
0b80c14f 579 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 580 bfregn = 0;
581 bfregi->count[bfregn]++;
e126ba97 582 }
2f5ff264 583 mutex_unlock(&bfregi->lock);
e126ba97 584
2f5ff264 585 return bfregn;
e126ba97
EC		 586}
587
4ed131d0 588void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 589{
2f5ff264 590 mutex_lock(&bfregi->lock);
b037c29a 591 bfregi->count[bfregn]--;
2f5ff264 592 mutex_unlock(&bfregi->lock);
e126ba97
EC		 593}
594
595static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
596{
597 switch (state) {
598 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
599 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
600 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
601 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
602 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
603 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
604 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
605 default: return -1;
606 }
607}
608
609static int to_mlx5_st(enum ib_qp_type type)
610{
611 switch (type) {
612 case IB_QPT_RC: return MLX5_QP_ST_RC;
613 case IB_QPT_UC: return MLX5_QP_ST_UC;
614 case IB_QPT_UD: return MLX5_QP_ST_UD;
615 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
616 case IB_QPT_XRC_INI:
617 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
618 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 619 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 620 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 621 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 622 case IB_QPT_RAW_PACKET:
0fb2ed66 623 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 624 case IB_QPT_MAX:
625 default: return -EINVAL;
626 }
627}
628
89ea94a7
MG		 629static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
630 struct mlx5_ib_cq *recv_cq);
631static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
632 struct mlx5_ib_cq *recv_cq);
633
7c043e90 634int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 635 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 636 bool dyn_bfreg)
e126ba97 637{
05f58ceb
LR		 638 unsigned int bfregs_per_sys_page;
639 u32 index_of_sys_page;
640 u32 offset;
b037c29a
EC		 641
642 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
643 MLX5_NON_FP_BFREGS_PER_UAR;
644 index_of_sys_page = bfregn / bfregs_per_sys_page;
645
1ee47ab3
YH		 646 if (dyn_bfreg) {
647 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 648
649 if (index_of_sys_page >= bfregi->num_sys_pages)
650 return -EINVAL;
651
1ee47ab3
YH		 652 if (bfregn > bfregi->num_dyn_bfregs ||
653 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
654 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
655 return -EINVAL;
656 }
657 }
b037c29a 658
1ee47ab3 659 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 660 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 661}
662
19098df2 663static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
664 struct ib_pd *pd,
665 unsigned long addr, size_t size,
666 struct ib_umem **umem,
667 int *npages, int *page_shift, int *ncont,
668 u32 *offset)
669{
670 int err;
671
672 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
673 if (IS_ERR(*umem)) {
674 mlx5_ib_dbg(dev, "umem_get failed\n");
675 return PTR_ERR(*umem);
676 }
677
762f899a 678 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 679
680 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
681 if (err) {
682 mlx5_ib_warn(dev, "bad offset\n");
683 goto err_umem;
684 }
685
686 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
687 addr, size, *npages, *page_shift, *ncont, *offset);
688
689 return 0;
690
691err_umem:
692 ib_umem_release(*umem);
693 *umem = NULL;
694
695 return err;
696}
697
fe248c3a
MG		 698static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
699 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 700{
701 struct mlx5_ib_ucontext *context;
702
fe248c3a
MG		 703 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
704 atomic_dec(&dev->delay_drop.rqs_cnt);
705
79b20a6c
YH		 706 context = to_mucontext(pd->uobject->context);
707 mlx5_ib_db_unmap_user(context, &rwq->db);
708 if (rwq->umem)
709 ib_umem_release(rwq->umem);
710}
711
712static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
713 struct mlx5_ib_rwq *rwq,
714 struct mlx5_ib_create_wq *ucmd)
715{
716 struct mlx5_ib_ucontext *context;
717 int page_shift = 0;
718 int npages;
719 u32 offset = 0;
720 int ncont = 0;
721 int err;
722
723 if (!ucmd->buf_addr)
724 return -EINVAL;
725
726 context = to_mucontext(pd->uobject->context);
727 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
728 rwq->buf_size, 0, 0);
729 if (IS_ERR(rwq->umem)) {
730 mlx5_ib_dbg(dev, "umem_get failed\n");
731 err = PTR_ERR(rwq->umem);
732 return err;
733 }
734
762f899a 735 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 736 &ncont, NULL);
737 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
738 &rwq->rq_page_offset);
739 if (err) {
740 mlx5_ib_warn(dev, "bad offset\n");
741 goto err_umem;
742 }
743
744 rwq->rq_num_pas = ncont;
745 rwq->page_shift = page_shift;
746 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
747 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
748
749 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
750 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
751 npages, page_shift, ncont, offset);
752
753 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
754 if (err) {
755 mlx5_ib_dbg(dev, "map failed\n");
756 goto err_umem;
757 }
758
759 rwq->create_type = MLX5_WQ_USER;
760 return 0;
761
762err_umem:
763 ib_umem_release(rwq->umem);
764 return err;
765}
766
b037c29a
EC		 767static int adjust_bfregn(struct mlx5_ib_dev *dev,
768 struct mlx5_bfreg_info *bfregi, int bfregn)
769{
770 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
771 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
772}
773
e126ba97
EC		 774static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
775 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 776 struct ib_qp_init_attr *attr,
09a7d9ec 777 u32 **in,
19098df2 778 struct mlx5_ib_create_qp_resp *resp, int *inlen,
779 struct mlx5_ib_qp_base *base)
e126ba97
EC		 780{
781 struct mlx5_ib_ucontext *context;
782 struct mlx5_ib_create_qp ucmd;
19098df2 783 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 784 int page_shift = 0;
1ee47ab3 785 int uar_index = 0;
e126ba97 786 int npages;
9e9c47d0 787 u32 offset = 0;
2f5ff264 788 int bfregn;
9e9c47d0 789 int ncont = 0;
09a7d9ec
SM		 790 __be64 *pas;
791 void *qpc;
e126ba97
EC		 792 int err;
793
794 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
795 if (err) {
796 mlx5_ib_dbg(dev, "copy failed\n");
797 return err;
798 }
799
800 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 801 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
802 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
803 ucmd.bfreg_index, true);
804 if (uar_index < 0)
805 return uar_index;
806
807 bfregn = MLX5_IB_INVALID_BFREG;
808 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
809 /*
810 * TBD: should come from the verbs when we have the API
811 */
051f2630 812 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 813 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 814 }
051f2630 815 else {
ffaf58de
LR		 816 bfregn = alloc_bfreg(dev, &context->bfregi);
817 if (bfregn < 0)
818 return bfregn;
e126ba97
EC		 819 }
820
2f5ff264 821 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 822 if (bfregn != MLX5_IB_INVALID_BFREG)
823 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
824 false);
e126ba97 825
48fea837
HE		 826 qp->rq.offset = 0;
827 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
828 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
829
0fb2ed66 830 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 831 if (err)
2f5ff264 832 goto err_bfreg;
e126ba97 833
19098df2 834 if (ucmd.buf_addr && ubuffer->buf_size) {
835 ubuffer->buf_addr = ucmd.buf_addr;
836 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
837 ubuffer->buf_size,
838 &ubuffer->umem, &npages, &page_shift,
839 &ncont, &offset);
840 if (err)
2f5ff264 841 goto err_bfreg;
9e9c47d0 842 } else {
19098df2 843 ubuffer->umem = NULL;
e126ba97 844 }
e126ba97 845
09a7d9ec
SM		 846 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
847 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 848 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 849 if (!*in) {
850 err = -ENOMEM;
851 goto err_umem;
852 }
09a7d9ec 853
991d2198 854 MLX5_SET(create_qp_in, *in, uid, to_mpd(pd)->uid);
09a7d9ec 855 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 856 if (ubuffer->umem)
09a7d9ec
SM		 857 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
858
859 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
860
861 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
862 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 863
09a7d9ec 864 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 865 if (bfregn != MLX5_IB_INVALID_BFREG)
866 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
867 else
868 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 869 qp->bfregn = bfregn;
e126ba97
EC		 870
871 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
872 if (err) {
873 mlx5_ib_dbg(dev, "map failed\n");
874 goto err_free;
875 }
876
41d902cb 877 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
e126ba97
EC		 878 if (err) {
879 mlx5_ib_dbg(dev, "copy failed\n");
880 goto err_unmap;
881 }
882 qp->create_type = MLX5_QP_USER;
883
884 return 0;
885
886err_unmap:
887 mlx5_ib_db_unmap_user(context, &qp->db);
888
889err_free:
479163f4 890 kvfree(*in);
e126ba97
EC		 891
892err_umem:
19098df2 893 if (ubuffer->umem)
894 ib_umem_release(ubuffer->umem);
e126ba97 895
2f5ff264 896err_bfreg:
1ee47ab3
YH		 897 if (bfregn != MLX5_IB_INVALID_BFREG)
898 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 899 return err;
900}
901
b037c29a
EC		 902static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
903 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 904{
905 struct mlx5_ib_ucontext *context;
906
907 context = to_mucontext(pd->uobject->context);
908 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 909 if (base->ubuffer.umem)
910 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 911
912 /*
913 * Free only the BFREGs which are handled by the kernel.
914 * BFREGs of UARs allocated dynamically are handled by user.
915 */
916 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
917 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 918}
919
920static int create_kernel_qp(struct mlx5_ib_dev *dev,
921 struct ib_qp_init_attr *init_attr,
922 struct mlx5_ib_qp *qp,
09a7d9ec 923 u32 **in, int *inlen,
19098df2 924 struct mlx5_ib_qp_base *base)
e126ba97 925{
e126ba97 926 int uar_index;
09a7d9ec 927 void *qpc;
e126ba97
EC		 928 int err;
929
f0313965
ES		 930 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
931 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 932 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 933 IB_QP_CREATE_NETIF_QP |
b11a4f9c 934 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 935 return -EINVAL;
e126ba97
EC		 936
937 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 938 qp->bf.bfreg = &dev->fp_bfreg;
939 else
940 qp->bf.bfreg = &dev->bfreg;
e126ba97 941
d8030b0d
EC		 942 /* We need to divide by two since each register is comprised of
943 * two buffers of identical size, namely odd and even
944 */
945 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 946 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 947
948 err = calc_sq_size(dev, init_attr, qp);
949 if (err < 0) {
950 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 951 return err;
e126ba97
EC		 952 }
953
954 qp->rq.offset = 0;
955 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 956 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 957
19098df2 958 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 959 if (err) {
960 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 961 return err;
e126ba97
EC		 962 }
963
964 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 965 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
966 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 967 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 968 if (!*in) {
969 err = -ENOMEM;
970 goto err_buf;
971 }
09a7d9ec
SM		 972
973 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
974 MLX5_SET(qpc, qpc, uar_page, uar_index);
975 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
976
e126ba97 977 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 978 MLX5_SET(qpc, qpc, fre, 1);
979 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 980
b11a4f9c 981 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 982 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 983 qp->flags |= MLX5_IB_QP_SQPN_QP1;
984 }
985
09a7d9ec
SM		 986 mlx5_fill_page_array(&qp->buf,
987 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 988
9603b61d 989 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 990 if (err) {
991 mlx5_ib_dbg(dev, "err %d\n", err);
992 goto err_free;
993 }
994
b5883008
LD		 995 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
996 sizeof(*qp->sq.wrid), GFP_KERNEL);
997 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
998 sizeof(*qp->sq.wr_data), GFP_KERNEL);
999 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1000 sizeof(*qp->rq.wrid), GFP_KERNEL);
1001 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1002 sizeof(*qp->sq.w_list), GFP_KERNEL);
1003 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1004 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1005
1006 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1007 !qp->sq.w_list || !qp->sq.wqe_head) {
1008 err = -ENOMEM;
1009 goto err_wrid;
1010 }
1011 qp->create_type = MLX5_QP_KERNEL;
1012
1013 return 0;
1014
1015err_wrid:
b5883008
LD		 1016 kvfree(qp->sq.wqe_head);
1017 kvfree(qp->sq.w_list);
1018 kvfree(qp->sq.wrid);
1019 kvfree(qp->sq.wr_data);
1020 kvfree(qp->rq.wrid);
f4044dac 1021 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1022
1023err_free:
479163f4 1024 kvfree(*in);
e126ba97
EC		 1025
1026err_buf:
9603b61d 1027 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1028 return err;
1029}
1030
1031static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1032{
b5883008
LD		 1033 kvfree(qp->sq.wqe_head);
1034 kvfree(qp->sq.w_list);
1035 kvfree(qp->sq.wrid);
1036 kvfree(qp->sq.wr_data);
1037 kvfree(qp->rq.wrid);
f4044dac 1038 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1039 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1040}
1041
09a7d9ec 1042static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1043{
1044 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1045 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1046 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1047 return MLX5_SRQ_RQ;
e126ba97 1048 else if (!qp->has_rq)
09a7d9ec 1049 return MLX5_ZERO_LEN_RQ;
e126ba97 1050 else
09a7d9ec 1051 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1052}
1053
1054static int is_connected(enum ib_qp_type qp_type)
1055{
1056 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1057 return 1;
1058
1059 return 0;
1060}
1061
0fb2ed66 1062static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1063 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1064 struct mlx5_ib_sq *sq, u32 tdn,
1065 struct ib_pd *pd)
0fb2ed66 1066{
c4f287c4 1067 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1068 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1069
1cd6dbd3 1070 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1071 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1072 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1073 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1074
0fb2ed66 1075 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1076}
1077
1078static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1079 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1080{
1cd6dbd3 1081 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1082}
1083
b96c9dde
MB		 1084static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1085 struct mlx5_ib_sq *sq)
1086{
1087 if (sq->flow_rule)
1088 mlx5_del_flow_rules(sq->flow_rule);
1089}
1090
0fb2ed66 1091static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1092 struct mlx5_ib_sq *sq, void *qpin,
1093 struct ib_pd *pd)
1094{
1095 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1096 __be64 *pas;
1097 void *in;
1098 void *sqc;
1099 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1100 void *wq;
1101 int inlen;
1102 int err;
1103 int page_shift = 0;
1104 int npages;
1105 int ncont = 0;
1106 u32 offset = 0;
1107
1108 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1109 &sq->ubuffer.umem, &npages, &page_shift,
1110 &ncont, &offset);
1111 if (err)
1112 return err;
1113
1114 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1115 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1116 if (!in) {
1117 err = -ENOMEM;
1118 goto err_umem;
1119 }
1120
c14003f0 1121 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1122 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1123 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1124 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1125 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1126 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1127 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1128 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1129 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1130 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1131 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1132 MLX5_CAP_ETH(dev->mdev, swp))
1133 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1134
1135 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1136 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1137 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1138 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1139 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1140 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1141 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1142 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1143 MLX5_SET(wq, wq, page_offset, offset);
1144
1145 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1146 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1147
1148 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1149
1150 kvfree(in);
1151
1152 if (err)
1153 goto err_umem;
1154
b96c9dde
MB		 1155 err = create_flow_rule_vport_sq(dev, sq);
1156 if (err)
1157 goto err_flow;
1158
0fb2ed66 1159 return 0;
1160
b96c9dde
MB		 1161err_flow:
1162 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1163
0fb2ed66 1164err_umem:
1165 ib_umem_release(sq->ubuffer.umem);
1166 sq->ubuffer.umem = NULL;
1167
1168 return err;
1169}
1170
1171static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1172 struct mlx5_ib_sq *sq)
1173{
b96c9dde 1174 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1175 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1176 ib_umem_release(sq->ubuffer.umem);
1177}
1178
2c292dbb 1179static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1180{
1181 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1182 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1183 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1184 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1185 u32 po_quanta = 1 << (log_page_size - 6);
1186 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1187 u32 page_size = 1 << log_page_size;
1188 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1189 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1190
1191 return rq_num_pas * sizeof(u64);
1192}
1193
1194static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1195 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1196 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1197{
358e42ea 1198 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1199 __be64 *pas;
1200 __be64 *qp_pas;
1201 void *in;
1202 void *rqc;
1203 void *wq;
1204 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1205 size_t rq_pas_size = get_rq_pas_size(qpc);
1206 size_t inlen;
0fb2ed66 1207 int err;
2c292dbb
BP		 1208
1209 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1210 return -EINVAL;
0fb2ed66 1211
1212 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1213 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1214 if (!in)
1215 return -ENOMEM;
1216
34d57585 1217 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1218 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1219 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1220 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1221 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1222 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1223 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1224 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1225 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1226
358e42ea
MD		 1227 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1228 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1229
0fb2ed66 1230 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1231 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1232 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1233 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1234 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1235 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1236 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1237 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1238 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1239 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1240
1241 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1242 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1243 memcpy(pas, qp_pas, rq_pas_size);
1244
1245 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1246
1247 kvfree(in);
1248
1249 return err;
1250}
1251
1252static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1253 struct mlx5_ib_rq *rq)
1254{
1255 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1256}
1257
f95ef6cb
MG		 1258static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1259{
1260 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1261 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1262 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1263}
1264
0042f9e4
MB		 1265static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1266 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1267 u32 qp_flags_en,
1268 struct ib_pd *pd)
0042f9e4
MB		 1269{
1270 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1271 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1272 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1273 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1274}
1275
0fb2ed66 1276static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1277 struct mlx5_ib_rq *rq, u32 tdn,
443c1cf9
YH		 1278 u32 *qp_flags_en,
1279 struct ib_pd *pd)
0fb2ed66 1280{
175edba8 1281 u8 lb_flag = 0;
0fb2ed66 1282 u32 *in;
1283 void *tirc;
1284 int inlen;
1285 int err;
1286
1287 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1288 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1289 if (!in)
1290 return -ENOMEM;
1291
443c1cf9 1292 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1293 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1294 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1295 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1296 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1297 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1298 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1299
175edba8
MB		 1300 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1301 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1302
1303 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1304 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1305
1306 if (dev->rep) {
1307 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1308 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1309 }
1310
1311 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
ec9c2fb8 1312
0fb2ed66 1313 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1314
0042f9e4
MB		 1315 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1316 err = mlx5_ib_enable_lb(dev, false, true);
1317
1318 if (err)
443c1cf9 1319 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1320 }
0fb2ed66 1321 kvfree(in);
1322
1323 return err;
1324}
1325
0fb2ed66 1326static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1327 u32 *in, size_t inlen,
7f72052c
YH		 1328 struct ib_pd *pd,
1329 struct ib_udata *udata,
1330 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1331{
1332 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1333 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1334 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1335 struct ib_uobject *uobj = pd->uobject;
1336 struct ib_ucontext *ucontext = uobj->context;
1337 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1338 int err;
1339 u32 tdn = mucontext->tdn;
7f72052c 1340 u16 uid = to_mpd(pd)->uid;
0fb2ed66 1341
1342 if (qp->sq.wqe_cnt) {
1cd6dbd3 1343 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1344 if (err)
1345 return err;
1346
1347 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1348 if (err)
1349 goto err_destroy_tis;
1350
7f72052c
YH		 1351 if (uid) {
1352 resp->tisn = sq->tisn;
1353 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1354 resp->sqn = sq->base.mqp.qpn;
1355 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1356 }
1357
0fb2ed66 1358 sq->base.container_mibqp = qp;
1d31e9c0 1359 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1360 }
1361
1362 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1363 rq->base.container_mibqp = qp;
1364
e4cc4fa7
NO		 1365 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1366 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1367 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1368 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1369 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1370 if (err)
1371 goto err_destroy_sq;
1372
443c1cf9 1373 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
0fb2ed66 1374 if (err)
1375 goto err_destroy_rq;
7f72052c
YH		 1376
1377 if (uid) {
1378 resp->rqn = rq->base.mqp.qpn;
1379 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1380 resp->tirn = rq->tirn;
1381 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1382 }
0fb2ed66 1383 }
1384
1385 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1386 rq->base.mqp.qpn;
7f72052c
YH		 1387 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1388 if (err)
1389 goto err_destroy_tir;
0fb2ed66 1390
1391 return 0;
1392
7f72052c
YH		 1393err_destroy_tir:
1394 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
0fb2ed66 1395err_destroy_rq:
1396 destroy_raw_packet_qp_rq(dev, rq);
1397err_destroy_sq:
1398 if (!qp->sq.wqe_cnt)
1399 return err;
1400 destroy_raw_packet_qp_sq(dev, sq);
1401err_destroy_tis:
1cd6dbd3 1402 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1403
1404 return err;
1405}
1406
1407static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1408 struct mlx5_ib_qp *qp)
1409{
1410 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1411 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1412 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1413
1414 if (qp->rq.wqe_cnt) {
443c1cf9 1415 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1416 destroy_raw_packet_qp_rq(dev, rq);
1417 }
1418
1419 if (qp->sq.wqe_cnt) {
1420 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1421 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1422 }
1423}
1424
1425static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1426 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1427{
1428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1430
1431 sq->sq = &qp->sq;
1432 rq->rq = &qp->rq;
1433 sq->doorbell = &qp->db;
1434 rq->doorbell = &qp->db;
1435}
1436
28d61370
YH		 1437static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1438{
0042f9e4
MB		 1439 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1440 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1441 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1442 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1443 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1444}
1445
1446static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1447 struct ib_pd *pd,
1448 struct ib_qp_init_attr *init_attr,
1449 struct ib_udata *udata)
1450{
1451 struct ib_uobject *uobj = pd->uobject;
1452 struct ib_ucontext *ucontext = uobj->context;
1453 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1454 struct mlx5_ib_create_qp_resp resp = {};
1455 int inlen;
1456 int err;
1457 u32 *in;
1458 void *tirc;
1459 void *hfso;
1460 u32 selected_fields = 0;
2d93fc85 1461 u32 outer_l4;
28d61370
YH		 1462 size_t min_resp_len;
1463 u32 tdn = mucontext->tdn;
1464 struct mlx5_ib_create_qp_rss ucmd = {};
1465 size_t required_cmd_sz;
175edba8 1466 u8 lb_flag = 0;
28d61370
YH		 1467
1468 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1469 return -EOPNOTSUPP;
1470
1471 if (init_attr->create_flags || init_attr->send_cq)
1472 return -EINVAL;
1473
2f5ff264 1474 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1475 if (udata->outlen < min_resp_len)
1476 return -EINVAL;
1477
f95ef6cb 1478 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1479 if (udata->inlen < required_cmd_sz) {
1480 mlx5_ib_dbg(dev, "invalid inlen\n");
1481 return -EINVAL;
1482 }
1483
1484 if (udata->inlen > sizeof(ucmd) &&
1485 !ib_is_udata_cleared(udata, sizeof(ucmd),
1486 udata->inlen - sizeof(ucmd))) {
1487 mlx5_ib_dbg(dev, "inlen is not supported\n");
1488 return -EOPNOTSUPP;
1489 }
1490
1491 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1492 mlx5_ib_dbg(dev, "copy failed\n");
1493 return -EFAULT;
1494 }
1495
1496 if (ucmd.comp_mask) {
1497 mlx5_ib_dbg(dev, "invalid comp mask\n");
1498 return -EOPNOTSUPP;
1499 }
1500
175edba8
MB		 1501 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1502 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1503 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
f95ef6cb
MG		 1504 mlx5_ib_dbg(dev, "invalid flags\n");
1505 return -EOPNOTSUPP;
1506 }
1507
1508 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1509 !tunnel_offload_supported(dev->mdev)) {
1510 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1511 return -EOPNOTSUPP;
1512 }
1513
309fa347
MG		 1514 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1515 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1516 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1517 return -EOPNOTSUPP;
1518 }
1519
175edba8
MB		 1520 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1521 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1522 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1523 }
1524
1525 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1526 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1527 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1528 }
1529
41d902cb 1530 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
28d61370
YH		 1531 if (err) {
1532 mlx5_ib_dbg(dev, "copy failed\n");
1533 return -EINVAL;
1534 }
1535
1536 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1537 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1538 if (!in)
1539 return -ENOMEM;
1540
443c1cf9 1541 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1542 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1543 MLX5_SET(tirc, tirc, disp_type,
1544 MLX5_TIRC_DISP_TYPE_INDIRECT);
1545 MLX5_SET(tirc, tirc, indirect_table,
1546 init_attr->rwq_ind_tbl->ind_tbl_num);
1547 MLX5_SET(tirc, tirc, transport_domain, tdn);
1548
1549 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1550
1551 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1552 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1553
175edba8
MB		 1554 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1555
309fa347
MG		 1556 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1557 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1558 else
1559 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1560
28d61370
YH		 1561 switch (ucmd.rx_hash_function) {
1562 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1563 {
1564 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1565 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1566
1567 if (len != ucmd.rx_key_len) {
1568 err = -EINVAL;
1569 goto err;
1570 }
1571
1572 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1573 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1574 memcpy(rss_key, ucmd.rx_hash_key, len);
1575 break;
1576 }
1577 default:
1578 err = -EOPNOTSUPP;
1579 goto err;
1580 }
1581
1582 if (!ucmd.rx_hash_fields_mask) {
1583 /* special case when this TIR serves as steering entry without hashing */
1584 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1585 goto create_tir;
1586 err = -EINVAL;
1587 goto err;
1588 }
1589
1590 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1591 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1592 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1593 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1594 err = -EINVAL;
1595 goto err;
1596 }
1597
1598 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1599 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1600 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1601 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1602 MLX5_L3_PROT_TYPE_IPV4);
1603 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1604 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1605 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1606 MLX5_L3_PROT_TYPE_IPV6);
1607
2d93fc85
MB		 1608 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1609 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1610 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1611 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1612 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1613
1614 /* Check that only one l4 protocol is set */
1615 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1616 err = -EINVAL;
1617 goto err;
1618 }
1619
1620 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1621 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1622 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1623 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1624 MLX5_L4_PROT_TYPE_TCP);
1625 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1626 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1627 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1628 MLX5_L4_PROT_TYPE_UDP);
1629
1630 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1631 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1632 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1633
1634 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1635 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1636 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1637
1638 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1639 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1640 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1641
1642 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1643 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1644 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1645
2d93fc85
MB		 1646 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1647 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1648
28d61370
YH		 1649 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1650
1651create_tir:
1652 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1653
0042f9e4
MB		 1654 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1655 err = mlx5_ib_enable_lb(dev, false, true);
1656
1657 if (err)
443c1cf9
YH		 1658 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1659 to_mpd(pd)->uid);
0042f9e4
MB		 1660 }
1661
28d61370
YH		 1662 if (err)
1663 goto err;
1664
7f72052c
YH		 1665 if (mucontext->devx_uid) {
1666 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1667 resp.tirn = qp->rss_qp.tirn;
1668 }
1669
1670 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1671 if (err)
1672 goto err_copy;
1673
28d61370
YH		 1674 kvfree(in);
1675 /* qpn is reserved for that QP */
1676 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1677 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1678 return 0;
1679
7f72052c
YH		 1680err_copy:
1681 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
28d61370
YH		 1682err:
1683 kvfree(in);
1684 return err;
1685}
1686
e126ba97
EC		 1687static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1688 struct ib_qp_init_attr *init_attr,
1689 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1690{
1691 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1692 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1693 struct mlx5_core_dev *mdev = dev->mdev;
0625b4ba 1694 struct mlx5_ib_create_qp_resp resp = {};
89ea94a7
MG		 1695 struct mlx5_ib_cq *send_cq;
1696 struct mlx5_ib_cq *recv_cq;
1697 unsigned long flags;
cfb5e088 1698 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1699 struct mlx5_ib_create_qp ucmd;
1700 struct mlx5_ib_qp_base *base;
e7b169f3 1701 int mlx5_st;
cfb5e088 1702 void *qpc;
09a7d9ec
SM		 1703 u32 *in;
1704 int err;
e126ba97
EC		 1705
1706 mutex_init(&qp->mutex);
1707 spin_lock_init(&qp->sq.lock);
1708 spin_lock_init(&qp->rq.lock);
1709
e7b169f3
NO		 1710 mlx5_st = to_mlx5_st(init_attr->qp_type);
1711 if (mlx5_st < 0)
1712 return -EINVAL;
1713
28d61370
YH		 1714 if (init_attr->rwq_ind_tbl) {
1715 if (!udata)
1716 return -ENOSYS;
1717
1718 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1719 return err;
1720 }
1721
f360d88a 1722 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1723 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1724 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1725 return -EINVAL;
1726 } else {
1727 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1728 }
1729 }
1730
051f2630
LR		 1731 if (init_attr->create_flags &
1732 (IB_QP_CREATE_CROSS_CHANNEL |
1733 IB_QP_CREATE_MANAGED_SEND |
1734 IB_QP_CREATE_MANAGED_RECV)) {
1735 if (!MLX5_CAP_GEN(mdev, cd)) {
1736 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1737 return -EINVAL;
1738 }
1739 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1740 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1741 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1742 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1743 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1744 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1745 }
f0313965
ES		 1746
1747 if (init_attr->qp_type == IB_QPT_UD &&
1748 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1749 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1750 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1751 return -EOPNOTSUPP;
1752 }
1753
358e42ea
MD		 1754 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1755 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1756 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1757 return -EOPNOTSUPP;
1758 }
1759 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1760 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1761 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1762 return -EOPNOTSUPP;
1763 }
1764 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1765 }
1766
e126ba97
EC		 1767 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1768 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1769
e4cc4fa7
NO		 1770 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1771 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1772 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1773 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1774 return -EOPNOTSUPP;
1775 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1776 }
1777
e126ba97
EC		 1778 if (pd && pd->uobject) {
1779 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1780 mlx5_ib_dbg(dev, "copy failed\n");
1781 return -EFAULT;
1782 }
1783
cfb5e088
HA		 1784 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1785 &ucmd, udata->inlen, &uidx);
1786 if (err)
1787 return err;
1788
e126ba97
EC		 1789 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1790 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1791 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1792 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1793 !tunnel_offload_supported(mdev)) {
1794 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1795 return -EOPNOTSUPP;
1796 }
175edba8
MB		 1797 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1798 }
1799
1800 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1801 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1802 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1803 return -EOPNOTSUPP;
1804 }
1805 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1806 }
1807
1808 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1809 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1810 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1811 return -EOPNOTSUPP;
1812 }
1813 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
f95ef6cb 1814 }
c2e53b2c
YH		 1815
1816 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1817 if (init_attr->qp_type != IB_QPT_UD ||
1818 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1819 MLX5_CAP_PORT_TYPE_IB) ||
1820 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1821 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1822 return -EOPNOTSUPP;
1823 }
1824
1825 qp->flags |= MLX5_IB_QP_UNDERLAY;
1826 qp->underlay_qpn = init_attr->source_qpn;
1827 }
e126ba97
EC		 1828 } else {
1829 qp->wq_sig = !!wq_signature;
1830 }
1831
c2e53b2c
YH		 1832 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1833 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1834 &qp->raw_packet_qp.rq.base :
1835 &qp->trans_qp.base;
1836
e126ba97
EC		 1837 qp->has_rq = qp_has_rq(init_attr);
1838 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1839 qp, (pd && pd->uobject) ? &ucmd : NULL);
1840 if (err) {
1841 mlx5_ib_dbg(dev, "err %d\n", err);
1842 return err;
1843 }
1844
1845 if (pd) {
1846 if (pd->uobject) {
938fe83c
SM		 1847 __u32 max_wqes =
1848 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1849 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1850 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1851 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1852 mlx5_ib_dbg(dev, "invalid rq params\n");
1853 return -EINVAL;
1854 }
938fe83c 1855 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1856 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1857 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1858 return -EINVAL;
1859 }
b11a4f9c
HE		 1860 if (init_attr->create_flags &
1861 mlx5_ib_create_qp_sqpn_qp1()) {
1862 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1863 return -EINVAL;
1864 }
0fb2ed66 1865 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1866 &resp, &inlen, base);
e126ba97
EC		 1867 if (err)
1868 mlx5_ib_dbg(dev, "err %d\n", err);
1869 } else {
19098df2 1870 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1871 base);
e126ba97
EC		 1872 if (err)
1873 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1874 }
1875
1876 if (err)
1877 return err;
1878 } else {
1b9a07ee 1879 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1880 if (!in)
1881 return -ENOMEM;
1882
1883 qp->create_type = MLX5_QP_EMPTY;
1884 }
1885
1886 if (is_sqp(init_attr->qp_type))
1887 qp->port = init_attr->port_num;
1888
09a7d9ec
SM		 1889 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1890
e7b169f3 1891 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1892 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1893
1894 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1895 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1896 else
09a7d9ec
SM		 1897 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1898
e126ba97
EC		 1899
1900 if (qp->wq_sig)
09a7d9ec 1901 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1902
f360d88a 1903 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1904 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1905
051f2630 1906 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1907 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1908 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1909 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1910 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1911 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1912
e126ba97
EC		 1913 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1914 int rcqe_sz;
1915 int scqe_sz;
1916
1917 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1918 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1919
1920 if (rcqe_sz == 128)
09a7d9ec 1921 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1922 else
09a7d9ec 1923 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1924
1925 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1926 if (scqe_sz == 128)
09a7d9ec 1927 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1928 else
09a7d9ec 1929 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1930 }
1931 }
1932
1933 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1934 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1935 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1936 }
1937
09a7d9ec 1938 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1939
3fd3307e 1940 if (qp->sq.wqe_cnt) {
09a7d9ec 1941 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1942 } else {
09a7d9ec 1943 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1944 if (init_attr->srq &&
1945 init_attr->srq->srq_type == IB_SRQT_TM)
1946 MLX5_SET(qpc, qpc, offload_type,
1947 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1948 }
e126ba97
EC		 1949
1950 /* Set default resources */
1951 switch (init_attr->qp_type) {
1952 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1953 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1954 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1955 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1956 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1957 break;
1958 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1959 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1960 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1961 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1962 break;
1963 default:
1964 if (init_attr->srq) {
09a7d9ec
SM		 1965 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1966 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1967 } else {
09a7d9ec
SM		 1968 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1969 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1970 }
1971 }
1972
1973 if (init_attr->send_cq)
09a7d9ec 1974 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1975
1976 if (init_attr->recv_cq)
09a7d9ec 1977 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1978
09a7d9ec 1979 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1980
09a7d9ec
SM		 1981 /* 0xffffff means we ask to work with cqe version 0 */
1982 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1983 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1984
f0313965
ES		 1985 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1986 if (init_attr->qp_type == IB_QPT_UD &&
1987 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1988 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1989 qp->flags |= MLX5_IB_QP_LSO;
1990 }
cfb5e088 1991
b1383aa6
NO		 1992 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1993 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1994 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1995 err = -EOPNOTSUPP;
1996 goto err;
1997 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1998 MLX5_SET(qpc, qpc, end_padding_mode,
1999 MLX5_WQ_END_PAD_MODE_ALIGN);
2000 } else {
2001 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2002 }
2003 }
2004
2c292dbb
BP		 2005 if (inlen < 0) {
2006 err = -EINVAL;
2007 goto err;
2008 }
2009
c2e53b2c
YH		 2010 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2011 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2012 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2013 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c
YH		 2014 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2015 &resp);
0fb2ed66 2016 } else {
2017 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2018 }
2019
e126ba97
EC		 2020 if (err) {
2021 mlx5_ib_dbg(dev, "create qp failed\n");
2022 goto err_create;
2023 }
2024
479163f4 2025 kvfree(in);
e126ba97 2026
19098df2 2027 base->container_mibqp = qp;
2028 base->mqp.event = mlx5_ib_qp_event;
e126ba97 2029
89ea94a7
MG		 2030 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2031 &send_cq, &recv_cq);
2032 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2033 mlx5_ib_lock_cqs(send_cq, recv_cq);
2034 /* Maintain device to QPs access, needed for further handling via reset
2035 * flow
2036 */
2037 list_add_tail(&qp->qps_list, &dev->qp_list);
2038 /* Maintain CQ to QPs access, needed for further handling via reset flow
2039 */
2040 if (send_cq)
2041 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2042 if (recv_cq)
2043 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2044 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2045 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2046
e126ba97
EC		 2047 return 0;
2048
2049err_create:
2050 if (qp->create_type == MLX5_QP_USER)
b037c29a 2051 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 2052 else if (qp->create_type == MLX5_QP_KERNEL)
2053 destroy_qp_kernel(dev, qp);
2054
b1383aa6 2055err:
479163f4 2056 kvfree(in);
e126ba97
EC		 2057 return err;
2058}
2059
2060static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2061 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2062{
2063 if (send_cq) {
2064 if (recv_cq) {
2065 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2066 spin_lock(&send_cq->lock);
e126ba97
EC		 2067 spin_lock_nested(&recv_cq->lock,
2068 SINGLE_DEPTH_NESTING);
2069 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2070 spin_lock(&send_cq->lock);
e126ba97
EC		 2071 __acquire(&recv_cq->lock);
2072 } else {
89ea94a7 2073 spin_lock(&recv_cq->lock);
e126ba97
EC		 2074 spin_lock_nested(&send_cq->lock,
2075 SINGLE_DEPTH_NESTING);
2076 }
2077 } else {
89ea94a7 2078 spin_lock(&send_cq->lock);
6a4f139a 2079 __acquire(&recv_cq->lock);
e126ba97
EC		 2080 }
2081 } else if (recv_cq) {
89ea94a7 2082 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2083 __acquire(&send_cq->lock);
2084 } else {
2085 __acquire(&send_cq->lock);
2086 __acquire(&recv_cq->lock);
e126ba97
EC		 2087 }
2088}
2089
2090static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2091 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2092{
2093 if (send_cq) {
2094 if (recv_cq) {
2095 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2096 spin_unlock(&recv_cq->lock);
89ea94a7 2097 spin_unlock(&send_cq->lock);
e126ba97
EC		 2098 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2099 __release(&recv_cq->lock);
89ea94a7 2100 spin_unlock(&send_cq->lock);
e126ba97
EC		 2101 } else {
2102 spin_unlock(&send_cq->lock);
89ea94a7 2103 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2104 }
2105 } else {
6a4f139a 2106 __release(&recv_cq->lock);
89ea94a7 2107 spin_unlock(&send_cq->lock);
e126ba97
EC		 2108 }
2109 } else if (recv_cq) {
6a4f139a 2110 __release(&send_cq->lock);
89ea94a7 2111 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2112 } else {
2113 __release(&recv_cq->lock);
2114 __release(&send_cq->lock);
e126ba97
EC		 2115 }
2116}
2117
2118static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2119{
2120 return to_mpd(qp->ibqp.pd);
2121}
2122
89ea94a7
MG		 2123static void get_cqs(enum ib_qp_type qp_type,
2124 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2125 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2126{
89ea94a7 2127 switch (qp_type) {
e126ba97
EC		 2128 case IB_QPT_XRC_TGT:
2129 *send_cq = NULL;
2130 *recv_cq = NULL;
2131 break;
2132 case MLX5_IB_QPT_REG_UMR:
2133 case IB_QPT_XRC_INI:
89ea94a7 2134 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2135 *recv_cq = NULL;
2136 break;
2137
2138 case IB_QPT_SMI:
d16e91da 2139 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2140 case IB_QPT_RC:
2141 case IB_QPT_UC:
2142 case IB_QPT_UD:
2143 case IB_QPT_RAW_IPV6:
2144 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2145 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2146 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2147 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2148 break;
2149
e126ba97
EC		 2150 case IB_QPT_MAX:
2151 default:
2152 *send_cq = NULL;
2153 *recv_cq = NULL;
2154 break;
2155 }
2156}
2157
ad5f8e96 2158static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2159 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2160 u8 lag_tx_affinity);
ad5f8e96 2161
e126ba97
EC		 2162static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2163{
2164 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2165 struct mlx5_ib_qp_base *base;
89ea94a7 2166 unsigned long flags;
e126ba97
EC		 2167 int err;
2168
28d61370
YH		 2169 if (qp->ibqp.rwq_ind_tbl) {
2170 destroy_rss_raw_qp_tir(dev, qp);
2171 return;
2172 }
2173
c2e53b2c
YH		 2174 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2175 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2176 &qp->raw_packet_qp.rq.base :
2177 &qp->trans_qp.base;
2178
6aec21f6 2179 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2180 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2181 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2182 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2183 MLX5_CMD_OP_2RST_QP, 0,
2184 NULL, &base->mqp);
ad5f8e96 2185 } else {
0680efa2
AV		 2186 struct mlx5_modify_raw_qp_param raw_qp_param = {
2187 .operation = MLX5_CMD_OP_2RST_QP
2188 };
2189
13eab21f 2190 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2191 }
2192 if (err)
427c1e7b 2193 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2194 base->mqp.qpn);
6aec21f6 2195 }
e126ba97 2196
89ea94a7
MG		 2197 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2198 &send_cq, &recv_cq);
2199
2200 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2201 mlx5_ib_lock_cqs(send_cq, recv_cq);
2202 /* del from lists under both locks above to protect reset flow paths */
2203 list_del(&qp->qps_list);
2204 if (send_cq)
2205 list_del(&qp->cq_send_list);
2206
2207 if (recv_cq)
2208 list_del(&qp->cq_recv_list);
e126ba97
EC		 2209
2210 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2211 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2212 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2213 if (send_cq != recv_cq)
19098df2 2214 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2215 NULL);
e126ba97 2216 }
89ea94a7
MG		 2217 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2218 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2219
c2e53b2c
YH		 2220 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2221 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2222 destroy_raw_packet_qp(dev, qp);
2223 } else {
2224 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2225 if (err)
2226 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2227 base->mqp.qpn);
2228 }
e126ba97 2229
e126ba97
EC		 2230 if (qp->create_type == MLX5_QP_KERNEL)
2231 destroy_qp_kernel(dev, qp);
2232 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2233 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2234}
2235
2236static const char *ib_qp_type_str(enum ib_qp_type type)
2237{
2238 switch (type) {
2239 case IB_QPT_SMI:
2240 return "IB_QPT_SMI";
2241 case IB_QPT_GSI:
2242 return "IB_QPT_GSI";
2243 case IB_QPT_RC:
2244 return "IB_QPT_RC";
2245 case IB_QPT_UC:
2246 return "IB_QPT_UC";
2247 case IB_QPT_UD:
2248 return "IB_QPT_UD";
2249 case IB_QPT_RAW_IPV6:
2250 return "IB_QPT_RAW_IPV6";
2251 case IB_QPT_RAW_ETHERTYPE:
2252 return "IB_QPT_RAW_ETHERTYPE";
2253 case IB_QPT_XRC_INI:
2254 return "IB_QPT_XRC_INI";
2255 case IB_QPT_XRC_TGT:
2256 return "IB_QPT_XRC_TGT";
2257 case IB_QPT_RAW_PACKET:
2258 return "IB_QPT_RAW_PACKET";
2259 case MLX5_IB_QPT_REG_UMR:
2260 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2261 case IB_QPT_DRIVER:
2262 return "IB_QPT_DRIVER";
e126ba97
EC		 2263 case IB_QPT_MAX:
2264 default:
2265 return "Invalid QP type";
2266 }
2267}
2268
b4aaa1f0
MS		 2269static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2270 struct ib_qp_init_attr *attr,
2271 struct mlx5_ib_create_qp *ucmd)
2272{
b4aaa1f0
MS		 2273 struct mlx5_ib_qp *qp;
2274 int err = 0;
2275 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2276 void *dctc;
2277
2278 if (!attr->srq || !attr->recv_cq)
2279 return ERR_PTR(-EINVAL);
2280
b4aaa1f0
MS		 2281 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2282 ucmd, sizeof(*ucmd), &uidx);
2283 if (err)
2284 return ERR_PTR(err);
2285
2286 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2287 if (!qp)
2288 return ERR_PTR(-ENOMEM);
2289
2290 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2291 if (!qp->dct.in) {
2292 err = -ENOMEM;
2293 goto err_free;
2294 }
2295
a01a5860 2296 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2297 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2298 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2299 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2300 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2301 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2302 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2303 MLX5_SET(dctc, dctc, user_index, uidx);
2304
2305 qp->state = IB_QPS_RESET;
2306
2307 return &qp->ibqp;
2308err_free:
2309 kfree(qp);
2310 return ERR_PTR(err);
2311}
2312
2313static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2314 struct ib_qp_init_attr *init_attr,
2315 struct mlx5_ib_create_qp *ucmd,
2316 struct ib_udata *udata)
2317{
2318 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2319 int err;
2320
2321 if (!udata)
2322 return -EINVAL;
2323
2324 if (udata->inlen < sizeof(*ucmd)) {
2325 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2326 return -EINVAL;
2327 }
2328 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2329 if (err)
2330 return err;
2331
2332 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2333 init_attr->qp_type = MLX5_IB_QPT_DCI;
2334 } else {
2335 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2336 init_attr->qp_type = MLX5_IB_QPT_DCT;
2337 } else {
2338 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2339 return -EINVAL;
2340 }
2341 }
2342
2343 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2344 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2345 return -EOPNOTSUPP;
2346 }
2347
2348 return 0;
2349}
2350
e126ba97 2351struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2352 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2353 struct ib_udata *udata)
2354{
2355 struct mlx5_ib_dev *dev;
2356 struct mlx5_ib_qp *qp;
2357 u16 xrcdn = 0;
2358 int err;
b4aaa1f0
MS		 2359 struct ib_qp_init_attr mlx_init_attr;
2360 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2361
2362 if (pd) {
2363 dev = to_mdev(pd->device);
0fb2ed66 2364
2365 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2366 if (!pd->uobject) {
2367 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2368 return ERR_PTR(-EINVAL);
2369 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2370 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2371 return ERR_PTR(-EINVAL);
2372 }
2373 }
09f16cf5
MD		 2374 } else {
2375 /* being cautious here */
2376 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2377 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2378 pr_warn("%s: no PD for transport %s\n", __func__,
2379 ib_qp_type_str(init_attr->qp_type));
2380 return ERR_PTR(-EINVAL);
2381 }
2382 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2383 }
2384
b4aaa1f0
MS		 2385 if (init_attr->qp_type == IB_QPT_DRIVER) {
2386 struct mlx5_ib_create_qp ucmd;
2387
2388 init_attr = &mlx_init_attr;
2389 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2390 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2391 if (err)
2392 return ERR_PTR(err);
c32a4f29
MS		 2393
2394 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2395 if (init_attr->cap.max_recv_wr ||
2396 init_attr->cap.max_recv_sge) {
2397 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2398 return ERR_PTR(-EINVAL);
2399 }
776a3906
MS		 2400 } else {
2401 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2402 }
b4aaa1f0
MS		 2403 }
2404
e126ba97
EC		 2405 switch (init_attr->qp_type) {
2406 case IB_QPT_XRC_TGT:
2407 case IB_QPT_XRC_INI:
938fe83c 2408 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2409 mlx5_ib_dbg(dev, "XRC not supported\n");
2410 return ERR_PTR(-ENOSYS);
2411 }
2412 init_attr->recv_cq = NULL;
2413 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2414 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2415 init_attr->send_cq = NULL;
2416 }
2417
2418 /* fall through */
0fb2ed66 2419 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2420 case IB_QPT_RC:
2421 case IB_QPT_UC:
2422 case IB_QPT_UD:
2423 case IB_QPT_SMI:
d16e91da 2424 case MLX5_IB_QPT_HW_GSI:
e126ba97 2425 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2426 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2427 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2428 if (!qp)
2429 return ERR_PTR(-ENOMEM);
2430
2431 err = create_qp_common(dev, pd, init_attr, udata, qp);
2432 if (err) {
2433 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2434 kfree(qp);
2435 return ERR_PTR(err);
2436 }
2437
2438 if (is_qp0(init_attr->qp_type))
2439 qp->ibqp.qp_num = 0;
2440 else if (is_qp1(init_attr->qp_type))
2441 qp->ibqp.qp_num = 1;
2442 else
19098df2 2443 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2444
2445 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2446 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2447 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2448 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2449
19098df2 2450 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2451
2452 break;
2453
d16e91da
HE		 2454 case IB_QPT_GSI:
2455 return mlx5_ib_gsi_create_qp(pd, init_attr);
2456
e126ba97
EC		 2457 case IB_QPT_RAW_IPV6:
2458 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2459 case IB_QPT_MAX:
2460 default:
2461 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2462 init_attr->qp_type);
2463 /* Don't support raw QPs */
2464 return ERR_PTR(-EINVAL);
2465 }
2466
b4aaa1f0
MS		 2467 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2468 qp->qp_sub_type = init_attr->qp_type;
2469
e126ba97
EC		 2470 return &qp->ibqp;
2471}
2472
776a3906
MS		 2473static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2474{
2475 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2476
2477 if (mqp->state == IB_QPS_RTR) {
2478 int err;
2479
2480 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2481 if (err) {
2482 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2483 return err;
2484 }
2485 }
2486
2487 kfree(mqp->dct.in);
2488 kfree(mqp);
2489 return 0;
2490}
2491
e126ba97
EC		 2492int mlx5_ib_destroy_qp(struct ib_qp *qp)
2493{
2494 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2495 struct mlx5_ib_qp *mqp = to_mqp(qp);
2496
d16e91da
HE		 2497 if (unlikely(qp->qp_type == IB_QPT_GSI))
2498 return mlx5_ib_gsi_destroy_qp(qp);
2499
776a3906
MS		 2500 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2501 return mlx5_ib_destroy_dct(mqp);
2502
e126ba97
EC		 2503 destroy_qp_common(dev, mqp);
2504
2505 kfree(mqp);
2506
2507 return 0;
2508}
2509
2510static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2511 int attr_mask)
2512{
2513 u32 hw_access_flags = 0;
2514 u8 dest_rd_atomic;
2515 u32 access_flags;
2516
2517 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2518 dest_rd_atomic = attr->max_dest_rd_atomic;
2519 else
19098df2 2520 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2521
2522 if (attr_mask & IB_QP_ACCESS_FLAGS)
2523 access_flags = attr->qp_access_flags;
2524 else
19098df2 2525 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2526
2527 if (!dest_rd_atomic)
2528 access_flags &= IB_ACCESS_REMOTE_WRITE;
2529
2530 if (access_flags & IB_ACCESS_REMOTE_READ)
2531 hw_access_flags |= MLX5_QP_BIT_RRE;
2532 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2533 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2534 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2535 hw_access_flags |= MLX5_QP_BIT_RWE;
2536
2537 return cpu_to_be32(hw_access_flags);
2538}
2539
2540enum {
2541 MLX5_PATH_FLAG_FL = 1 << 0,
2542 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2543 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2544};
2545
2546static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2547{
4f32ac2e 2548 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 2549 return 0;
4f32ac2e
DG		 2550
2551 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
e126ba97 2552 return -EINVAL;
e126ba97 2553
4f32ac2e
DG		 2554 while (rate != IB_RATE_PORT_CURRENT &&
2555 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2556 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2557 --rate;
2558
2559 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 2560}
2561
75850d0b 2562static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2563 struct mlx5_ib_sq *sq, u8 sl,
2564 struct ib_pd *pd)
75850d0b 2565{
2566 void *in;
2567 void *tisc;
2568 int inlen;
2569 int err;
2570
2571 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2572 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2573 if (!in)
2574 return -ENOMEM;
2575
2576 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 2577 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 2578
2579 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2580 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2581
2582 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2583
2584 kvfree(in);
2585
2586 return err;
2587}
2588
13eab21f 2589static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2590 struct mlx5_ib_sq *sq, u8 tx_affinity,
2591 struct ib_pd *pd)
13eab21f
AH		 2592{
2593 void *in;
2594 void *tisc;
2595 int inlen;
2596 int err;
2597
2598 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2599 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2600 if (!in)
2601 return -ENOMEM;
2602
2603 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 2604 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 2605
2606 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2607 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2608
2609 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2610
2611 kvfree(in);
2612
2613 return err;
2614}
2615
75850d0b 2616static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2617 const struct rdma_ah_attr *ah,
e126ba97 2618 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2619 u32 path_flags, const struct ib_qp_attr *attr,
2620 bool alt)
e126ba97 2621{
d8966fcd 2622 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2623 int err;
ed88451e 2624 enum ib_gid_type gid_type;
d8966fcd
DC		 2625 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2626 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2627
e126ba97 2628 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2629 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2630 attr->pkey_index);
e126ba97 2631
d8966fcd
DC		 2632 if (ah_flags & IB_AH_GRH) {
2633 if (grh->sgid_index >=
938fe83c 2634 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2635 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2636 grh->sgid_index,
938fe83c 2637 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2638 return -EINVAL;
2639 }
2811ba51 2640 }
44c58487
DC		 2641
2642 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2643 if (!(ah_flags & IB_AH_GRH))
2811ba51 2644 return -EINVAL;
47ec3866 2645
44c58487 2646 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2647 if (qp->ibqp.qp_type == IB_QPT_RC ||
2648 qp->ibqp.qp_type == IB_QPT_UC ||
2649 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2650 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
47ec3866
PP		 2651 path->udp_sport =
2652 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
d8966fcd 2653 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
47ec3866 2654 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 2655 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2656 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2657 } else {
d3ae2bde
NO		 2658 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2659 path->fl_free_ar |=
2660 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2661 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2662 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2663 if (ah_flags & IB_AH_GRH)
2811ba51 2664 path->grh_mlid |= 1 << 7;
d8966fcd 2665 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2666 }
2667
d8966fcd
DC		 2668 if (ah_flags & IB_AH_GRH) {
2669 path->mgid_index = grh->sgid_index;
2670 path->hop_limit = grh->hop_limit;
e126ba97 2671 path->tclass_flowlabel =
d8966fcd
DC		 2672 cpu_to_be32((grh->traffic_class << 20) |
2673 (grh->flow_label));
2674 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2675 }
2676
d8966fcd 2677 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2678 if (err < 0)
2679 return err;
2680 path->static_rate = err;
2681 path->port = port;
2682
e126ba97 2683 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2684 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2685
75850d0b 2686 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2687 return modify_raw_packet_eth_prio(dev->mdev,
2688 &qp->raw_packet_qp.sq,
1cd6dbd3 2689 sl & 0xf, qp->ibqp.pd);
75850d0b 2690
e126ba97
EC		 2691 return 0;
2692}
2693
2694static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2695 [MLX5_QP_STATE_INIT] = {
2696 [MLX5_QP_STATE_INIT] = {
2697 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2698 MLX5_QP_OPTPAR_RAE |
2699 MLX5_QP_OPTPAR_RWE |
2700 MLX5_QP_OPTPAR_PKEY_INDEX |
2701 MLX5_QP_OPTPAR_PRI_PORT,
2702 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2703 MLX5_QP_OPTPAR_PKEY_INDEX |
2704 MLX5_QP_OPTPAR_PRI_PORT,
2705 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2706 MLX5_QP_OPTPAR_Q_KEY |
2707 MLX5_QP_OPTPAR_PRI_PORT,
2708 },
2709 [MLX5_QP_STATE_RTR] = {
2710 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2711 MLX5_QP_OPTPAR_RRE |
2712 MLX5_QP_OPTPAR_RAE |
2713 MLX5_QP_OPTPAR_RWE |
2714 MLX5_QP_OPTPAR_PKEY_INDEX,
2715 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2716 MLX5_QP_OPTPAR_RWE |
2717 MLX5_QP_OPTPAR_PKEY_INDEX,
2718 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2719 MLX5_QP_OPTPAR_Q_KEY,
2720 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2721 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2722 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2723 MLX5_QP_OPTPAR_RRE |
2724 MLX5_QP_OPTPAR_RAE |
2725 MLX5_QP_OPTPAR_RWE |
2726 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2727 },
2728 },
2729 [MLX5_QP_STATE_RTR] = {
2730 [MLX5_QP_STATE_RTS] = {
2731 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2732 MLX5_QP_OPTPAR_RRE |
2733 MLX5_QP_OPTPAR_RAE |
2734 MLX5_QP_OPTPAR_RWE |
2735 MLX5_QP_OPTPAR_PM_STATE |
2736 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2737 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2738 MLX5_QP_OPTPAR_RWE |
2739 MLX5_QP_OPTPAR_PM_STATE,
2740 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2741 },
2742 },
2743 [MLX5_QP_STATE_RTS] = {
2744 [MLX5_QP_STATE_RTS] = {
2745 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2746 MLX5_QP_OPTPAR_RAE |
2747 MLX5_QP_OPTPAR_RWE |
2748 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2749 MLX5_QP_OPTPAR_PM_STATE |
2750 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2751 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2752 MLX5_QP_OPTPAR_PM_STATE |
2753 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2754 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2755 MLX5_QP_OPTPAR_SRQN |
2756 MLX5_QP_OPTPAR_CQN_RCV,
2757 },
2758 },
2759 [MLX5_QP_STATE_SQER] = {
2760 [MLX5_QP_STATE_RTS] = {
2761 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2762 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2763 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2764 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2765 MLX5_QP_OPTPAR_RWE |
2766 MLX5_QP_OPTPAR_RAE |
2767 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2768 },
2769 },
2770};
2771
2772static int ib_nr_to_mlx5_nr(int ib_mask)
2773{
2774 switch (ib_mask) {
2775 case IB_QP_STATE:
2776 return 0;
2777 case IB_QP_CUR_STATE:
2778 return 0;
2779 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2780 return 0;
2781 case IB_QP_ACCESS_FLAGS:
2782 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2783 MLX5_QP_OPTPAR_RAE;
2784 case IB_QP_PKEY_INDEX:
2785 return MLX5_QP_OPTPAR_PKEY_INDEX;
2786 case IB_QP_PORT:
2787 return MLX5_QP_OPTPAR_PRI_PORT;
2788 case IB_QP_QKEY:
2789 return MLX5_QP_OPTPAR_Q_KEY;
2790 case IB_QP_AV:
2791 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2792 MLX5_QP_OPTPAR_PRI_PORT;
2793 case IB_QP_PATH_MTU:
2794 return 0;
2795 case IB_QP_TIMEOUT:
2796 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2797 case IB_QP_RETRY_CNT:
2798 return MLX5_QP_OPTPAR_RETRY_COUNT;
2799 case IB_QP_RNR_RETRY:
2800 return MLX5_QP_OPTPAR_RNR_RETRY;
2801 case IB_QP_RQ_PSN:
2802 return 0;
2803 case IB_QP_MAX_QP_RD_ATOMIC:
2804 return MLX5_QP_OPTPAR_SRA_MAX;
2805 case IB_QP_ALT_PATH:
2806 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2807 case IB_QP_MIN_RNR_TIMER:
2808 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2809 case IB_QP_SQ_PSN:
2810 return 0;
2811 case IB_QP_MAX_DEST_RD_ATOMIC:
2812 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2813 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2814 case IB_QP_PATH_MIG_STATE:
2815 return MLX5_QP_OPTPAR_PM_STATE;
2816 case IB_QP_CAP:
2817 return 0;
2818 case IB_QP_DEST_QPN:
2819 return 0;
2820 }
2821 return 0;
2822}
2823
2824static int ib_mask_to_mlx5_opt(int ib_mask)
2825{
2826 int result = 0;
2827 int i;
2828
2829 for (i = 0; i < 8 * sizeof(int); i++) {
2830 if ((1 << i) & ib_mask)
2831 result |= ib_nr_to_mlx5_nr(1 << i);
2832 }
2833
2834 return result;
2835}
2836
34d57585
YH		 2837static int modify_raw_packet_qp_rq(
2838 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2839 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 2840{
2841 void *in;
2842 void *rqc;
2843 int inlen;
2844 int err;
2845
2846 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2847 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2848 if (!in)
2849 return -ENOMEM;
2850
2851 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 2852 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 2853
2854 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2855 MLX5_SET(rqc, rqc, state, new_state);
2856
eb49ab0c
AV		 2857 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2858 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2859 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2860 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2861 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2862 } else
5a738b5d
JG		 2863 dev_info_once(
2864 &dev->ib_dev.dev,
2865 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 2866 }
2867
2868 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2869 if (err)
2870 goto out;
2871
2872 rq->state = new_state;
2873
2874out:
2875 kvfree(in);
2876 return err;
2877}
2878
c14003f0
YH		 2879static int modify_raw_packet_qp_sq(
2880 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
2881 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 2882{
7d29f349 2883 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 2884 struct mlx5_rate_limit old_rl = ibqp->rl;
2885 struct mlx5_rate_limit new_rl = old_rl;
2886 bool new_rate_added = false;
7d29f349 2887 u16 rl_index = 0;
ad5f8e96 2888 void *in;
2889 void *sqc;
2890 int inlen;
2891 int err;
2892
2893 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2894 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2895 if (!in)
2896 return -ENOMEM;
2897
c14003f0 2898 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 2899 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2900
2901 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2902 MLX5_SET(sqc, sqc, state, new_state);
2903
7d29f349
BW		 2904 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2905 if (new_state != MLX5_SQC_STATE_RDY)
2906 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2907 __func__);
2908 else
61147f39 2909 new_rl = raw_qp_param->rl;
7d29f349
BW		 2910 }
2911
61147f39
BW		 2912 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2913 if (new_rl.rate) {
2914 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 2915 if (err) {
61147f39
BW		 2916 pr_err("Failed configuring rate limit(err %d): \
2917 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2918 err, new_rl.rate, new_rl.max_burst_sz,
2919 new_rl.typical_pkt_sz);
2920
7d29f349
BW		 2921 goto out;
2922 }
61147f39 2923 new_rate_added = true;
7d29f349
BW		 2924 }
2925
2926 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 2927 /* index 0 means no limit */
7d29f349
BW		 2928 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2929 }
2930
ad5f8e96 2931 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2932 if (err) {
2933 /* Remove new rate from table if failed */
61147f39
BW		 2934 if (new_rate_added)
2935 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 2936 goto out;
7d29f349
BW		 2937 }
2938
2939 /* Only remove the old rate after new rate was set */
61147f39
BW		 2940 if ((old_rl.rate &&
2941 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
7d29f349 2942 (new_state != MLX5_SQC_STATE_RDY))
61147f39 2943 mlx5_rl_remove_rate(dev, &old_rl);
ad5f8e96 2944
61147f39 2945 ibqp->rl = new_rl;
ad5f8e96 2946 sq->state = new_state;
2947
2948out:
2949 kvfree(in);
2950 return err;
2951}
2952
2953static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2954 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2955 u8 tx_affinity)
ad5f8e96 2956{
2957 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2958 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2959 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2960 int modify_rq = !!qp->rq.wqe_cnt;
2961 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2962 int rq_state;
2963 int sq_state;
2964 int err;
2965
0680efa2 2966 switch (raw_qp_param->operation) {
ad5f8e96 2967 case MLX5_CMD_OP_RST2INIT_QP:
2968 rq_state = MLX5_RQC_STATE_RDY;
2969 sq_state = MLX5_SQC_STATE_RDY;
2970 break;
2971 case MLX5_CMD_OP_2ERR_QP:
2972 rq_state = MLX5_RQC_STATE_ERR;
2973 sq_state = MLX5_SQC_STATE_ERR;
2974 break;
2975 case MLX5_CMD_OP_2RST_QP:
2976 rq_state = MLX5_RQC_STATE_RST;
2977 sq_state = MLX5_SQC_STATE_RST;
2978 break;
ad5f8e96 2979 case MLX5_CMD_OP_RTR2RTS_QP:
2980 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2981 if (raw_qp_param->set_mask ==
2982 MLX5_RAW_QP_RATE_LIMIT) {
2983 modify_rq = 0;
2984 sq_state = sq->state;
2985 } else {
2986 return raw_qp_param->set_mask ? -EINVAL : 0;
2987 }
2988 break;
2989 case MLX5_CMD_OP_INIT2INIT_QP:
2990 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2991 if (raw_qp_param->set_mask)
2992 return -EINVAL;
2993 else
2994 return 0;
ad5f8e96 2995 default:
2996 WARN_ON(1);
2997 return -EINVAL;
2998 }
2999
7d29f349 3000 if (modify_rq) {
34d57585
YH		 3001 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3002 qp->ibqp.pd);
ad5f8e96 3003 if (err)
3004 return err;
3005 }
3006
7d29f349 3007 if (modify_sq) {
13eab21f
AH		 3008 if (tx_affinity) {
3009 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3010 tx_affinity,
3011 qp->ibqp.pd);
13eab21f
AH		 3012 if (err)
3013 return err;
3014 }
3015
c14003f0
YH		 3016 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3017 raw_qp_param, qp->ibqp.pd);
13eab21f 3018 }
ad5f8e96 3019
3020 return 0;
3021}
3022
c6a21c38
MD		 3023static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3024 struct mlx5_ib_pd *pd,
3025 struct mlx5_ib_qp_base *qp_base,
3026 u8 port_num)
3027{
3028 struct mlx5_ib_ucontext *ucontext = NULL;
3029 unsigned int tx_port_affinity;
3030
3031 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3032 ucontext = to_mucontext(pd->ibpd.uobject->context);
3033
3034 if (ucontext) {
3035 tx_port_affinity = (unsigned int)atomic_add_return(
3036 1, &ucontext->tx_port_affinity) %
3037 MLX5_MAX_PORTS +
3038 1;
3039 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3040 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3041 } else {
3042 tx_port_affinity =
3043 (unsigned int)atomic_add_return(
3044 1, &dev->roce[port_num].tx_port_affinity) %
3045 MLX5_MAX_PORTS +
3046 1;
3047 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3048 tx_port_affinity, qp_base->mqp.qpn);
3049 }
3050
3051 return tx_port_affinity;
3052}
3053
e126ba97
EC		 3054static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3055 const struct ib_qp_attr *attr, int attr_mask,
61147f39
BW		 3056 enum ib_qp_state cur_state, enum ib_qp_state new_state,
3057 const struct mlx5_ib_modify_qp *ucmd)
e126ba97 3058{
427c1e7b 3059 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3060 [MLX5_QP_STATE_RST] = {
3061 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3062 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3063 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3064 },
3065 [MLX5_QP_STATE_INIT] = {
3066 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3067 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3068 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3069 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3070 },
3071 [MLX5_QP_STATE_RTR] = {
3072 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3073 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3074 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3075 },
3076 [MLX5_QP_STATE_RTS] = {
3077 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3078 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3079 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3080 },
3081 [MLX5_QP_STATE_SQD] = {
3082 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3083 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3084 },
3085 [MLX5_QP_STATE_SQER] = {
3086 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3087 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3088 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3089 },
3090 [MLX5_QP_STATE_ERR] = {
3091 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3092 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3093 }
3094 };
3095
e126ba97
EC		 3096 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3097 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3098 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 3099 struct mlx5_ib_cq *send_cq, *recv_cq;
3100 struct mlx5_qp_context *context;
e126ba97 3101 struct mlx5_ib_pd *pd;
eb49ab0c 3102 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 3103 enum mlx5_qp_state mlx5_cur, mlx5_new;
3104 enum mlx5_qp_optpar optpar;
e126ba97
EC		 3105 int mlx5_st;
3106 int err;
427c1e7b 3107 u16 op;
13eab21f 3108 u8 tx_affinity = 0;
e126ba97 3109
55de9a77
LR		 3110 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3111 qp->qp_sub_type : ibqp->qp_type);
3112 if (mlx5_st < 0)
3113 return -EINVAL;
3114
1a412fb1
SM		 3115 context = kzalloc(sizeof(*context), GFP_KERNEL);
3116 if (!context)
e126ba97
EC		 3117 return -ENOMEM;
3118
c6a21c38 3119 pd = get_pd(qp);
55de9a77 3120 context->flags = cpu_to_be32(mlx5_st << 16);
e126ba97
EC		 3121
3122 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3123 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3124 } else {
3125 switch (attr->path_mig_state) {
3126 case IB_MIG_MIGRATED:
3127 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3128 break;
3129 case IB_MIG_REARM:
3130 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3131 break;
3132 case IB_MIG_ARMED:
3133 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3134 break;
3135 }
3136 }
3137
13eab21f
AH		 3138 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3139 if ((ibqp->qp_type == IB_QPT_RC) ||
3140 (ibqp->qp_type == IB_QPT_UD &&
3141 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3142 (ibqp->qp_type == IB_QPT_UC) ||
3143 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3144 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3145 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3146 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 3147 u8 p = mlx5_core_native_port_num(dev->mdev);
c6a21c38 3148 tx_affinity = get_tx_affinity(dev, pd, base, p);
13eab21f
AH		 3149 context->flags |= cpu_to_be32(tx_affinity << 24);
3150 }
3151 }
3152 }
3153
d16e91da 3154 if (is_sqp(ibqp->qp_type)) {
e126ba97 3155 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 3156 } else if ((ibqp->qp_type == IB_QPT_UD &&
3157 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 3158 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3159 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3160 } else if (attr_mask & IB_QP_PATH_MTU) {
3161 if (attr->path_mtu < IB_MTU_256 ||
3162 attr->path_mtu > IB_MTU_4096) {
3163 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3164 err = -EINVAL;
3165 goto out;
3166 }
938fe83c
SM		 3167 context->mtu_msgmax = (attr->path_mtu << 5) |
3168 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3169 }
3170
3171 if (attr_mask & IB_QP_DEST_QPN)
3172 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3173
3174 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3175 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3176
3177 /* todo implement counter_index functionality */
3178
3179 if (is_sqp(ibqp->qp_type))
3180 context->pri_path.port = qp->port;
3181
3182 if (attr_mask & IB_QP_PORT)
3183 context->pri_path.port = attr->port_num;
3184
3185 if (attr_mask & IB_QP_AV) {
75850d0b 3186 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3187 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3188 attr_mask, 0, attr, false);
e126ba97
EC		 3189 if (err)
3190 goto out;
3191 }
3192
3193 if (attr_mask & IB_QP_TIMEOUT)
3194 context->pri_path.ackto_lt |= attr->timeout << 3;
3195
3196 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3197 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3198 &context->alt_path,
f879ee8d
AS		 3199 attr->alt_port_num,
3200 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3201 0, attr, true);
e126ba97
EC		 3202 if (err)
3203 goto out;
3204 }
3205
89ea94a7
MG		 3206 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3207 &send_cq, &recv_cq);
e126ba97
EC		 3208
3209 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3210 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3211 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3212 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3213
3214 if (attr_mask & IB_QP_RNR_RETRY)
3215 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3216
3217 if (attr_mask & IB_QP_RETRY_CNT)
3218 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3219
3220 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3221 if (attr->max_rd_atomic)
3222 context->params1 |=
3223 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3224 }
3225
3226 if (attr_mask & IB_QP_SQ_PSN)
3227 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3228
3229 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3230 if (attr->max_dest_rd_atomic)
3231 context->params2 |=
3232 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3233 }
3234
3235 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3236 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3237
3238 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3239 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3240
3241 if (attr_mask & IB_QP_RQ_PSN)
3242 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3243
3244 if (attr_mask & IB_QP_QKEY)
3245 context->qkey = cpu_to_be32(attr->qkey);
3246
3247 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3248 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3249
0837e86a
MB		 3250 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3251 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3252 qp->port) - 1;
c2e53b2c
YH		 3253
3254 /* Underlay port should be used - index 0 function per port */
3255 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3256 port_num = 0;
3257
eb49ab0c 3258 mibport = &dev->port[port_num];
0837e86a 3259 context->qp_counter_set_usr_page |=
e1f24a79 3260 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3261 }
3262
e126ba97
EC		 3263 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3264 context->sq_crq_size |= cpu_to_be16(1 << 4);
3265
b11a4f9c
HE		 3266 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3267 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3268
3269 mlx5_cur = to_mlx5_state(cur_state);
3270 mlx5_new = to_mlx5_state(new_state);
e126ba97 3271
427c1e7b 3272 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3273 !optab[mlx5_cur][mlx5_new]) {
3274 err = -EINVAL;
427c1e7b 3275 goto out;
5d414b17 3276 }
427c1e7b 3277
3278 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3279 optpar = ib_mask_to_mlx5_opt(attr_mask);
3280 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3281
c2e53b2c
YH		 3282 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3283 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3284 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3285
3286 raw_qp_param.operation = op;
eb49ab0c 3287 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3288 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3289 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3290 }
7d29f349
BW		 3291
3292 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3293 raw_qp_param.rl.rate = attr->rate_limit;
3294
3295 if (ucmd->burst_info.max_burst_sz) {
3296 if (attr->rate_limit &&
3297 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3298 raw_qp_param.rl.max_burst_sz =
3299 ucmd->burst_info.max_burst_sz;
3300 } else {
3301 err = -EINVAL;
3302 goto out;
3303 }
3304 }
3305
3306 if (ucmd->burst_info.typical_pkt_sz) {
3307 if (attr->rate_limit &&
3308 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3309 raw_qp_param.rl.typical_pkt_sz =
3310 ucmd->burst_info.typical_pkt_sz;
3311 } else {
3312 err = -EINVAL;
3313 goto out;
3314 }
3315 }
3316
7d29f349
BW		 3317 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3318 }
3319
13eab21f 3320 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3321 } else {
1a412fb1 3322 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3323 &base->mqp);
0680efa2
AV		 3324 }
3325
e126ba97
EC		 3326 if (err)
3327 goto out;
3328
3329 qp->state = new_state;
3330
3331 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3332 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3333 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3334 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3335 if (attr_mask & IB_QP_PORT)
3336 qp->port = attr->port_num;
3337 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3338 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3339
3340 /*
3341 * If we moved a kernel QP to RESET, clean up all old CQ
3342 * entries and reinitialize the QP.
3343 */
75a45982
LR		 3344 if (new_state == IB_QPS_RESET &&
3345 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 3346 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3347 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3348 if (send_cq != recv_cq)
19098df2 3349 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3350
3351 qp->rq.head = 0;
3352 qp->rq.tail = 0;
3353 qp->sq.head = 0;
3354 qp->sq.tail = 0;
3355 qp->sq.cur_post = 0;
3356 qp->sq.last_poll = 0;
3357 qp->db.db[MLX5_RCV_DBR] = 0;
3358 qp->db.db[MLX5_SND_DBR] = 0;
3359 }
3360
3361out:
1a412fb1 3362 kfree(context);
e126ba97
EC		 3363 return err;
3364}
3365
c32a4f29
MS		 3366static inline bool is_valid_mask(int mask, int req, int opt)
3367{
3368 if ((mask & req) != req)
3369 return false;
3370
3371 if (mask & ~(req | opt))
3372 return false;
3373
3374 return true;
3375}
3376
3377/* check valid transition for driver QP types
3378 * for now the only QP type that this function supports is DCI
3379 */
3380static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3381 enum ib_qp_attr_mask attr_mask)
3382{
3383 int req = IB_QP_STATE;
3384 int opt = 0;
3385
99ed748e
MS		 3386 if (new_state == IB_QPS_RESET) {
3387 return is_valid_mask(attr_mask, req, opt);
3388 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 3389 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3390 return is_valid_mask(attr_mask, req, opt);
3391 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3392 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3393 return is_valid_mask(attr_mask, req, opt);
3394 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3395 req |= IB_QP_PATH_MTU;
3396 opt = IB_QP_PKEY_INDEX;
3397 return is_valid_mask(attr_mask, req, opt);
3398 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3399 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3400 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3401 opt = IB_QP_MIN_RNR_TIMER;
3402 return is_valid_mask(attr_mask, req, opt);
3403 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3404 opt = IB_QP_MIN_RNR_TIMER;
3405 return is_valid_mask(attr_mask, req, opt);
3406 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3407 return is_valid_mask(attr_mask, req, opt);
3408 }
3409 return false;
3410}
3411
776a3906
MS		 3412/* mlx5_ib_modify_dct: modify a DCT QP
3413 * valid transitions are:
3414 * RESET to INIT: must set access_flags, pkey_index and port
3415 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3416 * mtu, gid_index and hop_limit
3417 * Other transitions and attributes are illegal
3418 */
3419static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3420 int attr_mask, struct ib_udata *udata)
3421{
3422 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3423 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3424 enum ib_qp_state cur_state, new_state;
3425 int err = 0;
3426 int required = IB_QP_STATE;
3427 void *dctc;
3428
3429 if (!(attr_mask & IB_QP_STATE))
3430 return -EINVAL;
3431
3432 cur_state = qp->state;
3433 new_state = attr->qp_state;
3434
3435 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3436 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3437 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3438 if (!is_valid_mask(attr_mask, required, 0))
3439 return -EINVAL;
3440
3441 if (attr->port_num == 0 ||
3442 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3443 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3444 attr->port_num, dev->num_ports);
3445 return -EINVAL;
3446 }
3447 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3448 MLX5_SET(dctc, dctc, rre, 1);
3449 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3450 MLX5_SET(dctc, dctc, rwe, 1);
3451 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3452 if (!mlx5_ib_dc_atomic_is_supported(dev))
3453 return -EOPNOTSUPP;
3454 MLX5_SET(dctc, dctc, rae, 1);
3455 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3456 }
3457 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3458 MLX5_SET(dctc, dctc, port, attr->port_num);
3459 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3460
3461 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3462 struct mlx5_ib_modify_qp_resp resp = {};
3463 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3464 sizeof(resp.dctn);
3465
3466 if (udata->outlen < min_resp_len)
3467 return -EINVAL;
3468 resp.response_length = min_resp_len;
3469
3470 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3471 if (!is_valid_mask(attr_mask, required, 0))
3472 return -EINVAL;
3473 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3474 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3475 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3476 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3477 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3478 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3479
3480 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3481 MLX5_ST_SZ_BYTES(create_dct_in));
3482 if (err)
3483 return err;
3484 resp.dctn = qp->dct.mdct.mqp.qpn;
3485 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3486 if (err) {
3487 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3488 return err;
3489 }
3490 } else {
3491 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3492 return -EINVAL;
3493 }
3494 if (err)
3495 qp->state = IB_QPS_ERR;
3496 else
3497 qp->state = new_state;
3498 return err;
3499}
3500
e126ba97
EC		 3501int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3502 int attr_mask, struct ib_udata *udata)
3503{
3504 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3505 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 3506 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 3507 enum ib_qp_type qp_type;
e126ba97 3508 enum ib_qp_state cur_state, new_state;
61147f39 3509 size_t required_cmd_sz;
e126ba97
EC		 3510 int err = -EINVAL;
3511 int port;
2811ba51 3512 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3513
28d61370
YH		 3514 if (ibqp->rwq_ind_tbl)
3515 return -ENOSYS;
3516
61147f39
BW		 3517 if (udata && udata->inlen) {
3518 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3519 sizeof(ucmd.reserved);
3520 if (udata->inlen < required_cmd_sz)
3521 return -EINVAL;
3522
3523 if (udata->inlen > sizeof(ucmd) &&
3524 !ib_is_udata_cleared(udata, sizeof(ucmd),
3525 udata->inlen - sizeof(ucmd)))
3526 return -EOPNOTSUPP;
3527
3528 if (ib_copy_from_udata(&ucmd, udata,
3529 min(udata->inlen, sizeof(ucmd))))
3530 return -EFAULT;
3531
3532 if (ucmd.comp_mask ||
3533 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3534 memchr_inv(&ucmd.burst_info.reserved, 0,
3535 sizeof(ucmd.burst_info.reserved)))
3536 return -EOPNOTSUPP;
3537 }
3538
d16e91da
HE		 3539 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3540 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3541
c32a4f29
MS		 3542 if (ibqp->qp_type == IB_QPT_DRIVER)
3543 qp_type = qp->qp_sub_type;
3544 else
3545 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3546 IB_QPT_GSI : ibqp->qp_type;
3547
776a3906
MS		 3548 if (qp_type == MLX5_IB_QPT_DCT)
3549 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3550
e126ba97
EC		 3551 mutex_lock(&qp->mutex);
3552
3553 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3554 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3555
2811ba51
AS		 3556 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3557 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3558 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3559 }
3560
c2e53b2c
YH		 3561 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3562 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3563 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3564 attr_mask);
3565 goto out;
3566 }
3567 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3568 qp_type != MLX5_IB_QPT_DCI &&
3569 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3570 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3571 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3572 goto out;
c32a4f29
MS		 3573 } else if (qp_type == MLX5_IB_QPT_DCI &&
3574 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3575 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3576 cur_state, new_state, qp_type, attr_mask);
3577 goto out;
158abf86 3578 }
e126ba97
EC		 3579
3580 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3581 (attr->port_num == 0 ||
508562d6 3582 attr->port_num > dev->num_ports)) {
158abf86
HE		 3583 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3584 attr->port_num, dev->num_ports);
e126ba97 3585 goto out;
158abf86 3586 }
e126ba97
EC		 3587
3588 if (attr_mask & IB_QP_PKEY_INDEX) {
3589 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3590 if (attr->pkey_index >=
158abf86
HE		 3591 dev->mdev->port_caps[port - 1].pkey_table_len) {
3592 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3593 attr->pkey_index);
e126ba97 3594 goto out;
158abf86 3595 }
e126ba97
EC		 3596 }
3597
3598 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3599 attr->max_rd_atomic >
158abf86
HE		 3600 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3601 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3602 attr->max_rd_atomic);
e126ba97 3603 goto out;
158abf86 3604 }
e126ba97
EC		 3605
3606 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3607 attr->max_dest_rd_atomic >
158abf86
HE		 3608 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3609 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3610 attr->max_dest_rd_atomic);
e126ba97 3611 goto out;
158abf86 3612 }
e126ba97
EC		 3613
3614 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3615 err = 0;
3616 goto out;
3617 }
3618
61147f39
BW		 3619 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3620 new_state, &ucmd);
e126ba97
EC		 3621
3622out:
3623 mutex_unlock(&qp->mutex);
3624 return err;
3625}
3626
3627static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3628{
3629 struct mlx5_ib_cq *cq;
3630 unsigned cur;
3631
3632 cur = wq->head - wq->tail;
3633 if (likely(cur + nreq < wq->max_post))
3634 return 0;
3635
3636 cq = to_mcq(ib_cq);
3637 spin_lock(&cq->lock);
3638 cur = wq->head - wq->tail;
3639 spin_unlock(&cq->lock);
3640
3641 return cur + nreq >= wq->max_post;
3642}
3643
3644static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3645 u64 remote_addr, u32 rkey)
3646{
3647 rseg->raddr = cpu_to_be64(remote_addr);
3648 rseg->rkey = cpu_to_be32(rkey);
3649 rseg->reserved = 0;
3650}
3651
f0313965 3652static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
f696bf6d 3653 const struct ib_send_wr *wr, void *qend,
f0313965
ES		 3654 struct mlx5_ib_qp *qp, int *size)
3655{
3656 void *seg = eseg;
3657
3658 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3659
3660 if (wr->send_flags & IB_SEND_IP_CSUM)
3661 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3662 MLX5_ETH_WQE_L4_CSUM;
3663
3664 seg += sizeof(struct mlx5_wqe_eth_seg);
3665 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3666
3667 if (wr->opcode == IB_WR_LSO) {
3668 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3669 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3670 u64 left, leftlen, copysz;
3671 void *pdata = ud_wr->header;
3672
3673 left = ud_wr->hlen;
3674 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3675 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3676
3677 /*
3678 * check if there is space till the end of queue, if yes,
3679 * copy all in one shot, otherwise copy till the end of queue,
3680 * rollback and than the copy the left
3681 */
2b31f7ae 3682 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3683 copysz = min_t(u64, leftlen, left);
3684
3685 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3686
3687 if (likely(copysz > size_of_inl_hdr_start)) {
3688 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3689 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3690 }
3691
3692 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3693 seg = mlx5_get_send_wqe(qp, 0);
3694 left -= copysz;
3695 pdata += copysz;
3696 memcpy(seg, pdata, left);
3697 seg += ALIGN(left, 16);
3698 *size += ALIGN(left, 16) / 16;
3699 }
3700 }
3701
3702 return seg;
3703}
3704
e126ba97 3705static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
f696bf6d 3706 const struct ib_send_wr *wr)
e126ba97 3707{
e622f2f4
CH		 3708 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3709 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3710 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3711}
3712
3713static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3714{
3715 dseg->byte_count = cpu_to_be32(sg->length);
3716 dseg->lkey = cpu_to_be32(sg->lkey);
3717 dseg->addr = cpu_to_be64(sg->addr);
3718}
3719
31616255 3720static u64 get_xlt_octo(u64 bytes)
e126ba97 3721{
31616255
AK		 3722 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3723 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3724}
3725
3726static __be64 frwr_mkey_mask(void)
3727{
3728 u64 result;
3729
3730 result = MLX5_MKEY_MASK_LEN |
3731 MLX5_MKEY_MASK_PAGE_SIZE |
3732 MLX5_MKEY_MASK_START_ADDR |
3733 MLX5_MKEY_MASK_EN_RINVAL |
3734 MLX5_MKEY_MASK_KEY |
3735 MLX5_MKEY_MASK_LR |
3736 MLX5_MKEY_MASK_LW |
3737 MLX5_MKEY_MASK_RR |
3738 MLX5_MKEY_MASK_RW |
3739 MLX5_MKEY_MASK_A |
3740 MLX5_MKEY_MASK_SMALL_FENCE |
3741 MLX5_MKEY_MASK_FREE;
3742
3743 return cpu_to_be64(result);
3744}
3745
e6631814
SG		 3746static __be64 sig_mkey_mask(void)
3747{
3748 u64 result;
3749
3750 result = MLX5_MKEY_MASK_LEN |
3751 MLX5_MKEY_MASK_PAGE_SIZE |
3752 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3753 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3754 MLX5_MKEY_MASK_EN_RINVAL |
3755 MLX5_MKEY_MASK_KEY |
3756 MLX5_MKEY_MASK_LR |
3757 MLX5_MKEY_MASK_LW |
3758 MLX5_MKEY_MASK_RR |
3759 MLX5_MKEY_MASK_RW |
3760 MLX5_MKEY_MASK_SMALL_FENCE |
3761 MLX5_MKEY_MASK_FREE |
3762 MLX5_MKEY_MASK_BSF_EN;
3763
3764 return cpu_to_be64(result);
3765}
3766
8a187ee5 3767static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
064e5262 3768 struct mlx5_ib_mr *mr, bool umr_inline)
8a187ee5 3769{
31616255 3770 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3771
3772 memset(umr, 0, sizeof(*umr));
b005d316 3773
8a187ee5 3774 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
064e5262
IB		 3775 if (umr_inline)
3776 umr->flags |= MLX5_UMR_INLINE;
31616255 3777 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3778 umr->mkey_mask = frwr_mkey_mask();
3779}
3780
dd01e66a 3781static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3782{
3783 memset(umr, 0, sizeof(*umr));
dd01e66a 3784 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3785 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3786}
3787
31616255 3788static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3789{
3790 u64 result;
3791
31616255 3792 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3793 MLX5_MKEY_MASK_FREE;
3794
968e78dd
HE		 3795 return cpu_to_be64(result);
3796}
3797
31616255 3798static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3799{
3800 u64 result;
3801
3802 result = MLX5_MKEY_MASK_FREE;
3803
3804 return cpu_to_be64(result);
3805}
3806
56e11d62
NO		 3807static __be64 get_umr_update_translation_mask(void)
3808{
3809 u64 result;
3810
3811 result = MLX5_MKEY_MASK_LEN |
3812 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3813 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3814
3815 return cpu_to_be64(result);
3816}
3817
31616255 3818static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3819{
3820 u64 result;
3821
31616255
AK		 3822 result = MLX5_MKEY_MASK_LR |
3823 MLX5_MKEY_MASK_LW |
56e11d62 3824 MLX5_MKEY_MASK_RR |
31616255
AK		 3825 MLX5_MKEY_MASK_RW;
3826
3827 if (atomic)
3828 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3829
3830 return cpu_to_be64(result);
3831}
3832
3833static __be64 get_umr_update_pd_mask(void)
3834{
3835 u64 result;
3836
31616255 3837 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3838
3839 return cpu_to_be64(result);
3840}
3841
c8d75a98
MD		 3842static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3843{
3844 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3845 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3846 (mask & MLX5_MKEY_MASK_A &&
3847 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3848 return -EPERM;
3849 return 0;
3850}
3851
3852static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3853 struct mlx5_wqe_umr_ctrl_seg *umr,
f696bf6d 3854 const struct ib_send_wr *wr, int atomic)
e126ba97 3855{
f696bf6d 3856 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3857
3858 memset(umr, 0, sizeof(*umr));
3859
968e78dd
HE		 3860 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3861 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3862 else
3863 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3864
31616255
AK		 3865 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3866 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3867 u64 offset = get_xlt_octo(umrwr->offset);
3868
3869 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3870 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3871 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3872 }
31616255
AK		 3873 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3874 umr->mkey_mask |= get_umr_update_translation_mask();
3875 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3876 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3877 umr->mkey_mask |= get_umr_update_pd_mask();
3878 }
3879 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3880 umr->mkey_mask |= get_umr_enable_mr_mask();
3881 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3882 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3883
3884 if (!wr->num_sge)
968e78dd 3885 umr->flags |= MLX5_UMR_INLINE;
c8d75a98
MD		 3886
3887 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
e126ba97
EC		 3888}
3889
3890static u8 get_umr_flags(int acc)
3891{
3892 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3893 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3894 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3895 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3896 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3897}
3898
8a187ee5
SG		 3899static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3900 struct mlx5_ib_mr *mr,
3901 u32 key, int access)
3902{
3903 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3904
3905 memset(seg, 0, sizeof(*seg));
b005d316 3906
ec22eb53 3907 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3908 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3909 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3910 /* KLMs take twice the size of MTTs */
3911 ndescs *= 2;
3912
3913 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3914 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3915 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3916 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3917 seg->len = cpu_to_be64(mr->ibmr.length);
3918 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3919}
3920
dd01e66a 3921static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3922{
3923 memset(seg, 0, sizeof(*seg));
dd01e66a 3924 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3925}
3926
f696bf6d
BVA		 3927static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3928 const struct ib_send_wr *wr)
e126ba97 3929{
f696bf6d 3930 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3931
e126ba97 3932 memset(seg, 0, sizeof(*seg));
31616255 3933 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3934 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3935
968e78dd 3936 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3937 if (umrwr->pd)
3938 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3939 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3940 !umrwr->length)
3941 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3942
3943 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3944 seg->len = cpu_to_be64(umrwr->length);
3945 seg->log2_page_size = umrwr->page_shift;
746b5583 3946 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3947 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3948}
3949
8a187ee5
SG		 3950static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3951 struct mlx5_ib_mr *mr,
3952 struct mlx5_ib_pd *pd)
3953{
3954 int bcount = mr->desc_size * mr->ndescs;
3955
3956 dseg->addr = cpu_to_be64(mr->desc_map);
3957 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3958 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3959}
3960
064e5262
IB		 3961static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3962 struct mlx5_ib_mr *mr, int mr_list_size)
3963{
3964 void *qend = qp->sq.qend;
3965 void *addr = mr->descs;
3966 int copy;
3967
3968 if (unlikely(seg + mr_list_size > qend)) {
3969 copy = qend - seg;
3970 memcpy(seg, addr, copy);
3971 addr += copy;
3972 mr_list_size -= copy;
3973 seg = mlx5_get_send_wqe(qp, 0);
3974 }
3975 memcpy(seg, addr, mr_list_size);
3976 seg += mr_list_size;
3977}
3978
f696bf6d 3979static __be32 send_ieth(const struct ib_send_wr *wr)
e126ba97
EC		 3980{
3981 switch (wr->opcode) {
3982 case IB_WR_SEND_WITH_IMM:
3983 case IB_WR_RDMA_WRITE_WITH_IMM:
3984 return wr->ex.imm_data;
3985
3986 case IB_WR_SEND_WITH_INV:
3987 return cpu_to_be32(wr->ex.invalidate_rkey);
3988
3989 default:
3990 return 0;
3991 }
3992}
3993
3994static u8 calc_sig(void *wqe, int size)
3995{
3996 u8 *p = wqe;
3997 u8 res = 0;
3998 int i;
3999
4000 for (i = 0; i < size; i++)
4001 res ^= p[i];
4002
4003 return ~res;
4004}
4005
4006static u8 wq_sig(void *wqe)
4007{
4008 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4009}
4010
f696bf6d 4011static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
e126ba97
EC		 4012 void *wqe, int *sz)
4013{
4014 struct mlx5_wqe_inline_seg *seg;
4015 void *qend = qp->sq.qend;
4016 void *addr;
4017 int inl = 0;
4018 int copy;
4019 int len;
4020 int i;
4021
4022 seg = wqe;
4023 wqe += sizeof(*seg);
4024 for (i = 0; i < wr->num_sge; i++) {
4025 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4026 len = wr->sg_list[i].length;
4027 inl += len;
4028
4029 if (unlikely(inl > qp->max_inline_data))
4030 return -ENOMEM;
4031
4032 if (unlikely(wqe + len > qend)) {
4033 copy = qend - wqe;
4034 memcpy(wqe, addr, copy);
4035 addr += copy;
4036 len -= copy;
4037 wqe = mlx5_get_send_wqe(qp, 0);
4038 }
4039 memcpy(wqe, addr, len);
4040 wqe += len;
4041 }
4042
4043 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4044
4045 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4046
4047 return 0;
4048}
4049
e6631814
SG		 4050static u16 prot_field_size(enum ib_signature_type type)
4051{
4052 switch (type) {
4053 case IB_SIG_TYPE_T10_DIF:
4054 return MLX5_DIF_SIZE;
4055 default:
4056 return 0;
4057 }
4058}
4059
4060static u8 bs_selector(int block_size)
4061{
4062 switch (block_size) {
4063 case 512: return 0x1;
4064 case 520: return 0x2;
4065 case 4096: return 0x3;
4066 case 4160: return 0x4;
4067 case 1073741824: return 0x5;
4068 default: return 0;
4069 }
4070}
4071
78eda2bb
SG		 4072static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4073 struct mlx5_bsf_inl *inl)
e6631814 4074{
142537f4
SG		 4075 /* Valid inline section and allow BSF refresh */
4076 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4077 MLX5_BSF_REFRESH_DIF);
4078 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4079 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 4080 /* repeating block */
4081 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4082 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4083 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 4084
78eda2bb
SG		 4085 if (domain->sig.dif.ref_remap)
4086 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 4087
78eda2bb
SG		 4088 if (domain->sig.dif.app_escape) {
4089 if (domain->sig.dif.ref_escape)
4090 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4091 else
4092 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 4093 }
4094
78eda2bb
SG		 4095 inl->dif_app_bitmask_check =
4096 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 4097}
4098
4099static int mlx5_set_bsf(struct ib_mr *sig_mr,
4100 struct ib_sig_attrs *sig_attrs,
4101 struct mlx5_bsf *bsf, u32 data_size)
4102{
4103 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4104 struct mlx5_bsf_basic *basic = &bsf->basic;
4105 struct ib_sig_domain *mem = &sig_attrs->mem;
4106 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 4107
c7f44fbd 4108 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 4109
4110 /* Basic + Extended + Inline */
4111 basic->bsf_size_sbs = 1 << 7;
4112 /* Input domain check byte mask */
4113 basic->check_byte_mask = sig_attrs->check_mask;
4114 basic->raw_data_size = cpu_to_be32(data_size);
4115
4116 /* Memory domain */
e6631814 4117 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 4118 case IB_SIG_TYPE_NONE:
4119 break;
e6631814 4120 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 4121 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4122 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4123 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4124 break;
4125 default:
4126 return -EINVAL;
4127 }
e6631814 4128
78eda2bb
SG		 4129 /* Wire domain */
4130 switch (sig_attrs->wire.sig_type) {
4131 case IB_SIG_TYPE_NONE:
4132 break;
4133 case IB_SIG_TYPE_T10_DIF:
e6631814 4134 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 4135 mem->sig_type == wire->sig_type) {
e6631814 4136 /* Same block structure */
142537f4 4137 basic->bsf_size_sbs |= 1 << 4;
e6631814 4138 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 4139 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 4140 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 4141 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 4142 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 4143 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 4144 } else
4145 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4146
142537f4 4147 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 4148 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 4149 break;
e6631814
SG		 4150 default:
4151 return -EINVAL;
4152 }
4153
4154 return 0;
4155}
4156
f696bf6d 4157static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
e622f2f4 4158 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 4159{
e622f2f4
CH		 4160 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4161 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4162 struct mlx5_bsf *bsf;
e622f2f4
CH		 4163 u32 data_len = wr->wr.sg_list->length;
4164 u32 data_key = wr->wr.sg_list->lkey;
4165 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 4166 int ret;
4167 int wqe_size;
4168
e622f2f4
CH		 4169 if (!wr->prot ||
4170 (data_key == wr->prot->lkey &&
4171 data_va == wr->prot->addr &&
4172 data_len == wr->prot->length)) {
e6631814
SG		 4173 /**
4174 * Source domain doesn't contain signature information
5c273b16 4175 * or data and protection are interleaved in memory.
e6631814
SG		 4176 * So need construct:
4177 * ------------------
4178 * | data_klm |
4179 * ------------------
4180 * | BSF |
4181 * ------------------
4182 **/
4183 struct mlx5_klm *data_klm = *seg;
4184
4185 data_klm->bcount = cpu_to_be32(data_len);
4186 data_klm->key = cpu_to_be32(data_key);
4187 data_klm->va = cpu_to_be64(data_va);
4188 wqe_size = ALIGN(sizeof(*data_klm), 64);
4189 } else {
4190 /**
4191 * Source domain contains signature information
4192 * So need construct a strided block format:
4193 * ---------------------------
4194 * | stride_block_ctrl |
4195 * ---------------------------
4196 * | data_klm |
4197 * ---------------------------
4198 * | prot_klm |
4199 * ---------------------------
4200 * | BSF |
4201 * ---------------------------
4202 **/
4203 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4204 struct mlx5_stride_block_entry *data_sentry;
4205 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 4206 u32 prot_key = wr->prot->lkey;
4207 u64 prot_va = wr->prot->addr;
e6631814
SG		 4208 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4209 int prot_size;
4210
4211 sblock_ctrl = *seg;
4212 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4213 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4214
4215 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4216 if (!prot_size) {
4217 pr_err("Bad block size given: %u\n", block_size);
4218 return -EINVAL;
4219 }
4220 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4221 prot_size);
4222 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4223 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4224 sblock_ctrl->num_entries = cpu_to_be16(2);
4225
4226 data_sentry->bcount = cpu_to_be16(block_size);
4227 data_sentry->key = cpu_to_be32(data_key);
4228 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 4229 data_sentry->stride = cpu_to_be16(block_size);
4230
e6631814
SG		 4231 prot_sentry->bcount = cpu_to_be16(prot_size);
4232 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 4233 prot_sentry->va = cpu_to_be64(prot_va);
4234 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 4235
e6631814
SG		 4236 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4237 sizeof(*prot_sentry), 64);
4238 }
4239
4240 *seg += wqe_size;
4241 *size += wqe_size / 16;
4242 if (unlikely((*seg == qp->sq.qend)))
4243 *seg = mlx5_get_send_wqe(qp, 0);
4244
4245 bsf = *seg;
4246 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4247 if (ret)
4248 return -EINVAL;
4249
4250 *seg += sizeof(*bsf);
4251 *size += sizeof(*bsf) / 16;
4252 if (unlikely((*seg == qp->sq.qend)))
4253 *seg = mlx5_get_send_wqe(qp, 0);
4254
4255 return 0;
4256}
4257
4258static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
f696bf6d 4259 const struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4260 u32 length, u32 pdn)
4261{
e622f2f4 4262 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4263 u32 sig_key = sig_mr->rkey;
d5436ba0 4264 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4265
4266 memset(seg, 0, sizeof(*seg));
4267
e622f2f4 4268 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4269 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4270 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4271 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4272 MLX5_MKEY_BSF_EN | pdn);
4273 seg->len = cpu_to_be64(length);
31616255 4274 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4275 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4276}
4277
4278static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4279 u32 size)
e6631814
SG		 4280{
4281 memset(umr, 0, sizeof(*umr));
4282
4283 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4284 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4285 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4286 umr->mkey_mask = sig_mkey_mask();
4287}
4288
4289
f696bf6d
BVA		 4290static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4291 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 4292{
f696bf6d 4293 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
e622f2f4 4294 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4295 u32 pdn = get_pd(qp)->pdn;
31616255 4296 u32 xlt_size;
e6631814
SG		 4297 int region_len, ret;
4298
e622f2f4
CH		 4299 if (unlikely(wr->wr.num_sge != 1) ||
4300 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4301 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4302 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4303 return -EINVAL;
4304
4305 /* length of the protected region, data + protection */
e622f2f4
CH		 4306 region_len = wr->wr.sg_list->length;
4307 if (wr->prot &&
4308 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4309 wr->prot->addr != wr->wr.sg_list->addr ||
4310 wr->prot->length != wr->wr.sg_list->length))
4311 region_len += wr->prot->length;
e6631814
SG		 4312
4313 /**
4314 * KLM octoword size - if protection was provided
4315 * then we use strided block format (3 octowords),
4316 * else we use single KLM (1 octoword)
4317 **/
31616255 4318 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4319
31616255 4320 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4321 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4322 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4323 if (unlikely((*seg == qp->sq.qend)))
4324 *seg = mlx5_get_send_wqe(qp, 0);
4325
31616255 4326 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4327 *seg += sizeof(struct mlx5_mkey_seg);
4328 *size += sizeof(struct mlx5_mkey_seg) / 16;
4329 if (unlikely((*seg == qp->sq.qend)))
4330 *seg = mlx5_get_send_wqe(qp, 0);
4331
4332 ret = set_sig_data_segment(wr, qp, seg, size);
4333 if (ret)
4334 return ret;
4335
d5436ba0 4336 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4337 return 0;
4338}
4339
4340static int set_psv_wr(struct ib_sig_domain *domain,
4341 u32 psv_idx, void **seg, int *size)
4342{
4343 struct mlx5_seg_set_psv *psv_seg = *seg;
4344
4345 memset(psv_seg, 0, sizeof(*psv_seg));
4346 psv_seg->psv_num = cpu_to_be32(psv_idx);
4347 switch (domain->sig_type) {
78eda2bb
SG		 4348 case IB_SIG_TYPE_NONE:
4349 break;
e6631814
SG		 4350 case IB_SIG_TYPE_T10_DIF:
4351 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4352 domain->sig.dif.app_tag);
4353 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4354 break;
e6631814 4355 default:
12bbf1ea
LR		 4356 pr_err("Bad signature type (%d) is given.\n",
4357 domain->sig_type);
4358 return -EINVAL;
e6631814
SG		 4359 }
4360
78eda2bb
SG		 4361 *seg += sizeof(*psv_seg);
4362 *size += sizeof(*psv_seg) / 16;
4363
e6631814
SG		 4364 return 0;
4365}
4366
8a187ee5 4367static int set_reg_wr(struct mlx5_ib_qp *qp,
f696bf6d 4368 const struct ib_reg_wr *wr,
8a187ee5
SG		 4369 void **seg, int *size)
4370{
4371 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4372 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
064e5262
IB		 4373 int mr_list_size = mr->ndescs * mr->desc_size;
4374 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
8a187ee5
SG		 4375
4376 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4377 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4378 "Invalid IB_SEND_INLINE send flag\n");
4379 return -EINVAL;
4380 }
4381
064e5262 4382 set_reg_umr_seg(*seg, mr, umr_inline);
8a187ee5
SG		 4383 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4384 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4385 if (unlikely((*seg == qp->sq.qend)))
4386 *seg = mlx5_get_send_wqe(qp, 0);
4387
4388 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4389 *seg += sizeof(struct mlx5_mkey_seg);
4390 *size += sizeof(struct mlx5_mkey_seg) / 16;
4391 if (unlikely((*seg == qp->sq.qend)))
4392 *seg = mlx5_get_send_wqe(qp, 0);
4393
064e5262
IB		 4394 if (umr_inline) {
4395 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4396 *size += get_xlt_octo(mr_list_size);
4397 } else {
4398 set_reg_data_seg(*seg, mr, pd);
4399 *seg += sizeof(struct mlx5_wqe_data_seg);
4400 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4401 }
8a187ee5
SG		 4402 return 0;
4403}
4404
dd01e66a 4405static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4406{
dd01e66a 4407 set_linv_umr_seg(*seg);
e126ba97
EC		 4408 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4409 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4410 if (unlikely((*seg == qp->sq.qend)))
4411 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4412 set_linv_mkey_seg(*seg);
e126ba97
EC		 4413 *seg += sizeof(struct mlx5_mkey_seg);
4414 *size += sizeof(struct mlx5_mkey_seg) / 16;
4415 if (unlikely((*seg == qp->sq.qend)))
4416 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4417}
4418
4419static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4420{
4421 __be32 *p = NULL;
4422 int tidx = idx;
4423 int i, j;
4424
4425 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4426 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4427 if ((i & 0xf) == 0) {
4428 void *buf = mlx5_get_send_wqe(qp, tidx);
4429 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4430 p = buf;
4431 j = 0;
4432 }
4433 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4434 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4435 be32_to_cpu(p[j + 3]));
4436 }
4437}
4438
7bb1fafc 4439static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
6e5eadac 4440 struct mlx5_wqe_ctrl_seg **ctrl,
f696bf6d 4441 const struct ib_send_wr *wr, unsigned *idx,
7bb1fafc 4442 int *size, int nreq, bool send_signaled, bool solicited)
6e5eadac 4443{
b2a232d2
LR		 4444 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4445 return -ENOMEM;
6e5eadac
SG		 4446
4447 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4448 *seg = mlx5_get_send_wqe(qp, *idx);
4449 *ctrl = *seg;
4450 *(uint32_t *)(*seg + 8) = 0;
4451 (*ctrl)->imm = send_ieth(wr);
4452 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
7bb1fafc
BVA		 4453 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4454 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
6e5eadac
SG		 4455
4456 *seg += sizeof(**ctrl);
4457 *size = sizeof(**ctrl) / 16;
4458
b2a232d2 4459 return 0;
6e5eadac
SG		 4460}
4461
7bb1fafc
BVA		 4462static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4463 struct mlx5_wqe_ctrl_seg **ctrl,
4464 const struct ib_send_wr *wr, unsigned *idx,
4465 int *size, int nreq)
4466{
4467 return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4468 wr->send_flags & IB_SEND_SIGNALED,
4469 wr->send_flags & IB_SEND_SOLICITED);
4470}
4471
6e5eadac
SG		 4472static void finish_wqe(struct mlx5_ib_qp *qp,
4473 struct mlx5_wqe_ctrl_seg *ctrl,
4474 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4475 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4476{
4477 u8 opmod = 0;
4478
4479 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4480 mlx5_opcode | ((u32)opmod << 24));
19098df2 4481 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4482 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4483 if (unlikely(qp->wq_sig))
4484 ctrl->signature = wq_sig(ctrl);
4485
4486 qp->sq.wrid[idx] = wr_id;
4487 qp->sq.w_list[idx].opcode = mlx5_opcode;
4488 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4489 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4490 qp->sq.w_list[idx].next = qp->sq.cur_post;
4491}
4492
d34ac5cd
BVA		 4493static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4494 const struct ib_send_wr **bad_wr, bool drain)
e126ba97
EC		 4495{
4496 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4497 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4498 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4499 struct mlx5_ib_qp *qp;
e6631814 4500 struct mlx5_ib_mr *mr;
e126ba97
EC		 4501 struct mlx5_wqe_data_seg *dpseg;
4502 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4503 struct mlx5_bf *bf;
e126ba97 4504 int uninitialized_var(size);
d16e91da 4505 void *qend;
e126ba97 4506 unsigned long flags;
e126ba97
EC		 4507 unsigned idx;
4508 int err = 0;
e126ba97
EC		 4509 int num_sge;
4510 void *seg;
4511 int nreq;
4512 int i;
4513 u8 next_fence = 0;
e126ba97
EC		 4514 u8 fence;
4515
6c75520f
PP		 4516 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4517 !drain)) {
4518 *bad_wr = wr;
4519 return -EIO;
4520 }
4521
d16e91da
HE		 4522 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4523 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4524
4525 qp = to_mqp(ibqp);
5fe9dec0 4526 bf = &qp->bf;
d16e91da
HE		 4527 qend = qp->sq.qend;
4528
e126ba97
EC		 4529 spin_lock_irqsave(&qp->sq.lock, flags);
4530
4531 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4532 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4533 mlx5_ib_warn(dev, "\n");
4534 err = -EINVAL;
4535 *bad_wr = wr;
4536 goto out;
4537 }
4538
6e5eadac
SG		 4539 num_sge = wr->num_sge;
4540 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4541 mlx5_ib_warn(dev, "\n");
24be409b 4542 err = -EINVAL;
e126ba97
EC		 4543 *bad_wr = wr;
4544 goto out;
4545 }
4546
6e5eadac
SG		 4547 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4548 if (err) {
e126ba97
EC		 4549 mlx5_ib_warn(dev, "\n");
4550 err = -ENOMEM;
4551 *bad_wr = wr;
4552 goto out;
4553 }
4554
6e8484c5
MG		 4555 if (wr->opcode == IB_WR_LOCAL_INV ||
4556 wr->opcode == IB_WR_REG_MR) {
4557 fence = dev->umr_fence;
4558 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4559 } else if (wr->send_flags & IB_SEND_FENCE) {
4560 if (qp->next_fence)
4561 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4562 else
4563 fence = MLX5_FENCE_MODE_FENCE;
4564 } else {
4565 fence = qp->next_fence;
4566 }
4567
e126ba97
EC		 4568 switch (ibqp->qp_type) {
4569 case IB_QPT_XRC_INI:
4570 xrc = seg;
e126ba97
EC		 4571 seg += sizeof(*xrc);
4572 size += sizeof(*xrc) / 16;
4573 /* fall through */
4574 case IB_QPT_RC:
4575 switch (wr->opcode) {
4576 case IB_WR_RDMA_READ:
4577 case IB_WR_RDMA_WRITE:
4578 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4579 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4580 rdma_wr(wr)->rkey);
f241e749 4581 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4582 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4583 break;
4584
4585 case IB_WR_ATOMIC_CMP_AND_SWP:
4586 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4587 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4588 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4589 err = -ENOSYS;
4590 *bad_wr = wr;
4591 goto out;
e126ba97
EC		 4592
4593 case IB_WR_LOCAL_INV:
e126ba97
EC		 4594 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4595 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4596 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4597 num_sge = 0;
4598 break;
4599
8a187ee5 4600 case IB_WR_REG_MR:
8a187ee5
SG		 4601 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4602 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4603 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4604 if (err) {
4605 *bad_wr = wr;
4606 goto out;
4607 }
4608 num_sge = 0;
4609 break;
4610
e6631814
SG		 4611 case IB_WR_REG_SIG_MR:
4612 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4613 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4614
4615 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4616 err = set_sig_umr_wr(wr, qp, &seg, &size);
4617 if (err) {
4618 mlx5_ib_warn(dev, "\n");
4619 *bad_wr = wr;
4620 goto out;
4621 }
4622
6e8484c5
MG		 4623 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4624 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4625 /*
4626 * SET_PSV WQEs are not signaled and solicited
4627 * on error
4628 */
7bb1fafc
BVA		 4629 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4630 &size, nreq, false, true);
e6631814
SG		 4631 if (err) {
4632 mlx5_ib_warn(dev, "\n");
4633 err = -ENOMEM;
4634 *bad_wr = wr;
4635 goto out;
4636 }
4637
e622f2f4 4638 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4639 mr->sig->psv_memory.psv_idx, &seg,
4640 &size);
4641 if (err) {
4642 mlx5_ib_warn(dev, "\n");
4643 *bad_wr = wr;
4644 goto out;
4645 }
4646
6e8484c5
MG		 4647 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4648 fence, MLX5_OPCODE_SET_PSV);
7bb1fafc
BVA		 4649 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4650 &size, nreq, false, true);
e6631814
SG		 4651 if (err) {
4652 mlx5_ib_warn(dev, "\n");
4653 err = -ENOMEM;
4654 *bad_wr = wr;
4655 goto out;
4656 }
4657
e622f2f4 4658 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4659 mr->sig->psv_wire.psv_idx, &seg,
4660 &size);
4661 if (err) {
4662 mlx5_ib_warn(dev, "\n");
4663 *bad_wr = wr;
4664 goto out;
4665 }
4666
6e8484c5
MG		 4667 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4668 fence, MLX5_OPCODE_SET_PSV);
4669 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4670 num_sge = 0;
4671 goto skip_psv;
4672
e126ba97
EC		 4673 default:
4674 break;
4675 }
4676 break;
4677
4678 case IB_QPT_UC:
4679 switch (wr->opcode) {
4680 case IB_WR_RDMA_WRITE:
4681 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4682 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4683 rdma_wr(wr)->rkey);
e126ba97
EC		 4684 seg += sizeof(struct mlx5_wqe_raddr_seg);
4685 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4686 break;
4687
4688 default:
4689 break;
4690 }
4691 break;
4692
e126ba97 4693 case IB_QPT_SMI:
1e0e50b6
MG		 4694 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4695 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4696 err = -EPERM;
4697 *bad_wr = wr;
4698 goto out;
4699 }
f6b1ee34 4700 /* fall through */
d16e91da 4701 case MLX5_IB_QPT_HW_GSI:
e126ba97 4702 set_datagram_seg(seg, wr);
f241e749 4703 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4704 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4705 if (unlikely((seg == qend)))
4706 seg = mlx5_get_send_wqe(qp, 0);
4707 break;
f0313965
ES		 4708 case IB_QPT_UD:
4709 set_datagram_seg(seg, wr);
4710 seg += sizeof(struct mlx5_wqe_datagram_seg);
4711 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4712
4713 if (unlikely((seg == qend)))
4714 seg = mlx5_get_send_wqe(qp, 0);
4715
4716 /* handle qp that supports ud offload */
4717 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4718 struct mlx5_wqe_eth_pad *pad;
e126ba97 4719
f0313965
ES		 4720 pad = seg;
4721 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4722 seg += sizeof(struct mlx5_wqe_eth_pad);
4723 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4724
4725 seg = set_eth_seg(seg, wr, qend, qp, &size);
4726
4727 if (unlikely((seg == qend)))
4728 seg = mlx5_get_send_wqe(qp, 0);
4729 }
4730 break;
e126ba97
EC		 4731 case MLX5_IB_QPT_REG_UMR:
4732 if (wr->opcode != MLX5_IB_WR_UMR) {
4733 err = -EINVAL;
4734 mlx5_ib_warn(dev, "bad opcode\n");
4735 goto out;
4736 }
4737 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4738 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
c8d75a98
MD		 4739 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4740 if (unlikely(err))
4741 goto out;
e126ba97
EC		 4742 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4743 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4744 if (unlikely((seg == qend)))
4745 seg = mlx5_get_send_wqe(qp, 0);
4746 set_reg_mkey_segment(seg, wr);
4747 seg += sizeof(struct mlx5_mkey_seg);
4748 size += sizeof(struct mlx5_mkey_seg) / 16;
4749 if (unlikely((seg == qend)))
4750 seg = mlx5_get_send_wqe(qp, 0);
4751 break;
4752
4753 default:
4754 break;
4755 }
4756
4757 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4758 int uninitialized_var(sz);
4759
4760 err = set_data_inl_seg(qp, wr, seg, &sz);
4761 if (unlikely(err)) {
4762 mlx5_ib_warn(dev, "\n");
4763 *bad_wr = wr;
4764 goto out;
4765 }
e126ba97
EC		 4766 size += sz;
4767 } else {
4768 dpseg = seg;
4769 for (i = 0; i < num_sge; i++) {
4770 if (unlikely(dpseg == qend)) {
4771 seg = mlx5_get_send_wqe(qp, 0);
4772 dpseg = seg;
4773 }
4774 if (likely(wr->sg_list[i].length)) {
4775 set_data_ptr_seg(dpseg, wr->sg_list + i);
4776 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4777 dpseg++;
4778 }
4779 }
4780 }
4781
6e8484c5
MG		 4782 qp->next_fence = next_fence;
4783 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4784 mlx5_ib_opcode[wr->opcode]);
e6631814 4785skip_psv:
e126ba97
EC		 4786 if (0)
4787 dump_wqe(qp, idx, size);
4788 }
4789
4790out:
4791 if (likely(nreq)) {
4792 qp->sq.head += nreq;
4793
4794 /* Make sure that descriptors are written before
4795 * updating doorbell record and ringing the doorbell
4796 */
4797 wmb();
4798
4799 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4800
ada388f7
EC		 4801 /* Make sure doorbell record is visible to the HCA before
4802 * we hit doorbell */
4803 wmb();
4804
5fe9dec0
EC		 4805 /* currently we support only regular doorbells */
4806 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4807 /* Make sure doorbells don't leak out of SQ spinlock
4808 * and reach the HCA out of order.
4809 */
4810 mmiowb();
e126ba97 4811 bf->offset ^= bf->buf_size;
e126ba97
EC		 4812 }
4813
4814 spin_unlock_irqrestore(&qp->sq.lock, flags);
4815
4816 return err;
4817}
4818
d34ac5cd
BVA		 4819int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4820 const struct ib_send_wr **bad_wr)
d0e84c0a
YH		 4821{
4822 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4823}
4824
e126ba97
EC		 4825static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4826{
4827 sig->signature = calc_sig(sig, size);
4828}
4829
d34ac5cd
BVA		 4830static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4831 const struct ib_recv_wr **bad_wr, bool drain)
e126ba97
EC		 4832{
4833 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4834 struct mlx5_wqe_data_seg *scat;
4835 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4836 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4837 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4838 unsigned long flags;
4839 int err = 0;
4840 int nreq;
4841 int ind;
4842 int i;
4843
6c75520f
PP		 4844 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4845 !drain)) {
4846 *bad_wr = wr;
4847 return -EIO;
4848 }
4849
d16e91da
HE		 4850 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4851 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4852
e126ba97
EC		 4853 spin_lock_irqsave(&qp->rq.lock, flags);
4854
4855 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4856
4857 for (nreq = 0; wr; nreq++, wr = wr->next) {
4858 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4859 err = -ENOMEM;
4860 *bad_wr = wr;
4861 goto out;
4862 }
4863
4864 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4865 err = -EINVAL;
4866 *bad_wr = wr;
4867 goto out;
4868 }
4869
4870 scat = get_recv_wqe(qp, ind);
4871 if (qp->wq_sig)
4872 scat++;
4873
4874 for (i = 0; i < wr->num_sge; i++)
4875 set_data_ptr_seg(scat + i, wr->sg_list + i);
4876
4877 if (i < qp->rq.max_gs) {
4878 scat[i].byte_count = 0;
4879 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4880 scat[i].addr = 0;
4881 }
4882
4883 if (qp->wq_sig) {
4884 sig = (struct mlx5_rwqe_sig *)scat;
4885 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4886 }
4887
4888 qp->rq.wrid[ind] = wr->wr_id;
4889
4890 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4891 }
4892
4893out:
4894 if (likely(nreq)) {
4895 qp->rq.head += nreq;
4896
4897 /* Make sure that descriptors are written before
4898 * doorbell record.
4899 */
4900 wmb();
4901
4902 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4903 }
4904
4905 spin_unlock_irqrestore(&qp->rq.lock, flags);
4906
4907 return err;
4908}
4909
d34ac5cd
BVA		 4910int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4911 const struct ib_recv_wr **bad_wr)
d0e84c0a
YH		 4912{
4913 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4914}
4915
e126ba97
EC		 4916static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4917{
4918 switch (mlx5_state) {
4919 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4920 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4921 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4922 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4923 case MLX5_QP_STATE_SQ_DRAINING:
4924 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4925 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4926 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4927 default: return -1;
4928 }
4929}
4930
4931static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4932{
4933 switch (mlx5_mig_state) {
4934 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4935 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4936 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4937 default: return -1;
4938 }
4939}
4940
4941static int to_ib_qp_access_flags(int mlx5_flags)
4942{
4943 int ib_flags = 0;
4944
4945 if (mlx5_flags & MLX5_QP_BIT_RRE)
4946 ib_flags |= IB_ACCESS_REMOTE_READ;
4947 if (mlx5_flags & MLX5_QP_BIT_RWE)
4948 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4949 if (mlx5_flags & MLX5_QP_BIT_RAE)
4950 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4951
4952 return ib_flags;
4953}
4954
38349389 4955static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4956 struct rdma_ah_attr *ah_attr,
38349389 4957 struct mlx5_qp_path *path)
e126ba97 4958{
e126ba97 4959
d8966fcd 4960 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4961
e7996a9a 4962 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 4963 return;
4964
ae59c3f0
LR		 4965 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4966
d8966fcd
DC		 4967 rdma_ah_set_port_num(ah_attr, path->port);
4968 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4969
4970 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4971 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4972 rdma_ah_set_static_rate(ah_attr,
4973 path->static_rate ? path->static_rate - 5 : 0);
4974 if (path->grh_mlid & (1 << 7)) {
4975 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4976
4977 rdma_ah_set_grh(ah_attr, NULL,
4978 tc_fl & 0xfffff,
4979 path->mgid_index,
4980 path->hop_limit,
4981 (tc_fl >> 20) & 0xff);
4982 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4983 }
4984}
4985
6d2f89df 4986static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4987 struct mlx5_ib_sq *sq,
4988 u8 *sq_state)
4989{
6d2f89df 4990 int err;
4991
28160771 4992 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 4993 if (err)
4994 goto out;
6d2f89df 4995 sq->state = *sq_state;
4996
4997out:
6d2f89df 4998 return err;
4999}
5000
5001static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5002 struct mlx5_ib_rq *rq,
5003 u8 *rq_state)
5004{
5005 void *out;
5006 void *rqc;
5007 int inlen;
5008 int err;
5009
5010 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 5011 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 5012 if (!out)
5013 return -ENOMEM;
5014
5015 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5016 if (err)
5017 goto out;
5018
5019 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5020 *rq_state = MLX5_GET(rqc, rqc, state);
5021 rq->state = *rq_state;
5022
5023out:
5024 kvfree(out);
5025 return err;
5026}
5027
5028static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5029 struct mlx5_ib_qp *qp, u8 *qp_state)
5030{
5031 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5032 [MLX5_RQC_STATE_RST] = {
5033 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5034 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5035 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5036 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5037 },
5038 [MLX5_RQC_STATE_RDY] = {
5039 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5040 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5041 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5042 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5043 },
5044 [MLX5_RQC_STATE_ERR] = {
5045 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5046 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5047 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5048 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5049 },
5050 [MLX5_RQ_STATE_NA] = {
5051 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5052 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5053 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5054 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5055 },
5056 };
5057
5058 *qp_state = sqrq_trans[rq_state][sq_state];
5059
5060 if (*qp_state == MLX5_QP_STATE_BAD) {
5061 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5062 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5063 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5064 return -EINVAL;
5065 }
5066
5067 if (*qp_state == MLX5_QP_STATE)
5068 *qp_state = qp->state;
5069
5070 return 0;
5071}
5072
5073static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5074 struct mlx5_ib_qp *qp,
5075 u8 *raw_packet_qp_state)
5076{
5077 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5078 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5079 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5080 int err;
5081 u8 sq_state = MLX5_SQ_STATE_NA;
5082 u8 rq_state = MLX5_RQ_STATE_NA;
5083
5084 if (qp->sq.wqe_cnt) {
5085 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5086 if (err)
5087 return err;
5088 }
5089
5090 if (qp->rq.wqe_cnt) {
5091 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5092 if (err)
5093 return err;
5094 }
5095
5096 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5097 raw_packet_qp_state);
5098}
5099
5100static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5101 struct ib_qp_attr *qp_attr)
e126ba97 5102{
09a7d9ec 5103 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 5104 struct mlx5_qp_context *context;
5105 int mlx5_state;
09a7d9ec 5106 u32 *outb;
e126ba97
EC		 5107 int err = 0;
5108
09a7d9ec 5109 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 5110 if (!outb)
5111 return -ENOMEM;
5112
19098df2 5113 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 5114 outlen);
e126ba97 5115 if (err)
6d2f89df 5116 goto out;
e126ba97 5117
09a7d9ec
SM		 5118 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5119 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5120
e126ba97
EC		 5121 mlx5_state = be32_to_cpu(context->flags) >> 28;
5122
5123 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 5124 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5125 qp_attr->path_mig_state =
5126 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5127 qp_attr->qkey = be32_to_cpu(context->qkey);
5128 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5129 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5130 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5131 qp_attr->qp_access_flags =
5132 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5133
5134 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 5135 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5136 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 5137 qp_attr->alt_pkey_index =
5138 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 5139 qp_attr->alt_port_num =
5140 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 5141 }
5142
d3ae2bde 5143 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 5144 qp_attr->port_num = context->pri_path.port;
5145
5146 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5147 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5148
5149 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5150
5151 qp_attr->max_dest_rd_atomic =
5152 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5153 qp_attr->min_rnr_timer =
5154 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5155 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5156 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5157 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5158 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 5159
5160out:
5161 kfree(outb);
5162 return err;
5163}
5164
776a3906
MS		 5165static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5166 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5167 struct ib_qp_init_attr *qp_init_attr)
5168{
5169 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5170 u32 *out;
5171 u32 access_flags = 0;
5172 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5173 void *dctc;
5174 int err;
5175 int supported_mask = IB_QP_STATE |
5176 IB_QP_ACCESS_FLAGS |
5177 IB_QP_PORT |
5178 IB_QP_MIN_RNR_TIMER |
5179 IB_QP_AV |
5180 IB_QP_PATH_MTU |
5181 IB_QP_PKEY_INDEX;
5182
5183 if (qp_attr_mask & ~supported_mask)
5184 return -EINVAL;
5185 if (mqp->state != IB_QPS_RTR)
5186 return -EINVAL;
5187
5188 out = kzalloc(outlen, GFP_KERNEL);
5189 if (!out)
5190 return -ENOMEM;
5191
5192 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5193 if (err)
5194 goto out;
5195
5196 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5197
5198 if (qp_attr_mask & IB_QP_STATE)
5199 qp_attr->qp_state = IB_QPS_RTR;
5200
5201 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5202 if (MLX5_GET(dctc, dctc, rre))
5203 access_flags |= IB_ACCESS_REMOTE_READ;
5204 if (MLX5_GET(dctc, dctc, rwe))
5205 access_flags |= IB_ACCESS_REMOTE_WRITE;
5206 if (MLX5_GET(dctc, dctc, rae))
5207 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5208 qp_attr->qp_access_flags = access_flags;
5209 }
5210
5211 if (qp_attr_mask & IB_QP_PORT)
5212 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5213 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5214 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5215 if (qp_attr_mask & IB_QP_AV) {
5216 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5217 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5218 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5219 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5220 }
5221 if (qp_attr_mask & IB_QP_PATH_MTU)
5222 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5223 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5224 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5225out:
5226 kfree(out);
5227 return err;
5228}
5229
6d2f89df 5230int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5231 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5232{
5233 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5234 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5235 int err = 0;
5236 u8 raw_packet_qp_state;
5237
28d61370
YH		 5238 if (ibqp->rwq_ind_tbl)
5239 return -ENOSYS;
5240
d16e91da
HE		 5241 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5242 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5243 qp_init_attr);
5244
c2e53b2c
YH		 5245 /* Not all of output fields are applicable, make sure to zero them */
5246 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5247 memset(qp_attr, 0, sizeof(*qp_attr));
5248
776a3906
MS		 5249 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5250 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5251 qp_attr_mask, qp_init_attr);
5252
6d2f89df 5253 mutex_lock(&qp->mutex);
5254
c2e53b2c
YH		 5255 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5256 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5257 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5258 if (err)
5259 goto out;
5260 qp->state = raw_packet_qp_state;
5261 qp_attr->port_num = 1;
5262 } else {
5263 err = query_qp_attr(dev, qp, qp_attr);
5264 if (err)
5265 goto out;
5266 }
5267
5268 qp_attr->qp_state = qp->state;
e126ba97
EC		 5269 qp_attr->cur_qp_state = qp_attr->qp_state;
5270 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5271 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5272
5273 if (!ibqp->uobject) {
0540d814 5274 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5275 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5276 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5277 } else {
5278 qp_attr->cap.max_send_wr = 0;
5279 qp_attr->cap.max_send_sge = 0;
5280 }
5281
0540d814
NO		 5282 qp_init_attr->qp_type = ibqp->qp_type;
5283 qp_init_attr->recv_cq = ibqp->recv_cq;
5284 qp_init_attr->send_cq = ibqp->send_cq;
5285 qp_init_attr->srq = ibqp->srq;
5286 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5287
5288 qp_init_attr->cap = qp_attr->cap;
5289
5290 qp_init_attr->create_flags = 0;
5291 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5292 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5293
051f2630
LR		 5294 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5295 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5296 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5297 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5298 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5299 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5300 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5301 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5302
e126ba97
EC		 5303 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5304 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5305
e126ba97
EC		 5306out:
5307 mutex_unlock(&qp->mutex);
5308 return err;
5309}
5310
5311struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5312 struct ib_ucontext *context,
5313 struct ib_udata *udata)
5314{
5315 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5316 struct mlx5_ib_xrcd *xrcd;
5317 int err;
d00614c0 5318 u16 uid;
e126ba97 5319
938fe83c 5320 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5321 return ERR_PTR(-ENOSYS);
5322
5323 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5324 if (!xrcd)
5325 return ERR_PTR(-ENOMEM);
5326
d00614c0
YH		 5327 uid = context ? to_mucontext(context)->devx_uid : 0;
5328 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, uid);
e126ba97
EC		 5329 if (err) {
5330 kfree(xrcd);
5331 return ERR_PTR(-ENOMEM);
5332 }
5333
d00614c0 5334 xrcd->uid = uid;
e126ba97
EC		 5335 return &xrcd->ibxrcd;
5336}
5337
5338int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5339{
5340 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5341 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
d00614c0 5342 u16 uid = to_mxrcd(xrcd)->uid;
e126ba97
EC		 5343 int err;
5344
d00614c0 5345 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, uid);
b081808a 5346 if (err)
e126ba97 5347 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5348
5349 kfree(xrcd);
e126ba97
EC		 5350 return 0;
5351}
79b20a6c 5352
350d0e4c
YH		 5353static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5354{
5355 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5356 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5357 struct ib_event event;
5358
5359 if (rwq->ibwq.event_handler) {
5360 event.device = rwq->ibwq.device;
5361 event.element.wq = &rwq->ibwq;
5362 switch (type) {
5363 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5364 event.event = IB_EVENT_WQ_FATAL;
5365 break;
5366 default:
5367 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5368 return;
5369 }
5370
5371 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5372 }
5373}
5374
03404e8a
MG		 5375static int set_delay_drop(struct mlx5_ib_dev *dev)
5376{
5377 int err = 0;
5378
5379 mutex_lock(&dev->delay_drop.lock);
5380 if (dev->delay_drop.activate)
5381 goto out;
5382
5383 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5384 if (err)
5385 goto out;
5386
5387 dev->delay_drop.activate = true;
5388out:
5389 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5390
5391 if (!err)
5392 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5393 return err;
5394}
5395
79b20a6c
YH		 5396static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5397 struct ib_wq_init_attr *init_attr)
5398{
5399 struct mlx5_ib_dev *dev;
4be6da1e 5400 int has_net_offloads;
79b20a6c
YH		 5401 __be64 *rq_pas0;
5402 void *in;
5403 void *rqc;
5404 void *wq;
5405 int inlen;
5406 int err;
5407
5408 dev = to_mdev(pd->device);
5409
5410 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5411 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5412 if (!in)
5413 return -ENOMEM;
5414
34d57585 5415 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 5416 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5417 MLX5_SET(rqc, rqc, mem_rq_type,
5418 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5419 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5420 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5421 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5422 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5423 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5424 MLX5_SET(wq, wq, wq_type,
5425 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5426 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5427 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5428 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5429 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5430 err = -EOPNOTSUPP;
5431 goto out;
5432 } else {
5433 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5434 }
5435 }
79b20a6c 5436 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5437 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5438 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5439 MLX5_SET(wq, wq, log_wqe_stride_size,
5440 rwq->single_stride_log_num_of_bytes -
5441 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5442 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5443 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5444 }
79b20a6c
YH		 5445 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5446 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5447 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5448 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5449 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5450 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5451 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5452 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5453 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5454 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5455 err = -EOPNOTSUPP;
5456 goto out;
5457 }
5458 } else {
5459 MLX5_SET(rqc, rqc, vsd, 1);
5460 }
4be6da1e
NO		 5461 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5462 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5463 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5464 err = -EOPNOTSUPP;
5465 goto out;
5466 }
5467 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5468 }
03404e8a
MG		 5469 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5470 if (!(dev->ib_dev.attrs.raw_packet_caps &
5471 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5472 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5473 err = -EOPNOTSUPP;
5474 goto out;
5475 }
5476 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5477 }
79b20a6c
YH		 5478 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5479 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5480 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5481 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5482 err = set_delay_drop(dev);
5483 if (err) {
5484 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5485 err);
5486 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5487 } else {
5488 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5489 }
5490 }
b1f74a84 5491out:
79b20a6c
YH		 5492 kvfree(in);
5493 return err;
5494}
5495
5496static int set_user_rq_size(struct mlx5_ib_dev *dev,
5497 struct ib_wq_init_attr *wq_init_attr,
5498 struct mlx5_ib_create_wq *ucmd,
5499 struct mlx5_ib_rwq *rwq)
5500{
5501 /* Sanity check RQ size before proceeding */
5502 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5503 return -EINVAL;
5504
5505 if (!ucmd->rq_wqe_count)
5506 return -EINVAL;
5507
5508 rwq->wqe_count = ucmd->rq_wqe_count;
5509 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 5510 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5511 return -EINVAL;
5512
79b20a6c
YH		 5513 rwq->log_rq_stride = rwq->wqe_shift;
5514 rwq->log_rq_size = ilog2(rwq->wqe_count);
5515 return 0;
5516}
5517
5518static int prepare_user_rq(struct ib_pd *pd,
5519 struct ib_wq_init_attr *init_attr,
5520 struct ib_udata *udata,
5521 struct mlx5_ib_rwq *rwq)
5522{
5523 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5524 struct mlx5_ib_create_wq ucmd = {};
5525 int err;
5526 size_t required_cmd_sz;
5527
ccc87087
NO		 5528 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5529 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5530 if (udata->inlen < required_cmd_sz) {
5531 mlx5_ib_dbg(dev, "invalid inlen\n");
5532 return -EINVAL;
5533 }
5534
5535 if (udata->inlen > sizeof(ucmd) &&
5536 !ib_is_udata_cleared(udata, sizeof(ucmd),
5537 udata->inlen - sizeof(ucmd))) {
5538 mlx5_ib_dbg(dev, "inlen is not supported\n");
5539 return -EOPNOTSUPP;
5540 }
5541
5542 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5543 mlx5_ib_dbg(dev, "copy failed\n");
5544 return -EFAULT;
5545 }
5546
ccc87087 5547 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5548 mlx5_ib_dbg(dev, "invalid comp mask\n");
5549 return -EOPNOTSUPP;
ccc87087
NO		 5550 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5551 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5552 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5553 return -EOPNOTSUPP;
5554 }
5555 if ((ucmd.single_stride_log_num_of_bytes <
5556 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5557 (ucmd.single_stride_log_num_of_bytes >
5558 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5559 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5560 ucmd.single_stride_log_num_of_bytes,
5561 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5562 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5563 return -EINVAL;
5564 }
5565 if ((ucmd.single_wqe_log_num_of_strides >
5566 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5567 (ucmd.single_wqe_log_num_of_strides <
5568 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5569 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5570 ucmd.single_wqe_log_num_of_strides,
5571 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5572 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5573 return -EINVAL;
5574 }
5575 rwq->single_stride_log_num_of_bytes =
5576 ucmd.single_stride_log_num_of_bytes;
5577 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5578 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5579 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5580 }
5581
5582 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5583 if (err) {
5584 mlx5_ib_dbg(dev, "err %d\n", err);
5585 return err;
5586 }
5587
5588 err = create_user_rq(dev, pd, rwq, &ucmd);
5589 if (err) {
5590 mlx5_ib_dbg(dev, "err %d\n", err);
5591 if (err)
5592 return err;
5593 }
5594
5595 rwq->user_index = ucmd.user_index;
5596 return 0;
5597}
5598
5599struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5600 struct ib_wq_init_attr *init_attr,
5601 struct ib_udata *udata)
5602{
5603 struct mlx5_ib_dev *dev;
5604 struct mlx5_ib_rwq *rwq;
5605 struct mlx5_ib_create_wq_resp resp = {};
5606 size_t min_resp_len;
5607 int err;
5608
5609 if (!udata)
5610 return ERR_PTR(-ENOSYS);
5611
5612 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5613 if (udata->outlen && udata->outlen < min_resp_len)
5614 return ERR_PTR(-EINVAL);
5615
5616 dev = to_mdev(pd->device);
5617 switch (init_attr->wq_type) {
5618 case IB_WQT_RQ:
5619 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5620 if (!rwq)
5621 return ERR_PTR(-ENOMEM);
5622 err = prepare_user_rq(pd, init_attr, udata, rwq);
5623 if (err)
5624 goto err;
5625 err = create_rq(rwq, pd, init_attr);
5626 if (err)
5627 goto err_user_rq;
5628 break;
5629 default:
5630 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5631 init_attr->wq_type);
5632 return ERR_PTR(-EINVAL);
5633 }
5634
350d0e4c 5635 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5636 rwq->ibwq.state = IB_WQS_RESET;
5637 if (udata->outlen) {
5638 resp.response_length = offsetof(typeof(resp), response_length) +
5639 sizeof(resp.response_length);
5640 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5641 if (err)
5642 goto err_copy;
5643 }
5644
350d0e4c
YH		 5645 rwq->core_qp.event = mlx5_ib_wq_event;
5646 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5647 return &rwq->ibwq;
5648
5649err_copy:
350d0e4c 5650 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5651err_user_rq:
fe248c3a 5652 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5653err:
5654 kfree(rwq);
5655 return ERR_PTR(err);
5656}
5657
5658int mlx5_ib_destroy_wq(struct ib_wq *wq)
5659{
5660 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5661 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5662
350d0e4c 5663 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5664 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5665 kfree(rwq);
5666
5667 return 0;
5668}
5669
c5f90929
YH		 5670struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5671 struct ib_rwq_ind_table_init_attr *init_attr,
5672 struct ib_udata *udata)
5673{
5674 struct mlx5_ib_dev *dev = to_mdev(device);
5675 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5676 int sz = 1 << init_attr->log_ind_tbl_size;
5677 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5678 size_t min_resp_len;
5679 int inlen;
5680 int err;
5681 int i;
5682 u32 *in;
5683 void *rqtc;
5684
5685 if (udata->inlen > 0 &&
5686 !ib_is_udata_cleared(udata, 0,
5687 udata->inlen))
5688 return ERR_PTR(-EOPNOTSUPP);
5689
efd7f400
MG		 5690 if (init_attr->log_ind_tbl_size >
5691 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5692 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5693 init_attr->log_ind_tbl_size,
5694 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5695 return ERR_PTR(-EINVAL);
5696 }
5697
c5f90929
YH		 5698 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5699 if (udata->outlen && udata->outlen < min_resp_len)
5700 return ERR_PTR(-EINVAL);
5701
5702 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5703 if (!rwq_ind_tbl)
5704 return ERR_PTR(-ENOMEM);
5705
5706 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5707 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5708 if (!in) {
5709 err = -ENOMEM;
5710 goto err;
5711 }
5712
5713 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5714
5715 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5716 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5717
5718 for (i = 0; i < sz; i++)
5719 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5720
5deba86e
YH		 5721 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5722 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5723
c5f90929
YH		 5724 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5725 kvfree(in);
5726
5727 if (err)
5728 goto err;
5729
5730 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5731 if (udata->outlen) {
5732 resp.response_length = offsetof(typeof(resp), response_length) +
5733 sizeof(resp.response_length);
5734 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5735 if (err)
5736 goto err_copy;
5737 }
5738
5739 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5740
5741err_copy:
5deba86e 5742 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5743err:
5744 kfree(rwq_ind_tbl);
5745 return ERR_PTR(err);
5746}
5747
5748int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5749{
5750 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5751 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5752
5deba86e 5753 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5754
5755 kfree(rwq_ind_tbl);
5756 return 0;
5757}
5758
79b20a6c
YH		 5759int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5760 u32 wq_attr_mask, struct ib_udata *udata)
5761{
5762 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5763 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5764 struct mlx5_ib_modify_wq ucmd = {};
5765 size_t required_cmd_sz;
5766 int curr_wq_state;
5767 int wq_state;
5768 int inlen;
5769 int err;
5770 void *rqc;
5771 void *in;
5772
5773 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5774 if (udata->inlen < required_cmd_sz)
5775 return -EINVAL;
5776
5777 if (udata->inlen > sizeof(ucmd) &&
5778 !ib_is_udata_cleared(udata, sizeof(ucmd),
5779 udata->inlen - sizeof(ucmd)))
5780 return -EOPNOTSUPP;
5781
5782 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5783 return -EFAULT;
5784
5785 if (ucmd.comp_mask || ucmd.reserved)
5786 return -EOPNOTSUPP;
5787
5788 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5789 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5790 if (!in)
5791 return -ENOMEM;
5792
5793 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5794
5795 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5796 wq_attr->curr_wq_state : wq->state;
5797 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5798 wq_attr->wq_state : curr_wq_state;
5799 if (curr_wq_state == IB_WQS_ERR)
5800 curr_wq_state = MLX5_RQC_STATE_ERR;
5801 if (wq_state == IB_WQS_ERR)
5802 wq_state = MLX5_RQC_STATE_ERR;
5803 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 5804 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 5805 MLX5_SET(rqc, rqc, state, wq_state);
5806
b1f74a84
NO		 5807 if (wq_attr_mask & IB_WQ_FLAGS) {
5808 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5809 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5810 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5811 mlx5_ib_dbg(dev, "VLAN offloads are not "
5812 "supported\n");
5813 err = -EOPNOTSUPP;
5814 goto out;
5815 }
5816 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5817 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5818 MLX5_SET(rqc, rqc, vsd,
5819 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5820 }
b1383aa6
NO		 5821
5822 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5823 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5824 err = -EOPNOTSUPP;
5825 goto out;
5826 }
b1f74a84
NO		 5827 }
5828
23a6964e
MD		 5829 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5830 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5831 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5832 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5833 MLX5_SET(rqc, rqc, counter_set_id,
5834 dev->port->cnts.set_id);
23a6964e 5835 } else
5a738b5d
JG		 5836 dev_info_once(
5837 &dev->ib_dev.dev,
5838 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 5839 }
5840
350d0e4c 5841 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5842 if (!err)
5843 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5844
b1f74a84
NO		 5845out:
5846 kvfree(in);
79b20a6c
YH		 5847 return err;
5848}
d0e84c0a
YH		 5849
5850struct mlx5_ib_drain_cqe {
5851 struct ib_cqe cqe;
5852 struct completion done;
5853};
5854
5855static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5856{
5857 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5858 struct mlx5_ib_drain_cqe,
5859 cqe);
5860
5861 complete(&cqe->done);
5862}
5863
5864/* This function returns only once the drained WR was completed */
5865static void handle_drain_completion(struct ib_cq *cq,
5866 struct mlx5_ib_drain_cqe *sdrain,
5867 struct mlx5_ib_dev *dev)
5868{
5869 struct mlx5_core_dev *mdev = dev->mdev;
5870
5871 if (cq->poll_ctx == IB_POLL_DIRECT) {
5872 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5873 ib_process_cq_direct(cq, -1);
5874 return;
5875 }
5876
5877 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5878 struct mlx5_ib_cq *mcq = to_mcq(cq);
5879 bool triggered = false;
5880 unsigned long flags;
5881
5882 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5883 /* Make sure that the CQ handler won't run if wasn't run yet */
5884 if (!mcq->mcq.reset_notify_added)
5885 mcq->mcq.reset_notify_added = 1;
5886 else
5887 triggered = true;
5888 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5889
5890 if (triggered) {
5891 /* Wait for any scheduled/running task to be ended */
5892 switch (cq->poll_ctx) {
5893 case IB_POLL_SOFTIRQ:
5894 irq_poll_disable(&cq->iop);
5895 irq_poll_enable(&cq->iop);
5896 break;
5897 case IB_POLL_WORKQUEUE:
5898 cancel_work_sync(&cq->work);
5899 break;
5900 default:
5901 WARN_ON_ONCE(1);
5902 }
5903 }
5904
5905 /* Run the CQ handler - this makes sure that the drain WR will
5906 * be processed if wasn't processed yet.
5907 */
5908 mcq->mcq.comp(&mcq->mcq);
5909 }
5910
5911 wait_for_completion(&sdrain->done);
5912}
5913
5914void mlx5_ib_drain_sq(struct ib_qp *qp)
5915{
5916 struct ib_cq *cq = qp->send_cq;
5917 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5918 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 5919 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 5920 struct ib_rdma_wr swr = {
5921 .wr = {
5922 .next = NULL,
5923 { .wr_cqe = &sdrain.cqe, },
5924 .opcode = IB_WR_RDMA_WRITE,
5925 },
5926 };
5927 int ret;
5928 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5929 struct mlx5_core_dev *mdev = dev->mdev;
5930
5931 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5932 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5933 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5934 return;
5935 }
5936
5937 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5938 init_completion(&sdrain.done);
5939
5940 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5941 if (ret) {
5942 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5943 return;
5944 }
5945
5946 handle_drain_completion(cq, &sdrain, dev);
5947}
5948
5949void mlx5_ib_drain_rq(struct ib_qp *qp)
5950{
5951 struct ib_cq *cq = qp->recv_cq;
5952 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5953 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 5954 struct ib_recv_wr rwr = {};
5955 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 5956 int ret;
5957 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5958 struct mlx5_core_dev *mdev = dev->mdev;
5959
5960 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5961 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5962 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5963 return;
5964 }
5965
5966 rwr.wr_cqe = &rdrain.cqe;
5967 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5968 init_completion(&rdrain.done);
5969
5970 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5971 if (ret) {
5972 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5973 return;
5974 }
5975
5976 handle_drain_completion(cq, &rdrain, dev);
5977}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git