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IB/mlx5: Refactor raw packet QP modify function
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97 79
0680efa2
AV		 80struct mlx5_modify_raw_qp_param {
81 u16 operation;
82};
83
89ea94a7
MG		 84static void get_cqs(enum ib_qp_type qp_type,
85 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
86 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
87
e126ba97
EC		 88static int is_qp0(enum ib_qp_type qp_type)
89{
90 return qp_type == IB_QPT_SMI;
91}
92
e126ba97
EC		 93static int is_sqp(enum ib_qp_type qp_type)
94{
95 return is_qp0(qp_type) || is_qp1(qp_type);
96}
97
98static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99{
100 return mlx5_buf_offset(&qp->buf, offset);
101}
102
103static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104{
105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106}
107
108void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109{
110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111}
112
c1395a2a
HE		 113/**
114 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
115 *
116 * @qp: QP to copy from.
117 * @send: copy from the send queue when non-zero, use the receive queue
118 * otherwise.
119 * @wqe_index: index to start copying from. For send work queues, the
120 * wqe_index is in units of MLX5_SEND_WQE_BB.
121 * For receive work queue, it is the number of work queue
122 * element in the queue.
123 * @buffer: destination buffer.
124 * @length: maximum number of bytes to copy.
125 *
126 * Copies at least a single WQE, but may copy more data.
127 *
128 * Return: the number of bytes copied, or an error code.
129 */
130int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 131 void *buffer, u32 length,
132 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 133{
134 struct ib_device *ibdev = qp->ibqp.device;
135 struct mlx5_ib_dev *dev = to_mdev(ibdev);
136 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
137 size_t offset;
138 size_t wq_end;
19098df2 139 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 140 u32 first_copy_length;
141 int wqe_length;
142 int ret;
143
144 if (wq->wqe_cnt == 0) {
145 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
146 qp->ibqp.qp_type);
147 return -EINVAL;
148 }
149
150 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
151 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
152
153 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
154 return -EINVAL;
155
156 if (offset > umem->length ||
157 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
158 return -EINVAL;
159
160 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
161 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
162 if (ret)
163 return ret;
164
165 if (send) {
166 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
167 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
168
169 wqe_length = ds * MLX5_WQE_DS_UNITS;
170 } else {
171 wqe_length = 1 << wq->wqe_shift;
172 }
173
174 if (wqe_length <= first_copy_length)
175 return first_copy_length;
176
177 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
178 wqe_length - first_copy_length);
179 if (ret)
180 return ret;
181
182 return wqe_length;
183}
184
e126ba97
EC		 185static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
186{
187 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
188 struct ib_event event;
189
19098df2 190 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
191 /* This event is only valid for trans_qps */
192 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
193 }
e126ba97
EC		 194
195 if (ibqp->event_handler) {
196 event.device = ibqp->device;
197 event.element.qp = ibqp;
198 switch (type) {
199 case MLX5_EVENT_TYPE_PATH_MIG:
200 event.event = IB_EVENT_PATH_MIG;
201 break;
202 case MLX5_EVENT_TYPE_COMM_EST:
203 event.event = IB_EVENT_COMM_EST;
204 break;
205 case MLX5_EVENT_TYPE_SQ_DRAINED:
206 event.event = IB_EVENT_SQ_DRAINED;
207 break;
208 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
209 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
210 break;
211 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
212 event.event = IB_EVENT_QP_FATAL;
213 break;
214 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
215 event.event = IB_EVENT_PATH_MIG_ERR;
216 break;
217 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
218 event.event = IB_EVENT_QP_REQ_ERR;
219 break;
220 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
221 event.event = IB_EVENT_QP_ACCESS_ERR;
222 break;
223 default:
224 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
225 return;
226 }
227
228 ibqp->event_handler(&event, ibqp->qp_context);
229 }
230}
231
232static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
233 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
234{
235 int wqe_size;
236 int wq_size;
237
238 /* Sanity check RQ size before proceeding */
938fe83c 239 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 240 return -EINVAL;
241
242 if (!has_rq) {
243 qp->rq.max_gs = 0;
244 qp->rq.wqe_cnt = 0;
245 qp->rq.wqe_shift = 0;
0540d814
NO		 246 cap->max_recv_wr = 0;
247 cap->max_recv_sge = 0;
e126ba97
EC		 248 } else {
249 if (ucmd) {
250 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
251 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
252 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
253 qp->rq.max_post = qp->rq.wqe_cnt;
254 } else {
255 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
256 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
257 wqe_size = roundup_pow_of_two(wqe_size);
258 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
259 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
260 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 261 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 262 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
263 wqe_size,
938fe83c
SM		 264 MLX5_CAP_GEN(dev->mdev,
265 max_wqe_sz_rq));
e126ba97
EC		 266 return -EINVAL;
267 }
268 qp->rq.wqe_shift = ilog2(wqe_size);
269 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
270 qp->rq.max_post = qp->rq.wqe_cnt;
271 }
272 }
273
274 return 0;
275}
276
f0313965 277static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 278{
618af384 279 int size = 0;
e126ba97 280
f0313965 281 switch (attr->qp_type) {
e126ba97 282 case IB_QPT_XRC_INI:
b125a54b 283 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 284 /* fall through */
285 case IB_QPT_RC:
286 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 287 max(sizeof(struct mlx5_wqe_atomic_seg) +
288 sizeof(struct mlx5_wqe_raddr_seg),
289 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
290 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 291 break;
292
b125a54b
EC		 293 case IB_QPT_XRC_TGT:
294 return 0;
295
e126ba97 296 case IB_QPT_UC:
b125a54b 297 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 298 max(sizeof(struct mlx5_wqe_raddr_seg),
299 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
300 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 301 break;
302
303 case IB_QPT_UD:
f0313965
ES		 304 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
305 size += sizeof(struct mlx5_wqe_eth_pad) +
306 sizeof(struct mlx5_wqe_eth_seg);
307 /* fall through */
e126ba97 308 case IB_QPT_SMI:
d16e91da 309 case MLX5_IB_QPT_HW_GSI:
b125a54b 310 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 311 sizeof(struct mlx5_wqe_datagram_seg);
312 break;
313
314 case MLX5_IB_QPT_REG_UMR:
b125a54b 315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 316 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
317 sizeof(struct mlx5_mkey_seg);
318 break;
319
320 default:
321 return -EINVAL;
322 }
323
324 return size;
325}
326
327static int calc_send_wqe(struct ib_qp_init_attr *attr)
328{
329 int inl_size = 0;
330 int size;
331
f0313965 332 size = sq_overhead(attr);
e126ba97
EC		 333 if (size < 0)
334 return size;
335
336 if (attr->cap.max_inline_data) {
337 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
338 attr->cap.max_inline_data;
339 }
340
341 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 342 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
343 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
344 return MLX5_SIG_WQE_SIZE;
345 else
346 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 347}
348
349static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
350 struct mlx5_ib_qp *qp)
351{
352 int wqe_size;
353 int wq_size;
354
355 if (!attr->cap.max_send_wr)
356 return 0;
357
358 wqe_size = calc_send_wqe(attr);
359 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
360 if (wqe_size < 0)
361 return wqe_size;
362
938fe83c 363 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 364 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 365 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 366 return -EINVAL;
367 }
368
f0313965
ES		 369 qp->max_inline_data = wqe_size - sq_overhead(attr) -
370 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 371 attr->cap.max_inline_data = qp->max_inline_data;
372
e1e66cc2
SG		 373 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
374 qp->signature_en = true;
375
e126ba97
EC		 376 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
377 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 378 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 379 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 380 qp->sq.wqe_cnt,
381 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 382 return -ENOMEM;
383 }
e126ba97
EC		 384 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
385 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 386 qp->sq.max_post = wq_size / wqe_size;
387 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 388
389 return wq_size;
390}
391
392static int set_user_buf_size(struct mlx5_ib_dev *dev,
393 struct mlx5_ib_qp *qp,
19098df2 394 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 395 struct mlx5_ib_qp_base *base,
396 struct ib_qp_init_attr *attr)
e126ba97
EC		 397{
398 int desc_sz = 1 << qp->sq.wqe_shift;
399
938fe83c 400 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 401 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 402 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 403 return -EINVAL;
404 }
405
406 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
407 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
408 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
409 return -EINVAL;
410 }
411
412 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
413
938fe83c 414 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 415 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 416 qp->sq.wqe_cnt,
417 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 418 return -EINVAL;
419 }
420
0fb2ed66 421 if (attr->qp_type == IB_QPT_RAW_PACKET) {
422 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
423 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
424 } else {
425 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
426 (qp->sq.wqe_cnt << 6);
427 }
e126ba97
EC		 428
429 return 0;
430}
431
432static int qp_has_rq(struct ib_qp_init_attr *attr)
433{
434 if (attr->qp_type == IB_QPT_XRC_INI ||
435 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
436 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
437 !attr->cap.max_recv_wr)
438 return 0;
439
440 return 1;
441}
442
c1be5232
EC		 443static int first_med_uuar(void)
444{
445 return 1;
446}
447
448static int next_uuar(int n)
449{
450 n++;
451
452 while (((n % 4) & 2))
453 n++;
454
455 return n;
456}
457
458static int num_med_uuar(struct mlx5_uuar_info *uuari)
459{
460 int n;
461
462 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
463 uuari->num_low_latency_uuars - 1;
464
465 return n >= 0 ? n : 0;
466}
467
468static int max_uuari(struct mlx5_uuar_info *uuari)
469{
470 return uuari->num_uars * 4;
471}
472
473static int first_hi_uuar(struct mlx5_uuar_info *uuari)
474{
475 int med;
476 int i;
477 int t;
478
479 med = num_med_uuar(uuari);
480 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
481 t++;
482 if (t == med)
483 return next_uuar(i);
484 }
485
486 return 0;
487}
488
e126ba97
EC		 489static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
490{
e126ba97
EC		 491 int i;
492
c1be5232 493 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 494 if (!test_bit(i, uuari->bitmap)) {
495 set_bit(i, uuari->bitmap);
496 uuari->count[i]++;
497 return i;
498 }
499 }
500
501 return -ENOMEM;
502}
503
504static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
505{
c1be5232 506 int minidx = first_med_uuar();
e126ba97
EC		 507 int i;
508
c1be5232 509 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 510 if (uuari->count[i] < uuari->count[minidx])
511 minidx = i;
512 }
513
514 uuari->count[minidx]++;
515 return minidx;
516}
517
518static int alloc_uuar(struct mlx5_uuar_info *uuari,
519 enum mlx5_ib_latency_class lat)
520{
521 int uuarn = -EINVAL;
522
523 mutex_lock(&uuari->lock);
524 switch (lat) {
525 case MLX5_IB_LATENCY_CLASS_LOW:
526 uuarn = 0;
527 uuari->count[uuarn]++;
528 break;
529
530 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 531 if (uuari->ver < 2)
532 uuarn = -ENOMEM;
533 else
534 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 535 break;
536
537 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 538 if (uuari->ver < 2)
539 uuarn = -ENOMEM;
540 else
541 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 542 break;
543
544 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
545 uuarn = 2;
546 break;
547 }
548 mutex_unlock(&uuari->lock);
549
550 return uuarn;
551}
552
553static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
554{
555 clear_bit(uuarn, uuari->bitmap);
556 --uuari->count[uuarn];
557}
558
559static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
560{
561 clear_bit(uuarn, uuari->bitmap);
562 --uuari->count[uuarn];
563}
564
565static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
566{
567 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
568 int high_uuar = nuuars - uuari->num_low_latency_uuars;
569
570 mutex_lock(&uuari->lock);
571 if (uuarn == 0) {
572 --uuari->count[uuarn];
573 goto out;
574 }
575
576 if (uuarn < high_uuar) {
577 free_med_class_uuar(uuari, uuarn);
578 goto out;
579 }
580
581 free_high_class_uuar(uuari, uuarn);
582
583out:
584 mutex_unlock(&uuari->lock);
585}
586
587static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
588{
589 switch (state) {
590 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
591 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
592 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
593 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
594 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
595 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
596 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
597 default: return -1;
598 }
599}
600
601static int to_mlx5_st(enum ib_qp_type type)
602{
603 switch (type) {
604 case IB_QPT_RC: return MLX5_QP_ST_RC;
605 case IB_QPT_UC: return MLX5_QP_ST_UC;
606 case IB_QPT_UD: return MLX5_QP_ST_UD;
607 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
608 case IB_QPT_XRC_INI:
609 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
610 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 611 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 612 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 613 case IB_QPT_RAW_PACKET:
0fb2ed66 614 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 615 case IB_QPT_MAX:
616 default: return -EINVAL;
617 }
618}
619
89ea94a7
MG		 620static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
621 struct mlx5_ib_cq *recv_cq);
622static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
623 struct mlx5_ib_cq *recv_cq);
624
e126ba97
EC		 625static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
626{
627 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
628}
629
19098df2 630static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
631 struct ib_pd *pd,
632 unsigned long addr, size_t size,
633 struct ib_umem **umem,
634 int *npages, int *page_shift, int *ncont,
635 u32 *offset)
636{
637 int err;
638
639 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
640 if (IS_ERR(*umem)) {
641 mlx5_ib_dbg(dev, "umem_get failed\n");
642 return PTR_ERR(*umem);
643 }
644
645 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
646
647 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
648 if (err) {
649 mlx5_ib_warn(dev, "bad offset\n");
650 goto err_umem;
651 }
652
653 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
654 addr, size, *npages, *page_shift, *ncont, *offset);
655
656 return 0;
657
658err_umem:
659 ib_umem_release(*umem);
660 *umem = NULL;
661
662 return err;
663}
664
79b20a6c
YH		 665static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
666{
667 struct mlx5_ib_ucontext *context;
668
669 context = to_mucontext(pd->uobject->context);
670 mlx5_ib_db_unmap_user(context, &rwq->db);
671 if (rwq->umem)
672 ib_umem_release(rwq->umem);
673}
674
675static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
676 struct mlx5_ib_rwq *rwq,
677 struct mlx5_ib_create_wq *ucmd)
678{
679 struct mlx5_ib_ucontext *context;
680 int page_shift = 0;
681 int npages;
682 u32 offset = 0;
683 int ncont = 0;
684 int err;
685
686 if (!ucmd->buf_addr)
687 return -EINVAL;
688
689 context = to_mucontext(pd->uobject->context);
690 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
691 rwq->buf_size, 0, 0);
692 if (IS_ERR(rwq->umem)) {
693 mlx5_ib_dbg(dev, "umem_get failed\n");
694 err = PTR_ERR(rwq->umem);
695 return err;
696 }
697
698 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
699 &ncont, NULL);
700 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
701 &rwq->rq_page_offset);
702 if (err) {
703 mlx5_ib_warn(dev, "bad offset\n");
704 goto err_umem;
705 }
706
707 rwq->rq_num_pas = ncont;
708 rwq->page_shift = page_shift;
709 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
710 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
711
712 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
713 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
714 npages, page_shift, ncont, offset);
715
716 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
717 if (err) {
718 mlx5_ib_dbg(dev, "map failed\n");
719 goto err_umem;
720 }
721
722 rwq->create_type = MLX5_WQ_USER;
723 return 0;
724
725err_umem:
726 ib_umem_release(rwq->umem);
727 return err;
728}
729
e126ba97
EC		 730static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
731 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 732 struct ib_qp_init_attr *attr,
09a7d9ec 733 u32 **in,
19098df2 734 struct mlx5_ib_create_qp_resp *resp, int *inlen,
735 struct mlx5_ib_qp_base *base)
e126ba97
EC		 736{
737 struct mlx5_ib_ucontext *context;
738 struct mlx5_ib_create_qp ucmd;
19098df2 739 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 740 int page_shift = 0;
e126ba97
EC		 741 int uar_index;
742 int npages;
9e9c47d0 743 u32 offset = 0;
e126ba97 744 int uuarn;
9e9c47d0 745 int ncont = 0;
09a7d9ec
SM		 746 __be64 *pas;
747 void *qpc;
e126ba97
EC		 748 int err;
749
750 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
751 if (err) {
752 mlx5_ib_dbg(dev, "copy failed\n");
753 return err;
754 }
755
756 context = to_mucontext(pd->uobject->context);
757 /*
758 * TBD: should come from the verbs when we have the API
759 */
051f2630
LR		 760 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
761 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
762 uuarn = MLX5_CROSS_CHANNEL_UUAR;
763 else {
764 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 765 if (uuarn < 0) {
051f2630
LR		 766 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
767 mlx5_ib_dbg(dev, "reverting to medium latency\n");
768 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 769 if (uuarn < 0) {
051f2630
LR		 770 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
771 mlx5_ib_dbg(dev, "reverting to high latency\n");
772 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
773 if (uuarn < 0) {
774 mlx5_ib_warn(dev, "uuar allocation failed\n");
775 return uuarn;
776 }
c1be5232 777 }
e126ba97
EC		 778 }
779 }
780
781 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
782 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
783
48fea837
HE		 784 qp->rq.offset = 0;
785 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
786 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
787
0fb2ed66 788 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 789 if (err)
790 goto err_uuar;
791
19098df2 792 if (ucmd.buf_addr && ubuffer->buf_size) {
793 ubuffer->buf_addr = ucmd.buf_addr;
794 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
795 ubuffer->buf_size,
796 &ubuffer->umem, &npages, &page_shift,
797 &ncont, &offset);
798 if (err)
9e9c47d0 799 goto err_uuar;
9e9c47d0 800 } else {
19098df2 801 ubuffer->umem = NULL;
e126ba97 802 }
e126ba97 803
09a7d9ec
SM		 804 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
805 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 806 *in = mlx5_vzalloc(*inlen);
807 if (!*in) {
808 err = -ENOMEM;
809 goto err_umem;
810 }
09a7d9ec
SM		 811
812 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 813 if (ubuffer->umem)
09a7d9ec
SM		 814 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
815
816 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
817
818 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
819 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 820
09a7d9ec 821 MLX5_SET(qpc, qpc, uar_page, uar_index);
e126ba97
EC		 822 resp->uuar_index = uuarn;
823 qp->uuarn = uuarn;
824
825 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
826 if (err) {
827 mlx5_ib_dbg(dev, "map failed\n");
828 goto err_free;
829 }
830
831 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
832 if (err) {
833 mlx5_ib_dbg(dev, "copy failed\n");
834 goto err_unmap;
835 }
836 qp->create_type = MLX5_QP_USER;
837
838 return 0;
839
840err_unmap:
841 mlx5_ib_db_unmap_user(context, &qp->db);
842
843err_free:
479163f4 844 kvfree(*in);
e126ba97
EC		 845
846err_umem:
19098df2 847 if (ubuffer->umem)
848 ib_umem_release(ubuffer->umem);
e126ba97
EC		 849
850err_uuar:
851 free_uuar(&context->uuari, uuarn);
852 return err;
853}
854
19098df2 855static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
856 struct mlx5_ib_qp_base *base)
e126ba97
EC		 857{
858 struct mlx5_ib_ucontext *context;
859
860 context = to_mucontext(pd->uobject->context);
861 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 862 if (base->ubuffer.umem)
863 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 864 free_uuar(&context->uuari, qp->uuarn);
865}
866
867static int create_kernel_qp(struct mlx5_ib_dev *dev,
868 struct ib_qp_init_attr *init_attr,
869 struct mlx5_ib_qp *qp,
09a7d9ec 870 u32 **in, int *inlen,
19098df2 871 struct mlx5_ib_qp_base *base)
e126ba97
EC		 872{
873 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
874 struct mlx5_uuar_info *uuari;
875 int uar_index;
09a7d9ec 876 void *qpc;
e126ba97
EC		 877 int uuarn;
878 int err;
879
9603b61d 880 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 881 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
882 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 883 IB_QP_CREATE_IPOIB_UD_LSO |
884 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 885 return -EINVAL;
e126ba97
EC		 886
887 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
888 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
889
890 uuarn = alloc_uuar(uuari, lc);
891 if (uuarn < 0) {
892 mlx5_ib_dbg(dev, "\n");
893 return -ENOMEM;
894 }
895
896 qp->bf = &uuari->bfs[uuarn];
897 uar_index = qp->bf->uar->index;
898
899 err = calc_sq_size(dev, init_attr, qp);
900 if (err < 0) {
901 mlx5_ib_dbg(dev, "err %d\n", err);
902 goto err_uuar;
903 }
904
905 qp->rq.offset = 0;
906 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 907 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 908
19098df2 909 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 910 if (err) {
911 mlx5_ib_dbg(dev, "err %d\n", err);
912 goto err_uuar;
913 }
914
915 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 916 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
917 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 918 *in = mlx5_vzalloc(*inlen);
919 if (!*in) {
920 err = -ENOMEM;
921 goto err_buf;
922 }
09a7d9ec
SM		 923
924 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
925 MLX5_SET(qpc, qpc, uar_page, uar_index);
926 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
927
e126ba97 928 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 929 MLX5_SET(qpc, qpc, fre, 1);
930 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 931
b11a4f9c 932 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 933 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 934 qp->flags |= MLX5_IB_QP_SQPN_QP1;
935 }
936
09a7d9ec
SM		 937 mlx5_fill_page_array(&qp->buf,
938 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 939
9603b61d 940 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 941 if (err) {
942 mlx5_ib_dbg(dev, "err %d\n", err);
943 goto err_free;
944 }
945
e126ba97
EC		 946 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
947 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
948 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
949 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
950 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
951
952 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
953 !qp->sq.w_list || !qp->sq.wqe_head) {
954 err = -ENOMEM;
955 goto err_wrid;
956 }
957 qp->create_type = MLX5_QP_KERNEL;
958
959 return 0;
960
961err_wrid:
9603b61d 962 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 963 kfree(qp->sq.wqe_head);
964 kfree(qp->sq.w_list);
965 kfree(qp->sq.wrid);
966 kfree(qp->sq.wr_data);
967 kfree(qp->rq.wrid);
968
969err_free:
479163f4 970 kvfree(*in);
e126ba97
EC		 971
972err_buf:
9603b61d 973 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 974
975err_uuar:
9603b61d 976 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 977 return err;
978}
979
980static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
981{
9603b61d 982 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 983 kfree(qp->sq.wqe_head);
984 kfree(qp->sq.w_list);
985 kfree(qp->sq.wrid);
986 kfree(qp->sq.wr_data);
987 kfree(qp->rq.wrid);
9603b61d
JM		 988 mlx5_buf_free(dev->mdev, &qp->buf);
989 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 990}
991
09a7d9ec 992static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 993{
994 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
995 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 996 return MLX5_SRQ_RQ;
e126ba97 997 else if (!qp->has_rq)
09a7d9ec 998 return MLX5_ZERO_LEN_RQ;
e126ba97 999 else
09a7d9ec 1000 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1001}
1002
1003static int is_connected(enum ib_qp_type qp_type)
1004{
1005 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1006 return 1;
1007
1008 return 0;
1009}
1010
0fb2ed66 1011static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1012 struct mlx5_ib_sq *sq, u32 tdn)
1013{
c4f287c4 1014 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1015 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1016
0fb2ed66 1017 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1018 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1019}
1020
1021static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1022 struct mlx5_ib_sq *sq)
1023{
1024 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1025}
1026
1027static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1028 struct mlx5_ib_sq *sq, void *qpin,
1029 struct ib_pd *pd)
1030{
1031 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1032 __be64 *pas;
1033 void *in;
1034 void *sqc;
1035 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1036 void *wq;
1037 int inlen;
1038 int err;
1039 int page_shift = 0;
1040 int npages;
1041 int ncont = 0;
1042 u32 offset = 0;
1043
1044 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1045 &sq->ubuffer.umem, &npages, &page_shift,
1046 &ncont, &offset);
1047 if (err)
1048 return err;
1049
1050 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1051 in = mlx5_vzalloc(inlen);
1052 if (!in) {
1053 err = -ENOMEM;
1054 goto err_umem;
1055 }
1056
1057 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1058 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1059 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1060 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1061 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1062 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1063 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1064
1065 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1066 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1067 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1068 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1069 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1070 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1071 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1072 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1073 MLX5_SET(wq, wq, page_offset, offset);
1074
1075 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1076 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1077
1078 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1079
1080 kvfree(in);
1081
1082 if (err)
1083 goto err_umem;
1084
1085 return 0;
1086
1087err_umem:
1088 ib_umem_release(sq->ubuffer.umem);
1089 sq->ubuffer.umem = NULL;
1090
1091 return err;
1092}
1093
1094static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1095 struct mlx5_ib_sq *sq)
1096{
1097 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1098 ib_umem_release(sq->ubuffer.umem);
1099}
1100
1101static int get_rq_pas_size(void *qpc)
1102{
1103 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1104 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1105 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1106 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1107 u32 po_quanta = 1 << (log_page_size - 6);
1108 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1109 u32 page_size = 1 << log_page_size;
1110 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1111 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1112
1113 return rq_num_pas * sizeof(u64);
1114}
1115
1116static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1117 struct mlx5_ib_rq *rq, void *qpin)
1118{
358e42ea 1119 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1120 __be64 *pas;
1121 __be64 *qp_pas;
1122 void *in;
1123 void *rqc;
1124 void *wq;
1125 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1126 int inlen;
1127 int err;
1128 u32 rq_pas_size = get_rq_pas_size(qpc);
1129
1130 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1131 in = mlx5_vzalloc(inlen);
1132 if (!in)
1133 return -ENOMEM;
1134
1135 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1136 MLX5_SET(rqc, rqc, vsd, 1);
1137 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1138 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1139 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1140 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1141 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1142
358e42ea
MD		 1143 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1144 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1145
0fb2ed66 1146 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1147 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1148 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1149 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1150 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1151 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1152 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1153 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1154 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1155 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1156
1157 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1158 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1159 memcpy(pas, qp_pas, rq_pas_size);
1160
1161 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1162
1163 kvfree(in);
1164
1165 return err;
1166}
1167
1168static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1169 struct mlx5_ib_rq *rq)
1170{
1171 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1172}
1173
1174static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1175 struct mlx5_ib_rq *rq, u32 tdn)
1176{
1177 u32 *in;
1178 void *tirc;
1179 int inlen;
1180 int err;
1181
1182 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1183 in = mlx5_vzalloc(inlen);
1184 if (!in)
1185 return -ENOMEM;
1186
1187 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1188 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1189 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1190 MLX5_SET(tirc, tirc, transport_domain, tdn);
1191
1192 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1193
1194 kvfree(in);
1195
1196 return err;
1197}
1198
1199static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1200 struct mlx5_ib_rq *rq)
1201{
1202 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1203}
1204
1205static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1206 u32 *in,
0fb2ed66 1207 struct ib_pd *pd)
1208{
1209 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1210 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1211 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1212 struct ib_uobject *uobj = pd->uobject;
1213 struct ib_ucontext *ucontext = uobj->context;
1214 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1215 int err;
1216 u32 tdn = mucontext->tdn;
1217
1218 if (qp->sq.wqe_cnt) {
1219 err = create_raw_packet_qp_tis(dev, sq, tdn);
1220 if (err)
1221 return err;
1222
1223 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1224 if (err)
1225 goto err_destroy_tis;
1226
1227 sq->base.container_mibqp = qp;
1228 }
1229
1230 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1231 rq->base.container_mibqp = qp;
1232
0fb2ed66 1233 err = create_raw_packet_qp_rq(dev, rq, in);
1234 if (err)
1235 goto err_destroy_sq;
1236
0fb2ed66 1237
1238 err = create_raw_packet_qp_tir(dev, rq, tdn);
1239 if (err)
1240 goto err_destroy_rq;
1241 }
1242
1243 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1244 rq->base.mqp.qpn;
1245
1246 return 0;
1247
1248err_destroy_rq:
1249 destroy_raw_packet_qp_rq(dev, rq);
1250err_destroy_sq:
1251 if (!qp->sq.wqe_cnt)
1252 return err;
1253 destroy_raw_packet_qp_sq(dev, sq);
1254err_destroy_tis:
1255 destroy_raw_packet_qp_tis(dev, sq);
1256
1257 return err;
1258}
1259
1260static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1261 struct mlx5_ib_qp *qp)
1262{
1263 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1264 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1265 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1266
1267 if (qp->rq.wqe_cnt) {
1268 destroy_raw_packet_qp_tir(dev, rq);
1269 destroy_raw_packet_qp_rq(dev, rq);
1270 }
1271
1272 if (qp->sq.wqe_cnt) {
1273 destroy_raw_packet_qp_sq(dev, sq);
1274 destroy_raw_packet_qp_tis(dev, sq);
1275 }
1276}
1277
1278static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1279 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1280{
1281 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1282 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1283
1284 sq->sq = &qp->sq;
1285 rq->rq = &qp->rq;
1286 sq->doorbell = &qp->db;
1287 rq->doorbell = &qp->db;
1288}
1289
28d61370
YH		 1290static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1291{
1292 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1293}
1294
1295static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1296 struct ib_pd *pd,
1297 struct ib_qp_init_attr *init_attr,
1298 struct ib_udata *udata)
1299{
1300 struct ib_uobject *uobj = pd->uobject;
1301 struct ib_ucontext *ucontext = uobj->context;
1302 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1303 struct mlx5_ib_create_qp_resp resp = {};
1304 int inlen;
1305 int err;
1306 u32 *in;
1307 void *tirc;
1308 void *hfso;
1309 u32 selected_fields = 0;
1310 size_t min_resp_len;
1311 u32 tdn = mucontext->tdn;
1312 struct mlx5_ib_create_qp_rss ucmd = {};
1313 size_t required_cmd_sz;
1314
1315 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1316 return -EOPNOTSUPP;
1317
1318 if (init_attr->create_flags || init_attr->send_cq)
1319 return -EINVAL;
1320
1321 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1322 if (udata->outlen < min_resp_len)
1323 return -EINVAL;
1324
1325 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1326 if (udata->inlen < required_cmd_sz) {
1327 mlx5_ib_dbg(dev, "invalid inlen\n");
1328 return -EINVAL;
1329 }
1330
1331 if (udata->inlen > sizeof(ucmd) &&
1332 !ib_is_udata_cleared(udata, sizeof(ucmd),
1333 udata->inlen - sizeof(ucmd))) {
1334 mlx5_ib_dbg(dev, "inlen is not supported\n");
1335 return -EOPNOTSUPP;
1336 }
1337
1338 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1339 mlx5_ib_dbg(dev, "copy failed\n");
1340 return -EFAULT;
1341 }
1342
1343 if (ucmd.comp_mask) {
1344 mlx5_ib_dbg(dev, "invalid comp mask\n");
1345 return -EOPNOTSUPP;
1346 }
1347
1348 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1349 mlx5_ib_dbg(dev, "invalid reserved\n");
1350 return -EOPNOTSUPP;
1351 }
1352
1353 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1354 if (err) {
1355 mlx5_ib_dbg(dev, "copy failed\n");
1356 return -EINVAL;
1357 }
1358
1359 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1360 in = mlx5_vzalloc(inlen);
1361 if (!in)
1362 return -ENOMEM;
1363
1364 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1365 MLX5_SET(tirc, tirc, disp_type,
1366 MLX5_TIRC_DISP_TYPE_INDIRECT);
1367 MLX5_SET(tirc, tirc, indirect_table,
1368 init_attr->rwq_ind_tbl->ind_tbl_num);
1369 MLX5_SET(tirc, tirc, transport_domain, tdn);
1370
1371 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1372 switch (ucmd.rx_hash_function) {
1373 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1374 {
1375 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1376 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1377
1378 if (len != ucmd.rx_key_len) {
1379 err = -EINVAL;
1380 goto err;
1381 }
1382
1383 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1384 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1385 memcpy(rss_key, ucmd.rx_hash_key, len);
1386 break;
1387 }
1388 default:
1389 err = -EOPNOTSUPP;
1390 goto err;
1391 }
1392
1393 if (!ucmd.rx_hash_fields_mask) {
1394 /* special case when this TIR serves as steering entry without hashing */
1395 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1396 goto create_tir;
1397 err = -EINVAL;
1398 goto err;
1399 }
1400
1401 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1402 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1403 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1404 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1405 err = -EINVAL;
1406 goto err;
1407 }
1408
1409 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1410 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1411 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1413 MLX5_L3_PROT_TYPE_IPV4);
1414 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1415 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1416 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1417 MLX5_L3_PROT_TYPE_IPV6);
1418
1419 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1420 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1421 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1422 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1423 err = -EINVAL;
1424 goto err;
1425 }
1426
1427 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1428 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1429 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1430 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1431 MLX5_L4_PROT_TYPE_TCP);
1432 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1433 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1434 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1435 MLX5_L4_PROT_TYPE_UDP);
1436
1437 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1439 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1440
1441 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1442 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1443 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1444
1445 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1447 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1448
1449 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1450 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1451 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1452
1453 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1454
1455create_tir:
1456 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1457
1458 if (err)
1459 goto err;
1460
1461 kvfree(in);
1462 /* qpn is reserved for that QP */
1463 qp->trans_qp.base.mqp.qpn = 0;
1464 return 0;
1465
1466err:
1467 kvfree(in);
1468 return err;
1469}
1470
e126ba97
EC		 1471static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1472 struct ib_qp_init_attr *init_attr,
1473 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1474{
1475 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1476 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1477 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1478 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1479 struct mlx5_ib_cq *send_cq;
1480 struct mlx5_ib_cq *recv_cq;
1481 unsigned long flags;
cfb5e088 1482 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1483 struct mlx5_ib_create_qp ucmd;
1484 struct mlx5_ib_qp_base *base;
cfb5e088 1485 void *qpc;
09a7d9ec
SM		 1486 u32 *in;
1487 int err;
e126ba97 1488
0fb2ed66 1489 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1490 &qp->raw_packet_qp.rq.base :
1491 &qp->trans_qp.base;
1492
1493 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1494 mlx5_ib_odp_create_qp(qp);
6aec21f6 1495
e126ba97
EC		 1496 mutex_init(&qp->mutex);
1497 spin_lock_init(&qp->sq.lock);
1498 spin_lock_init(&qp->rq.lock);
1499
28d61370
YH		 1500 if (init_attr->rwq_ind_tbl) {
1501 if (!udata)
1502 return -ENOSYS;
1503
1504 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1505 return err;
1506 }
1507
f360d88a 1508 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1509 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1510 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1511 return -EINVAL;
1512 } else {
1513 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1514 }
1515 }
1516
051f2630
LR		 1517 if (init_attr->create_flags &
1518 (IB_QP_CREATE_CROSS_CHANNEL |
1519 IB_QP_CREATE_MANAGED_SEND |
1520 IB_QP_CREATE_MANAGED_RECV)) {
1521 if (!MLX5_CAP_GEN(mdev, cd)) {
1522 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1523 return -EINVAL;
1524 }
1525 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1526 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1527 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1528 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1529 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1530 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1531 }
f0313965
ES		 1532
1533 if (init_attr->qp_type == IB_QPT_UD &&
1534 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1535 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1536 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1537 return -EOPNOTSUPP;
1538 }
1539
358e42ea
MD		 1540 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1541 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1542 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1543 return -EOPNOTSUPP;
1544 }
1545 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1546 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1547 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1548 return -EOPNOTSUPP;
1549 }
1550 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1551 }
1552
e126ba97
EC		 1553 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1554 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1555
1556 if (pd && pd->uobject) {
1557 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1558 mlx5_ib_dbg(dev, "copy failed\n");
1559 return -EFAULT;
1560 }
1561
cfb5e088
HA		 1562 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1563 &ucmd, udata->inlen, &uidx);
1564 if (err)
1565 return err;
1566
e126ba97
EC		 1567 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1568 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1569 } else {
1570 qp->wq_sig = !!wq_signature;
1571 }
1572
1573 qp->has_rq = qp_has_rq(init_attr);
1574 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1575 qp, (pd && pd->uobject) ? &ucmd : NULL);
1576 if (err) {
1577 mlx5_ib_dbg(dev, "err %d\n", err);
1578 return err;
1579 }
1580
1581 if (pd) {
1582 if (pd->uobject) {
938fe83c
SM		 1583 __u32 max_wqes =
1584 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1585 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1586 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1587 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1588 mlx5_ib_dbg(dev, "invalid rq params\n");
1589 return -EINVAL;
1590 }
938fe83c 1591 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1592 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1593 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1594 return -EINVAL;
1595 }
b11a4f9c
HE		 1596 if (init_attr->create_flags &
1597 mlx5_ib_create_qp_sqpn_qp1()) {
1598 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1599 return -EINVAL;
1600 }
0fb2ed66 1601 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1602 &resp, &inlen, base);
e126ba97
EC		 1603 if (err)
1604 mlx5_ib_dbg(dev, "err %d\n", err);
1605 } else {
19098df2 1606 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1607 base);
e126ba97
EC		 1608 if (err)
1609 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1610 }
1611
1612 if (err)
1613 return err;
1614 } else {
09a7d9ec 1615 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1616 if (!in)
1617 return -ENOMEM;
1618
1619 qp->create_type = MLX5_QP_EMPTY;
1620 }
1621
1622 if (is_sqp(init_attr->qp_type))
1623 qp->port = init_attr->port_num;
1624
09a7d9ec
SM		 1625 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1626
1627 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1628 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1629
1630 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1631 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1632 else
09a7d9ec
SM		 1633 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1634
e126ba97
EC		 1635
1636 if (qp->wq_sig)
09a7d9ec 1637 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1638
f360d88a 1639 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1640 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1641
051f2630 1642 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1643 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1644 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1645 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1646 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1647 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1648
e126ba97
EC		 1649 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1650 int rcqe_sz;
1651 int scqe_sz;
1652
1653 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1654 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1655
1656 if (rcqe_sz == 128)
09a7d9ec 1657 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1658 else
09a7d9ec 1659 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1660
1661 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1662 if (scqe_sz == 128)
09a7d9ec 1663 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1664 else
09a7d9ec 1665 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1666 }
1667 }
1668
1669 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1670 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1671 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1672 }
1673
09a7d9ec 1674 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1675
1676 if (qp->sq.wqe_cnt)
09a7d9ec 1677 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1678 else
09a7d9ec 1679 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1680
1681 /* Set default resources */
1682 switch (init_attr->qp_type) {
1683 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1684 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1685 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1686 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1687 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1688 break;
1689 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1690 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1691 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1692 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1693 break;
1694 default:
1695 if (init_attr->srq) {
09a7d9ec
SM		 1696 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1697 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1698 } else {
09a7d9ec
SM		 1699 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1700 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1701 }
1702 }
1703
1704 if (init_attr->send_cq)
09a7d9ec 1705 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1706
1707 if (init_attr->recv_cq)
09a7d9ec 1708 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1709
09a7d9ec 1710 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1711
09a7d9ec
SM		 1712 /* 0xffffff means we ask to work with cqe version 0 */
1713 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1714 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1715
f0313965
ES		 1716 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1717 if (init_attr->qp_type == IB_QPT_UD &&
1718 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1719 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1720 qp->flags |= MLX5_IB_QP_LSO;
1721 }
cfb5e088 1722
0fb2ed66 1723 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1724 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1725 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1726 err = create_raw_packet_qp(dev, qp, in, pd);
1727 } else {
1728 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1729 }
1730
e126ba97
EC		 1731 if (err) {
1732 mlx5_ib_dbg(dev, "create qp failed\n");
1733 goto err_create;
1734 }
1735
479163f4 1736 kvfree(in);
e126ba97 1737
19098df2 1738 base->container_mibqp = qp;
1739 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1740
89ea94a7
MG		 1741 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1742 &send_cq, &recv_cq);
1743 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1744 mlx5_ib_lock_cqs(send_cq, recv_cq);
1745 /* Maintain device to QPs access, needed for further handling via reset
1746 * flow
1747 */
1748 list_add_tail(&qp->qps_list, &dev->qp_list);
1749 /* Maintain CQ to QPs access, needed for further handling via reset flow
1750 */
1751 if (send_cq)
1752 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1753 if (recv_cq)
1754 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1755 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1756 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1757
e126ba97
EC		 1758 return 0;
1759
1760err_create:
1761 if (qp->create_type == MLX5_QP_USER)
19098df2 1762 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1763 else if (qp->create_type == MLX5_QP_KERNEL)
1764 destroy_qp_kernel(dev, qp);
1765
479163f4 1766 kvfree(in);
e126ba97
EC		 1767 return err;
1768}
1769
1770static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1771 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1772{
1773 if (send_cq) {
1774 if (recv_cq) {
1775 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1776 spin_lock(&send_cq->lock);
e126ba97
EC		 1777 spin_lock_nested(&recv_cq->lock,
1778 SINGLE_DEPTH_NESTING);
1779 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1780 spin_lock(&send_cq->lock);
e126ba97
EC		 1781 __acquire(&recv_cq->lock);
1782 } else {
89ea94a7 1783 spin_lock(&recv_cq->lock);
e126ba97
EC		 1784 spin_lock_nested(&send_cq->lock,
1785 SINGLE_DEPTH_NESTING);
1786 }
1787 } else {
89ea94a7 1788 spin_lock(&send_cq->lock);
6a4f139a 1789 __acquire(&recv_cq->lock);
e126ba97
EC		 1790 }
1791 } else if (recv_cq) {
89ea94a7 1792 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1793 __acquire(&send_cq->lock);
1794 } else {
1795 __acquire(&send_cq->lock);
1796 __acquire(&recv_cq->lock);
e126ba97
EC		 1797 }
1798}
1799
1800static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1801 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1802{
1803 if (send_cq) {
1804 if (recv_cq) {
1805 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1806 spin_unlock(&recv_cq->lock);
89ea94a7 1807 spin_unlock(&send_cq->lock);
e126ba97
EC		 1808 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1809 __release(&recv_cq->lock);
89ea94a7 1810 spin_unlock(&send_cq->lock);
e126ba97
EC		 1811 } else {
1812 spin_unlock(&send_cq->lock);
89ea94a7 1813 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1814 }
1815 } else {
6a4f139a 1816 __release(&recv_cq->lock);
89ea94a7 1817 spin_unlock(&send_cq->lock);
e126ba97
EC		 1818 }
1819 } else if (recv_cq) {
6a4f139a 1820 __release(&send_cq->lock);
89ea94a7 1821 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1822 } else {
1823 __release(&recv_cq->lock);
1824 __release(&send_cq->lock);
e126ba97
EC		 1825 }
1826}
1827
1828static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1829{
1830 return to_mpd(qp->ibqp.pd);
1831}
1832
89ea94a7
MG		 1833static void get_cqs(enum ib_qp_type qp_type,
1834 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1835 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1836{
89ea94a7 1837 switch (qp_type) {
e126ba97
EC		 1838 case IB_QPT_XRC_TGT:
1839 *send_cq = NULL;
1840 *recv_cq = NULL;
1841 break;
1842 case MLX5_IB_QPT_REG_UMR:
1843 case IB_QPT_XRC_INI:
89ea94a7 1844 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1845 *recv_cq = NULL;
1846 break;
1847
1848 case IB_QPT_SMI:
d16e91da 1849 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1850 case IB_QPT_RC:
1851 case IB_QPT_UC:
1852 case IB_QPT_UD:
1853 case IB_QPT_RAW_IPV6:
1854 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1855 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1856 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1857 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1858 break;
1859
e126ba97
EC		 1860 case IB_QPT_MAX:
1861 default:
1862 *send_cq = NULL;
1863 *recv_cq = NULL;
1864 break;
1865 }
1866}
1867
ad5f8e96 1868static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
0680efa2 1869 const struct mlx5_modify_raw_qp_param *raw_qp_param);
ad5f8e96 1870
e126ba97
EC		 1871static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1872{
1873 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1874 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1875 unsigned long flags;
e126ba97
EC		 1876 int err;
1877
28d61370
YH		 1878 if (qp->ibqp.rwq_ind_tbl) {
1879 destroy_rss_raw_qp_tir(dev, qp);
1880 return;
1881 }
1882
0fb2ed66 1883 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1884 &qp->raw_packet_qp.rq.base :
1885 &qp->trans_qp.base;
1886
6aec21f6 1887 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1888 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1889 mlx5_ib_qp_disable_pagefaults(qp);
1890 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1891 MLX5_CMD_OP_2RST_QP, 0,
1892 NULL, &base->mqp);
ad5f8e96 1893 } else {
0680efa2
AV		 1894 struct mlx5_modify_raw_qp_param raw_qp_param = {
1895 .operation = MLX5_CMD_OP_2RST_QP
1896 };
1897
1898 err = modify_raw_packet_qp(dev, qp, &raw_qp_param);
ad5f8e96 1899 }
1900 if (err)
427c1e7b 1901 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1902 base->mqp.qpn);
6aec21f6 1903 }
e126ba97 1904
89ea94a7
MG		 1905 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1906 &send_cq, &recv_cq);
1907
1908 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1909 mlx5_ib_lock_cqs(send_cq, recv_cq);
1910 /* del from lists under both locks above to protect reset flow paths */
1911 list_del(&qp->qps_list);
1912 if (send_cq)
1913 list_del(&qp->cq_send_list);
1914
1915 if (recv_cq)
1916 list_del(&qp->cq_recv_list);
e126ba97
EC		 1917
1918 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1919 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1920 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1921 if (send_cq != recv_cq)
19098df2 1922 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1923 NULL);
e126ba97 1924 }
89ea94a7
MG		 1925 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1926 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1927
0fb2ed66 1928 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1929 destroy_raw_packet_qp(dev, qp);
1930 } else {
1931 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1932 if (err)
1933 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1934 base->mqp.qpn);
1935 }
e126ba97 1936
e126ba97
EC		 1937 if (qp->create_type == MLX5_QP_KERNEL)
1938 destroy_qp_kernel(dev, qp);
1939 else if (qp->create_type == MLX5_QP_USER)
19098df2 1940 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1941}
1942
1943static const char *ib_qp_type_str(enum ib_qp_type type)
1944{
1945 switch (type) {
1946 case IB_QPT_SMI:
1947 return "IB_QPT_SMI";
1948 case IB_QPT_GSI:
1949 return "IB_QPT_GSI";
1950 case IB_QPT_RC:
1951 return "IB_QPT_RC";
1952 case IB_QPT_UC:
1953 return "IB_QPT_UC";
1954 case IB_QPT_UD:
1955 return "IB_QPT_UD";
1956 case IB_QPT_RAW_IPV6:
1957 return "IB_QPT_RAW_IPV6";
1958 case IB_QPT_RAW_ETHERTYPE:
1959 return "IB_QPT_RAW_ETHERTYPE";
1960 case IB_QPT_XRC_INI:
1961 return "IB_QPT_XRC_INI";
1962 case IB_QPT_XRC_TGT:
1963 return "IB_QPT_XRC_TGT";
1964 case IB_QPT_RAW_PACKET:
1965 return "IB_QPT_RAW_PACKET";
1966 case MLX5_IB_QPT_REG_UMR:
1967 return "MLX5_IB_QPT_REG_UMR";
1968 case IB_QPT_MAX:
1969 default:
1970 return "Invalid QP type";
1971 }
1972}
1973
1974struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1975 struct ib_qp_init_attr *init_attr,
1976 struct ib_udata *udata)
1977{
1978 struct mlx5_ib_dev *dev;
1979 struct mlx5_ib_qp *qp;
1980 u16 xrcdn = 0;
1981 int err;
1982
1983 if (pd) {
1984 dev = to_mdev(pd->device);
0fb2ed66 1985
1986 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1987 if (!pd->uobject) {
1988 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1989 return ERR_PTR(-EINVAL);
1990 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1991 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1992 return ERR_PTR(-EINVAL);
1993 }
1994 }
09f16cf5
MD		 1995 } else {
1996 /* being cautious here */
1997 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1998 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1999 pr_warn("%s: no PD for transport %s\n", __func__,
2000 ib_qp_type_str(init_attr->qp_type));
2001 return ERR_PTR(-EINVAL);
2002 }
2003 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2004 }
2005
2006 switch (init_attr->qp_type) {
2007 case IB_QPT_XRC_TGT:
2008 case IB_QPT_XRC_INI:
938fe83c 2009 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2010 mlx5_ib_dbg(dev, "XRC not supported\n");
2011 return ERR_PTR(-ENOSYS);
2012 }
2013 init_attr->recv_cq = NULL;
2014 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2015 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2016 init_attr->send_cq = NULL;
2017 }
2018
2019 /* fall through */
0fb2ed66 2020 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2021 case IB_QPT_RC:
2022 case IB_QPT_UC:
2023 case IB_QPT_UD:
2024 case IB_QPT_SMI:
d16e91da 2025 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2026 case MLX5_IB_QPT_REG_UMR:
2027 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2028 if (!qp)
2029 return ERR_PTR(-ENOMEM);
2030
2031 err = create_qp_common(dev, pd, init_attr, udata, qp);
2032 if (err) {
2033 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2034 kfree(qp);
2035 return ERR_PTR(err);
2036 }
2037
2038 if (is_qp0(init_attr->qp_type))
2039 qp->ibqp.qp_num = 0;
2040 else if (is_qp1(init_attr->qp_type))
2041 qp->ibqp.qp_num = 1;
2042 else
19098df2 2043 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2044
2045 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2046 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2047 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 2048 to_mcq(init_attr->send_cq)->mcq.cqn);
2049
19098df2 2050 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2051
2052 break;
2053
d16e91da
HE		 2054 case IB_QPT_GSI:
2055 return mlx5_ib_gsi_create_qp(pd, init_attr);
2056
e126ba97
EC		 2057 case IB_QPT_RAW_IPV6:
2058 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2059 case IB_QPT_MAX:
2060 default:
2061 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2062 init_attr->qp_type);
2063 /* Don't support raw QPs */
2064 return ERR_PTR(-EINVAL);
2065 }
2066
2067 return &qp->ibqp;
2068}
2069
2070int mlx5_ib_destroy_qp(struct ib_qp *qp)
2071{
2072 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2073 struct mlx5_ib_qp *mqp = to_mqp(qp);
2074
d16e91da
HE		 2075 if (unlikely(qp->qp_type == IB_QPT_GSI))
2076 return mlx5_ib_gsi_destroy_qp(qp);
2077
e126ba97
EC		 2078 destroy_qp_common(dev, mqp);
2079
2080 kfree(mqp);
2081
2082 return 0;
2083}
2084
2085static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2086 int attr_mask)
2087{
2088 u32 hw_access_flags = 0;
2089 u8 dest_rd_atomic;
2090 u32 access_flags;
2091
2092 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2093 dest_rd_atomic = attr->max_dest_rd_atomic;
2094 else
19098df2 2095 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2096
2097 if (attr_mask & IB_QP_ACCESS_FLAGS)
2098 access_flags = attr->qp_access_flags;
2099 else
19098df2 2100 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2101
2102 if (!dest_rd_atomic)
2103 access_flags &= IB_ACCESS_REMOTE_WRITE;
2104
2105 if (access_flags & IB_ACCESS_REMOTE_READ)
2106 hw_access_flags |= MLX5_QP_BIT_RRE;
2107 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2108 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2109 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2110 hw_access_flags |= MLX5_QP_BIT_RWE;
2111
2112 return cpu_to_be32(hw_access_flags);
2113}
2114
2115enum {
2116 MLX5_PATH_FLAG_FL = 1 << 0,
2117 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2118 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2119};
2120
2121static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2122{
2123 if (rate == IB_RATE_PORT_CURRENT) {
2124 return 0;
2125 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2126 return -EINVAL;
2127 } else {
2128 while (rate != IB_RATE_2_5_GBPS &&
2129 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2130 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2131 --rate;
2132 }
2133
2134 return rate + MLX5_STAT_RATE_OFFSET;
2135}
2136
75850d0b 2137static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2138 struct mlx5_ib_sq *sq, u8 sl)
2139{
2140 void *in;
2141 void *tisc;
2142 int inlen;
2143 int err;
2144
2145 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2146 in = mlx5_vzalloc(inlen);
2147 if (!in)
2148 return -ENOMEM;
2149
2150 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2151
2152 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2153 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2154
2155 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2156
2157 kvfree(in);
2158
2159 return err;
2160}
2161
2162static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2163 const struct ib_ah_attr *ah,
e126ba97 2164 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2165 u32 path_flags, const struct ib_qp_attr *attr,
2166 bool alt)
e126ba97 2167{
2811ba51 2168 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 2169 int err;
2170
e126ba97 2171 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2172 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2173 attr->pkey_index);
e126ba97 2174
e126ba97 2175 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2176 if (ah->grh.sgid_index >=
2177 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2178 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2179 ah->grh.sgid_index,
2180 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2181 return -EINVAL;
2182 }
2811ba51
AS		 2183 }
2184
2185 if (ll == IB_LINK_LAYER_ETHERNET) {
2186 if (!(ah->ah_flags & IB_AH_GRH))
2187 return -EINVAL;
2188 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2189 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2190 ah->grh.sgid_index);
2191 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2192 } else {
d3ae2bde
NO		 2193 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2194 path->fl_free_ar |=
2195 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2196 path->rlid = cpu_to_be16(ah->dlid);
2197 path->grh_mlid = ah->src_path_bits & 0x7f;
2198 if (ah->ah_flags & IB_AH_GRH)
2199 path->grh_mlid |= 1 << 7;
2200 path->dci_cfi_prio_sl = ah->sl & 0xf;
2201 }
2202
2203 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2204 path->mgid_index = ah->grh.sgid_index;
2205 path->hop_limit = ah->grh.hop_limit;
2206 path->tclass_flowlabel =
2207 cpu_to_be32((ah->grh.traffic_class << 20) |
2208 (ah->grh.flow_label));
2209 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2210 }
2211
2212 err = ib_rate_to_mlx5(dev, ah->static_rate);
2213 if (err < 0)
2214 return err;
2215 path->static_rate = err;
2216 path->port = port;
2217
e126ba97 2218 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2219 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2220
75850d0b 2221 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2222 return modify_raw_packet_eth_prio(dev->mdev,
2223 &qp->raw_packet_qp.sq,
2224 ah->sl & 0xf);
2225
e126ba97
EC		 2226 return 0;
2227}
2228
2229static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2230 [MLX5_QP_STATE_INIT] = {
2231 [MLX5_QP_STATE_INIT] = {
2232 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2233 MLX5_QP_OPTPAR_RAE |
2234 MLX5_QP_OPTPAR_RWE |
2235 MLX5_QP_OPTPAR_PKEY_INDEX |
2236 MLX5_QP_OPTPAR_PRI_PORT,
2237 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2238 MLX5_QP_OPTPAR_PKEY_INDEX |
2239 MLX5_QP_OPTPAR_PRI_PORT,
2240 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2241 MLX5_QP_OPTPAR_Q_KEY |
2242 MLX5_QP_OPTPAR_PRI_PORT,
2243 },
2244 [MLX5_QP_STATE_RTR] = {
2245 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2246 MLX5_QP_OPTPAR_RRE |
2247 MLX5_QP_OPTPAR_RAE |
2248 MLX5_QP_OPTPAR_RWE |
2249 MLX5_QP_OPTPAR_PKEY_INDEX,
2250 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2251 MLX5_QP_OPTPAR_RWE |
2252 MLX5_QP_OPTPAR_PKEY_INDEX,
2253 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2254 MLX5_QP_OPTPAR_Q_KEY,
2255 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2256 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2257 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2258 MLX5_QP_OPTPAR_RRE |
2259 MLX5_QP_OPTPAR_RAE |
2260 MLX5_QP_OPTPAR_RWE |
2261 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2262 },
2263 },
2264 [MLX5_QP_STATE_RTR] = {
2265 [MLX5_QP_STATE_RTS] = {
2266 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2267 MLX5_QP_OPTPAR_RRE |
2268 MLX5_QP_OPTPAR_RAE |
2269 MLX5_QP_OPTPAR_RWE |
2270 MLX5_QP_OPTPAR_PM_STATE |
2271 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2272 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2273 MLX5_QP_OPTPAR_RWE |
2274 MLX5_QP_OPTPAR_PM_STATE,
2275 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2276 },
2277 },
2278 [MLX5_QP_STATE_RTS] = {
2279 [MLX5_QP_STATE_RTS] = {
2280 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2281 MLX5_QP_OPTPAR_RAE |
2282 MLX5_QP_OPTPAR_RWE |
2283 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2284 MLX5_QP_OPTPAR_PM_STATE |
2285 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2286 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2287 MLX5_QP_OPTPAR_PM_STATE |
2288 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2289 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2290 MLX5_QP_OPTPAR_SRQN |
2291 MLX5_QP_OPTPAR_CQN_RCV,
2292 },
2293 },
2294 [MLX5_QP_STATE_SQER] = {
2295 [MLX5_QP_STATE_RTS] = {
2296 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2297 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2298 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2299 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2300 MLX5_QP_OPTPAR_RWE |
2301 MLX5_QP_OPTPAR_RAE |
2302 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2303 },
2304 },
2305};
2306
2307static int ib_nr_to_mlx5_nr(int ib_mask)
2308{
2309 switch (ib_mask) {
2310 case IB_QP_STATE:
2311 return 0;
2312 case IB_QP_CUR_STATE:
2313 return 0;
2314 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2315 return 0;
2316 case IB_QP_ACCESS_FLAGS:
2317 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2318 MLX5_QP_OPTPAR_RAE;
2319 case IB_QP_PKEY_INDEX:
2320 return MLX5_QP_OPTPAR_PKEY_INDEX;
2321 case IB_QP_PORT:
2322 return MLX5_QP_OPTPAR_PRI_PORT;
2323 case IB_QP_QKEY:
2324 return MLX5_QP_OPTPAR_Q_KEY;
2325 case IB_QP_AV:
2326 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2327 MLX5_QP_OPTPAR_PRI_PORT;
2328 case IB_QP_PATH_MTU:
2329 return 0;
2330 case IB_QP_TIMEOUT:
2331 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2332 case IB_QP_RETRY_CNT:
2333 return MLX5_QP_OPTPAR_RETRY_COUNT;
2334 case IB_QP_RNR_RETRY:
2335 return MLX5_QP_OPTPAR_RNR_RETRY;
2336 case IB_QP_RQ_PSN:
2337 return 0;
2338 case IB_QP_MAX_QP_RD_ATOMIC:
2339 return MLX5_QP_OPTPAR_SRA_MAX;
2340 case IB_QP_ALT_PATH:
2341 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2342 case IB_QP_MIN_RNR_TIMER:
2343 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2344 case IB_QP_SQ_PSN:
2345 return 0;
2346 case IB_QP_MAX_DEST_RD_ATOMIC:
2347 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2348 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2349 case IB_QP_PATH_MIG_STATE:
2350 return MLX5_QP_OPTPAR_PM_STATE;
2351 case IB_QP_CAP:
2352 return 0;
2353 case IB_QP_DEST_QPN:
2354 return 0;
2355 }
2356 return 0;
2357}
2358
2359static int ib_mask_to_mlx5_opt(int ib_mask)
2360{
2361 int result = 0;
2362 int i;
2363
2364 for (i = 0; i < 8 * sizeof(int); i++) {
2365 if ((1 << i) & ib_mask)
2366 result |= ib_nr_to_mlx5_nr(1 << i);
2367 }
2368
2369 return result;
2370}
2371
ad5f8e96 2372static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2373 struct mlx5_ib_rq *rq, int new_state)
2374{
2375 void *in;
2376 void *rqc;
2377 int inlen;
2378 int err;
2379
2380 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2381 in = mlx5_vzalloc(inlen);
2382 if (!in)
2383 return -ENOMEM;
2384
2385 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2386
2387 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2388 MLX5_SET(rqc, rqc, state, new_state);
2389
2390 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2391 if (err)
2392 goto out;
2393
2394 rq->state = new_state;
2395
2396out:
2397 kvfree(in);
2398 return err;
2399}
2400
2401static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2402 struct mlx5_ib_sq *sq, int new_state)
2403{
2404 void *in;
2405 void *sqc;
2406 int inlen;
2407 int err;
2408
2409 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2410 in = mlx5_vzalloc(inlen);
2411 if (!in)
2412 return -ENOMEM;
2413
2414 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2415
2416 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2417 MLX5_SET(sqc, sqc, state, new_state);
2418
2419 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2420 if (err)
2421 goto out;
2422
2423 sq->state = new_state;
2424
2425out:
2426 kvfree(in);
2427 return err;
2428}
2429
2430static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
0680efa2 2431 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2432{
2433 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2434 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2435 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2436 int rq_state;
2437 int sq_state;
2438 int err;
2439
0680efa2 2440 switch (raw_qp_param->operation) {
ad5f8e96 2441 case MLX5_CMD_OP_RST2INIT_QP:
2442 rq_state = MLX5_RQC_STATE_RDY;
2443 sq_state = MLX5_SQC_STATE_RDY;
2444 break;
2445 case MLX5_CMD_OP_2ERR_QP:
2446 rq_state = MLX5_RQC_STATE_ERR;
2447 sq_state = MLX5_SQC_STATE_ERR;
2448 break;
2449 case MLX5_CMD_OP_2RST_QP:
2450 rq_state = MLX5_RQC_STATE_RST;
2451 sq_state = MLX5_SQC_STATE_RST;
2452 break;
2453 case MLX5_CMD_OP_INIT2INIT_QP:
2454 case MLX5_CMD_OP_INIT2RTR_QP:
2455 case MLX5_CMD_OP_RTR2RTS_QP:
2456 case MLX5_CMD_OP_RTS2RTS_QP:
2457 /* Nothing to do here... */
2458 return 0;
2459 default:
2460 WARN_ON(1);
2461 return -EINVAL;
2462 }
2463
2464 if (qp->rq.wqe_cnt) {
2465 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2466 if (err)
2467 return err;
2468 }
2469
2470 if (qp->sq.wqe_cnt)
2471 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2472
2473 return 0;
2474}
2475
e126ba97
EC		 2476static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2477 const struct ib_qp_attr *attr, int attr_mask,
2478 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2479{
427c1e7b 2480 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2481 [MLX5_QP_STATE_RST] = {
2482 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2483 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2484 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2485 },
2486 [MLX5_QP_STATE_INIT] = {
2487 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2488 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2489 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2490 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2491 },
2492 [MLX5_QP_STATE_RTR] = {
2493 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2494 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2495 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2496 },
2497 [MLX5_QP_STATE_RTS] = {
2498 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2499 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2500 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2501 },
2502 [MLX5_QP_STATE_SQD] = {
2503 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2504 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2505 },
2506 [MLX5_QP_STATE_SQER] = {
2507 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2508 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2509 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2510 },
2511 [MLX5_QP_STATE_ERR] = {
2512 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2513 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2514 }
2515 };
2516
e126ba97
EC		 2517 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2518 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2519 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2520 struct mlx5_ib_cq *send_cq, *recv_cq;
2521 struct mlx5_qp_context *context;
e126ba97
EC		 2522 struct mlx5_ib_pd *pd;
2523 enum mlx5_qp_state mlx5_cur, mlx5_new;
2524 enum mlx5_qp_optpar optpar;
2525 int sqd_event;
2526 int mlx5_st;
2527 int err;
427c1e7b 2528 u16 op;
e126ba97 2529
1a412fb1
SM		 2530 context = kzalloc(sizeof(*context), GFP_KERNEL);
2531 if (!context)
e126ba97
EC		 2532 return -ENOMEM;
2533
e126ba97 2534 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2535 if (err < 0) {
2536 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2537 goto out;
158abf86 2538 }
e126ba97
EC		 2539
2540 context->flags = cpu_to_be32(err << 16);
2541
2542 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2543 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2544 } else {
2545 switch (attr->path_mig_state) {
2546 case IB_MIG_MIGRATED:
2547 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2548 break;
2549 case IB_MIG_REARM:
2550 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2551 break;
2552 case IB_MIG_ARMED:
2553 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2554 break;
2555 }
2556 }
2557
d16e91da 2558 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2559 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2560 } else if (ibqp->qp_type == IB_QPT_UD ||
2561 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2562 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2563 } else if (attr_mask & IB_QP_PATH_MTU) {
2564 if (attr->path_mtu < IB_MTU_256 ||
2565 attr->path_mtu > IB_MTU_4096) {
2566 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2567 err = -EINVAL;
2568 goto out;
2569 }
938fe83c
SM		 2570 context->mtu_msgmax = (attr->path_mtu << 5) |
2571 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2572 }
2573
2574 if (attr_mask & IB_QP_DEST_QPN)
2575 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2576
2577 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2578 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2579
2580 /* todo implement counter_index functionality */
2581
2582 if (is_sqp(ibqp->qp_type))
2583 context->pri_path.port = qp->port;
2584
2585 if (attr_mask & IB_QP_PORT)
2586 context->pri_path.port = attr->port_num;
2587
2588 if (attr_mask & IB_QP_AV) {
75850d0b 2589 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2590 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2591 attr_mask, 0, attr, false);
e126ba97
EC		 2592 if (err)
2593 goto out;
2594 }
2595
2596 if (attr_mask & IB_QP_TIMEOUT)
2597 context->pri_path.ackto_lt |= attr->timeout << 3;
2598
2599 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2600 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2601 &context->alt_path,
f879ee8d
AS		 2602 attr->alt_port_num,
2603 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2604 0, attr, true);
e126ba97
EC		 2605 if (err)
2606 goto out;
2607 }
2608
2609 pd = get_pd(qp);
89ea94a7
MG		 2610 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2611 &send_cq, &recv_cq);
e126ba97
EC		 2612
2613 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2614 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2615 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2616 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2617
2618 if (attr_mask & IB_QP_RNR_RETRY)
2619 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2620
2621 if (attr_mask & IB_QP_RETRY_CNT)
2622 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2623
2624 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2625 if (attr->max_rd_atomic)
2626 context->params1 |=
2627 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2628 }
2629
2630 if (attr_mask & IB_QP_SQ_PSN)
2631 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2632
2633 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2634 if (attr->max_dest_rd_atomic)
2635 context->params2 |=
2636 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2637 }
2638
2639 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2640 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2641
2642 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2643 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2644
2645 if (attr_mask & IB_QP_RQ_PSN)
2646 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2647
2648 if (attr_mask & IB_QP_QKEY)
2649 context->qkey = cpu_to_be32(attr->qkey);
2650
2651 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2652 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2653
2654 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2655 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2656 sqd_event = 1;
2657 else
2658 sqd_event = 0;
2659
0837e86a
MB		 2660 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2661 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2662 qp->port) - 1;
2663 struct mlx5_ib_port *mibport = &dev->port[port_num];
2664
2665 context->qp_counter_set_usr_page |=
321a9e3e 2666 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
0837e86a
MB		 2667 }
2668
e126ba97
EC		 2669 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2670 context->sq_crq_size |= cpu_to_be16(1 << 4);
2671
b11a4f9c
HE		 2672 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2673 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2674
2675 mlx5_cur = to_mlx5_state(cur_state);
2676 mlx5_new = to_mlx5_state(new_state);
2677 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2678 if (mlx5_st < 0)
e126ba97
EC		 2679 goto out;
2680
6aec21f6
HE		 2681 /* If moving to a reset or error state, we must disable page faults on
2682 * this QP and flush all current page faults. Otherwise a stale page
2683 * fault may attempt to work on this QP after it is reset and moved
2684 * again to RTS, and may cause the driver and the device to get out of
2685 * sync. */
2686 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2687 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2688 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2689 mlx5_ib_qp_disable_pagefaults(qp);
2690
427c1e7b 2691 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2692 !optab[mlx5_cur][mlx5_new])
2693 goto out;
2694
2695 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2696 optpar = ib_mask_to_mlx5_opt(attr_mask);
2697 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2698
0680efa2
AV		 2699 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2700 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2701
2702 raw_qp_param.operation = op;
2703 err = modify_raw_packet_qp(dev, qp, &raw_qp_param);
2704 } else {
1a412fb1 2705 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2706 &base->mqp);
0680efa2
AV		 2707 }
2708
e126ba97
EC		 2709 if (err)
2710 goto out;
2711
ad5f8e96 2712 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2713 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2714 mlx5_ib_qp_enable_pagefaults(qp);
2715
e126ba97
EC		 2716 qp->state = new_state;
2717
2718 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2719 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2720 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2721 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2722 if (attr_mask & IB_QP_PORT)
2723 qp->port = attr->port_num;
2724 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2725 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2726
2727 /*
2728 * If we moved a kernel QP to RESET, clean up all old CQ
2729 * entries and reinitialize the QP.
2730 */
2731 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2732 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2733 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2734 if (send_cq != recv_cq)
19098df2 2735 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2736
2737 qp->rq.head = 0;
2738 qp->rq.tail = 0;
2739 qp->sq.head = 0;
2740 qp->sq.tail = 0;
2741 qp->sq.cur_post = 0;
2742 qp->sq.last_poll = 0;
2743 qp->db.db[MLX5_RCV_DBR] = 0;
2744 qp->db.db[MLX5_SND_DBR] = 0;
2745 }
2746
2747out:
1a412fb1 2748 kfree(context);
e126ba97
EC		 2749 return err;
2750}
2751
2752int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2753 int attr_mask, struct ib_udata *udata)
2754{
2755 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2756 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2757 enum ib_qp_type qp_type;
e126ba97
EC		 2758 enum ib_qp_state cur_state, new_state;
2759 int err = -EINVAL;
2760 int port;
2811ba51 2761 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2762
28d61370
YH		 2763 if (ibqp->rwq_ind_tbl)
2764 return -ENOSYS;
2765
d16e91da
HE		 2766 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2767 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2768
2769 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2770 IB_QPT_GSI : ibqp->qp_type;
2771
e126ba97
EC		 2772 mutex_lock(&qp->mutex);
2773
2774 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2775 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2776
2811ba51
AS		 2777 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2778 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2779 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2780 }
2781
d16e91da
HE		 2782 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2783 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2784 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2785 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2786 goto out;
158abf86 2787 }
e126ba97
EC		 2788
2789 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2790 (attr->port_num == 0 ||
158abf86
HE		 2791 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2792 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2793 attr->port_num, dev->num_ports);
e126ba97 2794 goto out;
158abf86 2795 }
e126ba97
EC		 2796
2797 if (attr_mask & IB_QP_PKEY_INDEX) {
2798 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2799 if (attr->pkey_index >=
158abf86
HE		 2800 dev->mdev->port_caps[port - 1].pkey_table_len) {
2801 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2802 attr->pkey_index);
e126ba97 2803 goto out;
158abf86 2804 }
e126ba97
EC		 2805 }
2806
2807 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2808 attr->max_rd_atomic >
158abf86
HE		 2809 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2810 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2811 attr->max_rd_atomic);
e126ba97 2812 goto out;
158abf86 2813 }
e126ba97
EC		 2814
2815 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2816 attr->max_dest_rd_atomic >
158abf86
HE		 2817 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2818 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2819 attr->max_dest_rd_atomic);
e126ba97 2820 goto out;
158abf86 2821 }
e126ba97
EC		 2822
2823 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2824 err = 0;
2825 goto out;
2826 }
2827
2828 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2829
2830out:
2831 mutex_unlock(&qp->mutex);
2832 return err;
2833}
2834
2835static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2836{
2837 struct mlx5_ib_cq *cq;
2838 unsigned cur;
2839
2840 cur = wq->head - wq->tail;
2841 if (likely(cur + nreq < wq->max_post))
2842 return 0;
2843
2844 cq = to_mcq(ib_cq);
2845 spin_lock(&cq->lock);
2846 cur = wq->head - wq->tail;
2847 spin_unlock(&cq->lock);
2848
2849 return cur + nreq >= wq->max_post;
2850}
2851
2852static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2853 u64 remote_addr, u32 rkey)
2854{
2855 rseg->raddr = cpu_to_be64(remote_addr);
2856 rseg->rkey = cpu_to_be32(rkey);
2857 rseg->reserved = 0;
2858}
2859
f0313965
ES		 2860static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2861 struct ib_send_wr *wr, void *qend,
2862 struct mlx5_ib_qp *qp, int *size)
2863{
2864 void *seg = eseg;
2865
2866 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2867
2868 if (wr->send_flags & IB_SEND_IP_CSUM)
2869 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2870 MLX5_ETH_WQE_L4_CSUM;
2871
2872 seg += sizeof(struct mlx5_wqe_eth_seg);
2873 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2874
2875 if (wr->opcode == IB_WR_LSO) {
2876 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2877 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2878 u64 left, leftlen, copysz;
2879 void *pdata = ud_wr->header;
2880
2881 left = ud_wr->hlen;
2882 eseg->mss = cpu_to_be16(ud_wr->mss);
2883 eseg->inline_hdr_sz = cpu_to_be16(left);
2884
2885 /*
2886 * check if there is space till the end of queue, if yes,
2887 * copy all in one shot, otherwise copy till the end of queue,
2888 * rollback and than the copy the left
2889 */
2890 leftlen = qend - (void *)eseg->inline_hdr_start;
2891 copysz = min_t(u64, leftlen, left);
2892
2893 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2894
2895 if (likely(copysz > size_of_inl_hdr_start)) {
2896 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2897 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2898 }
2899
2900 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2901 seg = mlx5_get_send_wqe(qp, 0);
2902 left -= copysz;
2903 pdata += copysz;
2904 memcpy(seg, pdata, left);
2905 seg += ALIGN(left, 16);
2906 *size += ALIGN(left, 16) / 16;
2907 }
2908 }
2909
2910 return seg;
2911}
2912
e126ba97
EC		 2913static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2914 struct ib_send_wr *wr)
2915{
e622f2f4
CH		 2916 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2917 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2918 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2919}
2920
2921static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2922{
2923 dseg->byte_count = cpu_to_be32(sg->length);
2924 dseg->lkey = cpu_to_be32(sg->lkey);
2925 dseg->addr = cpu_to_be64(sg->addr);
2926}
2927
2928static __be16 get_klm_octo(int npages)
2929{
2930 return cpu_to_be16(ALIGN(npages, 8) / 2);
2931}
2932
2933static __be64 frwr_mkey_mask(void)
2934{
2935 u64 result;
2936
2937 result = MLX5_MKEY_MASK_LEN |
2938 MLX5_MKEY_MASK_PAGE_SIZE |
2939 MLX5_MKEY_MASK_START_ADDR |
2940 MLX5_MKEY_MASK_EN_RINVAL |
2941 MLX5_MKEY_MASK_KEY |
2942 MLX5_MKEY_MASK_LR |
2943 MLX5_MKEY_MASK_LW |
2944 MLX5_MKEY_MASK_RR |
2945 MLX5_MKEY_MASK_RW |
2946 MLX5_MKEY_MASK_A |
2947 MLX5_MKEY_MASK_SMALL_FENCE |
2948 MLX5_MKEY_MASK_FREE;
2949
2950 return cpu_to_be64(result);
2951}
2952
e6631814
SG		 2953static __be64 sig_mkey_mask(void)
2954{
2955 u64 result;
2956
2957 result = MLX5_MKEY_MASK_LEN |
2958 MLX5_MKEY_MASK_PAGE_SIZE |
2959 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2960 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2961 MLX5_MKEY_MASK_EN_RINVAL |
2962 MLX5_MKEY_MASK_KEY |
2963 MLX5_MKEY_MASK_LR |
2964 MLX5_MKEY_MASK_LW |
2965 MLX5_MKEY_MASK_RR |
2966 MLX5_MKEY_MASK_RW |
2967 MLX5_MKEY_MASK_SMALL_FENCE |
2968 MLX5_MKEY_MASK_FREE |
2969 MLX5_MKEY_MASK_BSF_EN;
2970
2971 return cpu_to_be64(result);
2972}
2973
8a187ee5
SG		 2974static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2975 struct mlx5_ib_mr *mr)
2976{
2977 int ndescs = mr->ndescs;
2978
2979 memset(umr, 0, sizeof(*umr));
b005d316 2980
ec22eb53 2981 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 2982 /* KLMs take twice the size of MTTs */
2983 ndescs *= 2;
2984
8a187ee5
SG		 2985 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2986 umr->klm_octowords = get_klm_octo(ndescs);
2987 umr->mkey_mask = frwr_mkey_mask();
2988}
2989
dd01e66a 2990static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2991{
2992 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2993 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2994 umr->flags = 1 << 7;
e126ba97
EC		 2995}
2996
968e78dd
HE		 2997static __be64 get_umr_reg_mr_mask(void)
2998{
2999 u64 result;
3000
3001 result = MLX5_MKEY_MASK_LEN |
3002 MLX5_MKEY_MASK_PAGE_SIZE |
3003 MLX5_MKEY_MASK_START_ADDR |
3004 MLX5_MKEY_MASK_PD |
3005 MLX5_MKEY_MASK_LR |
3006 MLX5_MKEY_MASK_LW |
3007 MLX5_MKEY_MASK_KEY |
3008 MLX5_MKEY_MASK_RR |
3009 MLX5_MKEY_MASK_RW |
3010 MLX5_MKEY_MASK_A |
3011 MLX5_MKEY_MASK_FREE;
3012
3013 return cpu_to_be64(result);
3014}
3015
3016static __be64 get_umr_unreg_mr_mask(void)
3017{
3018 u64 result;
3019
3020 result = MLX5_MKEY_MASK_FREE;
3021
3022 return cpu_to_be64(result);
3023}
3024
3025static __be64 get_umr_update_mtt_mask(void)
3026{
3027 u64 result;
3028
3029 result = MLX5_MKEY_MASK_FREE;
3030
3031 return cpu_to_be64(result);
3032}
3033
56e11d62
NO		 3034static __be64 get_umr_update_translation_mask(void)
3035{
3036 u64 result;
3037
3038 result = MLX5_MKEY_MASK_LEN |
3039 MLX5_MKEY_MASK_PAGE_SIZE |
3040 MLX5_MKEY_MASK_START_ADDR |
3041 MLX5_MKEY_MASK_KEY |
3042 MLX5_MKEY_MASK_FREE;
3043
3044 return cpu_to_be64(result);
3045}
3046
3047static __be64 get_umr_update_access_mask(void)
3048{
3049 u64 result;
3050
3051 result = MLX5_MKEY_MASK_LW |
3052 MLX5_MKEY_MASK_RR |
3053 MLX5_MKEY_MASK_RW |
3054 MLX5_MKEY_MASK_A |
3055 MLX5_MKEY_MASK_KEY |
3056 MLX5_MKEY_MASK_FREE;
3057
3058 return cpu_to_be64(result);
3059}
3060
3061static __be64 get_umr_update_pd_mask(void)
3062{
3063 u64 result;
3064
3065 result = MLX5_MKEY_MASK_PD |
3066 MLX5_MKEY_MASK_KEY |
3067 MLX5_MKEY_MASK_FREE;
3068
3069 return cpu_to_be64(result);
3070}
3071
e126ba97
EC		 3072static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3073 struct ib_send_wr *wr)
3074{
e622f2f4 3075 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3076
3077 memset(umr, 0, sizeof(*umr));
3078
968e78dd
HE		 3079 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3080 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3081 else
3082 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3083
e126ba97 3084 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 3085 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 3086 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3087 umr->mkey_mask = get_umr_update_mtt_mask();
3088 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3089 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 3090 }
56e11d62
NO		 3091 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3092 umr->mkey_mask |= get_umr_update_translation_mask();
3093 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3094 umr->mkey_mask |= get_umr_update_access_mask();
3095 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3096 umr->mkey_mask |= get_umr_update_pd_mask();
3097 if (!umr->mkey_mask)
3098 umr->mkey_mask = get_umr_reg_mr_mask();
e126ba97 3099 } else {
968e78dd 3100 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 3101 }
3102
3103 if (!wr->num_sge)
968e78dd 3104 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3105}
3106
3107static u8 get_umr_flags(int acc)
3108{
3109 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3110 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3111 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3112 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3113 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3114}
3115
8a187ee5
SG		 3116static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3117 struct mlx5_ib_mr *mr,
3118 u32 key, int access)
3119{
3120 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3121
3122 memset(seg, 0, sizeof(*seg));
b005d316 3123
ec22eb53 3124 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3125 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3126 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3127 /* KLMs take twice the size of MTTs */
3128 ndescs *= 2;
3129
3130 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3131 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3132 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3133 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3134 seg->len = cpu_to_be64(mr->ibmr.length);
3135 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3136}
3137
dd01e66a 3138static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3139{
3140 memset(seg, 0, sizeof(*seg));
dd01e66a 3141 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3142}
3143
3144static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3145{
e622f2f4 3146 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3147
e126ba97
EC		 3148 memset(seg, 0, sizeof(*seg));
3149 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 3150 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3151 return;
3152 }
3153
968e78dd
HE		 3154 seg->flags = convert_access(umrwr->access_flags);
3155 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 3156 if (umrwr->pd)
3157 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 3158 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3159 }
3160 seg->len = cpu_to_be64(umrwr->length);
3161 seg->log2_page_size = umrwr->page_shift;
746b5583 3162 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3163 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3164}
3165
8a187ee5
SG		 3166static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3167 struct mlx5_ib_mr *mr,
3168 struct mlx5_ib_pd *pd)
3169{
3170 int bcount = mr->desc_size * mr->ndescs;
3171
3172 dseg->addr = cpu_to_be64(mr->desc_map);
3173 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3174 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3175}
3176
e126ba97
EC		 3177static __be32 send_ieth(struct ib_send_wr *wr)
3178{
3179 switch (wr->opcode) {
3180 case IB_WR_SEND_WITH_IMM:
3181 case IB_WR_RDMA_WRITE_WITH_IMM:
3182 return wr->ex.imm_data;
3183
3184 case IB_WR_SEND_WITH_INV:
3185 return cpu_to_be32(wr->ex.invalidate_rkey);
3186
3187 default:
3188 return 0;
3189 }
3190}
3191
3192static u8 calc_sig(void *wqe, int size)
3193{
3194 u8 *p = wqe;
3195 u8 res = 0;
3196 int i;
3197
3198 for (i = 0; i < size; i++)
3199 res ^= p[i];
3200
3201 return ~res;
3202}
3203
3204static u8 wq_sig(void *wqe)
3205{
3206 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3207}
3208
3209static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3210 void *wqe, int *sz)
3211{
3212 struct mlx5_wqe_inline_seg *seg;
3213 void *qend = qp->sq.qend;
3214 void *addr;
3215 int inl = 0;
3216 int copy;
3217 int len;
3218 int i;
3219
3220 seg = wqe;
3221 wqe += sizeof(*seg);
3222 for (i = 0; i < wr->num_sge; i++) {
3223 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3224 len = wr->sg_list[i].length;
3225 inl += len;
3226
3227 if (unlikely(inl > qp->max_inline_data))
3228 return -ENOMEM;
3229
3230 if (unlikely(wqe + len > qend)) {
3231 copy = qend - wqe;
3232 memcpy(wqe, addr, copy);
3233 addr += copy;
3234 len -= copy;
3235 wqe = mlx5_get_send_wqe(qp, 0);
3236 }
3237 memcpy(wqe, addr, len);
3238 wqe += len;
3239 }
3240
3241 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3242
3243 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3244
3245 return 0;
3246}
3247
e6631814
SG		 3248static u16 prot_field_size(enum ib_signature_type type)
3249{
3250 switch (type) {
3251 case IB_SIG_TYPE_T10_DIF:
3252 return MLX5_DIF_SIZE;
3253 default:
3254 return 0;
3255 }
3256}
3257
3258static u8 bs_selector(int block_size)
3259{
3260 switch (block_size) {
3261 case 512: return 0x1;
3262 case 520: return 0x2;
3263 case 4096: return 0x3;
3264 case 4160: return 0x4;
3265 case 1073741824: return 0x5;
3266 default: return 0;
3267 }
3268}
3269
78eda2bb
SG		 3270static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3271 struct mlx5_bsf_inl *inl)
e6631814 3272{
142537f4
SG		 3273 /* Valid inline section and allow BSF refresh */
3274 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3275 MLX5_BSF_REFRESH_DIF);
3276 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3277 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3278 /* repeating block */
3279 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3280 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3281 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3282
78eda2bb
SG		 3283 if (domain->sig.dif.ref_remap)
3284 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3285
78eda2bb
SG		 3286 if (domain->sig.dif.app_escape) {
3287 if (domain->sig.dif.ref_escape)
3288 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3289 else
3290 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3291 }
3292
78eda2bb
SG		 3293 inl->dif_app_bitmask_check =
3294 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3295}
3296
3297static int mlx5_set_bsf(struct ib_mr *sig_mr,
3298 struct ib_sig_attrs *sig_attrs,
3299 struct mlx5_bsf *bsf, u32 data_size)
3300{
3301 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3302 struct mlx5_bsf_basic *basic = &bsf->basic;
3303 struct ib_sig_domain *mem = &sig_attrs->mem;
3304 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3305
c7f44fbd 3306 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3307
3308 /* Basic + Extended + Inline */
3309 basic->bsf_size_sbs = 1 << 7;
3310 /* Input domain check byte mask */
3311 basic->check_byte_mask = sig_attrs->check_mask;
3312 basic->raw_data_size = cpu_to_be32(data_size);
3313
3314 /* Memory domain */
e6631814 3315 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3316 case IB_SIG_TYPE_NONE:
3317 break;
e6631814 3318 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3319 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3320 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3321 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3322 break;
3323 default:
3324 return -EINVAL;
3325 }
e6631814 3326
78eda2bb
SG		 3327 /* Wire domain */
3328 switch (sig_attrs->wire.sig_type) {
3329 case IB_SIG_TYPE_NONE:
3330 break;
3331 case IB_SIG_TYPE_T10_DIF:
e6631814 3332 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3333 mem->sig_type == wire->sig_type) {
e6631814 3334 /* Same block structure */
142537f4 3335 basic->bsf_size_sbs |= 1 << 4;
e6631814 3336 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3337 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3338 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3339 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3340 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3341 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3342 } else
3343 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3344
142537f4 3345 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3346 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3347 break;
e6631814
SG		 3348 default:
3349 return -EINVAL;
3350 }
3351
3352 return 0;
3353}
3354
e622f2f4
CH		 3355static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3356 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3357{
e622f2f4
CH		 3358 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3359 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3360 struct mlx5_bsf *bsf;
e622f2f4
CH		 3361 u32 data_len = wr->wr.sg_list->length;
3362 u32 data_key = wr->wr.sg_list->lkey;
3363 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3364 int ret;
3365 int wqe_size;
3366
e622f2f4
CH		 3367 if (!wr->prot ||
3368 (data_key == wr->prot->lkey &&
3369 data_va == wr->prot->addr &&
3370 data_len == wr->prot->length)) {
e6631814
SG		 3371 /**
3372 * Source domain doesn't contain signature information
5c273b16 3373 * or data and protection are interleaved in memory.
e6631814
SG		 3374 * So need construct:
3375 * ------------------
3376 * | data_klm |
3377 * ------------------
3378 * | BSF |
3379 * ------------------
3380 **/
3381 struct mlx5_klm *data_klm = *seg;
3382
3383 data_klm->bcount = cpu_to_be32(data_len);
3384 data_klm->key = cpu_to_be32(data_key);
3385 data_klm->va = cpu_to_be64(data_va);
3386 wqe_size = ALIGN(sizeof(*data_klm), 64);
3387 } else {
3388 /**
3389 * Source domain contains signature information
3390 * So need construct a strided block format:
3391 * ---------------------------
3392 * | stride_block_ctrl |
3393 * ---------------------------
3394 * | data_klm |
3395 * ---------------------------
3396 * | prot_klm |
3397 * ---------------------------
3398 * | BSF |
3399 * ---------------------------
3400 **/
3401 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3402 struct mlx5_stride_block_entry *data_sentry;
3403 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3404 u32 prot_key = wr->prot->lkey;
3405 u64 prot_va = wr->prot->addr;
e6631814
SG		 3406 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3407 int prot_size;
3408
3409 sblock_ctrl = *seg;
3410 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3411 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3412
3413 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3414 if (!prot_size) {
3415 pr_err("Bad block size given: %u\n", block_size);
3416 return -EINVAL;
3417 }
3418 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3419 prot_size);
3420 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3421 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3422 sblock_ctrl->num_entries = cpu_to_be16(2);
3423
3424 data_sentry->bcount = cpu_to_be16(block_size);
3425 data_sentry->key = cpu_to_be32(data_key);
3426 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3427 data_sentry->stride = cpu_to_be16(block_size);
3428
e6631814
SG		 3429 prot_sentry->bcount = cpu_to_be16(prot_size);
3430 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3431 prot_sentry->va = cpu_to_be64(prot_va);
3432 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3433
e6631814
SG		 3434 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3435 sizeof(*prot_sentry), 64);
3436 }
3437
3438 *seg += wqe_size;
3439 *size += wqe_size / 16;
3440 if (unlikely((*seg == qp->sq.qend)))
3441 *seg = mlx5_get_send_wqe(qp, 0);
3442
3443 bsf = *seg;
3444 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3445 if (ret)
3446 return -EINVAL;
3447
3448 *seg += sizeof(*bsf);
3449 *size += sizeof(*bsf) / 16;
3450 if (unlikely((*seg == qp->sq.qend)))
3451 *seg = mlx5_get_send_wqe(qp, 0);
3452
3453 return 0;
3454}
3455
3456static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3457 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3458 u32 length, u32 pdn)
3459{
e622f2f4 3460 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3461 u32 sig_key = sig_mr->rkey;
d5436ba0 3462 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3463
3464 memset(seg, 0, sizeof(*seg));
3465
e622f2f4 3466 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3467 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3468 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3469 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3470 MLX5_MKEY_BSF_EN | pdn);
3471 seg->len = cpu_to_be64(length);
3472 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3473 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3474}
3475
3476static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3477 u32 nelements)
e6631814
SG		 3478{
3479 memset(umr, 0, sizeof(*umr));
3480
3481 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3482 umr->klm_octowords = get_klm_octo(nelements);
3483 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3484 umr->mkey_mask = sig_mkey_mask();
3485}
3486
3487
e622f2f4 3488static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3489 void **seg, int *size)
3490{
e622f2f4
CH		 3491 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3492 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3493 u32 pdn = get_pd(qp)->pdn;
3494 u32 klm_oct_size;
3495 int region_len, ret;
3496
e622f2f4
CH		 3497 if (unlikely(wr->wr.num_sge != 1) ||
3498 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3499 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3500 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3501 return -EINVAL;
3502
3503 /* length of the protected region, data + protection */
e622f2f4
CH		 3504 region_len = wr->wr.sg_list->length;
3505 if (wr->prot &&
3506 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3507 wr->prot->addr != wr->wr.sg_list->addr ||
3508 wr->prot->length != wr->wr.sg_list->length))
3509 region_len += wr->prot->length;
e6631814
SG		 3510
3511 /**
3512 * KLM octoword size - if protection was provided
3513 * then we use strided block format (3 octowords),
3514 * else we use single KLM (1 octoword)
3515 **/
e622f2f4 3516 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3517
e622f2f4 3518 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3519 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3520 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3521 if (unlikely((*seg == qp->sq.qend)))
3522 *seg = mlx5_get_send_wqe(qp, 0);
3523
3524 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3525 *seg += sizeof(struct mlx5_mkey_seg);
3526 *size += sizeof(struct mlx5_mkey_seg) / 16;
3527 if (unlikely((*seg == qp->sq.qend)))
3528 *seg = mlx5_get_send_wqe(qp, 0);
3529
3530 ret = set_sig_data_segment(wr, qp, seg, size);
3531 if (ret)
3532 return ret;
3533
d5436ba0 3534 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3535 return 0;
3536}
3537
3538static int set_psv_wr(struct ib_sig_domain *domain,
3539 u32 psv_idx, void **seg, int *size)
3540{
3541 struct mlx5_seg_set_psv *psv_seg = *seg;
3542
3543 memset(psv_seg, 0, sizeof(*psv_seg));
3544 psv_seg->psv_num = cpu_to_be32(psv_idx);
3545 switch (domain->sig_type) {
78eda2bb
SG		 3546 case IB_SIG_TYPE_NONE:
3547 break;
e6631814
SG		 3548 case IB_SIG_TYPE_T10_DIF:
3549 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3550 domain->sig.dif.app_tag);
3551 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3552 break;
e6631814
SG		 3553 default:
3554 pr_err("Bad signature type given.\n");
3555 return 1;
3556 }
3557
78eda2bb
SG		 3558 *seg += sizeof(*psv_seg);
3559 *size += sizeof(*psv_seg) / 16;
3560
e6631814
SG		 3561 return 0;
3562}
3563
8a187ee5
SG		 3564static int set_reg_wr(struct mlx5_ib_qp *qp,
3565 struct ib_reg_wr *wr,
3566 void **seg, int *size)
3567{
3568 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3569 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3570
3571 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3572 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3573 "Invalid IB_SEND_INLINE send flag\n");
3574 return -EINVAL;
3575 }
3576
3577 set_reg_umr_seg(*seg, mr);
3578 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3579 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3580 if (unlikely((*seg == qp->sq.qend)))
3581 *seg = mlx5_get_send_wqe(qp, 0);
3582
3583 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3584 *seg += sizeof(struct mlx5_mkey_seg);
3585 *size += sizeof(struct mlx5_mkey_seg) / 16;
3586 if (unlikely((*seg == qp->sq.qend)))
3587 *seg = mlx5_get_send_wqe(qp, 0);
3588
3589 set_reg_data_seg(*seg, mr, pd);
3590 *seg += sizeof(struct mlx5_wqe_data_seg);
3591 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3592
3593 return 0;
3594}
3595
dd01e66a 3596static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3597{
dd01e66a 3598 set_linv_umr_seg(*seg);
e126ba97
EC		 3599 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3600 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3601 if (unlikely((*seg == qp->sq.qend)))
3602 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3603 set_linv_mkey_seg(*seg);
e126ba97
EC		 3604 *seg += sizeof(struct mlx5_mkey_seg);
3605 *size += sizeof(struct mlx5_mkey_seg) / 16;
3606 if (unlikely((*seg == qp->sq.qend)))
3607 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3608}
3609
3610static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3611{
3612 __be32 *p = NULL;
3613 int tidx = idx;
3614 int i, j;
3615
3616 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3617 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3618 if ((i & 0xf) == 0) {
3619 void *buf = mlx5_get_send_wqe(qp, tidx);
3620 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3621 p = buf;
3622 j = 0;
3623 }
3624 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3625 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3626 be32_to_cpu(p[j + 3]));
3627 }
3628}
3629
3630static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3631 unsigned bytecnt, struct mlx5_ib_qp *qp)
3632{
3633 while (bytecnt > 0) {
3634 __iowrite64_copy(dst++, src++, 8);
3635 __iowrite64_copy(dst++, src++, 8);
3636 __iowrite64_copy(dst++, src++, 8);
3637 __iowrite64_copy(dst++, src++, 8);
3638 __iowrite64_copy(dst++, src++, 8);
3639 __iowrite64_copy(dst++, src++, 8);
3640 __iowrite64_copy(dst++, src++, 8);
3641 __iowrite64_copy(dst++, src++, 8);
3642 bytecnt -= 64;
3643 if (unlikely(src == qp->sq.qend))
3644 src = mlx5_get_send_wqe(qp, 0);
3645 }
3646}
3647
3648static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3649{
3650 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3651 wr->send_flags & IB_SEND_FENCE))
3652 return MLX5_FENCE_MODE_STRONG_ORDERING;
3653
3654 if (unlikely(fence)) {
3655 if (wr->send_flags & IB_SEND_FENCE)
3656 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3657 else
3658 return fence;
c9b25495
EC		 3659 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3660 return MLX5_FENCE_MODE_FENCE;
e126ba97 3661 }
c9b25495
EC		 3662
3663 return 0;
e126ba97
EC		 3664}
3665
6e5eadac
SG		 3666static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3667 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3668 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3669 int *size, int nreq)
3670{
3671 int err = 0;
3672
3673 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3674 err = -ENOMEM;
3675 return err;
3676 }
3677
3678 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3679 *seg = mlx5_get_send_wqe(qp, *idx);
3680 *ctrl = *seg;
3681 *(uint32_t *)(*seg + 8) = 0;
3682 (*ctrl)->imm = send_ieth(wr);
3683 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3684 (wr->send_flags & IB_SEND_SIGNALED ?
3685 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3686 (wr->send_flags & IB_SEND_SOLICITED ?
3687 MLX5_WQE_CTRL_SOLICITED : 0);
3688
3689 *seg += sizeof(**ctrl);
3690 *size = sizeof(**ctrl) / 16;
3691
3692 return err;
3693}
3694
3695static void finish_wqe(struct mlx5_ib_qp *qp,
3696 struct mlx5_wqe_ctrl_seg *ctrl,
3697 u8 size, unsigned idx, u64 wr_id,
3698 int nreq, u8 fence, u8 next_fence,
3699 u32 mlx5_opcode)
3700{
3701 u8 opmod = 0;
3702
3703 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3704 mlx5_opcode | ((u32)opmod << 24));
19098df2 3705 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3706 ctrl->fm_ce_se |= fence;
3707 qp->fm_cache = next_fence;
3708 if (unlikely(qp->wq_sig))
3709 ctrl->signature = wq_sig(ctrl);
3710
3711 qp->sq.wrid[idx] = wr_id;
3712 qp->sq.w_list[idx].opcode = mlx5_opcode;
3713 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3714 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3715 qp->sq.w_list[idx].next = qp->sq.cur_post;
3716}
3717
3718
e126ba97
EC		 3719int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3720 struct ib_send_wr **bad_wr)
3721{
3722 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3723 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3724 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3725 struct mlx5_ib_qp *qp;
e6631814 3726 struct mlx5_ib_mr *mr;
e126ba97
EC		 3727 struct mlx5_wqe_data_seg *dpseg;
3728 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3729 struct mlx5_bf *bf;
e126ba97 3730 int uninitialized_var(size);
d16e91da 3731 void *qend;
e126ba97 3732 unsigned long flags;
e126ba97
EC		 3733 unsigned idx;
3734 int err = 0;
3735 int inl = 0;
3736 int num_sge;
3737 void *seg;
3738 int nreq;
3739 int i;
3740 u8 next_fence = 0;
e126ba97
EC		 3741 u8 fence;
3742
d16e91da
HE		 3743 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3744 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3745
3746 qp = to_mqp(ibqp);
3747 bf = qp->bf;
3748 qend = qp->sq.qend;
3749
e126ba97
EC		 3750 spin_lock_irqsave(&qp->sq.lock, flags);
3751
89ea94a7
MG		 3752 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3753 err = -EIO;
3754 *bad_wr = wr;
3755 nreq = 0;
3756 goto out;
3757 }
3758
e126ba97 3759 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3760 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3761 mlx5_ib_warn(dev, "\n");
3762 err = -EINVAL;
3763 *bad_wr = wr;
3764 goto out;
3765 }
3766
6e5eadac
SG		 3767 fence = qp->fm_cache;
3768 num_sge = wr->num_sge;
3769 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3770 mlx5_ib_warn(dev, "\n");
3771 err = -ENOMEM;
3772 *bad_wr = wr;
3773 goto out;
3774 }
3775
6e5eadac
SG		 3776 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3777 if (err) {
e126ba97
EC		 3778 mlx5_ib_warn(dev, "\n");
3779 err = -ENOMEM;
3780 *bad_wr = wr;
3781 goto out;
3782 }
3783
e126ba97
EC		 3784 switch (ibqp->qp_type) {
3785 case IB_QPT_XRC_INI:
3786 xrc = seg;
e126ba97
EC		 3787 seg += sizeof(*xrc);
3788 size += sizeof(*xrc) / 16;
3789 /* fall through */
3790 case IB_QPT_RC:
3791 switch (wr->opcode) {
3792 case IB_WR_RDMA_READ:
3793 case IB_WR_RDMA_WRITE:
3794 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3795 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3796 rdma_wr(wr)->rkey);
f241e749 3797 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3798 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3799 break;
3800
3801 case IB_WR_ATOMIC_CMP_AND_SWP:
3802 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3803 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3804 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3805 err = -ENOSYS;
3806 *bad_wr = wr;
3807 goto out;
e126ba97
EC		 3808
3809 case IB_WR_LOCAL_INV:
3810 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3811 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3812 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3813 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3814 num_sge = 0;
3815 break;
3816
8a187ee5
SG		 3817 case IB_WR_REG_MR:
3818 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3819 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3820 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3821 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3822 if (err) {
3823 *bad_wr = wr;
3824 goto out;
3825 }
3826 num_sge = 0;
3827 break;
3828
e6631814
SG		 3829 case IB_WR_REG_SIG_MR:
3830 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3831 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3832
3833 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3834 err = set_sig_umr_wr(wr, qp, &seg, &size);
3835 if (err) {
3836 mlx5_ib_warn(dev, "\n");
3837 *bad_wr = wr;
3838 goto out;
3839 }
3840
3841 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3842 nreq, get_fence(fence, wr),
3843 next_fence, MLX5_OPCODE_UMR);
3844 /*
3845 * SET_PSV WQEs are not signaled and solicited
3846 * on error
3847 */
3848 wr->send_flags &= ~IB_SEND_SIGNALED;
3849 wr->send_flags |= IB_SEND_SOLICITED;
3850 err = begin_wqe(qp, &seg, &ctrl, wr,
3851 &idx, &size, nreq);
3852 if (err) {
3853 mlx5_ib_warn(dev, "\n");
3854 err = -ENOMEM;
3855 *bad_wr = wr;
3856 goto out;
3857 }
3858
e622f2f4 3859 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3860 mr->sig->psv_memory.psv_idx, &seg,
3861 &size);
3862 if (err) {
3863 mlx5_ib_warn(dev, "\n");
3864 *bad_wr = wr;
3865 goto out;
3866 }
3867
3868 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3869 nreq, get_fence(fence, wr),
3870 next_fence, MLX5_OPCODE_SET_PSV);
3871 err = begin_wqe(qp, &seg, &ctrl, wr,
3872 &idx, &size, nreq);
3873 if (err) {
3874 mlx5_ib_warn(dev, "\n");
3875 err = -ENOMEM;
3876 *bad_wr = wr;
3877 goto out;
3878 }
3879
3880 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3881 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3882 mr->sig->psv_wire.psv_idx, &seg,
3883 &size);
3884 if (err) {
3885 mlx5_ib_warn(dev, "\n");
3886 *bad_wr = wr;
3887 goto out;
3888 }
3889
3890 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3891 nreq, get_fence(fence, wr),
3892 next_fence, MLX5_OPCODE_SET_PSV);
3893 num_sge = 0;
3894 goto skip_psv;
3895
e126ba97
EC		 3896 default:
3897 break;
3898 }
3899 break;
3900
3901 case IB_QPT_UC:
3902 switch (wr->opcode) {
3903 case IB_WR_RDMA_WRITE:
3904 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3905 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3906 rdma_wr(wr)->rkey);
e126ba97
EC		 3907 seg += sizeof(struct mlx5_wqe_raddr_seg);
3908 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3909 break;
3910
3911 default:
3912 break;
3913 }
3914 break;
3915
e126ba97 3916 case IB_QPT_SMI:
d16e91da 3917 case MLX5_IB_QPT_HW_GSI:
e126ba97 3918 set_datagram_seg(seg, wr);
f241e749 3919 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3920 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3921 if (unlikely((seg == qend)))
3922 seg = mlx5_get_send_wqe(qp, 0);
3923 break;
f0313965
ES		 3924 case IB_QPT_UD:
3925 set_datagram_seg(seg, wr);
3926 seg += sizeof(struct mlx5_wqe_datagram_seg);
3927 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3928
3929 if (unlikely((seg == qend)))
3930 seg = mlx5_get_send_wqe(qp, 0);
3931
3932 /* handle qp that supports ud offload */
3933 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3934 struct mlx5_wqe_eth_pad *pad;
e126ba97 3935
f0313965
ES		 3936 pad = seg;
3937 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3938 seg += sizeof(struct mlx5_wqe_eth_pad);
3939 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3940
3941 seg = set_eth_seg(seg, wr, qend, qp, &size);
3942
3943 if (unlikely((seg == qend)))
3944 seg = mlx5_get_send_wqe(qp, 0);
3945 }
3946 break;
e126ba97
EC		 3947 case MLX5_IB_QPT_REG_UMR:
3948 if (wr->opcode != MLX5_IB_WR_UMR) {
3949 err = -EINVAL;
3950 mlx5_ib_warn(dev, "bad opcode\n");
3951 goto out;
3952 }
3953 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3954 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3955 set_reg_umr_segment(seg, wr);
3956 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3957 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3958 if (unlikely((seg == qend)))
3959 seg = mlx5_get_send_wqe(qp, 0);
3960 set_reg_mkey_segment(seg, wr);
3961 seg += sizeof(struct mlx5_mkey_seg);
3962 size += sizeof(struct mlx5_mkey_seg) / 16;
3963 if (unlikely((seg == qend)))
3964 seg = mlx5_get_send_wqe(qp, 0);
3965 break;
3966
3967 default:
3968 break;
3969 }
3970
3971 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3972 int uninitialized_var(sz);
3973
3974 err = set_data_inl_seg(qp, wr, seg, &sz);
3975 if (unlikely(err)) {
3976 mlx5_ib_warn(dev, "\n");
3977 *bad_wr = wr;
3978 goto out;
3979 }
3980 inl = 1;
3981 size += sz;
3982 } else {
3983 dpseg = seg;
3984 for (i = 0; i < num_sge; i++) {
3985 if (unlikely(dpseg == qend)) {
3986 seg = mlx5_get_send_wqe(qp, 0);
3987 dpseg = seg;
3988 }
3989 if (likely(wr->sg_list[i].length)) {
3990 set_data_ptr_seg(dpseg, wr->sg_list + i);
3991 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3992 dpseg++;
3993 }
3994 }
3995 }
3996
6e5eadac
SG		 3997 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3998 get_fence(fence, wr), next_fence,
3999 mlx5_ib_opcode[wr->opcode]);
e6631814 4000skip_psv:
e126ba97
EC		 4001 if (0)
4002 dump_wqe(qp, idx, size);
4003 }
4004
4005out:
4006 if (likely(nreq)) {
4007 qp->sq.head += nreq;
4008
4009 /* Make sure that descriptors are written before
4010 * updating doorbell record and ringing the doorbell
4011 */
4012 wmb();
4013
4014 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4015
ada388f7
EC		 4016 /* Make sure doorbell record is visible to the HCA before
4017 * we hit doorbell */
4018 wmb();
4019
e126ba97
EC		 4020 if (bf->need_lock)
4021 spin_lock(&bf->lock);
6a4f139a
EC		 4022 else
4023 __acquire(&bf->lock);
e126ba97
EC		 4024
4025 /* TBD enable WC */
4026 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4027 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4028 /* wc_wmb(); */
4029 } else {
4030 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4031 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4032 /* Make sure doorbells don't leak out of SQ spinlock
4033 * and reach the HCA out of order.
4034 */
4035 mmiowb();
4036 }
4037 bf->offset ^= bf->buf_size;
4038 if (bf->need_lock)
4039 spin_unlock(&bf->lock);
6a4f139a
EC		 4040 else
4041 __release(&bf->lock);
e126ba97
EC		 4042 }
4043
4044 spin_unlock_irqrestore(&qp->sq.lock, flags);
4045
4046 return err;
4047}
4048
4049static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4050{
4051 sig->signature = calc_sig(sig, size);
4052}
4053
4054int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4055 struct ib_recv_wr **bad_wr)
4056{
4057 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4058 struct mlx5_wqe_data_seg *scat;
4059 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4060 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4061 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4062 unsigned long flags;
4063 int err = 0;
4064 int nreq;
4065 int ind;
4066 int i;
4067
d16e91da
HE		 4068 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4069 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4070
e126ba97
EC		 4071 spin_lock_irqsave(&qp->rq.lock, flags);
4072
89ea94a7
MG		 4073 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4074 err = -EIO;
4075 *bad_wr = wr;
4076 nreq = 0;
4077 goto out;
4078 }
4079
e126ba97
EC		 4080 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4081
4082 for (nreq = 0; wr; nreq++, wr = wr->next) {
4083 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4084 err = -ENOMEM;
4085 *bad_wr = wr;
4086 goto out;
4087 }
4088
4089 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4090 err = -EINVAL;
4091 *bad_wr = wr;
4092 goto out;
4093 }
4094
4095 scat = get_recv_wqe(qp, ind);
4096 if (qp->wq_sig)
4097 scat++;
4098
4099 for (i = 0; i < wr->num_sge; i++)
4100 set_data_ptr_seg(scat + i, wr->sg_list + i);
4101
4102 if (i < qp->rq.max_gs) {
4103 scat[i].byte_count = 0;
4104 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4105 scat[i].addr = 0;
4106 }
4107
4108 if (qp->wq_sig) {
4109 sig = (struct mlx5_rwqe_sig *)scat;
4110 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4111 }
4112
4113 qp->rq.wrid[ind] = wr->wr_id;
4114
4115 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4116 }
4117
4118out:
4119 if (likely(nreq)) {
4120 qp->rq.head += nreq;
4121
4122 /* Make sure that descriptors are written before
4123 * doorbell record.
4124 */
4125 wmb();
4126
4127 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4128 }
4129
4130 spin_unlock_irqrestore(&qp->rq.lock, flags);
4131
4132 return err;
4133}
4134
4135static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4136{
4137 switch (mlx5_state) {
4138 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4139 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4140 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4141 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4142 case MLX5_QP_STATE_SQ_DRAINING:
4143 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4144 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4145 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4146 default: return -1;
4147 }
4148}
4149
4150static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4151{
4152 switch (mlx5_mig_state) {
4153 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4154 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4155 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4156 default: return -1;
4157 }
4158}
4159
4160static int to_ib_qp_access_flags(int mlx5_flags)
4161{
4162 int ib_flags = 0;
4163
4164 if (mlx5_flags & MLX5_QP_BIT_RRE)
4165 ib_flags |= IB_ACCESS_REMOTE_READ;
4166 if (mlx5_flags & MLX5_QP_BIT_RWE)
4167 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4168 if (mlx5_flags & MLX5_QP_BIT_RAE)
4169 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4170
4171 return ib_flags;
4172}
4173
4174static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4175 struct mlx5_qp_path *path)
4176{
9603b61d 4177 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4178
4179 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4180 ib_ah_attr->port_num = path->port;
4181
c7a08ac7 4182 if (ib_ah_attr->port_num == 0 ||
938fe83c 4183 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4184 return;
4185
2811ba51 4186 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4187
4188 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4189 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4190 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4191 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4192 if (ib_ah_attr->ah_flags) {
4193 ib_ah_attr->grh.sgid_index = path->mgid_index;
4194 ib_ah_attr->grh.hop_limit = path->hop_limit;
4195 ib_ah_attr->grh.traffic_class =
4196 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4197 ib_ah_attr->grh.flow_label =
4198 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4199 memcpy(ib_ah_attr->grh.dgid.raw,
4200 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4201 }
4202}
4203
6d2f89df 4204static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4205 struct mlx5_ib_sq *sq,
4206 u8 *sq_state)
4207{
4208 void *out;
4209 void *sqc;
4210 int inlen;
4211 int err;
4212
4213 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4214 out = mlx5_vzalloc(inlen);
4215 if (!out)
4216 return -ENOMEM;
4217
4218 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4219 if (err)
4220 goto out;
4221
4222 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4223 *sq_state = MLX5_GET(sqc, sqc, state);
4224 sq->state = *sq_state;
4225
4226out:
4227 kvfree(out);
4228 return err;
4229}
4230
4231static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4232 struct mlx5_ib_rq *rq,
4233 u8 *rq_state)
4234{
4235 void *out;
4236 void *rqc;
4237 int inlen;
4238 int err;
4239
4240 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4241 out = mlx5_vzalloc(inlen);
4242 if (!out)
4243 return -ENOMEM;
4244
4245 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4246 if (err)
4247 goto out;
4248
4249 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4250 *rq_state = MLX5_GET(rqc, rqc, state);
4251 rq->state = *rq_state;
4252
4253out:
4254 kvfree(out);
4255 return err;
4256}
4257
4258static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4259 struct mlx5_ib_qp *qp, u8 *qp_state)
4260{
4261 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4262 [MLX5_RQC_STATE_RST] = {
4263 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4264 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4265 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4266 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4267 },
4268 [MLX5_RQC_STATE_RDY] = {
4269 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4270 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4271 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4272 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4273 },
4274 [MLX5_RQC_STATE_ERR] = {
4275 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4276 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4277 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4278 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4279 },
4280 [MLX5_RQ_STATE_NA] = {
4281 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4282 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4283 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4284 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4285 },
4286 };
4287
4288 *qp_state = sqrq_trans[rq_state][sq_state];
4289
4290 if (*qp_state == MLX5_QP_STATE_BAD) {
4291 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4292 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4293 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4294 return -EINVAL;
4295 }
4296
4297 if (*qp_state == MLX5_QP_STATE)
4298 *qp_state = qp->state;
4299
4300 return 0;
4301}
4302
4303static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4304 struct mlx5_ib_qp *qp,
4305 u8 *raw_packet_qp_state)
4306{
4307 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4308 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4309 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4310 int err;
4311 u8 sq_state = MLX5_SQ_STATE_NA;
4312 u8 rq_state = MLX5_RQ_STATE_NA;
4313
4314 if (qp->sq.wqe_cnt) {
4315 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4316 if (err)
4317 return err;
4318 }
4319
4320 if (qp->rq.wqe_cnt) {
4321 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4322 if (err)
4323 return err;
4324 }
4325
4326 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4327 raw_packet_qp_state);
4328}
4329
4330static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4331 struct ib_qp_attr *qp_attr)
e126ba97 4332{
09a7d9ec 4333 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4334 struct mlx5_qp_context *context;
4335 int mlx5_state;
09a7d9ec 4336 u32 *outb;
e126ba97
EC		 4337 int err = 0;
4338
09a7d9ec 4339 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4340 if (!outb)
4341 return -ENOMEM;
4342
19098df2 4343 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4344 outlen);
e126ba97 4345 if (err)
6d2f89df 4346 goto out;
e126ba97 4347
09a7d9ec
SM		 4348 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4349 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4350
e126ba97
EC		 4351 mlx5_state = be32_to_cpu(context->flags) >> 28;
4352
4353 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4354 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4355 qp_attr->path_mig_state =
4356 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4357 qp_attr->qkey = be32_to_cpu(context->qkey);
4358 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4359 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4360 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4361 qp_attr->qp_access_flags =
4362 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4363
4364 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4365 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4366 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4367 qp_attr->alt_pkey_index =
4368 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4369 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4370 }
4371
d3ae2bde 4372 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4373 qp_attr->port_num = context->pri_path.port;
4374
4375 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4376 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4377
4378 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4379
4380 qp_attr->max_dest_rd_atomic =
4381 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4382 qp_attr->min_rnr_timer =
4383 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4384 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4385 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4386 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4387 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4388
4389out:
4390 kfree(outb);
4391 return err;
4392}
4393
4394int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4395 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4396{
4397 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4398 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4399 int err = 0;
4400 u8 raw_packet_qp_state;
4401
28d61370
YH		 4402 if (ibqp->rwq_ind_tbl)
4403 return -ENOSYS;
4404
d16e91da
HE		 4405 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4406 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4407 qp_init_attr);
4408
6d2f89df 4409#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4410 /*
4411 * Wait for any outstanding page faults, in case the user frees memory
4412 * based upon this query's result.
4413 */
4414 flush_workqueue(mlx5_ib_page_fault_wq);
4415#endif
4416
4417 mutex_lock(&qp->mutex);
4418
4419 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4420 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4421 if (err)
4422 goto out;
4423 qp->state = raw_packet_qp_state;
4424 qp_attr->port_num = 1;
4425 } else {
4426 err = query_qp_attr(dev, qp, qp_attr);
4427 if (err)
4428 goto out;
4429 }
4430
4431 qp_attr->qp_state = qp->state;
e126ba97
EC		 4432 qp_attr->cur_qp_state = qp_attr->qp_state;
4433 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4434 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4435
4436 if (!ibqp->uobject) {
0540d814 4437 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4438 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4439 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4440 } else {
4441 qp_attr->cap.max_send_wr = 0;
4442 qp_attr->cap.max_send_sge = 0;
4443 }
4444
0540d814
NO		 4445 qp_init_attr->qp_type = ibqp->qp_type;
4446 qp_init_attr->recv_cq = ibqp->recv_cq;
4447 qp_init_attr->send_cq = ibqp->send_cq;
4448 qp_init_attr->srq = ibqp->srq;
4449 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4450
4451 qp_init_attr->cap = qp_attr->cap;
4452
4453 qp_init_attr->create_flags = 0;
4454 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4455 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4456
051f2630
LR		 4457 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4458 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4459 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4460 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4461 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4462 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4463 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4464 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4465
e126ba97
EC		 4466 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4467 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4468
e126ba97
EC		 4469out:
4470 mutex_unlock(&qp->mutex);
4471 return err;
4472}
4473
4474struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4475 struct ib_ucontext *context,
4476 struct ib_udata *udata)
4477{
4478 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4479 struct mlx5_ib_xrcd *xrcd;
4480 int err;
4481
938fe83c 4482 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4483 return ERR_PTR(-ENOSYS);
4484
4485 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4486 if (!xrcd)
4487 return ERR_PTR(-ENOMEM);
4488
9603b61d 4489 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4490 if (err) {
4491 kfree(xrcd);
4492 return ERR_PTR(-ENOMEM);
4493 }
4494
4495 return &xrcd->ibxrcd;
4496}
4497
4498int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4499{
4500 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4501 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4502 int err;
4503
9603b61d 4504 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4505 if (err) {
4506 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4507 return err;
4508 }
4509
4510 kfree(xrcd);
4511
4512 return 0;
4513}
79b20a6c
YH		 4514
4515static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4516 struct ib_wq_init_attr *init_attr)
4517{
4518 struct mlx5_ib_dev *dev;
4519 __be64 *rq_pas0;
4520 void *in;
4521 void *rqc;
4522 void *wq;
4523 int inlen;
4524 int err;
4525
4526 dev = to_mdev(pd->device);
4527
4528 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4529 in = mlx5_vzalloc(inlen);
4530 if (!in)
4531 return -ENOMEM;
4532
4533 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4534 MLX5_SET(rqc, rqc, mem_rq_type,
4535 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4536 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4537 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4538 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4539 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4540 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4541 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4542 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4543 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4544 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4545 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4546 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4547 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4548 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4549 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4550 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4551 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4552 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4553 kvfree(in);
4554 return err;
4555}
4556
4557static int set_user_rq_size(struct mlx5_ib_dev *dev,
4558 struct ib_wq_init_attr *wq_init_attr,
4559 struct mlx5_ib_create_wq *ucmd,
4560 struct mlx5_ib_rwq *rwq)
4561{
4562 /* Sanity check RQ size before proceeding */
4563 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4564 return -EINVAL;
4565
4566 if (!ucmd->rq_wqe_count)
4567 return -EINVAL;
4568
4569 rwq->wqe_count = ucmd->rq_wqe_count;
4570 rwq->wqe_shift = ucmd->rq_wqe_shift;
4571 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4572 rwq->log_rq_stride = rwq->wqe_shift;
4573 rwq->log_rq_size = ilog2(rwq->wqe_count);
4574 return 0;
4575}
4576
4577static int prepare_user_rq(struct ib_pd *pd,
4578 struct ib_wq_init_attr *init_attr,
4579 struct ib_udata *udata,
4580 struct mlx5_ib_rwq *rwq)
4581{
4582 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4583 struct mlx5_ib_create_wq ucmd = {};
4584 int err;
4585 size_t required_cmd_sz;
4586
4587 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4588 if (udata->inlen < required_cmd_sz) {
4589 mlx5_ib_dbg(dev, "invalid inlen\n");
4590 return -EINVAL;
4591 }
4592
4593 if (udata->inlen > sizeof(ucmd) &&
4594 !ib_is_udata_cleared(udata, sizeof(ucmd),
4595 udata->inlen - sizeof(ucmd))) {
4596 mlx5_ib_dbg(dev, "inlen is not supported\n");
4597 return -EOPNOTSUPP;
4598 }
4599
4600 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4601 mlx5_ib_dbg(dev, "copy failed\n");
4602 return -EFAULT;
4603 }
4604
4605 if (ucmd.comp_mask) {
4606 mlx5_ib_dbg(dev, "invalid comp mask\n");
4607 return -EOPNOTSUPP;
4608 }
4609
4610 if (ucmd.reserved) {
4611 mlx5_ib_dbg(dev, "invalid reserved\n");
4612 return -EOPNOTSUPP;
4613 }
4614
4615 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4616 if (err) {
4617 mlx5_ib_dbg(dev, "err %d\n", err);
4618 return err;
4619 }
4620
4621 err = create_user_rq(dev, pd, rwq, &ucmd);
4622 if (err) {
4623 mlx5_ib_dbg(dev, "err %d\n", err);
4624 if (err)
4625 return err;
4626 }
4627
4628 rwq->user_index = ucmd.user_index;
4629 return 0;
4630}
4631
4632struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4633 struct ib_wq_init_attr *init_attr,
4634 struct ib_udata *udata)
4635{
4636 struct mlx5_ib_dev *dev;
4637 struct mlx5_ib_rwq *rwq;
4638 struct mlx5_ib_create_wq_resp resp = {};
4639 size_t min_resp_len;
4640 int err;
4641
4642 if (!udata)
4643 return ERR_PTR(-ENOSYS);
4644
4645 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4646 if (udata->outlen && udata->outlen < min_resp_len)
4647 return ERR_PTR(-EINVAL);
4648
4649 dev = to_mdev(pd->device);
4650 switch (init_attr->wq_type) {
4651 case IB_WQT_RQ:
4652 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4653 if (!rwq)
4654 return ERR_PTR(-ENOMEM);
4655 err = prepare_user_rq(pd, init_attr, udata, rwq);
4656 if (err)
4657 goto err;
4658 err = create_rq(rwq, pd, init_attr);
4659 if (err)
4660 goto err_user_rq;
4661 break;
4662 default:
4663 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4664 init_attr->wq_type);
4665 return ERR_PTR(-EINVAL);
4666 }
4667
4668 rwq->ibwq.wq_num = rwq->rqn;
4669 rwq->ibwq.state = IB_WQS_RESET;
4670 if (udata->outlen) {
4671 resp.response_length = offsetof(typeof(resp), response_length) +
4672 sizeof(resp.response_length);
4673 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4674 if (err)
4675 goto err_copy;
4676 }
4677
4678 return &rwq->ibwq;
4679
4680err_copy:
4681 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4682err_user_rq:
4683 destroy_user_rq(pd, rwq);
4684err:
4685 kfree(rwq);
4686 return ERR_PTR(err);
4687}
4688
4689int mlx5_ib_destroy_wq(struct ib_wq *wq)
4690{
4691 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4692 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4693
4694 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4695 destroy_user_rq(wq->pd, rwq);
4696 kfree(rwq);
4697
4698 return 0;
4699}
4700
c5f90929
YH		 4701struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4702 struct ib_rwq_ind_table_init_attr *init_attr,
4703 struct ib_udata *udata)
4704{
4705 struct mlx5_ib_dev *dev = to_mdev(device);
4706 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4707 int sz = 1 << init_attr->log_ind_tbl_size;
4708 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4709 size_t min_resp_len;
4710 int inlen;
4711 int err;
4712 int i;
4713 u32 *in;
4714 void *rqtc;
4715
4716 if (udata->inlen > 0 &&
4717 !ib_is_udata_cleared(udata, 0,
4718 udata->inlen))
4719 return ERR_PTR(-EOPNOTSUPP);
4720
4721 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4722 if (udata->outlen && udata->outlen < min_resp_len)
4723 return ERR_PTR(-EINVAL);
4724
4725 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4726 if (!rwq_ind_tbl)
4727 return ERR_PTR(-ENOMEM);
4728
4729 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4730 in = mlx5_vzalloc(inlen);
4731 if (!in) {
4732 err = -ENOMEM;
4733 goto err;
4734 }
4735
4736 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4737
4738 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4739 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4740
4741 for (i = 0; i < sz; i++)
4742 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4743
4744 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4745 kvfree(in);
4746
4747 if (err)
4748 goto err;
4749
4750 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4751 if (udata->outlen) {
4752 resp.response_length = offsetof(typeof(resp), response_length) +
4753 sizeof(resp.response_length);
4754 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4755 if (err)
4756 goto err_copy;
4757 }
4758
4759 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4760
4761err_copy:
4762 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4763err:
4764 kfree(rwq_ind_tbl);
4765 return ERR_PTR(err);
4766}
4767
4768int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4769{
4770 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4771 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4772
4773 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4774
4775 kfree(rwq_ind_tbl);
4776 return 0;
4777}
4778
79b20a6c
YH		 4779int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4780 u32 wq_attr_mask, struct ib_udata *udata)
4781{
4782 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4783 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4784 struct mlx5_ib_modify_wq ucmd = {};
4785 size_t required_cmd_sz;
4786 int curr_wq_state;
4787 int wq_state;
4788 int inlen;
4789 int err;
4790 void *rqc;
4791 void *in;
4792
4793 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4794 if (udata->inlen < required_cmd_sz)
4795 return -EINVAL;
4796
4797 if (udata->inlen > sizeof(ucmd) &&
4798 !ib_is_udata_cleared(udata, sizeof(ucmd),
4799 udata->inlen - sizeof(ucmd)))
4800 return -EOPNOTSUPP;
4801
4802 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4803 return -EFAULT;
4804
4805 if (ucmd.comp_mask || ucmd.reserved)
4806 return -EOPNOTSUPP;
4807
4808 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4809 in = mlx5_vzalloc(inlen);
4810 if (!in)
4811 return -ENOMEM;
4812
4813 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4814
4815 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4816 wq_attr->curr_wq_state : wq->state;
4817 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4818 wq_attr->wq_state : curr_wq_state;
4819 if (curr_wq_state == IB_WQS_ERR)
4820 curr_wq_state = MLX5_RQC_STATE_ERR;
4821 if (wq_state == IB_WQS_ERR)
4822 wq_state = MLX5_RQC_STATE_ERR;
4823 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4824 MLX5_SET(rqc, rqc, state, wq_state);
4825
4826 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4827 kvfree(in);
4828 if (!err)
4829 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4830
4831 return err;
4832}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git