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IB/mlx5: Modify QP debugging prints
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97
EC		 79
80static int is_qp0(enum ib_qp_type qp_type)
81{
82 return qp_type == IB_QPT_SMI;
83}
84
e126ba97
EC		 85static int is_sqp(enum ib_qp_type qp_type)
86{
87 return is_qp0(qp_type) || is_qp1(qp_type);
88}
89
90static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
91{
92 return mlx5_buf_offset(&qp->buf, offset);
93}
94
95static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
96{
97 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
98}
99
100void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
101{
102 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
103}
104
c1395a2a
HE		 105/**
106 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
107 *
108 * @qp: QP to copy from.
109 * @send: copy from the send queue when non-zero, use the receive queue
110 * otherwise.
111 * @wqe_index: index to start copying from. For send work queues, the
112 * wqe_index is in units of MLX5_SEND_WQE_BB.
113 * For receive work queue, it is the number of work queue
114 * element in the queue.
115 * @buffer: destination buffer.
116 * @length: maximum number of bytes to copy.
117 *
118 * Copies at least a single WQE, but may copy more data.
119 *
120 * Return: the number of bytes copied, or an error code.
121 */
122int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 123 void *buffer, u32 length,
124 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 125{
126 struct ib_device *ibdev = qp->ibqp.device;
127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
128 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
129 size_t offset;
130 size_t wq_end;
19098df2 131 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 132 u32 first_copy_length;
133 int wqe_length;
134 int ret;
135
136 if (wq->wqe_cnt == 0) {
137 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
138 qp->ibqp.qp_type);
139 return -EINVAL;
140 }
141
142 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
143 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
144
145 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
146 return -EINVAL;
147
148 if (offset > umem->length ||
149 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
150 return -EINVAL;
151
152 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
153 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
154 if (ret)
155 return ret;
156
157 if (send) {
158 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
159 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
160
161 wqe_length = ds * MLX5_WQE_DS_UNITS;
162 } else {
163 wqe_length = 1 << wq->wqe_shift;
164 }
165
166 if (wqe_length <= first_copy_length)
167 return first_copy_length;
168
169 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
170 wqe_length - first_copy_length);
171 if (ret)
172 return ret;
173
174 return wqe_length;
175}
176
e126ba97
EC		 177static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
178{
179 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
180 struct ib_event event;
181
19098df2 182 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
183 /* This event is only valid for trans_qps */
184 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
185 }
e126ba97
EC		 186
187 if (ibqp->event_handler) {
188 event.device = ibqp->device;
189 event.element.qp = ibqp;
190 switch (type) {
191 case MLX5_EVENT_TYPE_PATH_MIG:
192 event.event = IB_EVENT_PATH_MIG;
193 break;
194 case MLX5_EVENT_TYPE_COMM_EST:
195 event.event = IB_EVENT_COMM_EST;
196 break;
197 case MLX5_EVENT_TYPE_SQ_DRAINED:
198 event.event = IB_EVENT_SQ_DRAINED;
199 break;
200 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
201 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
202 break;
203 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
204 event.event = IB_EVENT_QP_FATAL;
205 break;
206 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
207 event.event = IB_EVENT_PATH_MIG_ERR;
208 break;
209 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
210 event.event = IB_EVENT_QP_REQ_ERR;
211 break;
212 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
213 event.event = IB_EVENT_QP_ACCESS_ERR;
214 break;
215 default:
216 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
217 return;
218 }
219
220 ibqp->event_handler(&event, ibqp->qp_context);
221 }
222}
223
224static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
225 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
226{
227 int wqe_size;
228 int wq_size;
229
230 /* Sanity check RQ size before proceeding */
938fe83c 231 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 232 return -EINVAL;
233
234 if (!has_rq) {
235 qp->rq.max_gs = 0;
236 qp->rq.wqe_cnt = 0;
237 qp->rq.wqe_shift = 0;
238 } else {
239 if (ucmd) {
240 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
241 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
242 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
243 qp->rq.max_post = qp->rq.wqe_cnt;
244 } else {
245 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
246 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
247 wqe_size = roundup_pow_of_two(wqe_size);
248 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
249 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
250 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 251 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 252 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
253 wqe_size,
938fe83c
SM		 254 MLX5_CAP_GEN(dev->mdev,
255 max_wqe_sz_rq));
e126ba97
EC		 256 return -EINVAL;
257 }
258 qp->rq.wqe_shift = ilog2(wqe_size);
259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260 qp->rq.max_post = qp->rq.wqe_cnt;
261 }
262 }
263
264 return 0;
265}
266
f0313965 267static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 268{
618af384 269 int size = 0;
e126ba97 270
f0313965 271 switch (attr->qp_type) {
e126ba97 272 case IB_QPT_XRC_INI:
b125a54b 273 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 274 /* fall through */
275 case IB_QPT_RC:
276 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 277 max(sizeof(struct mlx5_wqe_atomic_seg) +
278 sizeof(struct mlx5_wqe_raddr_seg),
279 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
280 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 281 break;
282
b125a54b
EC		 283 case IB_QPT_XRC_TGT:
284 return 0;
285
e126ba97 286 case IB_QPT_UC:
b125a54b 287 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 288 max(sizeof(struct mlx5_wqe_raddr_seg),
289 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
290 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 291 break;
292
293 case IB_QPT_UD:
f0313965
ES		 294 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
295 size += sizeof(struct mlx5_wqe_eth_pad) +
296 sizeof(struct mlx5_wqe_eth_seg);
297 /* fall through */
e126ba97
EC		 298 case IB_QPT_SMI:
299 case IB_QPT_GSI:
b125a54b 300 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 301 sizeof(struct mlx5_wqe_datagram_seg);
302 break;
303
304 case MLX5_IB_QPT_REG_UMR:
b125a54b 305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307 sizeof(struct mlx5_mkey_seg);
308 break;
309
310 default:
311 return -EINVAL;
312 }
313
314 return size;
315}
316
317static int calc_send_wqe(struct ib_qp_init_attr *attr)
318{
319 int inl_size = 0;
320 int size;
321
f0313965 322 size = sq_overhead(attr);
e126ba97
EC		 323 if (size < 0)
324 return size;
325
326 if (attr->cap.max_inline_data) {
327 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
328 attr->cap.max_inline_data;
329 }
330
331 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 332 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
333 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
334 return MLX5_SIG_WQE_SIZE;
335 else
336 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 337}
338
339static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
340 struct mlx5_ib_qp *qp)
341{
342 int wqe_size;
343 int wq_size;
344
345 if (!attr->cap.max_send_wr)
346 return 0;
347
348 wqe_size = calc_send_wqe(attr);
349 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
350 if (wqe_size < 0)
351 return wqe_size;
352
938fe83c 353 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 354 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 355 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 356 return -EINVAL;
357 }
358
f0313965
ES		 359 qp->max_inline_data = wqe_size - sq_overhead(attr) -
360 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 361 attr->cap.max_inline_data = qp->max_inline_data;
362
e1e66cc2
SG		 363 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
364 qp->signature_en = true;
365
e126ba97
EC		 366 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
367 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 368 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 369 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 370 qp->sq.wqe_cnt,
371 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 372 return -ENOMEM;
373 }
e126ba97
EC		 374 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
375 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 376 qp->sq.max_post = wq_size / wqe_size;
377 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 378
379 return wq_size;
380}
381
382static int set_user_buf_size(struct mlx5_ib_dev *dev,
383 struct mlx5_ib_qp *qp,
19098df2 384 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 385 struct mlx5_ib_qp_base *base,
386 struct ib_qp_init_attr *attr)
e126ba97
EC		 387{
388 int desc_sz = 1 << qp->sq.wqe_shift;
389
938fe83c 390 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 391 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 392 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 393 return -EINVAL;
394 }
395
396 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
397 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
398 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
399 return -EINVAL;
400 }
401
402 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
403
938fe83c 404 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 405 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 406 qp->sq.wqe_cnt,
407 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 408 return -EINVAL;
409 }
410
0fb2ed66 411 if (attr->qp_type == IB_QPT_RAW_PACKET) {
412 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
413 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
414 } else {
415 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
416 (qp->sq.wqe_cnt << 6);
417 }
e126ba97
EC		 418
419 return 0;
420}
421
422static int qp_has_rq(struct ib_qp_init_attr *attr)
423{
424 if (attr->qp_type == IB_QPT_XRC_INI ||
425 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
426 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
427 !attr->cap.max_recv_wr)
428 return 0;
429
430 return 1;
431}
432
c1be5232
EC		 433static int first_med_uuar(void)
434{
435 return 1;
436}
437
438static int next_uuar(int n)
439{
440 n++;
441
442 while (((n % 4) & 2))
443 n++;
444
445 return n;
446}
447
448static int num_med_uuar(struct mlx5_uuar_info *uuari)
449{
450 int n;
451
452 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
453 uuari->num_low_latency_uuars - 1;
454
455 return n >= 0 ? n : 0;
456}
457
458static int max_uuari(struct mlx5_uuar_info *uuari)
459{
460 return uuari->num_uars * 4;
461}
462
463static int first_hi_uuar(struct mlx5_uuar_info *uuari)
464{
465 int med;
466 int i;
467 int t;
468
469 med = num_med_uuar(uuari);
470 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
471 t++;
472 if (t == med)
473 return next_uuar(i);
474 }
475
476 return 0;
477}
478
e126ba97
EC		 479static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
480{
e126ba97
EC		 481 int i;
482
c1be5232 483 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 484 if (!test_bit(i, uuari->bitmap)) {
485 set_bit(i, uuari->bitmap);
486 uuari->count[i]++;
487 return i;
488 }
489 }
490
491 return -ENOMEM;
492}
493
494static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
495{
c1be5232 496 int minidx = first_med_uuar();
e126ba97
EC		 497 int i;
498
c1be5232 499 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 500 if (uuari->count[i] < uuari->count[minidx])
501 minidx = i;
502 }
503
504 uuari->count[minidx]++;
505 return minidx;
506}
507
508static int alloc_uuar(struct mlx5_uuar_info *uuari,
509 enum mlx5_ib_latency_class lat)
510{
511 int uuarn = -EINVAL;
512
513 mutex_lock(&uuari->lock);
514 switch (lat) {
515 case MLX5_IB_LATENCY_CLASS_LOW:
516 uuarn = 0;
517 uuari->count[uuarn]++;
518 break;
519
520 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 521 if (uuari->ver < 2)
522 uuarn = -ENOMEM;
523 else
524 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 525 break;
526
527 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 528 if (uuari->ver < 2)
529 uuarn = -ENOMEM;
530 else
531 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 532 break;
533
534 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
535 uuarn = 2;
536 break;
537 }
538 mutex_unlock(&uuari->lock);
539
540 return uuarn;
541}
542
543static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
544{
545 clear_bit(uuarn, uuari->bitmap);
546 --uuari->count[uuarn];
547}
548
549static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
550{
551 clear_bit(uuarn, uuari->bitmap);
552 --uuari->count[uuarn];
553}
554
555static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
556{
557 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
558 int high_uuar = nuuars - uuari->num_low_latency_uuars;
559
560 mutex_lock(&uuari->lock);
561 if (uuarn == 0) {
562 --uuari->count[uuarn];
563 goto out;
564 }
565
566 if (uuarn < high_uuar) {
567 free_med_class_uuar(uuari, uuarn);
568 goto out;
569 }
570
571 free_high_class_uuar(uuari, uuarn);
572
573out:
574 mutex_unlock(&uuari->lock);
575}
576
577static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
578{
579 switch (state) {
580 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
581 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
582 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
583 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
584 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
585 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
586 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
587 default: return -1;
588 }
589}
590
591static int to_mlx5_st(enum ib_qp_type type)
592{
593 switch (type) {
594 case IB_QPT_RC: return MLX5_QP_ST_RC;
595 case IB_QPT_UC: return MLX5_QP_ST_UC;
596 case IB_QPT_UD: return MLX5_QP_ST_UD;
597 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
598 case IB_QPT_XRC_INI:
599 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
600 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
601 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
602 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 603 case IB_QPT_RAW_PACKET:
0fb2ed66 604 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 605 case IB_QPT_MAX:
606 default: return -EINVAL;
607 }
608}
609
610static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
611{
612 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
613}
614
19098df2 615static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
616 struct ib_pd *pd,
617 unsigned long addr, size_t size,
618 struct ib_umem **umem,
619 int *npages, int *page_shift, int *ncont,
620 u32 *offset)
621{
622 int err;
623
624 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
625 if (IS_ERR(*umem)) {
626 mlx5_ib_dbg(dev, "umem_get failed\n");
627 return PTR_ERR(*umem);
628 }
629
630 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
631
632 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
633 if (err) {
634 mlx5_ib_warn(dev, "bad offset\n");
635 goto err_umem;
636 }
637
638 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
639 addr, size, *npages, *page_shift, *ncont, *offset);
640
641 return 0;
642
643err_umem:
644 ib_umem_release(*umem);
645 *umem = NULL;
646
647 return err;
648}
649
e126ba97
EC		 650static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
651 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 652 struct ib_qp_init_attr *attr,
e126ba97 653 struct mlx5_create_qp_mbox_in **in,
19098df2 654 struct mlx5_ib_create_qp_resp *resp, int *inlen,
655 struct mlx5_ib_qp_base *base)
e126ba97
EC		 656{
657 struct mlx5_ib_ucontext *context;
658 struct mlx5_ib_create_qp ucmd;
19098df2 659 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 660 int page_shift = 0;
e126ba97
EC		 661 int uar_index;
662 int npages;
9e9c47d0 663 u32 offset = 0;
e126ba97 664 int uuarn;
9e9c47d0 665 int ncont = 0;
e126ba97
EC		 666 int err;
667
668 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
669 if (err) {
670 mlx5_ib_dbg(dev, "copy failed\n");
671 return err;
672 }
673
674 context = to_mucontext(pd->uobject->context);
675 /*
676 * TBD: should come from the verbs when we have the API
677 */
051f2630
LR		 678 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
679 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
680 uuarn = MLX5_CROSS_CHANNEL_UUAR;
681 else {
682 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 683 if (uuarn < 0) {
051f2630
LR		 684 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
685 mlx5_ib_dbg(dev, "reverting to medium latency\n");
686 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 687 if (uuarn < 0) {
051f2630
LR		 688 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
689 mlx5_ib_dbg(dev, "reverting to high latency\n");
690 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
691 if (uuarn < 0) {
692 mlx5_ib_warn(dev, "uuar allocation failed\n");
693 return uuarn;
694 }
c1be5232 695 }
e126ba97
EC		 696 }
697 }
698
699 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
700 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
701
48fea837
HE		 702 qp->rq.offset = 0;
703 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
704 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
705
0fb2ed66 706 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 707 if (err)
708 goto err_uuar;
709
19098df2 710 if (ucmd.buf_addr && ubuffer->buf_size) {
711 ubuffer->buf_addr = ucmd.buf_addr;
712 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
713 ubuffer->buf_size,
714 &ubuffer->umem, &npages, &page_shift,
715 &ncont, &offset);
716 if (err)
9e9c47d0 717 goto err_uuar;
9e9c47d0 718 } else {
19098df2 719 ubuffer->umem = NULL;
e126ba97 720 }
e126ba97
EC		 721
722 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
723 *in = mlx5_vzalloc(*inlen);
724 if (!*in) {
725 err = -ENOMEM;
726 goto err_umem;
727 }
19098df2 728 if (ubuffer->umem)
729 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
730 (*in)->pas, 0);
e126ba97 731 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 732 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 733 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
734
735 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
736 resp->uuar_index = uuarn;
737 qp->uuarn = uuarn;
738
739 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
740 if (err) {
741 mlx5_ib_dbg(dev, "map failed\n");
742 goto err_free;
743 }
744
745 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
746 if (err) {
747 mlx5_ib_dbg(dev, "copy failed\n");
748 goto err_unmap;
749 }
750 qp->create_type = MLX5_QP_USER;
751
752 return 0;
753
754err_unmap:
755 mlx5_ib_db_unmap_user(context, &qp->db);
756
757err_free:
479163f4 758 kvfree(*in);
e126ba97
EC		 759
760err_umem:
19098df2 761 if (ubuffer->umem)
762 ib_umem_release(ubuffer->umem);
e126ba97
EC		 763
764err_uuar:
765 free_uuar(&context->uuari, uuarn);
766 return err;
767}
768
19098df2 769static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
770 struct mlx5_ib_qp_base *base)
e126ba97
EC		 771{
772 struct mlx5_ib_ucontext *context;
773
774 context = to_mucontext(pd->uobject->context);
775 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 776 if (base->ubuffer.umem)
777 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 778 free_uuar(&context->uuari, qp->uuarn);
779}
780
781static int create_kernel_qp(struct mlx5_ib_dev *dev,
782 struct ib_qp_init_attr *init_attr,
783 struct mlx5_ib_qp *qp,
19098df2 784 struct mlx5_create_qp_mbox_in **in, int *inlen,
785 struct mlx5_ib_qp_base *base)
e126ba97
EC		 786{
787 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
788 struct mlx5_uuar_info *uuari;
789 int uar_index;
790 int uuarn;
791 int err;
792
9603b61d 793 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 794 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
795 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 796 IB_QP_CREATE_IPOIB_UD_LSO |
797 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 798 return -EINVAL;
e126ba97
EC		 799
800 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
801 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
802
803 uuarn = alloc_uuar(uuari, lc);
804 if (uuarn < 0) {
805 mlx5_ib_dbg(dev, "\n");
806 return -ENOMEM;
807 }
808
809 qp->bf = &uuari->bfs[uuarn];
810 uar_index = qp->bf->uar->index;
811
812 err = calc_sq_size(dev, init_attr, qp);
813 if (err < 0) {
814 mlx5_ib_dbg(dev, "err %d\n", err);
815 goto err_uuar;
816 }
817
818 qp->rq.offset = 0;
819 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 820 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 821
19098df2 822 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 823 if (err) {
824 mlx5_ib_dbg(dev, "err %d\n", err);
825 goto err_uuar;
826 }
827
828 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
829 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
830 *in = mlx5_vzalloc(*inlen);
831 if (!*in) {
832 err = -ENOMEM;
833 goto err_buf;
834 }
835 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 836 (*in)->ctx.log_pg_sz_remote_qpn =
837 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 838 /* Set "fast registration enabled" for all kernel QPs */
839 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
840 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
841
b11a4f9c
HE		 842 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
843 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
844 qp->flags |= MLX5_IB_QP_SQPN_QP1;
845 }
846
e126ba97
EC		 847 mlx5_fill_page_array(&qp->buf, (*in)->pas);
848
9603b61d 849 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 850 if (err) {
851 mlx5_ib_dbg(dev, "err %d\n", err);
852 goto err_free;
853 }
854
e126ba97
EC		 855 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
856 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
857 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
858 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
859 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
860
861 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
862 !qp->sq.w_list || !qp->sq.wqe_head) {
863 err = -ENOMEM;
864 goto err_wrid;
865 }
866 qp->create_type = MLX5_QP_KERNEL;
867
868 return 0;
869
870err_wrid:
9603b61d 871 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 872 kfree(qp->sq.wqe_head);
873 kfree(qp->sq.w_list);
874 kfree(qp->sq.wrid);
875 kfree(qp->sq.wr_data);
876 kfree(qp->rq.wrid);
877
878err_free:
479163f4 879 kvfree(*in);
e126ba97
EC		 880
881err_buf:
9603b61d 882 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 883
884err_uuar:
9603b61d 885 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 886 return err;
887}
888
889static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
890{
9603b61d 891 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 892 kfree(qp->sq.wqe_head);
893 kfree(qp->sq.w_list);
894 kfree(qp->sq.wrid);
895 kfree(qp->sq.wr_data);
896 kfree(qp->rq.wrid);
9603b61d
JM		 897 mlx5_buf_free(dev->mdev, &qp->buf);
898 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 899}
900
901static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
902{
903 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
904 (attr->qp_type == IB_QPT_XRC_INI))
905 return cpu_to_be32(MLX5_SRQ_RQ);
906 else if (!qp->has_rq)
907 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
908 else
909 return cpu_to_be32(MLX5_NON_ZERO_RQ);
910}
911
912static int is_connected(enum ib_qp_type qp_type)
913{
914 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
915 return 1;
916
917 return 0;
918}
919
0fb2ed66 920static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
921 struct mlx5_ib_sq *sq, u32 tdn)
922{
923 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
924 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
925
926 memset(in, 0, sizeof(in));
927
928 MLX5_SET(tisc, tisc, transport_domain, tdn);
929
930 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
931}
932
933static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
934 struct mlx5_ib_sq *sq)
935{
936 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
937}
938
939static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
940 struct mlx5_ib_sq *sq, void *qpin,
941 struct ib_pd *pd)
942{
943 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
944 __be64 *pas;
945 void *in;
946 void *sqc;
947 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
948 void *wq;
949 int inlen;
950 int err;
951 int page_shift = 0;
952 int npages;
953 int ncont = 0;
954 u32 offset = 0;
955
956 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
957 &sq->ubuffer.umem, &npages, &page_shift,
958 &ncont, &offset);
959 if (err)
960 return err;
961
962 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
963 in = mlx5_vzalloc(inlen);
964 if (!in) {
965 err = -ENOMEM;
966 goto err_umem;
967 }
968
969 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
970 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
971 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
972 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
973 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
974 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
975 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
976
977 wq = MLX5_ADDR_OF(sqc, sqc, wq);
978 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
979 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
980 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
981 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
982 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
983 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
984 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
985 MLX5_SET(wq, wq, page_offset, offset);
986
987 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
988 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
989
990 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
991
992 kvfree(in);
993
994 if (err)
995 goto err_umem;
996
997 return 0;
998
999err_umem:
1000 ib_umem_release(sq->ubuffer.umem);
1001 sq->ubuffer.umem = NULL;
1002
1003 return err;
1004}
1005
1006static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1007 struct mlx5_ib_sq *sq)
1008{
1009 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1010 ib_umem_release(sq->ubuffer.umem);
1011}
1012
1013static int get_rq_pas_size(void *qpc)
1014{
1015 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1016 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1017 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1018 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1019 u32 po_quanta = 1 << (log_page_size - 6);
1020 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1021 u32 page_size = 1 << log_page_size;
1022 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1023 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1024
1025 return rq_num_pas * sizeof(u64);
1026}
1027
1028static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1029 struct mlx5_ib_rq *rq, void *qpin)
1030{
1031 __be64 *pas;
1032 __be64 *qp_pas;
1033 void *in;
1034 void *rqc;
1035 void *wq;
1036 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1037 int inlen;
1038 int err;
1039 u32 rq_pas_size = get_rq_pas_size(qpc);
1040
1041 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1042 in = mlx5_vzalloc(inlen);
1043 if (!in)
1044 return -ENOMEM;
1045
1046 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1047 MLX5_SET(rqc, rqc, vsd, 1);
1048 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1049 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1050 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1051 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1052 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1053
1054 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1055 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1056 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1057 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1058 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1059 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1060 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1061 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1062 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1063 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1064
1065 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1066 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1067 memcpy(pas, qp_pas, rq_pas_size);
1068
1069 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1070
1071 kvfree(in);
1072
1073 return err;
1074}
1075
1076static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1077 struct mlx5_ib_rq *rq)
1078{
1079 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1080}
1081
1082static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1083 struct mlx5_ib_rq *rq, u32 tdn)
1084{
1085 u32 *in;
1086 void *tirc;
1087 int inlen;
1088 int err;
1089
1090 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1091 in = mlx5_vzalloc(inlen);
1092 if (!in)
1093 return -ENOMEM;
1094
1095 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1096 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1097 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1098 MLX5_SET(tirc, tirc, transport_domain, tdn);
1099
1100 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1101
1102 kvfree(in);
1103
1104 return err;
1105}
1106
1107static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1108 struct mlx5_ib_rq *rq)
1109{
1110 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1111}
1112
1113static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1114 struct mlx5_create_qp_mbox_in *in,
1115 struct ib_pd *pd)
1116{
1117 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1118 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1119 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1120 struct ib_uobject *uobj = pd->uobject;
1121 struct ib_ucontext *ucontext = uobj->context;
1122 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1123 int err;
1124 u32 tdn = mucontext->tdn;
1125
1126 if (qp->sq.wqe_cnt) {
1127 err = create_raw_packet_qp_tis(dev, sq, tdn);
1128 if (err)
1129 return err;
1130
1131 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1132 if (err)
1133 goto err_destroy_tis;
1134
1135 sq->base.container_mibqp = qp;
1136 }
1137
1138 if (qp->rq.wqe_cnt) {
1139 err = create_raw_packet_qp_rq(dev, rq, in);
1140 if (err)
1141 goto err_destroy_sq;
1142
1143 rq->base.container_mibqp = qp;
1144
1145 err = create_raw_packet_qp_tir(dev, rq, tdn);
1146 if (err)
1147 goto err_destroy_rq;
1148 }
1149
1150 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1151 rq->base.mqp.qpn;
1152
1153 return 0;
1154
1155err_destroy_rq:
1156 destroy_raw_packet_qp_rq(dev, rq);
1157err_destroy_sq:
1158 if (!qp->sq.wqe_cnt)
1159 return err;
1160 destroy_raw_packet_qp_sq(dev, sq);
1161err_destroy_tis:
1162 destroy_raw_packet_qp_tis(dev, sq);
1163
1164 return err;
1165}
1166
1167static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1168 struct mlx5_ib_qp *qp)
1169{
1170 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1171 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1172 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1173
1174 if (qp->rq.wqe_cnt) {
1175 destroy_raw_packet_qp_tir(dev, rq);
1176 destroy_raw_packet_qp_rq(dev, rq);
1177 }
1178
1179 if (qp->sq.wqe_cnt) {
1180 destroy_raw_packet_qp_sq(dev, sq);
1181 destroy_raw_packet_qp_tis(dev, sq);
1182 }
1183}
1184
1185static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1186 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1187{
1188 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1189 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1190
1191 sq->sq = &qp->sq;
1192 rq->rq = &qp->rq;
1193 sq->doorbell = &qp->db;
1194 rq->doorbell = &qp->db;
1195}
1196
e126ba97
EC		 1197static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1198 struct ib_qp_init_attr *init_attr,
1199 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1200{
1201 struct mlx5_ib_resources *devr = &dev->devr;
938fe83c 1202 struct mlx5_core_dev *mdev = dev->mdev;
0fb2ed66 1203 struct mlx5_ib_qp_base *base;
e126ba97
EC		 1204 struct mlx5_ib_create_qp_resp resp;
1205 struct mlx5_create_qp_mbox_in *in;
1206 struct mlx5_ib_create_qp ucmd;
1207 int inlen = sizeof(*in);
1208 int err;
cfb5e088
HA		 1209 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1210 void *qpc;
e126ba97 1211
0fb2ed66 1212 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1213 &qp->raw_packet_qp.rq.base :
1214 &qp->trans_qp.base;
1215
1216 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1217 mlx5_ib_odp_create_qp(qp);
6aec21f6 1218
e126ba97
EC		 1219 mutex_init(&qp->mutex);
1220 spin_lock_init(&qp->sq.lock);
1221 spin_lock_init(&qp->rq.lock);
1222
f360d88a 1223 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1224 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1225 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1226 return -EINVAL;
1227 } else {
1228 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1229 }
1230 }
1231
051f2630
LR		 1232 if (init_attr->create_flags &
1233 (IB_QP_CREATE_CROSS_CHANNEL |
1234 IB_QP_CREATE_MANAGED_SEND |
1235 IB_QP_CREATE_MANAGED_RECV)) {
1236 if (!MLX5_CAP_GEN(mdev, cd)) {
1237 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1238 return -EINVAL;
1239 }
1240 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1241 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1242 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1243 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1244 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1245 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1246 }
f0313965
ES		 1247
1248 if (init_attr->qp_type == IB_QPT_UD &&
1249 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1250 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1251 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1252 return -EOPNOTSUPP;
1253 }
1254
e126ba97
EC		 1255 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1256 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1257
1258 if (pd && pd->uobject) {
1259 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1260 mlx5_ib_dbg(dev, "copy failed\n");
1261 return -EFAULT;
1262 }
1263
cfb5e088
HA		 1264 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1265 &ucmd, udata->inlen, &uidx);
1266 if (err)
1267 return err;
1268
e126ba97
EC		 1269 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1270 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1271 } else {
1272 qp->wq_sig = !!wq_signature;
1273 }
1274
1275 qp->has_rq = qp_has_rq(init_attr);
1276 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1277 qp, (pd && pd->uobject) ? &ucmd : NULL);
1278 if (err) {
1279 mlx5_ib_dbg(dev, "err %d\n", err);
1280 return err;
1281 }
1282
1283 if (pd) {
1284 if (pd->uobject) {
938fe83c
SM		 1285 __u32 max_wqes =
1286 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1287 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1288 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1289 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1290 mlx5_ib_dbg(dev, "invalid rq params\n");
1291 return -EINVAL;
1292 }
938fe83c 1293 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1294 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1295 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1296 return -EINVAL;
1297 }
b11a4f9c
HE		 1298 if (init_attr->create_flags &
1299 mlx5_ib_create_qp_sqpn_qp1()) {
1300 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1301 return -EINVAL;
1302 }
0fb2ed66 1303 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1304 &resp, &inlen, base);
e126ba97
EC		 1305 if (err)
1306 mlx5_ib_dbg(dev, "err %d\n", err);
1307 } else {
19098df2 1308 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1309 base);
e126ba97
EC		 1310 if (err)
1311 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1312 }
1313
1314 if (err)
1315 return err;
1316 } else {
1317 in = mlx5_vzalloc(sizeof(*in));
1318 if (!in)
1319 return -ENOMEM;
1320
1321 qp->create_type = MLX5_QP_EMPTY;
1322 }
1323
1324 if (is_sqp(init_attr->qp_type))
1325 qp->port = init_attr->port_num;
1326
1327 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1328 MLX5_QP_PM_MIGRATED << 11);
1329
1330 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1331 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1332 else
1333 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1334
1335 if (qp->wq_sig)
1336 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1337
f360d88a
EC		 1338 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1339 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1340
051f2630
LR		 1341 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1342 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1343 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1344 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1345 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1346 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1347
e126ba97
EC		 1348 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1349 int rcqe_sz;
1350 int scqe_sz;
1351
1352 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1353 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1354
1355 if (rcqe_sz == 128)
1356 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1357 else
1358 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1359
1360 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1361 if (scqe_sz == 128)
1362 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1363 else
1364 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1365 }
1366 }
1367
1368 if (qp->rq.wqe_cnt) {
1369 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1370 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1371 }
1372
1373 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1374
1375 if (qp->sq.wqe_cnt)
1376 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1377 else
1378 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1379
1380 /* Set default resources */
1381 switch (init_attr->qp_type) {
1382 case IB_QPT_XRC_TGT:
1383 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1384 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1385 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1386 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1387 break;
1388 case IB_QPT_XRC_INI:
1389 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1390 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1391 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1392 break;
1393 default:
1394 if (init_attr->srq) {
1395 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1396 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1397 } else {
1398 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
4aa17b28
HA		 1399 in->ctx.rq_type_srqn |=
1400 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1401 }
1402 }
1403
1404 if (init_attr->send_cq)
1405 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1406
1407 if (init_attr->recv_cq)
1408 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1409
1410 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1411
cfb5e088
HA		 1412 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1413 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1414 /* 0xffffff means we ask to work with cqe version 0 */
1415 MLX5_SET(qpc, qpc, user_index, uidx);
1416 }
f0313965
ES		 1417 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1418 if (init_attr->qp_type == IB_QPT_UD &&
1419 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1420 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1421 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1422 qp->flags |= MLX5_IB_QP_LSO;
1423 }
cfb5e088 1424
0fb2ed66 1425 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1426 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1427 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1428 err = create_raw_packet_qp(dev, qp, in, pd);
1429 } else {
1430 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1431 }
1432
e126ba97
EC		 1433 if (err) {
1434 mlx5_ib_dbg(dev, "create qp failed\n");
1435 goto err_create;
1436 }
1437
479163f4 1438 kvfree(in);
e126ba97 1439
19098df2 1440 base->container_mibqp = qp;
1441 base->mqp.event = mlx5_ib_qp_event;
e126ba97
EC		 1442
1443 return 0;
1444
1445err_create:
1446 if (qp->create_type == MLX5_QP_USER)
19098df2 1447 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1448 else if (qp->create_type == MLX5_QP_KERNEL)
1449 destroy_qp_kernel(dev, qp);
1450
479163f4 1451 kvfree(in);
e126ba97
EC		 1452 return err;
1453}
1454
1455static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1456 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1457{
1458 if (send_cq) {
1459 if (recv_cq) {
1460 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1461 spin_lock_irq(&send_cq->lock);
1462 spin_lock_nested(&recv_cq->lock,
1463 SINGLE_DEPTH_NESTING);
1464 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1465 spin_lock_irq(&send_cq->lock);
1466 __acquire(&recv_cq->lock);
1467 } else {
1468 spin_lock_irq(&recv_cq->lock);
1469 spin_lock_nested(&send_cq->lock,
1470 SINGLE_DEPTH_NESTING);
1471 }
1472 } else {
1473 spin_lock_irq(&send_cq->lock);
6a4f139a 1474 __acquire(&recv_cq->lock);
e126ba97
EC		 1475 }
1476 } else if (recv_cq) {
1477 spin_lock_irq(&recv_cq->lock);
6a4f139a
EC		 1478 __acquire(&send_cq->lock);
1479 } else {
1480 __acquire(&send_cq->lock);
1481 __acquire(&recv_cq->lock);
e126ba97
EC		 1482 }
1483}
1484
1485static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1486 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1487{
1488 if (send_cq) {
1489 if (recv_cq) {
1490 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1491 spin_unlock(&recv_cq->lock);
1492 spin_unlock_irq(&send_cq->lock);
1493 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1494 __release(&recv_cq->lock);
1495 spin_unlock_irq(&send_cq->lock);
1496 } else {
1497 spin_unlock(&send_cq->lock);
1498 spin_unlock_irq(&recv_cq->lock);
1499 }
1500 } else {
6a4f139a 1501 __release(&recv_cq->lock);
e126ba97
EC		 1502 spin_unlock_irq(&send_cq->lock);
1503 }
1504 } else if (recv_cq) {
6a4f139a 1505 __release(&send_cq->lock);
e126ba97 1506 spin_unlock_irq(&recv_cq->lock);
6a4f139a
EC		 1507 } else {
1508 __release(&recv_cq->lock);
1509 __release(&send_cq->lock);
e126ba97
EC		 1510 }
1511}
1512
1513static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1514{
1515 return to_mpd(qp->ibqp.pd);
1516}
1517
1518static void get_cqs(struct mlx5_ib_qp *qp,
1519 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1520{
1521 switch (qp->ibqp.qp_type) {
1522 case IB_QPT_XRC_TGT:
1523 *send_cq = NULL;
1524 *recv_cq = NULL;
1525 break;
1526 case MLX5_IB_QPT_REG_UMR:
1527 case IB_QPT_XRC_INI:
1528 *send_cq = to_mcq(qp->ibqp.send_cq);
1529 *recv_cq = NULL;
1530 break;
1531
1532 case IB_QPT_SMI:
1533 case IB_QPT_GSI:
1534 case IB_QPT_RC:
1535 case IB_QPT_UC:
1536 case IB_QPT_UD:
1537 case IB_QPT_RAW_IPV6:
1538 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1539 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1540 *send_cq = to_mcq(qp->ibqp.send_cq);
1541 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1542 break;
1543
e126ba97
EC		 1544 case IB_QPT_MAX:
1545 default:
1546 *send_cq = NULL;
1547 *recv_cq = NULL;
1548 break;
1549 }
1550}
1551
ad5f8e96 1552static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1553 u16 operation);
1554
e126ba97
EC		 1555static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1556{
1557 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1558 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
0fb2ed66 1559 struct mlx5_modify_qp_mbox_in *in;
e126ba97
EC		 1560 int err;
1561
0fb2ed66 1562 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1563 &qp->raw_packet_qp.rq.base :
1564 &qp->trans_qp.base;
1565
e126ba97
EC		 1566 in = kzalloc(sizeof(*in), GFP_KERNEL);
1567 if (!in)
1568 return;
7bef7ad2 1569
6aec21f6 1570 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1571 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1572 mlx5_ib_qp_disable_pagefaults(qp);
1573 err = mlx5_core_qp_modify(dev->mdev,
1574 MLX5_CMD_OP_2RST_QP, in, 0,
1575 &base->mqp);
1576 } else {
1577 err = modify_raw_packet_qp(dev, qp,
1578 MLX5_CMD_OP_2RST_QP);
1579 }
1580 if (err)
427c1e7b 1581 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1582 base->mqp.qpn);
6aec21f6 1583 }
e126ba97
EC		 1584
1585 get_cqs(qp, &send_cq, &recv_cq);
1586
1587 if (qp->create_type == MLX5_QP_KERNEL) {
1588 mlx5_ib_lock_cqs(send_cq, recv_cq);
19098df2 1589 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1590 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1591 if (send_cq != recv_cq)
19098df2 1592 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1593 NULL);
e126ba97
EC		 1594 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1595 }
1596
0fb2ed66 1597 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1598 destroy_raw_packet_qp(dev, qp);
1599 } else {
1600 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1601 if (err)
1602 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1603 base->mqp.qpn);
1604 }
e126ba97 1605
0fb2ed66 1606 kfree(in);
e126ba97
EC		 1607
1608 if (qp->create_type == MLX5_QP_KERNEL)
1609 destroy_qp_kernel(dev, qp);
1610 else if (qp->create_type == MLX5_QP_USER)
19098df2 1611 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1612}
1613
1614static const char *ib_qp_type_str(enum ib_qp_type type)
1615{
1616 switch (type) {
1617 case IB_QPT_SMI:
1618 return "IB_QPT_SMI";
1619 case IB_QPT_GSI:
1620 return "IB_QPT_GSI";
1621 case IB_QPT_RC:
1622 return "IB_QPT_RC";
1623 case IB_QPT_UC:
1624 return "IB_QPT_UC";
1625 case IB_QPT_UD:
1626 return "IB_QPT_UD";
1627 case IB_QPT_RAW_IPV6:
1628 return "IB_QPT_RAW_IPV6";
1629 case IB_QPT_RAW_ETHERTYPE:
1630 return "IB_QPT_RAW_ETHERTYPE";
1631 case IB_QPT_XRC_INI:
1632 return "IB_QPT_XRC_INI";
1633 case IB_QPT_XRC_TGT:
1634 return "IB_QPT_XRC_TGT";
1635 case IB_QPT_RAW_PACKET:
1636 return "IB_QPT_RAW_PACKET";
1637 case MLX5_IB_QPT_REG_UMR:
1638 return "MLX5_IB_QPT_REG_UMR";
1639 case IB_QPT_MAX:
1640 default:
1641 return "Invalid QP type";
1642 }
1643}
1644
1645struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1646 struct ib_qp_init_attr *init_attr,
1647 struct ib_udata *udata)
1648{
1649 struct mlx5_ib_dev *dev;
1650 struct mlx5_ib_qp *qp;
1651 u16 xrcdn = 0;
1652 int err;
1653
1654 if (pd) {
1655 dev = to_mdev(pd->device);
0fb2ed66 1656
1657 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1658 if (!pd->uobject) {
1659 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1660 return ERR_PTR(-EINVAL);
1661 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1662 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1663 return ERR_PTR(-EINVAL);
1664 }
1665 }
09f16cf5
MD		 1666 } else {
1667 /* being cautious here */
1668 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1669 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1670 pr_warn("%s: no PD for transport %s\n", __func__,
1671 ib_qp_type_str(init_attr->qp_type));
1672 return ERR_PTR(-EINVAL);
1673 }
1674 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 1675 }
1676
1677 switch (init_attr->qp_type) {
1678 case IB_QPT_XRC_TGT:
1679 case IB_QPT_XRC_INI:
938fe83c 1680 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 1681 mlx5_ib_dbg(dev, "XRC not supported\n");
1682 return ERR_PTR(-ENOSYS);
1683 }
1684 init_attr->recv_cq = NULL;
1685 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1686 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1687 init_attr->send_cq = NULL;
1688 }
1689
1690 /* fall through */
0fb2ed66 1691 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1692 case IB_QPT_RC:
1693 case IB_QPT_UC:
1694 case IB_QPT_UD:
1695 case IB_QPT_SMI:
1696 case IB_QPT_GSI:
1697 case MLX5_IB_QPT_REG_UMR:
1698 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1699 if (!qp)
1700 return ERR_PTR(-ENOMEM);
1701
1702 err = create_qp_common(dev, pd, init_attr, udata, qp);
1703 if (err) {
1704 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1705 kfree(qp);
1706 return ERR_PTR(err);
1707 }
1708
1709 if (is_qp0(init_attr->qp_type))
1710 qp->ibqp.qp_num = 0;
1711 else if (is_qp1(init_attr->qp_type))
1712 qp->ibqp.qp_num = 1;
1713 else
19098df2 1714 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 1715
1716 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 1717 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1718 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 1719 to_mcq(init_attr->send_cq)->mcq.cqn);
1720
19098df2 1721 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 1722
1723 break;
1724
1725 case IB_QPT_RAW_IPV6:
1726 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 1727 case IB_QPT_MAX:
1728 default:
1729 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1730 init_attr->qp_type);
1731 /* Don't support raw QPs */
1732 return ERR_PTR(-EINVAL);
1733 }
1734
1735 return &qp->ibqp;
1736}
1737
1738int mlx5_ib_destroy_qp(struct ib_qp *qp)
1739{
1740 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1741 struct mlx5_ib_qp *mqp = to_mqp(qp);
1742
1743 destroy_qp_common(dev, mqp);
1744
1745 kfree(mqp);
1746
1747 return 0;
1748}
1749
1750static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1751 int attr_mask)
1752{
1753 u32 hw_access_flags = 0;
1754 u8 dest_rd_atomic;
1755 u32 access_flags;
1756
1757 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1758 dest_rd_atomic = attr->max_dest_rd_atomic;
1759 else
19098df2 1760 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 1761
1762 if (attr_mask & IB_QP_ACCESS_FLAGS)
1763 access_flags = attr->qp_access_flags;
1764 else
19098df2 1765 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 1766
1767 if (!dest_rd_atomic)
1768 access_flags &= IB_ACCESS_REMOTE_WRITE;
1769
1770 if (access_flags & IB_ACCESS_REMOTE_READ)
1771 hw_access_flags |= MLX5_QP_BIT_RRE;
1772 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1773 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1774 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1775 hw_access_flags |= MLX5_QP_BIT_RWE;
1776
1777 return cpu_to_be32(hw_access_flags);
1778}
1779
1780enum {
1781 MLX5_PATH_FLAG_FL = 1 << 0,
1782 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1783 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1784};
1785
1786static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1787{
1788 if (rate == IB_RATE_PORT_CURRENT) {
1789 return 0;
1790 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1791 return -EINVAL;
1792 } else {
1793 while (rate != IB_RATE_2_5_GBPS &&
1794 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 1795 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 1796 --rate;
1797 }
1798
1799 return rate + MLX5_STAT_RATE_OFFSET;
1800}
1801
75850d0b 1802static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1803 struct mlx5_ib_sq *sq, u8 sl)
1804{
1805 void *in;
1806 void *tisc;
1807 int inlen;
1808 int err;
1809
1810 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1811 in = mlx5_vzalloc(inlen);
1812 if (!in)
1813 return -ENOMEM;
1814
1815 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1816
1817 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
1818 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
1819
1820 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
1821
1822 kvfree(in);
1823
1824 return err;
1825}
1826
1827static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1828 const struct ib_ah_attr *ah,
e126ba97
EC		 1829 struct mlx5_qp_path *path, u8 port, int attr_mask,
1830 u32 path_flags, const struct ib_qp_attr *attr)
1831{
2811ba51 1832 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 1833 int err;
1834
e126ba97
EC		 1835 if (attr_mask & IB_QP_PKEY_INDEX)
1836 path->pkey_index = attr->pkey_index;
1837
e126ba97 1838 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 1839 if (ah->grh.sgid_index >=
1840 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 1841 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 1842 ah->grh.sgid_index,
1843 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 1844 return -EINVAL;
1845 }
2811ba51
AS		 1846 }
1847
1848 if (ll == IB_LINK_LAYER_ETHERNET) {
1849 if (!(ah->ah_flags & IB_AH_GRH))
1850 return -EINVAL;
1851 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
1852 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
1853 ah->grh.sgid_index);
1854 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
1855 } else {
1856 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1857 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 :
1858 0;
1859 path->rlid = cpu_to_be16(ah->dlid);
1860 path->grh_mlid = ah->src_path_bits & 0x7f;
1861 if (ah->ah_flags & IB_AH_GRH)
1862 path->grh_mlid |= 1 << 7;
1863 path->dci_cfi_prio_sl = ah->sl & 0xf;
1864 }
1865
1866 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 1867 path->mgid_index = ah->grh.sgid_index;
1868 path->hop_limit = ah->grh.hop_limit;
1869 path->tclass_flowlabel =
1870 cpu_to_be32((ah->grh.traffic_class << 20) |
1871 (ah->grh.flow_label));
1872 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1873 }
1874
1875 err = ib_rate_to_mlx5(dev, ah->static_rate);
1876 if (err < 0)
1877 return err;
1878 path->static_rate = err;
1879 path->port = port;
1880
e126ba97
EC		 1881 if (attr_mask & IB_QP_TIMEOUT)
1882 path->ackto_lt = attr->timeout << 3;
1883
75850d0b 1884 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
1885 return modify_raw_packet_eth_prio(dev->mdev,
1886 &qp->raw_packet_qp.sq,
1887 ah->sl & 0xf);
1888
e126ba97
EC		 1889 return 0;
1890}
1891
1892static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1893 [MLX5_QP_STATE_INIT] = {
1894 [MLX5_QP_STATE_INIT] = {
1895 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1896 MLX5_QP_OPTPAR_RAE |
1897 MLX5_QP_OPTPAR_RWE |
1898 MLX5_QP_OPTPAR_PKEY_INDEX |
1899 MLX5_QP_OPTPAR_PRI_PORT,
1900 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1901 MLX5_QP_OPTPAR_PKEY_INDEX |
1902 MLX5_QP_OPTPAR_PRI_PORT,
1903 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1904 MLX5_QP_OPTPAR_Q_KEY |
1905 MLX5_QP_OPTPAR_PRI_PORT,
1906 },
1907 [MLX5_QP_STATE_RTR] = {
1908 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1909 MLX5_QP_OPTPAR_RRE |
1910 MLX5_QP_OPTPAR_RAE |
1911 MLX5_QP_OPTPAR_RWE |
1912 MLX5_QP_OPTPAR_PKEY_INDEX,
1913 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1914 MLX5_QP_OPTPAR_RWE |
1915 MLX5_QP_OPTPAR_PKEY_INDEX,
1916 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1917 MLX5_QP_OPTPAR_Q_KEY,
1918 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1919 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 1920 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1921 MLX5_QP_OPTPAR_RRE |
1922 MLX5_QP_OPTPAR_RAE |
1923 MLX5_QP_OPTPAR_RWE |
1924 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 1925 },
1926 },
1927 [MLX5_QP_STATE_RTR] = {
1928 [MLX5_QP_STATE_RTS] = {
1929 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1930 MLX5_QP_OPTPAR_RRE |
1931 MLX5_QP_OPTPAR_RAE |
1932 MLX5_QP_OPTPAR_RWE |
1933 MLX5_QP_OPTPAR_PM_STATE |
1934 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1935 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1936 MLX5_QP_OPTPAR_RWE |
1937 MLX5_QP_OPTPAR_PM_STATE,
1938 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1939 },
1940 },
1941 [MLX5_QP_STATE_RTS] = {
1942 [MLX5_QP_STATE_RTS] = {
1943 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1944 MLX5_QP_OPTPAR_RAE |
1945 MLX5_QP_OPTPAR_RWE |
1946 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 1947 MLX5_QP_OPTPAR_PM_STATE |
1948 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 1949 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 1950 MLX5_QP_OPTPAR_PM_STATE |
1951 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 1952 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1953 MLX5_QP_OPTPAR_SRQN |
1954 MLX5_QP_OPTPAR_CQN_RCV,
1955 },
1956 },
1957 [MLX5_QP_STATE_SQER] = {
1958 [MLX5_QP_STATE_RTS] = {
1959 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1960 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 1961 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 1962 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1963 MLX5_QP_OPTPAR_RWE |
1964 MLX5_QP_OPTPAR_RAE |
1965 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 1966 },
1967 },
1968};
1969
1970static int ib_nr_to_mlx5_nr(int ib_mask)
1971{
1972 switch (ib_mask) {
1973 case IB_QP_STATE:
1974 return 0;
1975 case IB_QP_CUR_STATE:
1976 return 0;
1977 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1978 return 0;
1979 case IB_QP_ACCESS_FLAGS:
1980 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1981 MLX5_QP_OPTPAR_RAE;
1982 case IB_QP_PKEY_INDEX:
1983 return MLX5_QP_OPTPAR_PKEY_INDEX;
1984 case IB_QP_PORT:
1985 return MLX5_QP_OPTPAR_PRI_PORT;
1986 case IB_QP_QKEY:
1987 return MLX5_QP_OPTPAR_Q_KEY;
1988 case IB_QP_AV:
1989 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1990 MLX5_QP_OPTPAR_PRI_PORT;
1991 case IB_QP_PATH_MTU:
1992 return 0;
1993 case IB_QP_TIMEOUT:
1994 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1995 case IB_QP_RETRY_CNT:
1996 return MLX5_QP_OPTPAR_RETRY_COUNT;
1997 case IB_QP_RNR_RETRY:
1998 return MLX5_QP_OPTPAR_RNR_RETRY;
1999 case IB_QP_RQ_PSN:
2000 return 0;
2001 case IB_QP_MAX_QP_RD_ATOMIC:
2002 return MLX5_QP_OPTPAR_SRA_MAX;
2003 case IB_QP_ALT_PATH:
2004 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2005 case IB_QP_MIN_RNR_TIMER:
2006 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2007 case IB_QP_SQ_PSN:
2008 return 0;
2009 case IB_QP_MAX_DEST_RD_ATOMIC:
2010 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2011 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2012 case IB_QP_PATH_MIG_STATE:
2013 return MLX5_QP_OPTPAR_PM_STATE;
2014 case IB_QP_CAP:
2015 return 0;
2016 case IB_QP_DEST_QPN:
2017 return 0;
2018 }
2019 return 0;
2020}
2021
2022static int ib_mask_to_mlx5_opt(int ib_mask)
2023{
2024 int result = 0;
2025 int i;
2026
2027 for (i = 0; i < 8 * sizeof(int); i++) {
2028 if ((1 << i) & ib_mask)
2029 result |= ib_nr_to_mlx5_nr(1 << i);
2030 }
2031
2032 return result;
2033}
2034
ad5f8e96 2035static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2036 struct mlx5_ib_rq *rq, int new_state)
2037{
2038 void *in;
2039 void *rqc;
2040 int inlen;
2041 int err;
2042
2043 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2044 in = mlx5_vzalloc(inlen);
2045 if (!in)
2046 return -ENOMEM;
2047
2048 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2049
2050 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2051 MLX5_SET(rqc, rqc, state, new_state);
2052
2053 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2054 if (err)
2055 goto out;
2056
2057 rq->state = new_state;
2058
2059out:
2060 kvfree(in);
2061 return err;
2062}
2063
2064static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2065 struct mlx5_ib_sq *sq, int new_state)
2066{
2067 void *in;
2068 void *sqc;
2069 int inlen;
2070 int err;
2071
2072 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2073 in = mlx5_vzalloc(inlen);
2074 if (!in)
2075 return -ENOMEM;
2076
2077 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2078
2079 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2080 MLX5_SET(sqc, sqc, state, new_state);
2081
2082 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2083 if (err)
2084 goto out;
2085
2086 sq->state = new_state;
2087
2088out:
2089 kvfree(in);
2090 return err;
2091}
2092
2093static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2094 u16 operation)
2095{
2096 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2097 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2098 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2099 int rq_state;
2100 int sq_state;
2101 int err;
2102
2103 switch (operation) {
2104 case MLX5_CMD_OP_RST2INIT_QP:
2105 rq_state = MLX5_RQC_STATE_RDY;
2106 sq_state = MLX5_SQC_STATE_RDY;
2107 break;
2108 case MLX5_CMD_OP_2ERR_QP:
2109 rq_state = MLX5_RQC_STATE_ERR;
2110 sq_state = MLX5_SQC_STATE_ERR;
2111 break;
2112 case MLX5_CMD_OP_2RST_QP:
2113 rq_state = MLX5_RQC_STATE_RST;
2114 sq_state = MLX5_SQC_STATE_RST;
2115 break;
2116 case MLX5_CMD_OP_INIT2INIT_QP:
2117 case MLX5_CMD_OP_INIT2RTR_QP:
2118 case MLX5_CMD_OP_RTR2RTS_QP:
2119 case MLX5_CMD_OP_RTS2RTS_QP:
2120 /* Nothing to do here... */
2121 return 0;
2122 default:
2123 WARN_ON(1);
2124 return -EINVAL;
2125 }
2126
2127 if (qp->rq.wqe_cnt) {
2128 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2129 if (err)
2130 return err;
2131 }
2132
2133 if (qp->sq.wqe_cnt)
2134 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2135
2136 return 0;
2137}
2138
e126ba97
EC		 2139static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2140 const struct ib_qp_attr *attr, int attr_mask,
2141 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2142{
427c1e7b 2143 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2144 [MLX5_QP_STATE_RST] = {
2145 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2146 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2147 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2148 },
2149 [MLX5_QP_STATE_INIT] = {
2150 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2151 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2152 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2153 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2154 },
2155 [MLX5_QP_STATE_RTR] = {
2156 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2157 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2158 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2159 },
2160 [MLX5_QP_STATE_RTS] = {
2161 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2162 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2163 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2164 },
2165 [MLX5_QP_STATE_SQD] = {
2166 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2167 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2168 },
2169 [MLX5_QP_STATE_SQER] = {
2170 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2171 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2172 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2173 },
2174 [MLX5_QP_STATE_ERR] = {
2175 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2176 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2177 }
2178 };
2179
e126ba97
EC		 2180 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2181 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2182 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2183 struct mlx5_ib_cq *send_cq, *recv_cq;
2184 struct mlx5_qp_context *context;
2185 struct mlx5_modify_qp_mbox_in *in;
2186 struct mlx5_ib_pd *pd;
2187 enum mlx5_qp_state mlx5_cur, mlx5_new;
2188 enum mlx5_qp_optpar optpar;
2189 int sqd_event;
2190 int mlx5_st;
2191 int err;
427c1e7b 2192 u16 op;
e126ba97
EC		 2193
2194 in = kzalloc(sizeof(*in), GFP_KERNEL);
2195 if (!in)
2196 return -ENOMEM;
2197
2198 context = &in->ctx;
2199 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2200 if (err < 0) {
2201 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2202 goto out;
158abf86 2203 }
e126ba97
EC		 2204
2205 context->flags = cpu_to_be32(err << 16);
2206
2207 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2208 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2209 } else {
2210 switch (attr->path_mig_state) {
2211 case IB_MIG_MIGRATED:
2212 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2213 break;
2214 case IB_MIG_REARM:
2215 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2216 break;
2217 case IB_MIG_ARMED:
2218 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2219 break;
2220 }
2221 }
2222
2223 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
2224 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2225 } else if (ibqp->qp_type == IB_QPT_UD ||
2226 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2227 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2228 } else if (attr_mask & IB_QP_PATH_MTU) {
2229 if (attr->path_mtu < IB_MTU_256 ||
2230 attr->path_mtu > IB_MTU_4096) {
2231 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2232 err = -EINVAL;
2233 goto out;
2234 }
938fe83c
SM		 2235 context->mtu_msgmax = (attr->path_mtu << 5) |
2236 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2237 }
2238
2239 if (attr_mask & IB_QP_DEST_QPN)
2240 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2241
2242 if (attr_mask & IB_QP_PKEY_INDEX)
2243 context->pri_path.pkey_index = attr->pkey_index;
2244
2245 /* todo implement counter_index functionality */
2246
2247 if (is_sqp(ibqp->qp_type))
2248 context->pri_path.port = qp->port;
2249
2250 if (attr_mask & IB_QP_PORT)
2251 context->pri_path.port = attr->port_num;
2252
2253 if (attr_mask & IB_QP_AV) {
75850d0b 2254 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97
EC		 2255 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2256 attr_mask, 0, attr);
2257 if (err)
2258 goto out;
2259 }
2260
2261 if (attr_mask & IB_QP_TIMEOUT)
2262 context->pri_path.ackto_lt |= attr->timeout << 3;
2263
2264 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2265 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2266 &context->alt_path,
e126ba97
EC		 2267 attr->alt_port_num, attr_mask, 0, attr);
2268 if (err)
2269 goto out;
2270 }
2271
2272 pd = get_pd(qp);
2273 get_cqs(qp, &send_cq, &recv_cq);
2274
2275 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2276 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2277 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2278 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2279
2280 if (attr_mask & IB_QP_RNR_RETRY)
2281 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2282
2283 if (attr_mask & IB_QP_RETRY_CNT)
2284 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2285
2286 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2287 if (attr->max_rd_atomic)
2288 context->params1 |=
2289 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2290 }
2291
2292 if (attr_mask & IB_QP_SQ_PSN)
2293 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2294
2295 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2296 if (attr->max_dest_rd_atomic)
2297 context->params2 |=
2298 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2299 }
2300
2301 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2302 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2303
2304 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2305 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2306
2307 if (attr_mask & IB_QP_RQ_PSN)
2308 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2309
2310 if (attr_mask & IB_QP_QKEY)
2311 context->qkey = cpu_to_be32(attr->qkey);
2312
2313 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2314 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2315
2316 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2317 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2318 sqd_event = 1;
2319 else
2320 sqd_event = 0;
2321
2322 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2323 context->sq_crq_size |= cpu_to_be16(1 << 4);
2324
b11a4f9c
HE		 2325 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2326 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2327
2328 mlx5_cur = to_mlx5_state(cur_state);
2329 mlx5_new = to_mlx5_state(new_state);
2330 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2331 if (mlx5_st < 0)
e126ba97
EC		 2332 goto out;
2333
6aec21f6
HE		 2334 /* If moving to a reset or error state, we must disable page faults on
2335 * this QP and flush all current page faults. Otherwise a stale page
2336 * fault may attempt to work on this QP after it is reset and moved
2337 * again to RTS, and may cause the driver and the device to get out of
2338 * sync. */
2339 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2340 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2341 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2342 mlx5_ib_qp_disable_pagefaults(qp);
2343
427c1e7b 2344 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2345 !optab[mlx5_cur][mlx5_new])
2346 goto out;
2347
2348 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2349 optpar = ib_mask_to_mlx5_opt(attr_mask);
2350 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2351 in->optparam = cpu_to_be32(optpar);
ad5f8e96 2352
2353 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2354 err = modify_raw_packet_qp(dev, qp, op);
2355 else
2356 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2357 &base->mqp);
e126ba97
EC		 2358 if (err)
2359 goto out;
2360
ad5f8e96 2361 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2362 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2363 mlx5_ib_qp_enable_pagefaults(qp);
2364
e126ba97
EC		 2365 qp->state = new_state;
2366
2367 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2368 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2369 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2370 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2371 if (attr_mask & IB_QP_PORT)
2372 qp->port = attr->port_num;
2373 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2374 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2375
2376 /*
2377 * If we moved a kernel QP to RESET, clean up all old CQ
2378 * entries and reinitialize the QP.
2379 */
2380 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2381 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2382 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2383 if (send_cq != recv_cq)
19098df2 2384 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2385
2386 qp->rq.head = 0;
2387 qp->rq.tail = 0;
2388 qp->sq.head = 0;
2389 qp->sq.tail = 0;
2390 qp->sq.cur_post = 0;
2391 qp->sq.last_poll = 0;
2392 qp->db.db[MLX5_RCV_DBR] = 0;
2393 qp->db.db[MLX5_SND_DBR] = 0;
2394 }
2395
2396out:
2397 kfree(in);
2398 return err;
2399}
2400
2401int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2402 int attr_mask, struct ib_udata *udata)
2403{
2404 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2405 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2406 enum ib_qp_state cur_state, new_state;
2407 int err = -EINVAL;
2408 int port;
2811ba51 2409 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97
EC		 2410
2411 mutex_lock(&qp->mutex);
2412
2413 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2414 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2415
2811ba51
AS		 2416 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2417 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2418 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2419 }
2420
e126ba97 2421 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
dd5f03be 2422 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
158abf86
HE		 2423 ll)) {
2424 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2425 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2426 goto out;
158abf86 2427 }
e126ba97
EC		 2428
2429 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2430 (attr->port_num == 0 ||
158abf86
HE		 2431 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2432 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2433 attr->port_num, dev->num_ports);
e126ba97 2434 goto out;
158abf86 2435 }
e126ba97
EC		 2436
2437 if (attr_mask & IB_QP_PKEY_INDEX) {
2438 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2439 if (attr->pkey_index >=
158abf86
HE		 2440 dev->mdev->port_caps[port - 1].pkey_table_len) {
2441 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2442 attr->pkey_index);
e126ba97 2443 goto out;
158abf86 2444 }
e126ba97
EC		 2445 }
2446
2447 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2448 attr->max_rd_atomic >
158abf86
HE		 2449 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2450 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2451 attr->max_rd_atomic);
e126ba97 2452 goto out;
158abf86 2453 }
e126ba97
EC		 2454
2455 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2456 attr->max_dest_rd_atomic >
158abf86
HE		 2457 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2458 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2459 attr->max_dest_rd_atomic);
e126ba97 2460 goto out;
158abf86 2461 }
e126ba97
EC		 2462
2463 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2464 err = 0;
2465 goto out;
2466 }
2467
2468 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2469
2470out:
2471 mutex_unlock(&qp->mutex);
2472 return err;
2473}
2474
2475static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2476{
2477 struct mlx5_ib_cq *cq;
2478 unsigned cur;
2479
2480 cur = wq->head - wq->tail;
2481 if (likely(cur + nreq < wq->max_post))
2482 return 0;
2483
2484 cq = to_mcq(ib_cq);
2485 spin_lock(&cq->lock);
2486 cur = wq->head - wq->tail;
2487 spin_unlock(&cq->lock);
2488
2489 return cur + nreq >= wq->max_post;
2490}
2491
2492static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2493 u64 remote_addr, u32 rkey)
2494{
2495 rseg->raddr = cpu_to_be64(remote_addr);
2496 rseg->rkey = cpu_to_be32(rkey);
2497 rseg->reserved = 0;
2498}
2499
f0313965
ES		 2500static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2501 struct ib_send_wr *wr, void *qend,
2502 struct mlx5_ib_qp *qp, int *size)
2503{
2504 void *seg = eseg;
2505
2506 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2507
2508 if (wr->send_flags & IB_SEND_IP_CSUM)
2509 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2510 MLX5_ETH_WQE_L4_CSUM;
2511
2512 seg += sizeof(struct mlx5_wqe_eth_seg);
2513 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2514
2515 if (wr->opcode == IB_WR_LSO) {
2516 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2517 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2518 u64 left, leftlen, copysz;
2519 void *pdata = ud_wr->header;
2520
2521 left = ud_wr->hlen;
2522 eseg->mss = cpu_to_be16(ud_wr->mss);
2523 eseg->inline_hdr_sz = cpu_to_be16(left);
2524
2525 /*
2526 * check if there is space till the end of queue, if yes,
2527 * copy all in one shot, otherwise copy till the end of queue,
2528 * rollback and than the copy the left
2529 */
2530 leftlen = qend - (void *)eseg->inline_hdr_start;
2531 copysz = min_t(u64, leftlen, left);
2532
2533 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2534
2535 if (likely(copysz > size_of_inl_hdr_start)) {
2536 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2537 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2538 }
2539
2540 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2541 seg = mlx5_get_send_wqe(qp, 0);
2542 left -= copysz;
2543 pdata += copysz;
2544 memcpy(seg, pdata, left);
2545 seg += ALIGN(left, 16);
2546 *size += ALIGN(left, 16) / 16;
2547 }
2548 }
2549
2550 return seg;
2551}
2552
e126ba97
EC		 2553static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2554 struct ib_send_wr *wr)
2555{
e622f2f4
CH		 2556 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2557 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2558 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2559}
2560
2561static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2562{
2563 dseg->byte_count = cpu_to_be32(sg->length);
2564 dseg->lkey = cpu_to_be32(sg->lkey);
2565 dseg->addr = cpu_to_be64(sg->addr);
2566}
2567
2568static __be16 get_klm_octo(int npages)
2569{
2570 return cpu_to_be16(ALIGN(npages, 8) / 2);
2571}
2572
2573static __be64 frwr_mkey_mask(void)
2574{
2575 u64 result;
2576
2577 result = MLX5_MKEY_MASK_LEN |
2578 MLX5_MKEY_MASK_PAGE_SIZE |
2579 MLX5_MKEY_MASK_START_ADDR |
2580 MLX5_MKEY_MASK_EN_RINVAL |
2581 MLX5_MKEY_MASK_KEY |
2582 MLX5_MKEY_MASK_LR |
2583 MLX5_MKEY_MASK_LW |
2584 MLX5_MKEY_MASK_RR |
2585 MLX5_MKEY_MASK_RW |
2586 MLX5_MKEY_MASK_A |
2587 MLX5_MKEY_MASK_SMALL_FENCE |
2588 MLX5_MKEY_MASK_FREE;
2589
2590 return cpu_to_be64(result);
2591}
2592
e6631814
SG		 2593static __be64 sig_mkey_mask(void)
2594{
2595 u64 result;
2596
2597 result = MLX5_MKEY_MASK_LEN |
2598 MLX5_MKEY_MASK_PAGE_SIZE |
2599 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2600 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2601 MLX5_MKEY_MASK_EN_RINVAL |
2602 MLX5_MKEY_MASK_KEY |
2603 MLX5_MKEY_MASK_LR |
2604 MLX5_MKEY_MASK_LW |
2605 MLX5_MKEY_MASK_RR |
2606 MLX5_MKEY_MASK_RW |
2607 MLX5_MKEY_MASK_SMALL_FENCE |
2608 MLX5_MKEY_MASK_FREE |
2609 MLX5_MKEY_MASK_BSF_EN;
2610
2611 return cpu_to_be64(result);
2612}
2613
8a187ee5
SG		 2614static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2615 struct mlx5_ib_mr *mr)
2616{
2617 int ndescs = mr->ndescs;
2618
2619 memset(umr, 0, sizeof(*umr));
2620 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2621 umr->klm_octowords = get_klm_octo(ndescs);
2622 umr->mkey_mask = frwr_mkey_mask();
2623}
2624
dd01e66a 2625static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2626{
2627 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2628 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2629 umr->flags = 1 << 7;
e126ba97
EC		 2630}
2631
968e78dd
HE		 2632static __be64 get_umr_reg_mr_mask(void)
2633{
2634 u64 result;
2635
2636 result = MLX5_MKEY_MASK_LEN |
2637 MLX5_MKEY_MASK_PAGE_SIZE |
2638 MLX5_MKEY_MASK_START_ADDR |
2639 MLX5_MKEY_MASK_PD |
2640 MLX5_MKEY_MASK_LR |
2641 MLX5_MKEY_MASK_LW |
2642 MLX5_MKEY_MASK_KEY |
2643 MLX5_MKEY_MASK_RR |
2644 MLX5_MKEY_MASK_RW |
2645 MLX5_MKEY_MASK_A |
2646 MLX5_MKEY_MASK_FREE;
2647
2648 return cpu_to_be64(result);
2649}
2650
2651static __be64 get_umr_unreg_mr_mask(void)
2652{
2653 u64 result;
2654
2655 result = MLX5_MKEY_MASK_FREE;
2656
2657 return cpu_to_be64(result);
2658}
2659
2660static __be64 get_umr_update_mtt_mask(void)
2661{
2662 u64 result;
2663
2664 result = MLX5_MKEY_MASK_FREE;
2665
2666 return cpu_to_be64(result);
2667}
2668
e126ba97
EC		 2669static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2670 struct ib_send_wr *wr)
2671{
e622f2f4 2672 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 2673
2674 memset(umr, 0, sizeof(*umr));
2675
968e78dd
HE		 2676 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
2677 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
2678 else
2679 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
2680
e126ba97 2681 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 2682 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 2683 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
2684 umr->mkey_mask = get_umr_update_mtt_mask();
2685 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2686 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
2687 } else {
2688 umr->mkey_mask = get_umr_reg_mr_mask();
2689 }
e126ba97 2690 } else {
968e78dd 2691 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 2692 }
2693
2694 if (!wr->num_sge)
968e78dd 2695 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 2696}
2697
2698static u8 get_umr_flags(int acc)
2699{
2700 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
2701 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
2702 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
2703 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 2704 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 2705}
2706
8a187ee5
SG		 2707static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2708 struct mlx5_ib_mr *mr,
2709 u32 key, int access)
2710{
2711 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2712
2713 memset(seg, 0, sizeof(*seg));
2714 seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT;
2715 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2716 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2717 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2718 seg->len = cpu_to_be64(mr->ibmr.length);
2719 seg->xlt_oct_size = cpu_to_be32(ndescs);
2720 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2721}
2722
dd01e66a 2723static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 2724{
2725 memset(seg, 0, sizeof(*seg));
dd01e66a 2726 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2727}
2728
2729static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2730{
e622f2f4 2731 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 2732
e126ba97
EC		 2733 memset(seg, 0, sizeof(*seg));
2734 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 2735 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2736 return;
2737 }
2738
968e78dd
HE		 2739 seg->flags = convert_access(umrwr->access_flags);
2740 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2741 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2742 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2743 }
2744 seg->len = cpu_to_be64(umrwr->length);
2745 seg->log2_page_size = umrwr->page_shift;
746b5583 2746 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 2747 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 2748}
2749
8a187ee5
SG		 2750static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2751 struct mlx5_ib_mr *mr,
2752 struct mlx5_ib_pd *pd)
2753{
2754 int bcount = mr->desc_size * mr->ndescs;
2755
2756 dseg->addr = cpu_to_be64(mr->desc_map);
2757 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2758 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2759}
2760
e126ba97
EC		 2761static __be32 send_ieth(struct ib_send_wr *wr)
2762{
2763 switch (wr->opcode) {
2764 case IB_WR_SEND_WITH_IMM:
2765 case IB_WR_RDMA_WRITE_WITH_IMM:
2766 return wr->ex.imm_data;
2767
2768 case IB_WR_SEND_WITH_INV:
2769 return cpu_to_be32(wr->ex.invalidate_rkey);
2770
2771 default:
2772 return 0;
2773 }
2774}
2775
2776static u8 calc_sig(void *wqe, int size)
2777{
2778 u8 *p = wqe;
2779 u8 res = 0;
2780 int i;
2781
2782 for (i = 0; i < size; i++)
2783 res ^= p[i];
2784
2785 return ~res;
2786}
2787
2788static u8 wq_sig(void *wqe)
2789{
2790 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2791}
2792
2793static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2794 void *wqe, int *sz)
2795{
2796 struct mlx5_wqe_inline_seg *seg;
2797 void *qend = qp->sq.qend;
2798 void *addr;
2799 int inl = 0;
2800 int copy;
2801 int len;
2802 int i;
2803
2804 seg = wqe;
2805 wqe += sizeof(*seg);
2806 for (i = 0; i < wr->num_sge; i++) {
2807 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2808 len = wr->sg_list[i].length;
2809 inl += len;
2810
2811 if (unlikely(inl > qp->max_inline_data))
2812 return -ENOMEM;
2813
2814 if (unlikely(wqe + len > qend)) {
2815 copy = qend - wqe;
2816 memcpy(wqe, addr, copy);
2817 addr += copy;
2818 len -= copy;
2819 wqe = mlx5_get_send_wqe(qp, 0);
2820 }
2821 memcpy(wqe, addr, len);
2822 wqe += len;
2823 }
2824
2825 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2826
2827 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2828
2829 return 0;
2830}
2831
e6631814
SG		 2832static u16 prot_field_size(enum ib_signature_type type)
2833{
2834 switch (type) {
2835 case IB_SIG_TYPE_T10_DIF:
2836 return MLX5_DIF_SIZE;
2837 default:
2838 return 0;
2839 }
2840}
2841
2842static u8 bs_selector(int block_size)
2843{
2844 switch (block_size) {
2845 case 512: return 0x1;
2846 case 520: return 0x2;
2847 case 4096: return 0x3;
2848 case 4160: return 0x4;
2849 case 1073741824: return 0x5;
2850 default: return 0;
2851 }
2852}
2853
78eda2bb
SG		 2854static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2855 struct mlx5_bsf_inl *inl)
e6631814 2856{
142537f4
SG		 2857 /* Valid inline section and allow BSF refresh */
2858 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2859 MLX5_BSF_REFRESH_DIF);
2860 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2861 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 2862 /* repeating block */
2863 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2864 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2865 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 2866
78eda2bb
SG		 2867 if (domain->sig.dif.ref_remap)
2868 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 2869
78eda2bb
SG		 2870 if (domain->sig.dif.app_escape) {
2871 if (domain->sig.dif.ref_escape)
2872 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2873 else
2874 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 2875 }
2876
78eda2bb
SG		 2877 inl->dif_app_bitmask_check =
2878 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 2879}
2880
2881static int mlx5_set_bsf(struct ib_mr *sig_mr,
2882 struct ib_sig_attrs *sig_attrs,
2883 struct mlx5_bsf *bsf, u32 data_size)
2884{
2885 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2886 struct mlx5_bsf_basic *basic = &bsf->basic;
2887 struct ib_sig_domain *mem = &sig_attrs->mem;
2888 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 2889
c7f44fbd 2890 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 2891
2892 /* Basic + Extended + Inline */
2893 basic->bsf_size_sbs = 1 << 7;
2894 /* Input domain check byte mask */
2895 basic->check_byte_mask = sig_attrs->check_mask;
2896 basic->raw_data_size = cpu_to_be32(data_size);
2897
2898 /* Memory domain */
e6631814 2899 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 2900 case IB_SIG_TYPE_NONE:
2901 break;
e6631814 2902 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 2903 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2904 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2905 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2906 break;
2907 default:
2908 return -EINVAL;
2909 }
e6631814 2910
78eda2bb
SG		 2911 /* Wire domain */
2912 switch (sig_attrs->wire.sig_type) {
2913 case IB_SIG_TYPE_NONE:
2914 break;
2915 case IB_SIG_TYPE_T10_DIF:
e6631814 2916 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 2917 mem->sig_type == wire->sig_type) {
e6631814 2918 /* Same block structure */
142537f4 2919 basic->bsf_size_sbs |= 1 << 4;
e6631814 2920 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 2921 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 2922 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 2923 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 2924 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 2925 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 2926 } else
2927 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2928
142537f4 2929 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 2930 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 2931 break;
e6631814
SG		 2932 default:
2933 return -EINVAL;
2934 }
2935
2936 return 0;
2937}
2938
e622f2f4
CH		 2939static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
2940 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 2941{
e622f2f4
CH		 2942 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
2943 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 2944 struct mlx5_bsf *bsf;
e622f2f4
CH		 2945 u32 data_len = wr->wr.sg_list->length;
2946 u32 data_key = wr->wr.sg_list->lkey;
2947 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 2948 int ret;
2949 int wqe_size;
2950
e622f2f4
CH		 2951 if (!wr->prot ||
2952 (data_key == wr->prot->lkey &&
2953 data_va == wr->prot->addr &&
2954 data_len == wr->prot->length)) {
e6631814
SG		 2955 /**
2956 * Source domain doesn't contain signature information
5c273b16 2957 * or data and protection are interleaved in memory.
e6631814
SG		 2958 * So need construct:
2959 * ------------------
2960 * | data_klm |
2961 * ------------------
2962 * | BSF |
2963 * ------------------
2964 **/
2965 struct mlx5_klm *data_klm = *seg;
2966
2967 data_klm->bcount = cpu_to_be32(data_len);
2968 data_klm->key = cpu_to_be32(data_key);
2969 data_klm->va = cpu_to_be64(data_va);
2970 wqe_size = ALIGN(sizeof(*data_klm), 64);
2971 } else {
2972 /**
2973 * Source domain contains signature information
2974 * So need construct a strided block format:
2975 * ---------------------------
2976 * | stride_block_ctrl |
2977 * ---------------------------
2978 * | data_klm |
2979 * ---------------------------
2980 * | prot_klm |
2981 * ---------------------------
2982 * | BSF |
2983 * ---------------------------
2984 **/
2985 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2986 struct mlx5_stride_block_entry *data_sentry;
2987 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 2988 u32 prot_key = wr->prot->lkey;
2989 u64 prot_va = wr->prot->addr;
e6631814
SG		 2990 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2991 int prot_size;
2992
2993 sblock_ctrl = *seg;
2994 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2995 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2996
2997 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2998 if (!prot_size) {
2999 pr_err("Bad block size given: %u\n", block_size);
3000 return -EINVAL;
3001 }
3002 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3003 prot_size);
3004 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3005 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3006 sblock_ctrl->num_entries = cpu_to_be16(2);
3007
3008 data_sentry->bcount = cpu_to_be16(block_size);
3009 data_sentry->key = cpu_to_be32(data_key);
3010 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3011 data_sentry->stride = cpu_to_be16(block_size);
3012
e6631814
SG		 3013 prot_sentry->bcount = cpu_to_be16(prot_size);
3014 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3015 prot_sentry->va = cpu_to_be64(prot_va);
3016 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3017
e6631814
SG		 3018 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3019 sizeof(*prot_sentry), 64);
3020 }
3021
3022 *seg += wqe_size;
3023 *size += wqe_size / 16;
3024 if (unlikely((*seg == qp->sq.qend)))
3025 *seg = mlx5_get_send_wqe(qp, 0);
3026
3027 bsf = *seg;
3028 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3029 if (ret)
3030 return -EINVAL;
3031
3032 *seg += sizeof(*bsf);
3033 *size += sizeof(*bsf) / 16;
3034 if (unlikely((*seg == qp->sq.qend)))
3035 *seg = mlx5_get_send_wqe(qp, 0);
3036
3037 return 0;
3038}
3039
3040static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3041 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3042 u32 length, u32 pdn)
3043{
e622f2f4 3044 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3045 u32 sig_key = sig_mr->rkey;
d5436ba0 3046 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3047
3048 memset(seg, 0, sizeof(*seg));
3049
e622f2f4 3050 seg->flags = get_umr_flags(wr->access_flags) |
e6631814
SG		 3051 MLX5_ACCESS_MODE_KLM;
3052 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3053 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3054 MLX5_MKEY_BSF_EN | pdn);
3055 seg->len = cpu_to_be64(length);
3056 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3057 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3058}
3059
3060static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3061 u32 nelements)
e6631814
SG		 3062{
3063 memset(umr, 0, sizeof(*umr));
3064
3065 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3066 umr->klm_octowords = get_klm_octo(nelements);
3067 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3068 umr->mkey_mask = sig_mkey_mask();
3069}
3070
3071
e622f2f4 3072static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3073 void **seg, int *size)
3074{
e622f2f4
CH		 3075 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3076 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3077 u32 pdn = get_pd(qp)->pdn;
3078 u32 klm_oct_size;
3079 int region_len, ret;
3080
e622f2f4
CH		 3081 if (unlikely(wr->wr.num_sge != 1) ||
3082 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3083 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3084 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3085 return -EINVAL;
3086
3087 /* length of the protected region, data + protection */
e622f2f4
CH		 3088 region_len = wr->wr.sg_list->length;
3089 if (wr->prot &&
3090 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3091 wr->prot->addr != wr->wr.sg_list->addr ||
3092 wr->prot->length != wr->wr.sg_list->length))
3093 region_len += wr->prot->length;
e6631814
SG		 3094
3095 /**
3096 * KLM octoword size - if protection was provided
3097 * then we use strided block format (3 octowords),
3098 * else we use single KLM (1 octoword)
3099 **/
e622f2f4 3100 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3101
e622f2f4 3102 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3103 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3104 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3105 if (unlikely((*seg == qp->sq.qend)))
3106 *seg = mlx5_get_send_wqe(qp, 0);
3107
3108 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3109 *seg += sizeof(struct mlx5_mkey_seg);
3110 *size += sizeof(struct mlx5_mkey_seg) / 16;
3111 if (unlikely((*seg == qp->sq.qend)))
3112 *seg = mlx5_get_send_wqe(qp, 0);
3113
3114 ret = set_sig_data_segment(wr, qp, seg, size);
3115 if (ret)
3116 return ret;
3117
d5436ba0 3118 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3119 return 0;
3120}
3121
3122static int set_psv_wr(struct ib_sig_domain *domain,
3123 u32 psv_idx, void **seg, int *size)
3124{
3125 struct mlx5_seg_set_psv *psv_seg = *seg;
3126
3127 memset(psv_seg, 0, sizeof(*psv_seg));
3128 psv_seg->psv_num = cpu_to_be32(psv_idx);
3129 switch (domain->sig_type) {
78eda2bb
SG		 3130 case IB_SIG_TYPE_NONE:
3131 break;
e6631814
SG		 3132 case IB_SIG_TYPE_T10_DIF:
3133 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3134 domain->sig.dif.app_tag);
3135 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3136 break;
e6631814
SG		 3137 default:
3138 pr_err("Bad signature type given.\n");
3139 return 1;
3140 }
3141
78eda2bb
SG		 3142 *seg += sizeof(*psv_seg);
3143 *size += sizeof(*psv_seg) / 16;
3144
e6631814
SG		 3145 return 0;
3146}
3147
8a187ee5
SG		 3148static int set_reg_wr(struct mlx5_ib_qp *qp,
3149 struct ib_reg_wr *wr,
3150 void **seg, int *size)
3151{
3152 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3153 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3154
3155 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3156 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3157 "Invalid IB_SEND_INLINE send flag\n");
3158 return -EINVAL;
3159 }
3160
3161 set_reg_umr_seg(*seg, mr);
3162 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3163 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3164 if (unlikely((*seg == qp->sq.qend)))
3165 *seg = mlx5_get_send_wqe(qp, 0);
3166
3167 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3168 *seg += sizeof(struct mlx5_mkey_seg);
3169 *size += sizeof(struct mlx5_mkey_seg) / 16;
3170 if (unlikely((*seg == qp->sq.qend)))
3171 *seg = mlx5_get_send_wqe(qp, 0);
3172
3173 set_reg_data_seg(*seg, mr, pd);
3174 *seg += sizeof(struct mlx5_wqe_data_seg);
3175 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3176
3177 return 0;
3178}
3179
dd01e66a 3180static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3181{
dd01e66a 3182 set_linv_umr_seg(*seg);
e126ba97
EC		 3183 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3184 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3185 if (unlikely((*seg == qp->sq.qend)))
3186 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3187 set_linv_mkey_seg(*seg);
e126ba97
EC		 3188 *seg += sizeof(struct mlx5_mkey_seg);
3189 *size += sizeof(struct mlx5_mkey_seg) / 16;
3190 if (unlikely((*seg == qp->sq.qend)))
3191 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3192}
3193
3194static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3195{
3196 __be32 *p = NULL;
3197 int tidx = idx;
3198 int i, j;
3199
3200 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3201 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3202 if ((i & 0xf) == 0) {
3203 void *buf = mlx5_get_send_wqe(qp, tidx);
3204 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3205 p = buf;
3206 j = 0;
3207 }
3208 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3209 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3210 be32_to_cpu(p[j + 3]));
3211 }
3212}
3213
3214static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3215 unsigned bytecnt, struct mlx5_ib_qp *qp)
3216{
3217 while (bytecnt > 0) {
3218 __iowrite64_copy(dst++, src++, 8);
3219 __iowrite64_copy(dst++, src++, 8);
3220 __iowrite64_copy(dst++, src++, 8);
3221 __iowrite64_copy(dst++, src++, 8);
3222 __iowrite64_copy(dst++, src++, 8);
3223 __iowrite64_copy(dst++, src++, 8);
3224 __iowrite64_copy(dst++, src++, 8);
3225 __iowrite64_copy(dst++, src++, 8);
3226 bytecnt -= 64;
3227 if (unlikely(src == qp->sq.qend))
3228 src = mlx5_get_send_wqe(qp, 0);
3229 }
3230}
3231
3232static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3233{
3234 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3235 wr->send_flags & IB_SEND_FENCE))
3236 return MLX5_FENCE_MODE_STRONG_ORDERING;
3237
3238 if (unlikely(fence)) {
3239 if (wr->send_flags & IB_SEND_FENCE)
3240 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3241 else
3242 return fence;
3243
3244 } else {
3245 return 0;
3246 }
3247}
3248
6e5eadac
SG		 3249static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3250 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3251 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3252 int *size, int nreq)
3253{
3254 int err = 0;
3255
3256 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3257 err = -ENOMEM;
3258 return err;
3259 }
3260
3261 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3262 *seg = mlx5_get_send_wqe(qp, *idx);
3263 *ctrl = *seg;
3264 *(uint32_t *)(*seg + 8) = 0;
3265 (*ctrl)->imm = send_ieth(wr);
3266 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3267 (wr->send_flags & IB_SEND_SIGNALED ?
3268 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3269 (wr->send_flags & IB_SEND_SOLICITED ?
3270 MLX5_WQE_CTRL_SOLICITED : 0);
3271
3272 *seg += sizeof(**ctrl);
3273 *size = sizeof(**ctrl) / 16;
3274
3275 return err;
3276}
3277
3278static void finish_wqe(struct mlx5_ib_qp *qp,
3279 struct mlx5_wqe_ctrl_seg *ctrl,
3280 u8 size, unsigned idx, u64 wr_id,
3281 int nreq, u8 fence, u8 next_fence,
3282 u32 mlx5_opcode)
3283{
3284 u8 opmod = 0;
3285
3286 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3287 mlx5_opcode | ((u32)opmod << 24));
19098df2 3288 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3289 ctrl->fm_ce_se |= fence;
3290 qp->fm_cache = next_fence;
3291 if (unlikely(qp->wq_sig))
3292 ctrl->signature = wq_sig(ctrl);
3293
3294 qp->sq.wrid[idx] = wr_id;
3295 qp->sq.w_list[idx].opcode = mlx5_opcode;
3296 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3297 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3298 qp->sq.w_list[idx].next = qp->sq.cur_post;
3299}
3300
3301
e126ba97
EC		 3302int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3303 struct ib_send_wr **bad_wr)
3304{
3305 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3306 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
e126ba97 3307 struct mlx5_ib_qp *qp = to_mqp(ibqp);
e6631814 3308 struct mlx5_ib_mr *mr;
e126ba97
EC		 3309 struct mlx5_wqe_data_seg *dpseg;
3310 struct mlx5_wqe_xrc_seg *xrc;
3311 struct mlx5_bf *bf = qp->bf;
3312 int uninitialized_var(size);
3313 void *qend = qp->sq.qend;
3314 unsigned long flags;
e126ba97
EC		 3315 unsigned idx;
3316 int err = 0;
3317 int inl = 0;
3318 int num_sge;
3319 void *seg;
3320 int nreq;
3321 int i;
3322 u8 next_fence = 0;
e126ba97
EC		 3323 u8 fence;
3324
3325 spin_lock_irqsave(&qp->sq.lock, flags);
3326
3327 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3328 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3329 mlx5_ib_warn(dev, "\n");
3330 err = -EINVAL;
3331 *bad_wr = wr;
3332 goto out;
3333 }
3334
6e5eadac
SG		 3335 fence = qp->fm_cache;
3336 num_sge = wr->num_sge;
3337 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3338 mlx5_ib_warn(dev, "\n");
3339 err = -ENOMEM;
3340 *bad_wr = wr;
3341 goto out;
3342 }
3343
6e5eadac
SG		 3344 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3345 if (err) {
e126ba97
EC		 3346 mlx5_ib_warn(dev, "\n");
3347 err = -ENOMEM;
3348 *bad_wr = wr;
3349 goto out;
3350 }
3351
e126ba97
EC		 3352 switch (ibqp->qp_type) {
3353 case IB_QPT_XRC_INI:
3354 xrc = seg;
e126ba97
EC		 3355 seg += sizeof(*xrc);
3356 size += sizeof(*xrc) / 16;
3357 /* fall through */
3358 case IB_QPT_RC:
3359 switch (wr->opcode) {
3360 case IB_WR_RDMA_READ:
3361 case IB_WR_RDMA_WRITE:
3362 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3363 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3364 rdma_wr(wr)->rkey);
f241e749 3365 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3366 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3367 break;
3368
3369 case IB_WR_ATOMIC_CMP_AND_SWP:
3370 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3371 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3372 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3373 err = -ENOSYS;
3374 *bad_wr = wr;
3375 goto out;
e126ba97
EC		 3376
3377 case IB_WR_LOCAL_INV:
3378 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3379 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3380 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3381 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3382 num_sge = 0;
3383 break;
3384
8a187ee5
SG		 3385 case IB_WR_REG_MR:
3386 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3387 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3388 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3389 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3390 if (err) {
3391 *bad_wr = wr;
3392 goto out;
3393 }
3394 num_sge = 0;
3395 break;
3396
e6631814
SG		 3397 case IB_WR_REG_SIG_MR:
3398 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3399 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3400
3401 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3402 err = set_sig_umr_wr(wr, qp, &seg, &size);
3403 if (err) {
3404 mlx5_ib_warn(dev, "\n");
3405 *bad_wr = wr;
3406 goto out;
3407 }
3408
3409 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3410 nreq, get_fence(fence, wr),
3411 next_fence, MLX5_OPCODE_UMR);
3412 /*
3413 * SET_PSV WQEs are not signaled and solicited
3414 * on error
3415 */
3416 wr->send_flags &= ~IB_SEND_SIGNALED;
3417 wr->send_flags |= IB_SEND_SOLICITED;
3418 err = begin_wqe(qp, &seg, &ctrl, wr,
3419 &idx, &size, nreq);
3420 if (err) {
3421 mlx5_ib_warn(dev, "\n");
3422 err = -ENOMEM;
3423 *bad_wr = wr;
3424 goto out;
3425 }
3426
e622f2f4 3427 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3428 mr->sig->psv_memory.psv_idx, &seg,
3429 &size);
3430 if (err) {
3431 mlx5_ib_warn(dev, "\n");
3432 *bad_wr = wr;
3433 goto out;
3434 }
3435
3436 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3437 nreq, get_fence(fence, wr),
3438 next_fence, MLX5_OPCODE_SET_PSV);
3439 err = begin_wqe(qp, &seg, &ctrl, wr,
3440 &idx, &size, nreq);
3441 if (err) {
3442 mlx5_ib_warn(dev, "\n");
3443 err = -ENOMEM;
3444 *bad_wr = wr;
3445 goto out;
3446 }
3447
3448 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3449 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3450 mr->sig->psv_wire.psv_idx, &seg,
3451 &size);
3452 if (err) {
3453 mlx5_ib_warn(dev, "\n");
3454 *bad_wr = wr;
3455 goto out;
3456 }
3457
3458 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3459 nreq, get_fence(fence, wr),
3460 next_fence, MLX5_OPCODE_SET_PSV);
3461 num_sge = 0;
3462 goto skip_psv;
3463
e126ba97
EC		 3464 default:
3465 break;
3466 }
3467 break;
3468
3469 case IB_QPT_UC:
3470 switch (wr->opcode) {
3471 case IB_WR_RDMA_WRITE:
3472 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3473 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3474 rdma_wr(wr)->rkey);
e126ba97
EC		 3475 seg += sizeof(struct mlx5_wqe_raddr_seg);
3476 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3477 break;
3478
3479 default:
3480 break;
3481 }
3482 break;
3483
e126ba97
EC		 3484 case IB_QPT_SMI:
3485 case IB_QPT_GSI:
3486 set_datagram_seg(seg, wr);
f241e749 3487 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3488 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3489 if (unlikely((seg == qend)))
3490 seg = mlx5_get_send_wqe(qp, 0);
3491 break;
f0313965
ES		 3492 case IB_QPT_UD:
3493 set_datagram_seg(seg, wr);
3494 seg += sizeof(struct mlx5_wqe_datagram_seg);
3495 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3496
3497 if (unlikely((seg == qend)))
3498 seg = mlx5_get_send_wqe(qp, 0);
3499
3500 /* handle qp that supports ud offload */
3501 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3502 struct mlx5_wqe_eth_pad *pad;
e126ba97 3503
f0313965
ES		 3504 pad = seg;
3505 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3506 seg += sizeof(struct mlx5_wqe_eth_pad);
3507 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3508
3509 seg = set_eth_seg(seg, wr, qend, qp, &size);
3510
3511 if (unlikely((seg == qend)))
3512 seg = mlx5_get_send_wqe(qp, 0);
3513 }
3514 break;
e126ba97
EC		 3515 case MLX5_IB_QPT_REG_UMR:
3516 if (wr->opcode != MLX5_IB_WR_UMR) {
3517 err = -EINVAL;
3518 mlx5_ib_warn(dev, "bad opcode\n");
3519 goto out;
3520 }
3521 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3522 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3523 set_reg_umr_segment(seg, wr);
3524 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3525 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3526 if (unlikely((seg == qend)))
3527 seg = mlx5_get_send_wqe(qp, 0);
3528 set_reg_mkey_segment(seg, wr);
3529 seg += sizeof(struct mlx5_mkey_seg);
3530 size += sizeof(struct mlx5_mkey_seg) / 16;
3531 if (unlikely((seg == qend)))
3532 seg = mlx5_get_send_wqe(qp, 0);
3533 break;
3534
3535 default:
3536 break;
3537 }
3538
3539 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3540 int uninitialized_var(sz);
3541
3542 err = set_data_inl_seg(qp, wr, seg, &sz);
3543 if (unlikely(err)) {
3544 mlx5_ib_warn(dev, "\n");
3545 *bad_wr = wr;
3546 goto out;
3547 }
3548 inl = 1;
3549 size += sz;
3550 } else {
3551 dpseg = seg;
3552 for (i = 0; i < num_sge; i++) {
3553 if (unlikely(dpseg == qend)) {
3554 seg = mlx5_get_send_wqe(qp, 0);
3555 dpseg = seg;
3556 }
3557 if (likely(wr->sg_list[i].length)) {
3558 set_data_ptr_seg(dpseg, wr->sg_list + i);
3559 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3560 dpseg++;
3561 }
3562 }
3563 }
3564
6e5eadac
SG		 3565 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3566 get_fence(fence, wr), next_fence,
3567 mlx5_ib_opcode[wr->opcode]);
e6631814 3568skip_psv:
e126ba97
EC		 3569 if (0)
3570 dump_wqe(qp, idx, size);
3571 }
3572
3573out:
3574 if (likely(nreq)) {
3575 qp->sq.head += nreq;
3576
3577 /* Make sure that descriptors are written before
3578 * updating doorbell record and ringing the doorbell
3579 */
3580 wmb();
3581
3582 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3583
ada388f7
EC		 3584 /* Make sure doorbell record is visible to the HCA before
3585 * we hit doorbell */
3586 wmb();
3587
e126ba97
EC		 3588 if (bf->need_lock)
3589 spin_lock(&bf->lock);
6a4f139a
EC		 3590 else
3591 __acquire(&bf->lock);
e126ba97
EC		 3592
3593 /* TBD enable WC */
3594 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3595 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3596 /* wc_wmb(); */
3597 } else {
3598 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3599 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3600 /* Make sure doorbells don't leak out of SQ spinlock
3601 * and reach the HCA out of order.
3602 */
3603 mmiowb();
3604 }
3605 bf->offset ^= bf->buf_size;
3606 if (bf->need_lock)
3607 spin_unlock(&bf->lock);
6a4f139a
EC		 3608 else
3609 __release(&bf->lock);
e126ba97
EC		 3610 }
3611
3612 spin_unlock_irqrestore(&qp->sq.lock, flags);
3613
3614 return err;
3615}
3616
3617static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3618{
3619 sig->signature = calc_sig(sig, size);
3620}
3621
3622int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3623 struct ib_recv_wr **bad_wr)
3624{
3625 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3626 struct mlx5_wqe_data_seg *scat;
3627 struct mlx5_rwqe_sig *sig;
3628 unsigned long flags;
3629 int err = 0;
3630 int nreq;
3631 int ind;
3632 int i;
3633
3634 spin_lock_irqsave(&qp->rq.lock, flags);
3635
3636 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3637
3638 for (nreq = 0; wr; nreq++, wr = wr->next) {
3639 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3640 err = -ENOMEM;
3641 *bad_wr = wr;
3642 goto out;
3643 }
3644
3645 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3646 err = -EINVAL;
3647 *bad_wr = wr;
3648 goto out;
3649 }
3650
3651 scat = get_recv_wqe(qp, ind);
3652 if (qp->wq_sig)
3653 scat++;
3654
3655 for (i = 0; i < wr->num_sge; i++)
3656 set_data_ptr_seg(scat + i, wr->sg_list + i);
3657
3658 if (i < qp->rq.max_gs) {
3659 scat[i].byte_count = 0;
3660 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3661 scat[i].addr = 0;
3662 }
3663
3664 if (qp->wq_sig) {
3665 sig = (struct mlx5_rwqe_sig *)scat;
3666 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3667 }
3668
3669 qp->rq.wrid[ind] = wr->wr_id;
3670
3671 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3672 }
3673
3674out:
3675 if (likely(nreq)) {
3676 qp->rq.head += nreq;
3677
3678 /* Make sure that descriptors are written before
3679 * doorbell record.
3680 */
3681 wmb();
3682
3683 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3684 }
3685
3686 spin_unlock_irqrestore(&qp->rq.lock, flags);
3687
3688 return err;
3689}
3690
3691static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3692{
3693 switch (mlx5_state) {
3694 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3695 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3696 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3697 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3698 case MLX5_QP_STATE_SQ_DRAINING:
3699 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3700 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3701 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3702 default: return -1;
3703 }
3704}
3705
3706static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3707{
3708 switch (mlx5_mig_state) {
3709 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3710 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3711 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3712 default: return -1;
3713 }
3714}
3715
3716static int to_ib_qp_access_flags(int mlx5_flags)
3717{
3718 int ib_flags = 0;
3719
3720 if (mlx5_flags & MLX5_QP_BIT_RRE)
3721 ib_flags |= IB_ACCESS_REMOTE_READ;
3722 if (mlx5_flags & MLX5_QP_BIT_RWE)
3723 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3724 if (mlx5_flags & MLX5_QP_BIT_RAE)
3725 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3726
3727 return ib_flags;
3728}
3729
3730static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3731 struct mlx5_qp_path *path)
3732{
9603b61d 3733 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 3734
3735 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3736 ib_ah_attr->port_num = path->port;
3737
c7a08ac7 3738 if (ib_ah_attr->port_num == 0 ||
938fe83c 3739 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 3740 return;
3741
2811ba51 3742 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 3743
3744 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3745 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3746 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3747 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3748 if (ib_ah_attr->ah_flags) {
3749 ib_ah_attr->grh.sgid_index = path->mgid_index;
3750 ib_ah_attr->grh.hop_limit = path->hop_limit;
3751 ib_ah_attr->grh.traffic_class =
3752 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3753 ib_ah_attr->grh.flow_label =
3754 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3755 memcpy(ib_ah_attr->grh.dgid.raw,
3756 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3757 }
3758}
3759
6d2f89df 3760static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
3761 struct mlx5_ib_sq *sq,
3762 u8 *sq_state)
3763{
3764 void *out;
3765 void *sqc;
3766 int inlen;
3767 int err;
3768
3769 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
3770 out = mlx5_vzalloc(inlen);
3771 if (!out)
3772 return -ENOMEM;
3773
3774 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
3775 if (err)
3776 goto out;
3777
3778 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
3779 *sq_state = MLX5_GET(sqc, sqc, state);
3780 sq->state = *sq_state;
3781
3782out:
3783 kvfree(out);
3784 return err;
3785}
3786
3787static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
3788 struct mlx5_ib_rq *rq,
3789 u8 *rq_state)
3790{
3791 void *out;
3792 void *rqc;
3793 int inlen;
3794 int err;
3795
3796 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
3797 out = mlx5_vzalloc(inlen);
3798 if (!out)
3799 return -ENOMEM;
3800
3801 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
3802 if (err)
3803 goto out;
3804
3805 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3806 *rq_state = MLX5_GET(rqc, rqc, state);
3807 rq->state = *rq_state;
3808
3809out:
3810 kvfree(out);
3811 return err;
3812}
3813
3814static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
3815 struct mlx5_ib_qp *qp, u8 *qp_state)
3816{
3817 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
3818 [MLX5_RQC_STATE_RST] = {
3819 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3820 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3821 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
3822 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
3823 },
3824 [MLX5_RQC_STATE_RDY] = {
3825 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3826 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3827 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
3828 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
3829 },
3830 [MLX5_RQC_STATE_ERR] = {
3831 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3832 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3833 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
3834 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
3835 },
3836 [MLX5_RQ_STATE_NA] = {
3837 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3838 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3839 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
3840 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
3841 },
3842 };
3843
3844 *qp_state = sqrq_trans[rq_state][sq_state];
3845
3846 if (*qp_state == MLX5_QP_STATE_BAD) {
3847 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
3848 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
3849 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
3850 return -EINVAL;
3851 }
3852
3853 if (*qp_state == MLX5_QP_STATE)
3854 *qp_state = qp->state;
3855
3856 return 0;
3857}
3858
3859static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
3860 struct mlx5_ib_qp *qp,
3861 u8 *raw_packet_qp_state)
3862{
3863 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3864 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3865 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3866 int err;
3867 u8 sq_state = MLX5_SQ_STATE_NA;
3868 u8 rq_state = MLX5_RQ_STATE_NA;
3869
3870 if (qp->sq.wqe_cnt) {
3871 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
3872 if (err)
3873 return err;
3874 }
3875
3876 if (qp->rq.wqe_cnt) {
3877 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
3878 if (err)
3879 return err;
3880 }
3881
3882 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
3883 raw_packet_qp_state);
3884}
3885
3886static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3887 struct ib_qp_attr *qp_attr)
e126ba97 3888{
e126ba97
EC		 3889 struct mlx5_query_qp_mbox_out *outb;
3890 struct mlx5_qp_context *context;
3891 int mlx5_state;
3892 int err = 0;
3893
e126ba97 3894 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
6d2f89df 3895 if (!outb)
3896 return -ENOMEM;
3897
e126ba97 3898 context = &outb->ctx;
19098df2 3899 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
3900 sizeof(*outb));
e126ba97 3901 if (err)
6d2f89df 3902 goto out;
e126ba97
EC		 3903
3904 mlx5_state = be32_to_cpu(context->flags) >> 28;
3905
3906 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 3907 qp_attr->path_mtu = context->mtu_msgmax >> 5;
3908 qp_attr->path_mig_state =
3909 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3910 qp_attr->qkey = be32_to_cpu(context->qkey);
3911 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3912 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
3913 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3914 qp_attr->qp_access_flags =
3915 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3916
3917 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3918 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3919 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3920 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3921 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3922 }
3923
3924 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3925 qp_attr->port_num = context->pri_path.port;
3926
3927 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3928 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3929
3930 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3931
3932 qp_attr->max_dest_rd_atomic =
3933 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3934 qp_attr->min_rnr_timer =
3935 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3936 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
3937 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
3938 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
3939 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 3940
3941out:
3942 kfree(outb);
3943 return err;
3944}
3945
3946int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3947 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3948{
3949 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3950 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3951 int err = 0;
3952 u8 raw_packet_qp_state;
3953
3954#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3955 /*
3956 * Wait for any outstanding page faults, in case the user frees memory
3957 * based upon this query's result.
3958 */
3959 flush_workqueue(mlx5_ib_page_fault_wq);
3960#endif
3961
3962 mutex_lock(&qp->mutex);
3963
3964 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3965 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
3966 if (err)
3967 goto out;
3968 qp->state = raw_packet_qp_state;
3969 qp_attr->port_num = 1;
3970 } else {
3971 err = query_qp_attr(dev, qp, qp_attr);
3972 if (err)
3973 goto out;
3974 }
3975
3976 qp_attr->qp_state = qp->state;
e126ba97
EC		 3977 qp_attr->cur_qp_state = qp_attr->qp_state;
3978 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3979 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3980
3981 if (!ibqp->uobject) {
3982 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3983 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3984 } else {
3985 qp_attr->cap.max_send_wr = 0;
3986 qp_attr->cap.max_send_sge = 0;
3987 }
3988
3989 /* We don't support inline sends for kernel QPs (yet), and we
3990 * don't know what userspace's value should be.
3991 */
3992 qp_attr->cap.max_inline_data = 0;
3993
3994 qp_init_attr->cap = qp_attr->cap;
3995
3996 qp_init_attr->create_flags = 0;
3997 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3998 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3999
051f2630
LR		 4000 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4001 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4002 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4003 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4004 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4005 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4006 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4007 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4008
e126ba97
EC		 4009 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4010 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4011
e126ba97
EC		 4012out:
4013 mutex_unlock(&qp->mutex);
4014 return err;
4015}
4016
4017struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4018 struct ib_ucontext *context,
4019 struct ib_udata *udata)
4020{
4021 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4022 struct mlx5_ib_xrcd *xrcd;
4023 int err;
4024
938fe83c 4025 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4026 return ERR_PTR(-ENOSYS);
4027
4028 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4029 if (!xrcd)
4030 return ERR_PTR(-ENOMEM);
4031
9603b61d 4032 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4033 if (err) {
4034 kfree(xrcd);
4035 return ERR_PTR(-ENOMEM);
4036 }
4037
4038 return &xrcd->ibxrcd;
4039}
4040
4041int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4042{
4043 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4044 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4045 int err;
4046
9603b61d 4047 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4048 if (err) {
4049 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4050 return err;
4051 }
4052
4053 kfree(xrcd);
4054
4055 return 0;
4056}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git