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IB/core: Add accessor functions for rdma_ah_attr fields
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39/* not supported currently */
40static int wq_signature;
41
42enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44};
45
46enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51};
52
53enum {
54 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 59 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72};
73
f0313965
ES		 74struct mlx5_wqe_eth_pad {
75 u8 rsvd0[16];
76};
e126ba97 77
eb49ab0c
AV		 78enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 81};
82
0680efa2
AV		 83struct mlx5_modify_raw_qp_param {
84 u16 operation;
eb49ab0c
AV		 85
86 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 87 u32 rate_limit;
eb49ab0c 88 u8 rq_q_ctr_id;
0680efa2
AV		 89};
90
89ea94a7
MG		 91static void get_cqs(enum ib_qp_type qp_type,
92 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
e126ba97
EC		 95static int is_qp0(enum ib_qp_type qp_type)
96{
97 return qp_type == IB_QPT_SMI;
98}
99
e126ba97
EC		 100static int is_sqp(enum ib_qp_type qp_type)
101{
102 return is_qp0(qp_type) || is_qp1(qp_type);
103}
104
105static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106{
107 return mlx5_buf_offset(&qp->buf, offset);
108}
109
110static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111{
112 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113}
114
115void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116{
117 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118}
119
c1395a2a
HE		 120/**
121 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122 *
123 * @qp: QP to copy from.
124 * @send: copy from the send queue when non-zero, use the receive queue
125 * otherwise.
126 * @wqe_index: index to start copying from. For send work queues, the
127 * wqe_index is in units of MLX5_SEND_WQE_BB.
128 * For receive work queue, it is the number of work queue
129 * element in the queue.
130 * @buffer: destination buffer.
131 * @length: maximum number of bytes to copy.
132 *
133 * Copies at least a single WQE, but may copy more data.
134 *
135 * Return: the number of bytes copied, or an error code.
136 */
137int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 138 void *buffer, u32 length,
139 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 140{
141 struct ib_device *ibdev = qp->ibqp.device;
142 struct mlx5_ib_dev *dev = to_mdev(ibdev);
143 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144 size_t offset;
145 size_t wq_end;
19098df2 146 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 147 u32 first_copy_length;
148 int wqe_length;
149 int ret;
150
151 if (wq->wqe_cnt == 0) {
152 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153 qp->ibqp.qp_type);
154 return -EINVAL;
155 }
156
157 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161 return -EINVAL;
162
163 if (offset > umem->length ||
164 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165 return -EINVAL;
166
167 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169 if (ret)
170 return ret;
171
172 if (send) {
173 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176 wqe_length = ds * MLX5_WQE_DS_UNITS;
177 } else {
178 wqe_length = 1 << wq->wqe_shift;
179 }
180
181 if (wqe_length <= first_copy_length)
182 return first_copy_length;
183
184 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185 wqe_length - first_copy_length);
186 if (ret)
187 return ret;
188
189 return wqe_length;
190}
191
e126ba97
EC		 192static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193{
194 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195 struct ib_event event;
196
19098df2 197 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198 /* This event is only valid for trans_qps */
199 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200 }
e126ba97
EC		 201
202 if (ibqp->event_handler) {
203 event.device = ibqp->device;
204 event.element.qp = ibqp;
205 switch (type) {
206 case MLX5_EVENT_TYPE_PATH_MIG:
207 event.event = IB_EVENT_PATH_MIG;
208 break;
209 case MLX5_EVENT_TYPE_COMM_EST:
210 event.event = IB_EVENT_COMM_EST;
211 break;
212 case MLX5_EVENT_TYPE_SQ_DRAINED:
213 event.event = IB_EVENT_SQ_DRAINED;
214 break;
215 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217 break;
218 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219 event.event = IB_EVENT_QP_FATAL;
220 break;
221 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222 event.event = IB_EVENT_PATH_MIG_ERR;
223 break;
224 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225 event.event = IB_EVENT_QP_REQ_ERR;
226 break;
227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228 event.event = IB_EVENT_QP_ACCESS_ERR;
229 break;
230 default:
231 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232 return;
233 }
234
235 ibqp->event_handler(&event, ibqp->qp_context);
236 }
237}
238
239static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241{
242 int wqe_size;
243 int wq_size;
244
245 /* Sanity check RQ size before proceeding */
938fe83c 246 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 247 return -EINVAL;
248
249 if (!has_rq) {
250 qp->rq.max_gs = 0;
251 qp->rq.wqe_cnt = 0;
252 qp->rq.wqe_shift = 0;
0540d814
NO		 253 cap->max_recv_wr = 0;
254 cap->max_recv_sge = 0;
e126ba97
EC		 255 } else {
256 if (ucmd) {
257 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260 qp->rq.max_post = qp->rq.wqe_cnt;
261 } else {
262 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264 wqe_size = roundup_pow_of_two(wqe_size);
265 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 268 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 269 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270 wqe_size,
938fe83c
SM		 271 MLX5_CAP_GEN(dev->mdev,
272 max_wqe_sz_rq));
e126ba97
EC		 273 return -EINVAL;
274 }
275 qp->rq.wqe_shift = ilog2(wqe_size);
276 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277 qp->rq.max_post = qp->rq.wqe_cnt;
278 }
279 }
280
281 return 0;
282}
283
f0313965 284static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 285{
618af384 286 int size = 0;
e126ba97 287
f0313965 288 switch (attr->qp_type) {
e126ba97 289 case IB_QPT_XRC_INI:
b125a54b 290 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 291 /* fall through */
292 case IB_QPT_RC:
293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_atomic_seg) +
295 sizeof(struct mlx5_wqe_raddr_seg),
296 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 298 break;
299
b125a54b
EC		 300 case IB_QPT_XRC_TGT:
301 return 0;
302
e126ba97 303 case IB_QPT_UC:
b125a54b 304 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 305 max(sizeof(struct mlx5_wqe_raddr_seg),
306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 308 break;
309
310 case IB_QPT_UD:
f0313965
ES		 311 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312 size += sizeof(struct mlx5_wqe_eth_pad) +
313 sizeof(struct mlx5_wqe_eth_seg);
314 /* fall through */
e126ba97 315 case IB_QPT_SMI:
d16e91da 316 case MLX5_IB_QPT_HW_GSI:
b125a54b 317 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 318 sizeof(struct mlx5_wqe_datagram_seg);
319 break;
320
321 case MLX5_IB_QPT_REG_UMR:
b125a54b 322 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 323 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324 sizeof(struct mlx5_mkey_seg);
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return size;
332}
333
334static int calc_send_wqe(struct ib_qp_init_attr *attr)
335{
336 int inl_size = 0;
337 int size;
338
f0313965 339 size = sq_overhead(attr);
e126ba97
EC		 340 if (size < 0)
341 return size;
342
343 if (attr->cap.max_inline_data) {
344 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345 attr->cap.max_inline_data;
346 }
347
348 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351 return MLX5_SIG_WQE_SIZE;
352 else
353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 354}
355
288c01b7
EC		 356static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357{
358 int max_sge;
359
360 if (attr->qp_type == IB_QPT_RC)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_raddr_seg)) /
364 sizeof(struct mlx5_wqe_data_seg);
365 else if (attr->qp_type == IB_QPT_XRC_INI)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_xrc_seg) -
369 sizeof(struct mlx5_wqe_raddr_seg)) /
370 sizeof(struct mlx5_wqe_data_seg);
371 else
372 max_sge = (wqe_size - sq_overhead(attr)) /
373 sizeof(struct mlx5_wqe_data_seg);
374
375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376 sizeof(struct mlx5_wqe_data_seg));
377}
378
e126ba97
EC		 379static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380 struct mlx5_ib_qp *qp)
381{
382 int wqe_size;
383 int wq_size;
384
385 if (!attr->cap.max_send_wr)
386 return 0;
387
388 wqe_size = calc_send_wqe(attr);
389 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390 if (wqe_size < 0)
391 return wqe_size;
392
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 394 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 395 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 396 return -EINVAL;
397 }
398
f0313965
ES		 399 qp->max_inline_data = wqe_size - sq_overhead(attr) -
400 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 401 attr->cap.max_inline_data = qp->max_inline_data;
402
e1e66cc2
SG		 403 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404 qp->signature_en = true;
405
e126ba97
EC		 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 411 qp->sq.wqe_cnt,
412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 413 return -ENOMEM;
414 }
e126ba97 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 416 qp->sq.max_gs = get_send_sge(attr, wqe_size);
417 if (qp->sq.max_gs < attr->cap.max_send_sge)
418 return -ENOMEM;
419
420 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 421 qp->sq.max_post = wq_size / wqe_size;
422 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 423
424 return wq_size;
425}
426
427static int set_user_buf_size(struct mlx5_ib_dev *dev,
428 struct mlx5_ib_qp *qp,
19098df2 429 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 430 struct mlx5_ib_qp_base *base,
431 struct ib_qp_init_attr *attr)
e126ba97
EC		 432{
433 int desc_sz = 1 << qp->sq.wqe_shift;
434
938fe83c 435 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 436 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 437 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 438 return -EINVAL;
439 }
440
441 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444 return -EINVAL;
445 }
446
447 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
938fe83c 449 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 450 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 451 qp->sq.wqe_cnt,
452 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 453 return -EINVAL;
454 }
455
0fb2ed66 456 if (attr->qp_type == IB_QPT_RAW_PACKET) {
457 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459 } else {
460 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461 (qp->sq.wqe_cnt << 6);
462 }
e126ba97
EC		 463
464 return 0;
465}
466
467static int qp_has_rq(struct ib_qp_init_attr *attr)
468{
469 if (attr->qp_type == IB_QPT_XRC_INI ||
470 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472 !attr->cap.max_recv_wr)
473 return 0;
474
475 return 1;
476}
477
2f5ff264 478static int first_med_bfreg(void)
c1be5232
EC		 479{
480 return 1;
481}
482
0b80c14f
EC		 483enum {
484 /* this is the first blue flame register in the array of bfregs assigned
485 * to a processes. Since we do not use it for blue flame but rather
486 * regular 64 bit doorbells, we do not need a lock for maintaiing
487 * "odd/even" order
488 */
489 NUM_NON_BLUE_FLAME_BFREGS = 1,
490};
491
b037c29a
EC		 492static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
493{
494 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
495}
496
497static int num_med_bfreg(struct mlx5_ib_dev *dev,
498 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 499{
500 int n;
501
b037c29a
EC		 502 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
503 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 504
505 return n >= 0 ? n : 0;
506}
507
b037c29a
EC		 508static int first_hi_bfreg(struct mlx5_ib_dev *dev,
509 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 510{
511 int med;
c1be5232 512
b037c29a
EC		 513 med = num_med_bfreg(dev, bfregi);
514 return ++med;
c1be5232
EC		 515}
516
b037c29a
EC		 517static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
518 struct mlx5_bfreg_info *bfregi)
e126ba97 519{
e126ba97
EC		 520 int i;
521
b037c29a
EC		 522 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
523 if (!bfregi->count[i]) {
2f5ff264 524 bfregi->count[i]++;
e126ba97
EC		 525 return i;
526 }
527 }
528
529 return -ENOMEM;
530}
531
b037c29a
EC		 532static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
533 struct mlx5_bfreg_info *bfregi)
e126ba97 534{
2f5ff264 535 int minidx = first_med_bfreg();
e126ba97
EC		 536 int i;
537
b037c29a 538 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 539 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 540 minidx = i;
0b80c14f
EC		 541 if (!bfregi->count[minidx])
542 break;
e126ba97
EC		 543 }
544
2f5ff264 545 bfregi->count[minidx]++;
e126ba97
EC		 546 return minidx;
547}
548
b037c29a
EC		 549static int alloc_bfreg(struct mlx5_ib_dev *dev,
550 struct mlx5_bfreg_info *bfregi,
2f5ff264 551 enum mlx5_ib_latency_class lat)
e126ba97 552{
2f5ff264 553 int bfregn = -EINVAL;
e126ba97 554
2f5ff264 555 mutex_lock(&bfregi->lock);
e126ba97
EC		 556 switch (lat) {
557 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 558 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 559 bfregn = 0;
560 bfregi->count[bfregn]++;
e126ba97
EC		 561 break;
562
563 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 564 if (bfregi->ver < 2)
565 bfregn = -ENOMEM;
78c0f98c 566 else
b037c29a 567 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 568 break;
569
570 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 571 if (bfregi->ver < 2)
572 bfregn = -ENOMEM;
78c0f98c 573 else
b037c29a 574 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 575 break;
576 }
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97 578
2f5ff264 579 return bfregn;
e126ba97
EC		 580}
581
b037c29a 582static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 583{
2f5ff264 584 mutex_lock(&bfregi->lock);
b037c29a 585 bfregi->count[bfregn]--;
2f5ff264 586 mutex_unlock(&bfregi->lock);
e126ba97
EC		 587}
588
589static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
590{
591 switch (state) {
592 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
593 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
594 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
595 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
596 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
597 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
598 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
599 default: return -1;
600 }
601}
602
603static int to_mlx5_st(enum ib_qp_type type)
604{
605 switch (type) {
606 case IB_QPT_RC: return MLX5_QP_ST_RC;
607 case IB_QPT_UC: return MLX5_QP_ST_UC;
608 case IB_QPT_UD: return MLX5_QP_ST_UD;
609 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
610 case IB_QPT_XRC_INI:
611 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
612 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 613 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 614 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 615 case IB_QPT_RAW_PACKET:
0fb2ed66 616 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 617 case IB_QPT_MAX:
618 default: return -EINVAL;
619 }
620}
621
89ea94a7
MG		 622static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
623 struct mlx5_ib_cq *recv_cq);
624static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626
b037c29a
EC		 627static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
628 struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 629{
b037c29a
EC		 630 int bfregs_per_sys_page;
631 int index_of_sys_page;
632 int offset;
633
634 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
635 MLX5_NON_FP_BFREGS_PER_UAR;
636 index_of_sys_page = bfregn / bfregs_per_sys_page;
637
638 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
639
640 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 641}
642
19098df2 643static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
644 struct ib_pd *pd,
645 unsigned long addr, size_t size,
646 struct ib_umem **umem,
647 int *npages, int *page_shift, int *ncont,
648 u32 *offset)
649{
650 int err;
651
652 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
653 if (IS_ERR(*umem)) {
654 mlx5_ib_dbg(dev, "umem_get failed\n");
655 return PTR_ERR(*umem);
656 }
657
762f899a 658 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 659
660 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
661 if (err) {
662 mlx5_ib_warn(dev, "bad offset\n");
663 goto err_umem;
664 }
665
666 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
667 addr, size, *npages, *page_shift, *ncont, *offset);
668
669 return 0;
670
671err_umem:
672 ib_umem_release(*umem);
673 *umem = NULL;
674
675 return err;
676}
677
79b20a6c
YH		 678static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
679{
680 struct mlx5_ib_ucontext *context;
681
682 context = to_mucontext(pd->uobject->context);
683 mlx5_ib_db_unmap_user(context, &rwq->db);
684 if (rwq->umem)
685 ib_umem_release(rwq->umem);
686}
687
688static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
689 struct mlx5_ib_rwq *rwq,
690 struct mlx5_ib_create_wq *ucmd)
691{
692 struct mlx5_ib_ucontext *context;
693 int page_shift = 0;
694 int npages;
695 u32 offset = 0;
696 int ncont = 0;
697 int err;
698
699 if (!ucmd->buf_addr)
700 return -EINVAL;
701
702 context = to_mucontext(pd->uobject->context);
703 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
704 rwq->buf_size, 0, 0);
705 if (IS_ERR(rwq->umem)) {
706 mlx5_ib_dbg(dev, "umem_get failed\n");
707 err = PTR_ERR(rwq->umem);
708 return err;
709 }
710
762f899a 711 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 712 &ncont, NULL);
713 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
714 &rwq->rq_page_offset);
715 if (err) {
716 mlx5_ib_warn(dev, "bad offset\n");
717 goto err_umem;
718 }
719
720 rwq->rq_num_pas = ncont;
721 rwq->page_shift = page_shift;
722 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
723 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
724
725 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
726 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
727 npages, page_shift, ncont, offset);
728
729 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
730 if (err) {
731 mlx5_ib_dbg(dev, "map failed\n");
732 goto err_umem;
733 }
734
735 rwq->create_type = MLX5_WQ_USER;
736 return 0;
737
738err_umem:
739 ib_umem_release(rwq->umem);
740 return err;
741}
742
b037c29a
EC		 743static int adjust_bfregn(struct mlx5_ib_dev *dev,
744 struct mlx5_bfreg_info *bfregi, int bfregn)
745{
746 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
747 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
748}
749
e126ba97
EC		 750static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
751 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 752 struct ib_qp_init_attr *attr,
09a7d9ec 753 u32 **in,
19098df2 754 struct mlx5_ib_create_qp_resp *resp, int *inlen,
755 struct mlx5_ib_qp_base *base)
e126ba97
EC		 756{
757 struct mlx5_ib_ucontext *context;
758 struct mlx5_ib_create_qp ucmd;
19098df2 759 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 760 int page_shift = 0;
e126ba97
EC		 761 int uar_index;
762 int npages;
9e9c47d0 763 u32 offset = 0;
2f5ff264 764 int bfregn;
9e9c47d0 765 int ncont = 0;
09a7d9ec
SM		 766 __be64 *pas;
767 void *qpc;
e126ba97
EC		 768 int err;
769
770 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
771 if (err) {
772 mlx5_ib_dbg(dev, "copy failed\n");
773 return err;
774 }
775
776 context = to_mucontext(pd->uobject->context);
777 /*
778 * TBD: should come from the verbs when we have the API
779 */
051f2630
LR		 780 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
781 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 782 bfregn = MLX5_CROSS_CHANNEL_BFREG;
051f2630 783 else {
b037c29a 784 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 785 if (bfregn < 0) {
786 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 787 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 788 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 789 if (bfregn < 0) {
790 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 791 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 792 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 793 if (bfregn < 0) {
794 mlx5_ib_warn(dev, "bfreg allocation failed\n");
795 return bfregn;
051f2630 796 }
c1be5232 797 }
e126ba97
EC		 798 }
799 }
800
b037c29a 801 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
2f5ff264 802 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
e126ba97 803
48fea837
HE		 804 qp->rq.offset = 0;
805 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807
0fb2ed66 808 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 809 if (err)
2f5ff264 810 goto err_bfreg;
e126ba97 811
19098df2 812 if (ucmd.buf_addr && ubuffer->buf_size) {
813 ubuffer->buf_addr = ucmd.buf_addr;
814 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
815 ubuffer->buf_size,
816 &ubuffer->umem, &npages, &page_shift,
817 &ncont, &offset);
818 if (err)
2f5ff264 819 goto err_bfreg;
9e9c47d0 820 } else {
19098df2 821 ubuffer->umem = NULL;
e126ba97 822 }
e126ba97 823
09a7d9ec
SM		 824 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
825 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 826 *in = mlx5_vzalloc(*inlen);
827 if (!*in) {
828 err = -ENOMEM;
829 goto err_umem;
830 }
09a7d9ec
SM		 831
832 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 833 if (ubuffer->umem)
09a7d9ec
SM		 834 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
835
836 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
837
838 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
839 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 840
09a7d9ec 841 MLX5_SET(qpc, qpc, uar_page, uar_index);
b037c29a 842 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
2f5ff264 843 qp->bfregn = bfregn;
e126ba97
EC		 844
845 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
846 if (err) {
847 mlx5_ib_dbg(dev, "map failed\n");
848 goto err_free;
849 }
850
851 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
852 if (err) {
853 mlx5_ib_dbg(dev, "copy failed\n");
854 goto err_unmap;
855 }
856 qp->create_type = MLX5_QP_USER;
857
858 return 0;
859
860err_unmap:
861 mlx5_ib_db_unmap_user(context, &qp->db);
862
863err_free:
479163f4 864 kvfree(*in);
e126ba97
EC		 865
866err_umem:
19098df2 867 if (ubuffer->umem)
868 ib_umem_release(ubuffer->umem);
e126ba97 869
2f5ff264 870err_bfreg:
b037c29a 871 free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 872 return err;
873}
874
b037c29a
EC		 875static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
876 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 877{
878 struct mlx5_ib_ucontext *context;
879
880 context = to_mucontext(pd->uobject->context);
881 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 882 if (base->ubuffer.umem)
883 ib_umem_release(base->ubuffer.umem);
b037c29a 884 free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 885}
886
887static int create_kernel_qp(struct mlx5_ib_dev *dev,
888 struct ib_qp_init_attr *init_attr,
889 struct mlx5_ib_qp *qp,
09a7d9ec 890 u32 **in, int *inlen,
19098df2 891 struct mlx5_ib_qp_base *base)
e126ba97 892{
e126ba97 893 int uar_index;
09a7d9ec 894 void *qpc;
e126ba97
EC		 895 int err;
896
f0313965
ES		 897 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
898 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 899 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 900 IB_QP_CREATE_NETIF_QP |
b11a4f9c 901 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 902 return -EINVAL;
e126ba97
EC		 903
904 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 905 qp->bf.bfreg = &dev->fp_bfreg;
906 else
907 qp->bf.bfreg = &dev->bfreg;
e126ba97 908
d8030b0d
EC		 909 /* We need to divide by two since each register is comprised of
910 * two buffers of identical size, namely odd and even
911 */
912 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 913 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 914
915 err = calc_sq_size(dev, init_attr, qp);
916 if (err < 0) {
917 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 918 return err;
e126ba97
EC		 919 }
920
921 qp->rq.offset = 0;
922 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 923 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 924
19098df2 925 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 926 if (err) {
927 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 928 return err;
e126ba97
EC		 929 }
930
931 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 932 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
933 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 934 *in = mlx5_vzalloc(*inlen);
935 if (!*in) {
936 err = -ENOMEM;
937 goto err_buf;
938 }
09a7d9ec
SM		 939
940 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
941 MLX5_SET(qpc, qpc, uar_page, uar_index);
942 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
943
e126ba97 944 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 945 MLX5_SET(qpc, qpc, fre, 1);
946 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 947
b11a4f9c 948 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 949 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 950 qp->flags |= MLX5_IB_QP_SQPN_QP1;
951 }
952
09a7d9ec
SM		 953 mlx5_fill_page_array(&qp->buf,
954 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 955
9603b61d 956 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 957 if (err) {
958 mlx5_ib_dbg(dev, "err %d\n", err);
959 goto err_free;
960 }
961
e126ba97
EC		 962 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
963 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
964 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
965 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
966 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
967
968 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
969 !qp->sq.w_list || !qp->sq.wqe_head) {
970 err = -ENOMEM;
971 goto err_wrid;
972 }
973 qp->create_type = MLX5_QP_KERNEL;
974
975 return 0;
976
977err_wrid:
e126ba97
EC		 978 kfree(qp->sq.wqe_head);
979 kfree(qp->sq.w_list);
980 kfree(qp->sq.wrid);
981 kfree(qp->sq.wr_data);
982 kfree(qp->rq.wrid);
f4044dac 983 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 984
985err_free:
479163f4 986 kvfree(*in);
e126ba97
EC		 987
988err_buf:
9603b61d 989 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 990 return err;
991}
992
993static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
994{
e126ba97
EC		 995 kfree(qp->sq.wqe_head);
996 kfree(qp->sq.w_list);
997 kfree(qp->sq.wrid);
998 kfree(qp->sq.wr_data);
999 kfree(qp->rq.wrid);
f4044dac 1000 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1001 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1002}
1003
09a7d9ec 1004static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1005{
1006 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1007 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1008 return MLX5_SRQ_RQ;
e126ba97 1009 else if (!qp->has_rq)
09a7d9ec 1010 return MLX5_ZERO_LEN_RQ;
e126ba97 1011 else
09a7d9ec 1012 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1013}
1014
1015static int is_connected(enum ib_qp_type qp_type)
1016{
1017 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1018 return 1;
1019
1020 return 0;
1021}
1022
0fb2ed66 1023static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1024 struct mlx5_ib_sq *sq, u32 tdn)
1025{
c4f287c4 1026 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1027 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1028
0fb2ed66 1029 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1030 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1031}
1032
1033static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1034 struct mlx5_ib_sq *sq)
1035{
1036 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1037}
1038
1039static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1040 struct mlx5_ib_sq *sq, void *qpin,
1041 struct ib_pd *pd)
1042{
1043 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1044 __be64 *pas;
1045 void *in;
1046 void *sqc;
1047 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1048 void *wq;
1049 int inlen;
1050 int err;
1051 int page_shift = 0;
1052 int npages;
1053 int ncont = 0;
1054 u32 offset = 0;
1055
1056 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1057 &sq->ubuffer.umem, &npages, &page_shift,
1058 &ncont, &offset);
1059 if (err)
1060 return err;
1061
1062 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1063 in = mlx5_vzalloc(inlen);
1064 if (!in) {
1065 err = -ENOMEM;
1066 goto err_umem;
1067 }
1068
1069 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1070 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1071 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1072 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1073 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1074 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1075 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1076
1077 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1078 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1079 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1080 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1081 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1082 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1083 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1084 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1085 MLX5_SET(wq, wq, page_offset, offset);
1086
1087 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1088 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1089
1090 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1091
1092 kvfree(in);
1093
1094 if (err)
1095 goto err_umem;
1096
1097 return 0;
1098
1099err_umem:
1100 ib_umem_release(sq->ubuffer.umem);
1101 sq->ubuffer.umem = NULL;
1102
1103 return err;
1104}
1105
1106static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1107 struct mlx5_ib_sq *sq)
1108{
1109 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1110 ib_umem_release(sq->ubuffer.umem);
1111}
1112
1113static int get_rq_pas_size(void *qpc)
1114{
1115 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1116 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1117 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1118 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1119 u32 po_quanta = 1 << (log_page_size - 6);
1120 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1121 u32 page_size = 1 << log_page_size;
1122 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1123 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1124
1125 return rq_num_pas * sizeof(u64);
1126}
1127
1128static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1129 struct mlx5_ib_rq *rq, void *qpin)
1130{
358e42ea 1131 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1132 __be64 *pas;
1133 __be64 *qp_pas;
1134 void *in;
1135 void *rqc;
1136 void *wq;
1137 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1138 int inlen;
1139 int err;
1140 u32 rq_pas_size = get_rq_pas_size(qpc);
1141
1142 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1143 in = mlx5_vzalloc(inlen);
1144 if (!in)
1145 return -ENOMEM;
1146
1147 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1148 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1149 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1150 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1151 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1152 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1153 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1154 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1155
358e42ea
MD		 1156 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1157 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1158
0fb2ed66 1159 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1160 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1161 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1162 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1163 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1164 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1165 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1166 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1167 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1168 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1169
1170 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1171 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1172 memcpy(pas, qp_pas, rq_pas_size);
1173
1174 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1175
1176 kvfree(in);
1177
1178 return err;
1179}
1180
1181static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1182 struct mlx5_ib_rq *rq)
1183{
1184 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1185}
1186
1187static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1188 struct mlx5_ib_rq *rq, u32 tdn)
1189{
1190 u32 *in;
1191 void *tirc;
1192 int inlen;
1193 int err;
1194
1195 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1196 in = mlx5_vzalloc(inlen);
1197 if (!in)
1198 return -ENOMEM;
1199
1200 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1201 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1202 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1203 MLX5_SET(tirc, tirc, transport_domain, tdn);
1204
1205 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1206
1207 kvfree(in);
1208
1209 return err;
1210}
1211
1212static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1213 struct mlx5_ib_rq *rq)
1214{
1215 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1216}
1217
1218static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1219 u32 *in,
0fb2ed66 1220 struct ib_pd *pd)
1221{
1222 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1223 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1224 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1225 struct ib_uobject *uobj = pd->uobject;
1226 struct ib_ucontext *ucontext = uobj->context;
1227 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1228 int err;
1229 u32 tdn = mucontext->tdn;
1230
1231 if (qp->sq.wqe_cnt) {
1232 err = create_raw_packet_qp_tis(dev, sq, tdn);
1233 if (err)
1234 return err;
1235
1236 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1237 if (err)
1238 goto err_destroy_tis;
1239
1240 sq->base.container_mibqp = qp;
1241 }
1242
1243 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1244 rq->base.container_mibqp = qp;
1245
e4cc4fa7
NO		 1246 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1247 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
0fb2ed66 1248 err = create_raw_packet_qp_rq(dev, rq, in);
1249 if (err)
1250 goto err_destroy_sq;
1251
0fb2ed66 1252
1253 err = create_raw_packet_qp_tir(dev, rq, tdn);
1254 if (err)
1255 goto err_destroy_rq;
1256 }
1257
1258 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1259 rq->base.mqp.qpn;
1260
1261 return 0;
1262
1263err_destroy_rq:
1264 destroy_raw_packet_qp_rq(dev, rq);
1265err_destroy_sq:
1266 if (!qp->sq.wqe_cnt)
1267 return err;
1268 destroy_raw_packet_qp_sq(dev, sq);
1269err_destroy_tis:
1270 destroy_raw_packet_qp_tis(dev, sq);
1271
1272 return err;
1273}
1274
1275static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1276 struct mlx5_ib_qp *qp)
1277{
1278 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1279 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1280 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1281
1282 if (qp->rq.wqe_cnt) {
1283 destroy_raw_packet_qp_tir(dev, rq);
1284 destroy_raw_packet_qp_rq(dev, rq);
1285 }
1286
1287 if (qp->sq.wqe_cnt) {
1288 destroy_raw_packet_qp_sq(dev, sq);
1289 destroy_raw_packet_qp_tis(dev, sq);
1290 }
1291}
1292
1293static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1294 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1295{
1296 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1297 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1298
1299 sq->sq = &qp->sq;
1300 rq->rq = &qp->rq;
1301 sq->doorbell = &qp->db;
1302 rq->doorbell = &qp->db;
1303}
1304
28d61370
YH		 1305static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1306{
1307 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1308}
1309
1310static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1311 struct ib_pd *pd,
1312 struct ib_qp_init_attr *init_attr,
1313 struct ib_udata *udata)
1314{
1315 struct ib_uobject *uobj = pd->uobject;
1316 struct ib_ucontext *ucontext = uobj->context;
1317 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1318 struct mlx5_ib_create_qp_resp resp = {};
1319 int inlen;
1320 int err;
1321 u32 *in;
1322 void *tirc;
1323 void *hfso;
1324 u32 selected_fields = 0;
1325 size_t min_resp_len;
1326 u32 tdn = mucontext->tdn;
1327 struct mlx5_ib_create_qp_rss ucmd = {};
1328 size_t required_cmd_sz;
1329
1330 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1331 return -EOPNOTSUPP;
1332
1333 if (init_attr->create_flags || init_attr->send_cq)
1334 return -EINVAL;
1335
2f5ff264 1336 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1337 if (udata->outlen < min_resp_len)
1338 return -EINVAL;
1339
1340 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1341 if (udata->inlen < required_cmd_sz) {
1342 mlx5_ib_dbg(dev, "invalid inlen\n");
1343 return -EINVAL;
1344 }
1345
1346 if (udata->inlen > sizeof(ucmd) &&
1347 !ib_is_udata_cleared(udata, sizeof(ucmd),
1348 udata->inlen - sizeof(ucmd))) {
1349 mlx5_ib_dbg(dev, "inlen is not supported\n");
1350 return -EOPNOTSUPP;
1351 }
1352
1353 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1354 mlx5_ib_dbg(dev, "copy failed\n");
1355 return -EFAULT;
1356 }
1357
1358 if (ucmd.comp_mask) {
1359 mlx5_ib_dbg(dev, "invalid comp mask\n");
1360 return -EOPNOTSUPP;
1361 }
1362
1363 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1364 mlx5_ib_dbg(dev, "invalid reserved\n");
1365 return -EOPNOTSUPP;
1366 }
1367
1368 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1369 if (err) {
1370 mlx5_ib_dbg(dev, "copy failed\n");
1371 return -EINVAL;
1372 }
1373
1374 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1375 in = mlx5_vzalloc(inlen);
1376 if (!in)
1377 return -ENOMEM;
1378
1379 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1380 MLX5_SET(tirc, tirc, disp_type,
1381 MLX5_TIRC_DISP_TYPE_INDIRECT);
1382 MLX5_SET(tirc, tirc, indirect_table,
1383 init_attr->rwq_ind_tbl->ind_tbl_num);
1384 MLX5_SET(tirc, tirc, transport_domain, tdn);
1385
1386 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1387 switch (ucmd.rx_hash_function) {
1388 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1389 {
1390 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1391 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1392
1393 if (len != ucmd.rx_key_len) {
1394 err = -EINVAL;
1395 goto err;
1396 }
1397
1398 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1399 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1400 memcpy(rss_key, ucmd.rx_hash_key, len);
1401 break;
1402 }
1403 default:
1404 err = -EOPNOTSUPP;
1405 goto err;
1406 }
1407
1408 if (!ucmd.rx_hash_fields_mask) {
1409 /* special case when this TIR serves as steering entry without hashing */
1410 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1411 goto create_tir;
1412 err = -EINVAL;
1413 goto err;
1414 }
1415
1416 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1417 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1418 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1419 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1420 err = -EINVAL;
1421 goto err;
1422 }
1423
1424 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1425 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1426 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1427 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1428 MLX5_L3_PROT_TYPE_IPV4);
1429 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1430 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1431 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1432 MLX5_L3_PROT_TYPE_IPV6);
1433
1434 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1435 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1436 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1437 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1438 err = -EINVAL;
1439 goto err;
1440 }
1441
1442 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1443 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1444 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1445 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1446 MLX5_L4_PROT_TYPE_TCP);
1447 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1448 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1449 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1450 MLX5_L4_PROT_TYPE_UDP);
1451
1452 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1453 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1454 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1455
1456 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1457 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1458 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1459
1460 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1461 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1462 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1463
1464 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1465 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1466 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1467
1468 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1469
1470create_tir:
1471 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1472
1473 if (err)
1474 goto err;
1475
1476 kvfree(in);
1477 /* qpn is reserved for that QP */
1478 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1479 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1480 return 0;
1481
1482err:
1483 kvfree(in);
1484 return err;
1485}
1486
e126ba97
EC		 1487static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1488 struct ib_qp_init_attr *init_attr,
1489 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1490{
1491 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1492 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1493 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1494 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1495 struct mlx5_ib_cq *send_cq;
1496 struct mlx5_ib_cq *recv_cq;
1497 unsigned long flags;
cfb5e088 1498 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1499 struct mlx5_ib_create_qp ucmd;
1500 struct mlx5_ib_qp_base *base;
cfb5e088 1501 void *qpc;
09a7d9ec
SM		 1502 u32 *in;
1503 int err;
e126ba97 1504
0fb2ed66 1505 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1506 &qp->raw_packet_qp.rq.base :
1507 &qp->trans_qp.base;
1508
e126ba97
EC		 1509 mutex_init(&qp->mutex);
1510 spin_lock_init(&qp->sq.lock);
1511 spin_lock_init(&qp->rq.lock);
1512
28d61370
YH		 1513 if (init_attr->rwq_ind_tbl) {
1514 if (!udata)
1515 return -ENOSYS;
1516
1517 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1518 return err;
1519 }
1520
f360d88a 1521 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1522 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1523 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1524 return -EINVAL;
1525 } else {
1526 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1527 }
1528 }
1529
051f2630
LR		 1530 if (init_attr->create_flags &
1531 (IB_QP_CREATE_CROSS_CHANNEL |
1532 IB_QP_CREATE_MANAGED_SEND |
1533 IB_QP_CREATE_MANAGED_RECV)) {
1534 if (!MLX5_CAP_GEN(mdev, cd)) {
1535 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1536 return -EINVAL;
1537 }
1538 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1539 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1540 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1541 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1542 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1543 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1544 }
f0313965
ES		 1545
1546 if (init_attr->qp_type == IB_QPT_UD &&
1547 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1548 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1549 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1550 return -EOPNOTSUPP;
1551 }
1552
358e42ea
MD		 1553 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1554 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1555 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1556 return -EOPNOTSUPP;
1557 }
1558 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1559 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1560 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1561 return -EOPNOTSUPP;
1562 }
1563 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1564 }
1565
e126ba97
EC		 1566 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1567 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1568
e4cc4fa7
NO		 1569 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1570 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1571 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1572 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1573 return -EOPNOTSUPP;
1574 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1575 }
1576
e126ba97
EC		 1577 if (pd && pd->uobject) {
1578 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1579 mlx5_ib_dbg(dev, "copy failed\n");
1580 return -EFAULT;
1581 }
1582
cfb5e088
HA		 1583 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1584 &ucmd, udata->inlen, &uidx);
1585 if (err)
1586 return err;
1587
e126ba97
EC		 1588 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1589 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1590 } else {
1591 qp->wq_sig = !!wq_signature;
1592 }
1593
1594 qp->has_rq = qp_has_rq(init_attr);
1595 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1596 qp, (pd && pd->uobject) ? &ucmd : NULL);
1597 if (err) {
1598 mlx5_ib_dbg(dev, "err %d\n", err);
1599 return err;
1600 }
1601
1602 if (pd) {
1603 if (pd->uobject) {
938fe83c
SM		 1604 __u32 max_wqes =
1605 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1606 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1607 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1608 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1609 mlx5_ib_dbg(dev, "invalid rq params\n");
1610 return -EINVAL;
1611 }
938fe83c 1612 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1613 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1614 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1615 return -EINVAL;
1616 }
b11a4f9c
HE		 1617 if (init_attr->create_flags &
1618 mlx5_ib_create_qp_sqpn_qp1()) {
1619 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1620 return -EINVAL;
1621 }
0fb2ed66 1622 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1623 &resp, &inlen, base);
e126ba97
EC		 1624 if (err)
1625 mlx5_ib_dbg(dev, "err %d\n", err);
1626 } else {
19098df2 1627 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1628 base);
e126ba97
EC		 1629 if (err)
1630 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1631 }
1632
1633 if (err)
1634 return err;
1635 } else {
09a7d9ec 1636 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1637 if (!in)
1638 return -ENOMEM;
1639
1640 qp->create_type = MLX5_QP_EMPTY;
1641 }
1642
1643 if (is_sqp(init_attr->qp_type))
1644 qp->port = init_attr->port_num;
1645
09a7d9ec
SM		 1646 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1647
1648 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1649 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1650
1651 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1652 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1653 else
09a7d9ec
SM		 1654 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1655
e126ba97
EC		 1656
1657 if (qp->wq_sig)
09a7d9ec 1658 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1659
f360d88a 1660 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1661 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1662
051f2630 1663 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1664 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1665 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1666 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1667 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1668 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1669
e126ba97
EC		 1670 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1671 int rcqe_sz;
1672 int scqe_sz;
1673
1674 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1675 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1676
1677 if (rcqe_sz == 128)
09a7d9ec 1678 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1679 else
09a7d9ec 1680 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1681
1682 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1683 if (scqe_sz == 128)
09a7d9ec 1684 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1685 else
09a7d9ec 1686 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1687 }
1688 }
1689
1690 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1691 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1692 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1693 }
1694
09a7d9ec 1695 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1696
1697 if (qp->sq.wqe_cnt)
09a7d9ec 1698 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1699 else
09a7d9ec 1700 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1701
1702 /* Set default resources */
1703 switch (init_attr->qp_type) {
1704 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1705 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1706 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1707 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1708 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1709 break;
1710 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1711 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1712 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1713 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1714 break;
1715 default:
1716 if (init_attr->srq) {
09a7d9ec
SM		 1717 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1718 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1719 } else {
09a7d9ec
SM		 1720 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1721 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1722 }
1723 }
1724
1725 if (init_attr->send_cq)
09a7d9ec 1726 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1727
1728 if (init_attr->recv_cq)
09a7d9ec 1729 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1730
09a7d9ec 1731 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1732
09a7d9ec
SM		 1733 /* 0xffffff means we ask to work with cqe version 0 */
1734 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1735 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1736
f0313965
ES		 1737 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1738 if (init_attr->qp_type == IB_QPT_UD &&
1739 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1740 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1741 qp->flags |= MLX5_IB_QP_LSO;
1742 }
cfb5e088 1743
0fb2ed66 1744 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1745 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1746 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1747 err = create_raw_packet_qp(dev, qp, in, pd);
1748 } else {
1749 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1750 }
1751
e126ba97
EC		 1752 if (err) {
1753 mlx5_ib_dbg(dev, "create qp failed\n");
1754 goto err_create;
1755 }
1756
479163f4 1757 kvfree(in);
e126ba97 1758
19098df2 1759 base->container_mibqp = qp;
1760 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1761
89ea94a7
MG		 1762 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1763 &send_cq, &recv_cq);
1764 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1765 mlx5_ib_lock_cqs(send_cq, recv_cq);
1766 /* Maintain device to QPs access, needed for further handling via reset
1767 * flow
1768 */
1769 list_add_tail(&qp->qps_list, &dev->qp_list);
1770 /* Maintain CQ to QPs access, needed for further handling via reset flow
1771 */
1772 if (send_cq)
1773 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1774 if (recv_cq)
1775 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1776 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1777 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1778
e126ba97
EC		 1779 return 0;
1780
1781err_create:
1782 if (qp->create_type == MLX5_QP_USER)
b037c29a 1783 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1784 else if (qp->create_type == MLX5_QP_KERNEL)
1785 destroy_qp_kernel(dev, qp);
1786
479163f4 1787 kvfree(in);
e126ba97
EC		 1788 return err;
1789}
1790
1791static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1792 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1793{
1794 if (send_cq) {
1795 if (recv_cq) {
1796 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1797 spin_lock(&send_cq->lock);
e126ba97
EC		 1798 spin_lock_nested(&recv_cq->lock,
1799 SINGLE_DEPTH_NESTING);
1800 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1801 spin_lock(&send_cq->lock);
e126ba97
EC		 1802 __acquire(&recv_cq->lock);
1803 } else {
89ea94a7 1804 spin_lock(&recv_cq->lock);
e126ba97
EC		 1805 spin_lock_nested(&send_cq->lock,
1806 SINGLE_DEPTH_NESTING);
1807 }
1808 } else {
89ea94a7 1809 spin_lock(&send_cq->lock);
6a4f139a 1810 __acquire(&recv_cq->lock);
e126ba97
EC		 1811 }
1812 } else if (recv_cq) {
89ea94a7 1813 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1814 __acquire(&send_cq->lock);
1815 } else {
1816 __acquire(&send_cq->lock);
1817 __acquire(&recv_cq->lock);
e126ba97
EC		 1818 }
1819}
1820
1821static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1822 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1823{
1824 if (send_cq) {
1825 if (recv_cq) {
1826 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1827 spin_unlock(&recv_cq->lock);
89ea94a7 1828 spin_unlock(&send_cq->lock);
e126ba97
EC		 1829 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1830 __release(&recv_cq->lock);
89ea94a7 1831 spin_unlock(&send_cq->lock);
e126ba97
EC		 1832 } else {
1833 spin_unlock(&send_cq->lock);
89ea94a7 1834 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1835 }
1836 } else {
6a4f139a 1837 __release(&recv_cq->lock);
89ea94a7 1838 spin_unlock(&send_cq->lock);
e126ba97
EC		 1839 }
1840 } else if (recv_cq) {
6a4f139a 1841 __release(&send_cq->lock);
89ea94a7 1842 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1843 } else {
1844 __release(&recv_cq->lock);
1845 __release(&send_cq->lock);
e126ba97
EC		 1846 }
1847}
1848
1849static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1850{
1851 return to_mpd(qp->ibqp.pd);
1852}
1853
89ea94a7
MG		 1854static void get_cqs(enum ib_qp_type qp_type,
1855 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1856 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1857{
89ea94a7 1858 switch (qp_type) {
e126ba97
EC		 1859 case IB_QPT_XRC_TGT:
1860 *send_cq = NULL;
1861 *recv_cq = NULL;
1862 break;
1863 case MLX5_IB_QPT_REG_UMR:
1864 case IB_QPT_XRC_INI:
89ea94a7 1865 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1866 *recv_cq = NULL;
1867 break;
1868
1869 case IB_QPT_SMI:
d16e91da 1870 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1871 case IB_QPT_RC:
1872 case IB_QPT_UC:
1873 case IB_QPT_UD:
1874 case IB_QPT_RAW_IPV6:
1875 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1876 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1877 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1878 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1879 break;
1880
e126ba97
EC		 1881 case IB_QPT_MAX:
1882 default:
1883 *send_cq = NULL;
1884 *recv_cq = NULL;
1885 break;
1886 }
1887}
1888
ad5f8e96 1889static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1890 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1891 u8 lag_tx_affinity);
ad5f8e96 1892
e126ba97
EC		 1893static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1894{
1895 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1896 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1897 unsigned long flags;
e126ba97
EC		 1898 int err;
1899
28d61370
YH		 1900 if (qp->ibqp.rwq_ind_tbl) {
1901 destroy_rss_raw_qp_tir(dev, qp);
1902 return;
1903 }
1904
0fb2ed66 1905 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1906 &qp->raw_packet_qp.rq.base :
1907 &qp->trans_qp.base;
1908
6aec21f6 1909 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1910 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
ad5f8e96 1911 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1912 MLX5_CMD_OP_2RST_QP, 0,
1913 NULL, &base->mqp);
ad5f8e96 1914 } else {
0680efa2
AV		 1915 struct mlx5_modify_raw_qp_param raw_qp_param = {
1916 .operation = MLX5_CMD_OP_2RST_QP
1917 };
1918
13eab21f 1919 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1920 }
1921 if (err)
427c1e7b 1922 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1923 base->mqp.qpn);
6aec21f6 1924 }
e126ba97 1925
89ea94a7
MG		 1926 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1927 &send_cq, &recv_cq);
1928
1929 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1930 mlx5_ib_lock_cqs(send_cq, recv_cq);
1931 /* del from lists under both locks above to protect reset flow paths */
1932 list_del(&qp->qps_list);
1933 if (send_cq)
1934 list_del(&qp->cq_send_list);
1935
1936 if (recv_cq)
1937 list_del(&qp->cq_recv_list);
e126ba97
EC		 1938
1939 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1940 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1941 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1942 if (send_cq != recv_cq)
19098df2 1943 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1944 NULL);
e126ba97 1945 }
89ea94a7
MG		 1946 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1947 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1948
0fb2ed66 1949 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1950 destroy_raw_packet_qp(dev, qp);
1951 } else {
1952 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1953 if (err)
1954 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1955 base->mqp.qpn);
1956 }
e126ba97 1957
e126ba97
EC		 1958 if (qp->create_type == MLX5_QP_KERNEL)
1959 destroy_qp_kernel(dev, qp);
1960 else if (qp->create_type == MLX5_QP_USER)
b037c29a 1961 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1962}
1963
1964static const char *ib_qp_type_str(enum ib_qp_type type)
1965{
1966 switch (type) {
1967 case IB_QPT_SMI:
1968 return "IB_QPT_SMI";
1969 case IB_QPT_GSI:
1970 return "IB_QPT_GSI";
1971 case IB_QPT_RC:
1972 return "IB_QPT_RC";
1973 case IB_QPT_UC:
1974 return "IB_QPT_UC";
1975 case IB_QPT_UD:
1976 return "IB_QPT_UD";
1977 case IB_QPT_RAW_IPV6:
1978 return "IB_QPT_RAW_IPV6";
1979 case IB_QPT_RAW_ETHERTYPE:
1980 return "IB_QPT_RAW_ETHERTYPE";
1981 case IB_QPT_XRC_INI:
1982 return "IB_QPT_XRC_INI";
1983 case IB_QPT_XRC_TGT:
1984 return "IB_QPT_XRC_TGT";
1985 case IB_QPT_RAW_PACKET:
1986 return "IB_QPT_RAW_PACKET";
1987 case MLX5_IB_QPT_REG_UMR:
1988 return "MLX5_IB_QPT_REG_UMR";
1989 case IB_QPT_MAX:
1990 default:
1991 return "Invalid QP type";
1992 }
1993}
1994
1995struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1996 struct ib_qp_init_attr *init_attr,
1997 struct ib_udata *udata)
1998{
1999 struct mlx5_ib_dev *dev;
2000 struct mlx5_ib_qp *qp;
2001 u16 xrcdn = 0;
2002 int err;
2003
2004 if (pd) {
2005 dev = to_mdev(pd->device);
0fb2ed66 2006
2007 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2008 if (!pd->uobject) {
2009 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2010 return ERR_PTR(-EINVAL);
2011 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2012 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2013 return ERR_PTR(-EINVAL);
2014 }
2015 }
09f16cf5
MD		 2016 } else {
2017 /* being cautious here */
2018 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2019 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2020 pr_warn("%s: no PD for transport %s\n", __func__,
2021 ib_qp_type_str(init_attr->qp_type));
2022 return ERR_PTR(-EINVAL);
2023 }
2024 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2025 }
2026
2027 switch (init_attr->qp_type) {
2028 case IB_QPT_XRC_TGT:
2029 case IB_QPT_XRC_INI:
938fe83c 2030 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2031 mlx5_ib_dbg(dev, "XRC not supported\n");
2032 return ERR_PTR(-ENOSYS);
2033 }
2034 init_attr->recv_cq = NULL;
2035 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2036 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2037 init_attr->send_cq = NULL;
2038 }
2039
2040 /* fall through */
0fb2ed66 2041 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2042 case IB_QPT_RC:
2043 case IB_QPT_UC:
2044 case IB_QPT_UD:
2045 case IB_QPT_SMI:
d16e91da 2046 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2047 case MLX5_IB_QPT_REG_UMR:
2048 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2049 if (!qp)
2050 return ERR_PTR(-ENOMEM);
2051
2052 err = create_qp_common(dev, pd, init_attr, udata, qp);
2053 if (err) {
2054 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2055 kfree(qp);
2056 return ERR_PTR(err);
2057 }
2058
2059 if (is_qp0(init_attr->qp_type))
2060 qp->ibqp.qp_num = 0;
2061 else if (is_qp1(init_attr->qp_type))
2062 qp->ibqp.qp_num = 1;
2063 else
19098df2 2064 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2065
2066 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2067 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2068 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2069 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2070
19098df2 2071 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2072
2073 break;
2074
d16e91da
HE		 2075 case IB_QPT_GSI:
2076 return mlx5_ib_gsi_create_qp(pd, init_attr);
2077
e126ba97
EC		 2078 case IB_QPT_RAW_IPV6:
2079 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2080 case IB_QPT_MAX:
2081 default:
2082 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2083 init_attr->qp_type);
2084 /* Don't support raw QPs */
2085 return ERR_PTR(-EINVAL);
2086 }
2087
2088 return &qp->ibqp;
2089}
2090
2091int mlx5_ib_destroy_qp(struct ib_qp *qp)
2092{
2093 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2094 struct mlx5_ib_qp *mqp = to_mqp(qp);
2095
d16e91da
HE		 2096 if (unlikely(qp->qp_type == IB_QPT_GSI))
2097 return mlx5_ib_gsi_destroy_qp(qp);
2098
e126ba97
EC		 2099 destroy_qp_common(dev, mqp);
2100
2101 kfree(mqp);
2102
2103 return 0;
2104}
2105
2106static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2107 int attr_mask)
2108{
2109 u32 hw_access_flags = 0;
2110 u8 dest_rd_atomic;
2111 u32 access_flags;
2112
2113 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2114 dest_rd_atomic = attr->max_dest_rd_atomic;
2115 else
19098df2 2116 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2117
2118 if (attr_mask & IB_QP_ACCESS_FLAGS)
2119 access_flags = attr->qp_access_flags;
2120 else
19098df2 2121 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2122
2123 if (!dest_rd_atomic)
2124 access_flags &= IB_ACCESS_REMOTE_WRITE;
2125
2126 if (access_flags & IB_ACCESS_REMOTE_READ)
2127 hw_access_flags |= MLX5_QP_BIT_RRE;
2128 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2129 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2130 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2131 hw_access_flags |= MLX5_QP_BIT_RWE;
2132
2133 return cpu_to_be32(hw_access_flags);
2134}
2135
2136enum {
2137 MLX5_PATH_FLAG_FL = 1 << 0,
2138 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2139 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2140};
2141
2142static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2143{
2144 if (rate == IB_RATE_PORT_CURRENT) {
2145 return 0;
2146 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2147 return -EINVAL;
2148 } else {
2149 while (rate != IB_RATE_2_5_GBPS &&
2150 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2151 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2152 --rate;
2153 }
2154
2155 return rate + MLX5_STAT_RATE_OFFSET;
2156}
2157
75850d0b 2158static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2159 struct mlx5_ib_sq *sq, u8 sl)
2160{
2161 void *in;
2162 void *tisc;
2163 int inlen;
2164 int err;
2165
2166 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2167 in = mlx5_vzalloc(inlen);
2168 if (!in)
2169 return -ENOMEM;
2170
2171 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2172
2173 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2174 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2175
2176 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2177
2178 kvfree(in);
2179
2180 return err;
2181}
2182
13eab21f
AH		 2183static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2184 struct mlx5_ib_sq *sq, u8 tx_affinity)
2185{
2186 void *in;
2187 void *tisc;
2188 int inlen;
2189 int err;
2190
2191 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2192 in = mlx5_vzalloc(inlen);
2193 if (!in)
2194 return -ENOMEM;
2195
2196 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2197
2198 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2199 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2200
2201 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2202
2203 kvfree(in);
2204
2205 return err;
2206}
2207
75850d0b 2208static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2209 const struct rdma_ah_attr *ah,
e126ba97 2210 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2211 u32 path_flags, const struct ib_qp_attr *attr,
2212 bool alt)
e126ba97 2213{
2811ba51 2214 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97 2215 int err;
ed88451e 2216 enum ib_gid_type gid_type;
e126ba97 2217
e126ba97 2218 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2219 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2220 attr->pkey_index);
e126ba97 2221
e126ba97 2222 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2223 if (ah->grh.sgid_index >=
2224 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2225 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2226 ah->grh.sgid_index,
2227 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2228 return -EINVAL;
2229 }
2811ba51
AS		 2230 }
2231
2232 if (ll == IB_LINK_LAYER_ETHERNET) {
2233 if (!(ah->ah_flags & IB_AH_GRH))
2234 return -EINVAL;
ed88451e
MD		 2235 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2236 &gid_type);
2237 if (err)
2238 return err;
2811ba51
AS		 2239 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2240 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2241 ah->grh.sgid_index);
2242 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
ed88451e
MD		 2243 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2244 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2811ba51 2245 } else {
d3ae2bde
NO		 2246 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2247 path->fl_free_ar |=
2248 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2249 path->rlid = cpu_to_be16(ah->dlid);
2250 path->grh_mlid = ah->src_path_bits & 0x7f;
2251 if (ah->ah_flags & IB_AH_GRH)
2252 path->grh_mlid |= 1 << 7;
2253 path->dci_cfi_prio_sl = ah->sl & 0xf;
2254 }
2255
2256 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2257 path->mgid_index = ah->grh.sgid_index;
2258 path->hop_limit = ah->grh.hop_limit;
2259 path->tclass_flowlabel =
2260 cpu_to_be32((ah->grh.traffic_class << 20) |
2261 (ah->grh.flow_label));
2262 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2263 }
2264
2265 err = ib_rate_to_mlx5(dev, ah->static_rate);
2266 if (err < 0)
2267 return err;
2268 path->static_rate = err;
2269 path->port = port;
2270
e126ba97 2271 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2272 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2273
75850d0b 2274 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2275 return modify_raw_packet_eth_prio(dev->mdev,
2276 &qp->raw_packet_qp.sq,
2277 ah->sl & 0xf);
2278
e126ba97
EC		 2279 return 0;
2280}
2281
2282static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2283 [MLX5_QP_STATE_INIT] = {
2284 [MLX5_QP_STATE_INIT] = {
2285 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2286 MLX5_QP_OPTPAR_RAE |
2287 MLX5_QP_OPTPAR_RWE |
2288 MLX5_QP_OPTPAR_PKEY_INDEX |
2289 MLX5_QP_OPTPAR_PRI_PORT,
2290 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2291 MLX5_QP_OPTPAR_PKEY_INDEX |
2292 MLX5_QP_OPTPAR_PRI_PORT,
2293 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2294 MLX5_QP_OPTPAR_Q_KEY |
2295 MLX5_QP_OPTPAR_PRI_PORT,
2296 },
2297 [MLX5_QP_STATE_RTR] = {
2298 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2299 MLX5_QP_OPTPAR_RRE |
2300 MLX5_QP_OPTPAR_RAE |
2301 MLX5_QP_OPTPAR_RWE |
2302 MLX5_QP_OPTPAR_PKEY_INDEX,
2303 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2304 MLX5_QP_OPTPAR_RWE |
2305 MLX5_QP_OPTPAR_PKEY_INDEX,
2306 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2307 MLX5_QP_OPTPAR_Q_KEY,
2308 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2309 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2310 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2311 MLX5_QP_OPTPAR_RRE |
2312 MLX5_QP_OPTPAR_RAE |
2313 MLX5_QP_OPTPAR_RWE |
2314 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2315 },
2316 },
2317 [MLX5_QP_STATE_RTR] = {
2318 [MLX5_QP_STATE_RTS] = {
2319 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2320 MLX5_QP_OPTPAR_RRE |
2321 MLX5_QP_OPTPAR_RAE |
2322 MLX5_QP_OPTPAR_RWE |
2323 MLX5_QP_OPTPAR_PM_STATE |
2324 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2325 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2326 MLX5_QP_OPTPAR_RWE |
2327 MLX5_QP_OPTPAR_PM_STATE,
2328 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2329 },
2330 },
2331 [MLX5_QP_STATE_RTS] = {
2332 [MLX5_QP_STATE_RTS] = {
2333 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2334 MLX5_QP_OPTPAR_RAE |
2335 MLX5_QP_OPTPAR_RWE |
2336 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2337 MLX5_QP_OPTPAR_PM_STATE |
2338 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2339 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2340 MLX5_QP_OPTPAR_PM_STATE |
2341 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2342 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2343 MLX5_QP_OPTPAR_SRQN |
2344 MLX5_QP_OPTPAR_CQN_RCV,
2345 },
2346 },
2347 [MLX5_QP_STATE_SQER] = {
2348 [MLX5_QP_STATE_RTS] = {
2349 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2350 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2351 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2352 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2353 MLX5_QP_OPTPAR_RWE |
2354 MLX5_QP_OPTPAR_RAE |
2355 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2356 },
2357 },
2358};
2359
2360static int ib_nr_to_mlx5_nr(int ib_mask)
2361{
2362 switch (ib_mask) {
2363 case IB_QP_STATE:
2364 return 0;
2365 case IB_QP_CUR_STATE:
2366 return 0;
2367 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2368 return 0;
2369 case IB_QP_ACCESS_FLAGS:
2370 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2371 MLX5_QP_OPTPAR_RAE;
2372 case IB_QP_PKEY_INDEX:
2373 return MLX5_QP_OPTPAR_PKEY_INDEX;
2374 case IB_QP_PORT:
2375 return MLX5_QP_OPTPAR_PRI_PORT;
2376 case IB_QP_QKEY:
2377 return MLX5_QP_OPTPAR_Q_KEY;
2378 case IB_QP_AV:
2379 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2380 MLX5_QP_OPTPAR_PRI_PORT;
2381 case IB_QP_PATH_MTU:
2382 return 0;
2383 case IB_QP_TIMEOUT:
2384 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2385 case IB_QP_RETRY_CNT:
2386 return MLX5_QP_OPTPAR_RETRY_COUNT;
2387 case IB_QP_RNR_RETRY:
2388 return MLX5_QP_OPTPAR_RNR_RETRY;
2389 case IB_QP_RQ_PSN:
2390 return 0;
2391 case IB_QP_MAX_QP_RD_ATOMIC:
2392 return MLX5_QP_OPTPAR_SRA_MAX;
2393 case IB_QP_ALT_PATH:
2394 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2395 case IB_QP_MIN_RNR_TIMER:
2396 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2397 case IB_QP_SQ_PSN:
2398 return 0;
2399 case IB_QP_MAX_DEST_RD_ATOMIC:
2400 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2401 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2402 case IB_QP_PATH_MIG_STATE:
2403 return MLX5_QP_OPTPAR_PM_STATE;
2404 case IB_QP_CAP:
2405 return 0;
2406 case IB_QP_DEST_QPN:
2407 return 0;
2408 }
2409 return 0;
2410}
2411
2412static int ib_mask_to_mlx5_opt(int ib_mask)
2413{
2414 int result = 0;
2415 int i;
2416
2417 for (i = 0; i < 8 * sizeof(int); i++) {
2418 if ((1 << i) & ib_mask)
2419 result |= ib_nr_to_mlx5_nr(1 << i);
2420 }
2421
2422 return result;
2423}
2424
eb49ab0c
AV		 2425static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2426 struct mlx5_ib_rq *rq, int new_state,
2427 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2428{
2429 void *in;
2430 void *rqc;
2431 int inlen;
2432 int err;
2433
2434 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2435 in = mlx5_vzalloc(inlen);
2436 if (!in)
2437 return -ENOMEM;
2438
2439 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2440
2441 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2442 MLX5_SET(rqc, rqc, state, new_state);
2443
eb49ab0c
AV		 2444 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2445 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2446 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2447 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2448 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2449 } else
2450 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2451 dev->ib_dev.name);
2452 }
2453
2454 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2455 if (err)
2456 goto out;
2457
2458 rq->state = new_state;
2459
2460out:
2461 kvfree(in);
2462 return err;
2463}
2464
2465static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2466 struct mlx5_ib_sq *sq,
2467 int new_state,
2468 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2469{
7d29f349
BW		 2470 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2471 u32 old_rate = ibqp->rate_limit;
2472 u32 new_rate = old_rate;
2473 u16 rl_index = 0;
ad5f8e96 2474 void *in;
2475 void *sqc;
2476 int inlen;
2477 int err;
2478
2479 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2480 in = mlx5_vzalloc(inlen);
2481 if (!in)
2482 return -ENOMEM;
2483
2484 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2485
2486 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2487 MLX5_SET(sqc, sqc, state, new_state);
2488
7d29f349
BW		 2489 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2490 if (new_state != MLX5_SQC_STATE_RDY)
2491 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2492 __func__);
2493 else
2494 new_rate = raw_qp_param->rate_limit;
2495 }
2496
2497 if (old_rate != new_rate) {
2498 if (new_rate) {
2499 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2500 if (err) {
2501 pr_err("Failed configuring rate %u: %d\n",
2502 new_rate, err);
2503 goto out;
2504 }
2505 }
2506
2507 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2508 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2509 }
2510
ad5f8e96 2511 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2512 if (err) {
2513 /* Remove new rate from table if failed */
2514 if (new_rate &&
2515 old_rate != new_rate)
2516 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2517 goto out;
7d29f349
BW		 2518 }
2519
2520 /* Only remove the old rate after new rate was set */
2521 if ((old_rate &&
2522 (old_rate != new_rate)) ||
2523 (new_state != MLX5_SQC_STATE_RDY))
2524 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2525
7d29f349 2526 ibqp->rate_limit = new_rate;
ad5f8e96 2527 sq->state = new_state;
2528
2529out:
2530 kvfree(in);
2531 return err;
2532}
2533
2534static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2535 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2536 u8 tx_affinity)
ad5f8e96 2537{
2538 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2539 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2540 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2541 int modify_rq = !!qp->rq.wqe_cnt;
2542 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2543 int rq_state;
2544 int sq_state;
2545 int err;
2546
0680efa2 2547 switch (raw_qp_param->operation) {
ad5f8e96 2548 case MLX5_CMD_OP_RST2INIT_QP:
2549 rq_state = MLX5_RQC_STATE_RDY;
2550 sq_state = MLX5_SQC_STATE_RDY;
2551 break;
2552 case MLX5_CMD_OP_2ERR_QP:
2553 rq_state = MLX5_RQC_STATE_ERR;
2554 sq_state = MLX5_SQC_STATE_ERR;
2555 break;
2556 case MLX5_CMD_OP_2RST_QP:
2557 rq_state = MLX5_RQC_STATE_RST;
2558 sq_state = MLX5_SQC_STATE_RST;
2559 break;
ad5f8e96 2560 case MLX5_CMD_OP_RTR2RTS_QP:
2561 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2562 if (raw_qp_param->set_mask ==
2563 MLX5_RAW_QP_RATE_LIMIT) {
2564 modify_rq = 0;
2565 sq_state = sq->state;
2566 } else {
2567 return raw_qp_param->set_mask ? -EINVAL : 0;
2568 }
2569 break;
2570 case MLX5_CMD_OP_INIT2INIT_QP:
2571 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2572 if (raw_qp_param->set_mask)
2573 return -EINVAL;
2574 else
2575 return 0;
ad5f8e96 2576 default:
2577 WARN_ON(1);
2578 return -EINVAL;
2579 }
2580
7d29f349
BW		 2581 if (modify_rq) {
2582 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2583 if (err)
2584 return err;
2585 }
2586
7d29f349 2587 if (modify_sq) {
13eab21f
AH		 2588 if (tx_affinity) {
2589 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2590 tx_affinity);
2591 if (err)
2592 return err;
2593 }
2594
7d29f349 2595 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2596 }
ad5f8e96 2597
2598 return 0;
2599}
2600
e126ba97
EC		 2601static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2602 const struct ib_qp_attr *attr, int attr_mask,
2603 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2604{
427c1e7b 2605 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2606 [MLX5_QP_STATE_RST] = {
2607 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2608 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2609 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2610 },
2611 [MLX5_QP_STATE_INIT] = {
2612 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2613 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2614 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2615 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2616 },
2617 [MLX5_QP_STATE_RTR] = {
2618 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2619 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2620 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2621 },
2622 [MLX5_QP_STATE_RTS] = {
2623 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2624 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2625 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2626 },
2627 [MLX5_QP_STATE_SQD] = {
2628 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2629 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2630 },
2631 [MLX5_QP_STATE_SQER] = {
2632 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2633 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2634 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2635 },
2636 [MLX5_QP_STATE_ERR] = {
2637 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2638 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2639 }
2640 };
2641
e126ba97
EC		 2642 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2643 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2644 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2645 struct mlx5_ib_cq *send_cq, *recv_cq;
2646 struct mlx5_qp_context *context;
e126ba97 2647 struct mlx5_ib_pd *pd;
eb49ab0c 2648 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2649 enum mlx5_qp_state mlx5_cur, mlx5_new;
2650 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2651 int mlx5_st;
2652 int err;
427c1e7b 2653 u16 op;
13eab21f 2654 u8 tx_affinity = 0;
e126ba97 2655
1a412fb1
SM		 2656 context = kzalloc(sizeof(*context), GFP_KERNEL);
2657 if (!context)
e126ba97
EC		 2658 return -ENOMEM;
2659
e126ba97 2660 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2661 if (err < 0) {
2662 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2663 goto out;
158abf86 2664 }
e126ba97
EC		 2665
2666 context->flags = cpu_to_be32(err << 16);
2667
2668 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2669 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2670 } else {
2671 switch (attr->path_mig_state) {
2672 case IB_MIG_MIGRATED:
2673 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2674 break;
2675 case IB_MIG_REARM:
2676 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2677 break;
2678 case IB_MIG_ARMED:
2679 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2680 break;
2681 }
2682 }
2683
13eab21f
AH		 2684 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2685 if ((ibqp->qp_type == IB_QPT_RC) ||
2686 (ibqp->qp_type == IB_QPT_UD &&
2687 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2688 (ibqp->qp_type == IB_QPT_UC) ||
2689 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2690 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2691 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2692 if (mlx5_lag_is_active(dev->mdev)) {
2693 tx_affinity = (unsigned int)atomic_add_return(1,
2694 &dev->roce.next_port) %
2695 MLX5_MAX_PORTS + 1;
2696 context->flags |= cpu_to_be32(tx_affinity << 24);
2697 }
2698 }
2699 }
2700
d16e91da 2701 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2702 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2703 } else if (ibqp->qp_type == IB_QPT_UD ||
2704 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2705 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2706 } else if (attr_mask & IB_QP_PATH_MTU) {
2707 if (attr->path_mtu < IB_MTU_256 ||
2708 attr->path_mtu > IB_MTU_4096) {
2709 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2710 err = -EINVAL;
2711 goto out;
2712 }
938fe83c
SM		 2713 context->mtu_msgmax = (attr->path_mtu << 5) |
2714 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2715 }
2716
2717 if (attr_mask & IB_QP_DEST_QPN)
2718 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2719
2720 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2721 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2722
2723 /* todo implement counter_index functionality */
2724
2725 if (is_sqp(ibqp->qp_type))
2726 context->pri_path.port = qp->port;
2727
2728 if (attr_mask & IB_QP_PORT)
2729 context->pri_path.port = attr->port_num;
2730
2731 if (attr_mask & IB_QP_AV) {
75850d0b 2732 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2733 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2734 attr_mask, 0, attr, false);
e126ba97
EC		 2735 if (err)
2736 goto out;
2737 }
2738
2739 if (attr_mask & IB_QP_TIMEOUT)
2740 context->pri_path.ackto_lt |= attr->timeout << 3;
2741
2742 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2743 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2744 &context->alt_path,
f879ee8d
AS		 2745 attr->alt_port_num,
2746 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2747 0, attr, true);
e126ba97
EC		 2748 if (err)
2749 goto out;
2750 }
2751
2752 pd = get_pd(qp);
89ea94a7
MG		 2753 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2754 &send_cq, &recv_cq);
e126ba97
EC		 2755
2756 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2757 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2758 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2759 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2760
2761 if (attr_mask & IB_QP_RNR_RETRY)
2762 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2763
2764 if (attr_mask & IB_QP_RETRY_CNT)
2765 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2766
2767 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2768 if (attr->max_rd_atomic)
2769 context->params1 |=
2770 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2771 }
2772
2773 if (attr_mask & IB_QP_SQ_PSN)
2774 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2775
2776 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2777 if (attr->max_dest_rd_atomic)
2778 context->params2 |=
2779 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2780 }
2781
2782 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2783 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2784
2785 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2786 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2787
2788 if (attr_mask & IB_QP_RQ_PSN)
2789 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2790
2791 if (attr_mask & IB_QP_QKEY)
2792 context->qkey = cpu_to_be32(attr->qkey);
2793
2794 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2795 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2796
0837e86a
MB		 2797 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2798 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2799 qp->port) - 1;
eb49ab0c 2800 mibport = &dev->port[port_num];
0837e86a 2801 context->qp_counter_set_usr_page |=
e1f24a79 2802 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 2803 }
2804
e126ba97
EC		 2805 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2806 context->sq_crq_size |= cpu_to_be16(1 << 4);
2807
b11a4f9c
HE		 2808 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2809 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2810
2811 mlx5_cur = to_mlx5_state(cur_state);
2812 mlx5_new = to_mlx5_state(new_state);
2813 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2814 if (mlx5_st < 0)
e126ba97
EC		 2815 goto out;
2816
427c1e7b 2817 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2818 !optab[mlx5_cur][mlx5_new])
2819 goto out;
2820
2821 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2822 optpar = ib_mask_to_mlx5_opt(attr_mask);
2823 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2824
0680efa2
AV		 2825 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2826 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2827
2828 raw_qp_param.operation = op;
eb49ab0c 2829 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 2830 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 2831 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2832 }
7d29f349
BW		 2833
2834 if (attr_mask & IB_QP_RATE_LIMIT) {
2835 raw_qp_param.rate_limit = attr->rate_limit;
2836 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2837 }
2838
13eab21f 2839 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2840 } else {
1a412fb1 2841 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2842 &base->mqp);
0680efa2
AV		 2843 }
2844
e126ba97
EC		 2845 if (err)
2846 goto out;
2847
2848 qp->state = new_state;
2849
2850 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2851 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2852 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2853 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2854 if (attr_mask & IB_QP_PORT)
2855 qp->port = attr->port_num;
2856 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2857 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2858
2859 /*
2860 * If we moved a kernel QP to RESET, clean up all old CQ
2861 * entries and reinitialize the QP.
2862 */
2863 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2864 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2865 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2866 if (send_cq != recv_cq)
19098df2 2867 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2868
2869 qp->rq.head = 0;
2870 qp->rq.tail = 0;
2871 qp->sq.head = 0;
2872 qp->sq.tail = 0;
2873 qp->sq.cur_post = 0;
2874 qp->sq.last_poll = 0;
2875 qp->db.db[MLX5_RCV_DBR] = 0;
2876 qp->db.db[MLX5_SND_DBR] = 0;
2877 }
2878
2879out:
1a412fb1 2880 kfree(context);
e126ba97
EC		 2881 return err;
2882}
2883
2884int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2885 int attr_mask, struct ib_udata *udata)
2886{
2887 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2888 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2889 enum ib_qp_type qp_type;
e126ba97
EC		 2890 enum ib_qp_state cur_state, new_state;
2891 int err = -EINVAL;
2892 int port;
2811ba51 2893 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2894
28d61370
YH		 2895 if (ibqp->rwq_ind_tbl)
2896 return -ENOSYS;
2897
d16e91da
HE		 2898 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2899 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2900
2901 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2902 IB_QPT_GSI : ibqp->qp_type;
2903
e126ba97
EC		 2904 mutex_lock(&qp->mutex);
2905
2906 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2907 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2908
2811ba51
AS		 2909 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2910 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2911 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2912 }
2913
d16e91da
HE		 2914 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2915 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2916 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2917 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2918 goto out;
158abf86 2919 }
e126ba97
EC		 2920
2921 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2922 (attr->port_num == 0 ||
158abf86
HE		 2923 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2924 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2925 attr->port_num, dev->num_ports);
e126ba97 2926 goto out;
158abf86 2927 }
e126ba97
EC		 2928
2929 if (attr_mask & IB_QP_PKEY_INDEX) {
2930 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2931 if (attr->pkey_index >=
158abf86
HE		 2932 dev->mdev->port_caps[port - 1].pkey_table_len) {
2933 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2934 attr->pkey_index);
e126ba97 2935 goto out;
158abf86 2936 }
e126ba97
EC		 2937 }
2938
2939 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2940 attr->max_rd_atomic >
158abf86
HE		 2941 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2942 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2943 attr->max_rd_atomic);
e126ba97 2944 goto out;
158abf86 2945 }
e126ba97
EC		 2946
2947 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2948 attr->max_dest_rd_atomic >
158abf86
HE		 2949 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2950 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2951 attr->max_dest_rd_atomic);
e126ba97 2952 goto out;
158abf86 2953 }
e126ba97
EC		 2954
2955 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2956 err = 0;
2957 goto out;
2958 }
2959
2960 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2961
2962out:
2963 mutex_unlock(&qp->mutex);
2964 return err;
2965}
2966
2967static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2968{
2969 struct mlx5_ib_cq *cq;
2970 unsigned cur;
2971
2972 cur = wq->head - wq->tail;
2973 if (likely(cur + nreq < wq->max_post))
2974 return 0;
2975
2976 cq = to_mcq(ib_cq);
2977 spin_lock(&cq->lock);
2978 cur = wq->head - wq->tail;
2979 spin_unlock(&cq->lock);
2980
2981 return cur + nreq >= wq->max_post;
2982}
2983
2984static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2985 u64 remote_addr, u32 rkey)
2986{
2987 rseg->raddr = cpu_to_be64(remote_addr);
2988 rseg->rkey = cpu_to_be32(rkey);
2989 rseg->reserved = 0;
2990}
2991
f0313965
ES		 2992static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2993 struct ib_send_wr *wr, void *qend,
2994 struct mlx5_ib_qp *qp, int *size)
2995{
2996 void *seg = eseg;
2997
2998 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2999
3000 if (wr->send_flags & IB_SEND_IP_CSUM)
3001 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3002 MLX5_ETH_WQE_L4_CSUM;
3003
3004 seg += sizeof(struct mlx5_wqe_eth_seg);
3005 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3006
3007 if (wr->opcode == IB_WR_LSO) {
3008 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3009 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3010 u64 left, leftlen, copysz;
3011 void *pdata = ud_wr->header;
3012
3013 left = ud_wr->hlen;
3014 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3015 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3016
3017 /*
3018 * check if there is space till the end of queue, if yes,
3019 * copy all in one shot, otherwise copy till the end of queue,
3020 * rollback and than the copy the left
3021 */
2b31f7ae 3022 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3023 copysz = min_t(u64, leftlen, left);
3024
3025 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3026
3027 if (likely(copysz > size_of_inl_hdr_start)) {
3028 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3029 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3030 }
3031
3032 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3033 seg = mlx5_get_send_wqe(qp, 0);
3034 left -= copysz;
3035 pdata += copysz;
3036 memcpy(seg, pdata, left);
3037 seg += ALIGN(left, 16);
3038 *size += ALIGN(left, 16) / 16;
3039 }
3040 }
3041
3042 return seg;
3043}
3044
e126ba97
EC		 3045static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3046 struct ib_send_wr *wr)
3047{
e622f2f4
CH		 3048 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3049 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3050 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3051}
3052
3053static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3054{
3055 dseg->byte_count = cpu_to_be32(sg->length);
3056 dseg->lkey = cpu_to_be32(sg->lkey);
3057 dseg->addr = cpu_to_be64(sg->addr);
3058}
3059
31616255 3060static u64 get_xlt_octo(u64 bytes)
e126ba97 3061{
31616255
AK		 3062 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3063 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3064}
3065
3066static __be64 frwr_mkey_mask(void)
3067{
3068 u64 result;
3069
3070 result = MLX5_MKEY_MASK_LEN |
3071 MLX5_MKEY_MASK_PAGE_SIZE |
3072 MLX5_MKEY_MASK_START_ADDR |
3073 MLX5_MKEY_MASK_EN_RINVAL |
3074 MLX5_MKEY_MASK_KEY |
3075 MLX5_MKEY_MASK_LR |
3076 MLX5_MKEY_MASK_LW |
3077 MLX5_MKEY_MASK_RR |
3078 MLX5_MKEY_MASK_RW |
3079 MLX5_MKEY_MASK_A |
3080 MLX5_MKEY_MASK_SMALL_FENCE |
3081 MLX5_MKEY_MASK_FREE;
3082
3083 return cpu_to_be64(result);
3084}
3085
e6631814
SG		 3086static __be64 sig_mkey_mask(void)
3087{
3088 u64 result;
3089
3090 result = MLX5_MKEY_MASK_LEN |
3091 MLX5_MKEY_MASK_PAGE_SIZE |
3092 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3093 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3094 MLX5_MKEY_MASK_EN_RINVAL |
3095 MLX5_MKEY_MASK_KEY |
3096 MLX5_MKEY_MASK_LR |
3097 MLX5_MKEY_MASK_LW |
3098 MLX5_MKEY_MASK_RR |
3099 MLX5_MKEY_MASK_RW |
3100 MLX5_MKEY_MASK_SMALL_FENCE |
3101 MLX5_MKEY_MASK_FREE |
3102 MLX5_MKEY_MASK_BSF_EN;
3103
3104 return cpu_to_be64(result);
3105}
3106
8a187ee5 3107static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3108 struct mlx5_ib_mr *mr)
8a187ee5 3109{
31616255 3110 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3111
3112 memset(umr, 0, sizeof(*umr));
b005d316 3113
8a187ee5 3114 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3115 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3116 umr->mkey_mask = frwr_mkey_mask();
3117}
3118
dd01e66a 3119static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3120{
3121 memset(umr, 0, sizeof(*umr));
dd01e66a 3122 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3123 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3124}
3125
31616255 3126static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3127{
3128 u64 result;
3129
31616255 3130 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3131 MLX5_MKEY_MASK_FREE;
3132
968e78dd
HE		 3133 return cpu_to_be64(result);
3134}
3135
31616255 3136static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3137{
3138 u64 result;
3139
3140 result = MLX5_MKEY_MASK_FREE;
3141
3142 return cpu_to_be64(result);
3143}
3144
56e11d62
NO		 3145static __be64 get_umr_update_translation_mask(void)
3146{
3147 u64 result;
3148
3149 result = MLX5_MKEY_MASK_LEN |
3150 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3151 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3152
3153 return cpu_to_be64(result);
3154}
3155
31616255 3156static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3157{
3158 u64 result;
3159
31616255
AK		 3160 result = MLX5_MKEY_MASK_LR |
3161 MLX5_MKEY_MASK_LW |
56e11d62 3162 MLX5_MKEY_MASK_RR |
31616255
AK		 3163 MLX5_MKEY_MASK_RW;
3164
3165 if (atomic)
3166 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3167
3168 return cpu_to_be64(result);
3169}
3170
3171static __be64 get_umr_update_pd_mask(void)
3172{
3173 u64 result;
3174
31616255 3175 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3176
3177 return cpu_to_be64(result);
3178}
3179
e126ba97 3180static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3181 struct ib_send_wr *wr, int atomic)
e126ba97 3182{
e622f2f4 3183 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3184
3185 memset(umr, 0, sizeof(*umr));
3186
968e78dd
HE		 3187 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3188 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3189 else
3190 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3191
31616255
AK		 3192 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3193 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3194 u64 offset = get_xlt_octo(umrwr->offset);
3195
3196 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3197 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3198 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3199 }
31616255
AK		 3200 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3201 umr->mkey_mask |= get_umr_update_translation_mask();
3202 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3203 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3204 umr->mkey_mask |= get_umr_update_pd_mask();
3205 }
3206 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3207 umr->mkey_mask |= get_umr_enable_mr_mask();
3208 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3209 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3210
3211 if (!wr->num_sge)
968e78dd 3212 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3213}
3214
3215static u8 get_umr_flags(int acc)
3216{
3217 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3218 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3219 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3220 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3221 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3222}
3223
8a187ee5
SG		 3224static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3225 struct mlx5_ib_mr *mr,
3226 u32 key, int access)
3227{
3228 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3229
3230 memset(seg, 0, sizeof(*seg));
b005d316 3231
ec22eb53 3232 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3233 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3234 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3235 /* KLMs take twice the size of MTTs */
3236 ndescs *= 2;
3237
3238 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3239 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3240 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3241 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3242 seg->len = cpu_to_be64(mr->ibmr.length);
3243 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3244}
3245
dd01e66a 3246static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3247{
3248 memset(seg, 0, sizeof(*seg));
dd01e66a 3249 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3250}
3251
3252static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3253{
e622f2f4 3254 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3255
e126ba97 3256 memset(seg, 0, sizeof(*seg));
31616255 3257 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3258 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3259
968e78dd 3260 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3261 if (umrwr->pd)
3262 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3263 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3264 !umrwr->length)
3265 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3266
3267 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3268 seg->len = cpu_to_be64(umrwr->length);
3269 seg->log2_page_size = umrwr->page_shift;
746b5583 3270 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3271 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3272}
3273
8a187ee5
SG		 3274static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3275 struct mlx5_ib_mr *mr,
3276 struct mlx5_ib_pd *pd)
3277{
3278 int bcount = mr->desc_size * mr->ndescs;
3279
3280 dseg->addr = cpu_to_be64(mr->desc_map);
3281 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3282 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3283}
3284
e126ba97
EC		 3285static __be32 send_ieth(struct ib_send_wr *wr)
3286{
3287 switch (wr->opcode) {
3288 case IB_WR_SEND_WITH_IMM:
3289 case IB_WR_RDMA_WRITE_WITH_IMM:
3290 return wr->ex.imm_data;
3291
3292 case IB_WR_SEND_WITH_INV:
3293 return cpu_to_be32(wr->ex.invalidate_rkey);
3294
3295 default:
3296 return 0;
3297 }
3298}
3299
3300static u8 calc_sig(void *wqe, int size)
3301{
3302 u8 *p = wqe;
3303 u8 res = 0;
3304 int i;
3305
3306 for (i = 0; i < size; i++)
3307 res ^= p[i];
3308
3309 return ~res;
3310}
3311
3312static u8 wq_sig(void *wqe)
3313{
3314 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3315}
3316
3317static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3318 void *wqe, int *sz)
3319{
3320 struct mlx5_wqe_inline_seg *seg;
3321 void *qend = qp->sq.qend;
3322 void *addr;
3323 int inl = 0;
3324 int copy;
3325 int len;
3326 int i;
3327
3328 seg = wqe;
3329 wqe += sizeof(*seg);
3330 for (i = 0; i < wr->num_sge; i++) {
3331 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3332 len = wr->sg_list[i].length;
3333 inl += len;
3334
3335 if (unlikely(inl > qp->max_inline_data))
3336 return -ENOMEM;
3337
3338 if (unlikely(wqe + len > qend)) {
3339 copy = qend - wqe;
3340 memcpy(wqe, addr, copy);
3341 addr += copy;
3342 len -= copy;
3343 wqe = mlx5_get_send_wqe(qp, 0);
3344 }
3345 memcpy(wqe, addr, len);
3346 wqe += len;
3347 }
3348
3349 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3350
3351 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3352
3353 return 0;
3354}
3355
e6631814
SG		 3356static u16 prot_field_size(enum ib_signature_type type)
3357{
3358 switch (type) {
3359 case IB_SIG_TYPE_T10_DIF:
3360 return MLX5_DIF_SIZE;
3361 default:
3362 return 0;
3363 }
3364}
3365
3366static u8 bs_selector(int block_size)
3367{
3368 switch (block_size) {
3369 case 512: return 0x1;
3370 case 520: return 0x2;
3371 case 4096: return 0x3;
3372 case 4160: return 0x4;
3373 case 1073741824: return 0x5;
3374 default: return 0;
3375 }
3376}
3377
78eda2bb
SG		 3378static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3379 struct mlx5_bsf_inl *inl)
e6631814 3380{
142537f4
SG		 3381 /* Valid inline section and allow BSF refresh */
3382 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3383 MLX5_BSF_REFRESH_DIF);
3384 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3385 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3386 /* repeating block */
3387 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3388 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3389 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3390
78eda2bb
SG		 3391 if (domain->sig.dif.ref_remap)
3392 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3393
78eda2bb
SG		 3394 if (domain->sig.dif.app_escape) {
3395 if (domain->sig.dif.ref_escape)
3396 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3397 else
3398 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3399 }
3400
78eda2bb
SG		 3401 inl->dif_app_bitmask_check =
3402 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3403}
3404
3405static int mlx5_set_bsf(struct ib_mr *sig_mr,
3406 struct ib_sig_attrs *sig_attrs,
3407 struct mlx5_bsf *bsf, u32 data_size)
3408{
3409 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3410 struct mlx5_bsf_basic *basic = &bsf->basic;
3411 struct ib_sig_domain *mem = &sig_attrs->mem;
3412 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3413
c7f44fbd 3414 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3415
3416 /* Basic + Extended + Inline */
3417 basic->bsf_size_sbs = 1 << 7;
3418 /* Input domain check byte mask */
3419 basic->check_byte_mask = sig_attrs->check_mask;
3420 basic->raw_data_size = cpu_to_be32(data_size);
3421
3422 /* Memory domain */
e6631814 3423 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3424 case IB_SIG_TYPE_NONE:
3425 break;
e6631814 3426 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3427 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3428 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3429 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3430 break;
3431 default:
3432 return -EINVAL;
3433 }
e6631814 3434
78eda2bb
SG		 3435 /* Wire domain */
3436 switch (sig_attrs->wire.sig_type) {
3437 case IB_SIG_TYPE_NONE:
3438 break;
3439 case IB_SIG_TYPE_T10_DIF:
e6631814 3440 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3441 mem->sig_type == wire->sig_type) {
e6631814 3442 /* Same block structure */
142537f4 3443 basic->bsf_size_sbs |= 1 << 4;
e6631814 3444 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3445 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3446 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3447 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3448 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3449 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3450 } else
3451 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3452
142537f4 3453 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3454 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3455 break;
e6631814
SG		 3456 default:
3457 return -EINVAL;
3458 }
3459
3460 return 0;
3461}
3462
e622f2f4
CH		 3463static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3464 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3465{
e622f2f4
CH		 3466 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3467 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3468 struct mlx5_bsf *bsf;
e622f2f4
CH		 3469 u32 data_len = wr->wr.sg_list->length;
3470 u32 data_key = wr->wr.sg_list->lkey;
3471 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3472 int ret;
3473 int wqe_size;
3474
e622f2f4
CH		 3475 if (!wr->prot ||
3476 (data_key == wr->prot->lkey &&
3477 data_va == wr->prot->addr &&
3478 data_len == wr->prot->length)) {
e6631814
SG		 3479 /**
3480 * Source domain doesn't contain signature information
5c273b16 3481 * or data and protection are interleaved in memory.
e6631814
SG		 3482 * So need construct:
3483 * ------------------
3484 * | data_klm |
3485 * ------------------
3486 * | BSF |
3487 * ------------------
3488 **/
3489 struct mlx5_klm *data_klm = *seg;
3490
3491 data_klm->bcount = cpu_to_be32(data_len);
3492 data_klm->key = cpu_to_be32(data_key);
3493 data_klm->va = cpu_to_be64(data_va);
3494 wqe_size = ALIGN(sizeof(*data_klm), 64);
3495 } else {
3496 /**
3497 * Source domain contains signature information
3498 * So need construct a strided block format:
3499 * ---------------------------
3500 * | stride_block_ctrl |
3501 * ---------------------------
3502 * | data_klm |
3503 * ---------------------------
3504 * | prot_klm |
3505 * ---------------------------
3506 * | BSF |
3507 * ---------------------------
3508 **/
3509 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3510 struct mlx5_stride_block_entry *data_sentry;
3511 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3512 u32 prot_key = wr->prot->lkey;
3513 u64 prot_va = wr->prot->addr;
e6631814
SG		 3514 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3515 int prot_size;
3516
3517 sblock_ctrl = *seg;
3518 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3519 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3520
3521 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3522 if (!prot_size) {
3523 pr_err("Bad block size given: %u\n", block_size);
3524 return -EINVAL;
3525 }
3526 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3527 prot_size);
3528 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3529 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3530 sblock_ctrl->num_entries = cpu_to_be16(2);
3531
3532 data_sentry->bcount = cpu_to_be16(block_size);
3533 data_sentry->key = cpu_to_be32(data_key);
3534 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3535 data_sentry->stride = cpu_to_be16(block_size);
3536
e6631814
SG		 3537 prot_sentry->bcount = cpu_to_be16(prot_size);
3538 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3539 prot_sentry->va = cpu_to_be64(prot_va);
3540 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3541
e6631814
SG		 3542 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3543 sizeof(*prot_sentry), 64);
3544 }
3545
3546 *seg += wqe_size;
3547 *size += wqe_size / 16;
3548 if (unlikely((*seg == qp->sq.qend)))
3549 *seg = mlx5_get_send_wqe(qp, 0);
3550
3551 bsf = *seg;
3552 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3553 if (ret)
3554 return -EINVAL;
3555
3556 *seg += sizeof(*bsf);
3557 *size += sizeof(*bsf) / 16;
3558 if (unlikely((*seg == qp->sq.qend)))
3559 *seg = mlx5_get_send_wqe(qp, 0);
3560
3561 return 0;
3562}
3563
3564static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3565 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3566 u32 length, u32 pdn)
3567{
e622f2f4 3568 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3569 u32 sig_key = sig_mr->rkey;
d5436ba0 3570 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3571
3572 memset(seg, 0, sizeof(*seg));
3573
e622f2f4 3574 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3575 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3576 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3577 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3578 MLX5_MKEY_BSF_EN | pdn);
3579 seg->len = cpu_to_be64(length);
31616255 3580 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3581 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3582}
3583
3584static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3585 u32 size)
e6631814
SG		 3586{
3587 memset(umr, 0, sizeof(*umr));
3588
3589 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3590 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3591 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3592 umr->mkey_mask = sig_mkey_mask();
3593}
3594
3595
e622f2f4 3596static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3597 void **seg, int *size)
3598{
e622f2f4
CH		 3599 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3600 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3601 u32 pdn = get_pd(qp)->pdn;
31616255 3602 u32 xlt_size;
e6631814
SG		 3603 int region_len, ret;
3604
e622f2f4
CH		 3605 if (unlikely(wr->wr.num_sge != 1) ||
3606 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3607 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3608 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3609 return -EINVAL;
3610
3611 /* length of the protected region, data + protection */
e622f2f4
CH		 3612 region_len = wr->wr.sg_list->length;
3613 if (wr->prot &&
3614 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3615 wr->prot->addr != wr->wr.sg_list->addr ||
3616 wr->prot->length != wr->wr.sg_list->length))
3617 region_len += wr->prot->length;
e6631814
SG		 3618
3619 /**
3620 * KLM octoword size - if protection was provided
3621 * then we use strided block format (3 octowords),
3622 * else we use single KLM (1 octoword)
3623 **/
31616255 3624 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3625
31616255 3626 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3627 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3628 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3629 if (unlikely((*seg == qp->sq.qend)))
3630 *seg = mlx5_get_send_wqe(qp, 0);
3631
31616255 3632 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3633 *seg += sizeof(struct mlx5_mkey_seg);
3634 *size += sizeof(struct mlx5_mkey_seg) / 16;
3635 if (unlikely((*seg == qp->sq.qend)))
3636 *seg = mlx5_get_send_wqe(qp, 0);
3637
3638 ret = set_sig_data_segment(wr, qp, seg, size);
3639 if (ret)
3640 return ret;
3641
d5436ba0 3642 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3643 return 0;
3644}
3645
3646static int set_psv_wr(struct ib_sig_domain *domain,
3647 u32 psv_idx, void **seg, int *size)
3648{
3649 struct mlx5_seg_set_psv *psv_seg = *seg;
3650
3651 memset(psv_seg, 0, sizeof(*psv_seg));
3652 psv_seg->psv_num = cpu_to_be32(psv_idx);
3653 switch (domain->sig_type) {
78eda2bb
SG		 3654 case IB_SIG_TYPE_NONE:
3655 break;
e6631814
SG		 3656 case IB_SIG_TYPE_T10_DIF:
3657 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3658 domain->sig.dif.app_tag);
3659 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3660 break;
e6631814 3661 default:
12bbf1ea
LR		 3662 pr_err("Bad signature type (%d) is given.\n",
3663 domain->sig_type);
3664 return -EINVAL;
e6631814
SG		 3665 }
3666
78eda2bb
SG		 3667 *seg += sizeof(*psv_seg);
3668 *size += sizeof(*psv_seg) / 16;
3669
e6631814
SG		 3670 return 0;
3671}
3672
8a187ee5
SG		 3673static int set_reg_wr(struct mlx5_ib_qp *qp,
3674 struct ib_reg_wr *wr,
3675 void **seg, int *size)
3676{
3677 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3678 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3679
3680 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3681 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3682 "Invalid IB_SEND_INLINE send flag\n");
3683 return -EINVAL;
3684 }
3685
3686 set_reg_umr_seg(*seg, mr);
3687 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3688 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3689 if (unlikely((*seg == qp->sq.qend)))
3690 *seg = mlx5_get_send_wqe(qp, 0);
3691
3692 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3693 *seg += sizeof(struct mlx5_mkey_seg);
3694 *size += sizeof(struct mlx5_mkey_seg) / 16;
3695 if (unlikely((*seg == qp->sq.qend)))
3696 *seg = mlx5_get_send_wqe(qp, 0);
3697
3698 set_reg_data_seg(*seg, mr, pd);
3699 *seg += sizeof(struct mlx5_wqe_data_seg);
3700 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3701
3702 return 0;
3703}
3704
dd01e66a 3705static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3706{
dd01e66a 3707 set_linv_umr_seg(*seg);
e126ba97
EC		 3708 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3709 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3710 if (unlikely((*seg == qp->sq.qend)))
3711 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3712 set_linv_mkey_seg(*seg);
e126ba97
EC		 3713 *seg += sizeof(struct mlx5_mkey_seg);
3714 *size += sizeof(struct mlx5_mkey_seg) / 16;
3715 if (unlikely((*seg == qp->sq.qend)))
3716 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3717}
3718
3719static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3720{
3721 __be32 *p = NULL;
3722 int tidx = idx;
3723 int i, j;
3724
3725 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3726 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3727 if ((i & 0xf) == 0) {
3728 void *buf = mlx5_get_send_wqe(qp, tidx);
3729 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3730 p = buf;
3731 j = 0;
3732 }
3733 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3734 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3735 be32_to_cpu(p[j + 3]));
3736 }
3737}
3738
e126ba97
EC		 3739static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3740{
3741 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3742 wr->send_flags & IB_SEND_FENCE))
3743 return MLX5_FENCE_MODE_STRONG_ORDERING;
3744
3745 if (unlikely(fence)) {
3746 if (wr->send_flags & IB_SEND_FENCE)
3747 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3748 else
3749 return fence;
c9b25495
EC		 3750 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3751 return MLX5_FENCE_MODE_FENCE;
e126ba97 3752 }
c9b25495
EC		 3753
3754 return 0;
e126ba97
EC		 3755}
3756
6e5eadac
SG		 3757static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3758 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3759 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3760 int *size, int nreq)
3761{
b2a232d2
LR		 3762 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3763 return -ENOMEM;
6e5eadac
SG		 3764
3765 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3766 *seg = mlx5_get_send_wqe(qp, *idx);
3767 *ctrl = *seg;
3768 *(uint32_t *)(*seg + 8) = 0;
3769 (*ctrl)->imm = send_ieth(wr);
3770 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3771 (wr->send_flags & IB_SEND_SIGNALED ?
3772 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3773 (wr->send_flags & IB_SEND_SOLICITED ?
3774 MLX5_WQE_CTRL_SOLICITED : 0);
3775
3776 *seg += sizeof(**ctrl);
3777 *size = sizeof(**ctrl) / 16;
3778
b2a232d2 3779 return 0;
6e5eadac
SG		 3780}
3781
3782static void finish_wqe(struct mlx5_ib_qp *qp,
3783 struct mlx5_wqe_ctrl_seg *ctrl,
3784 u8 size, unsigned idx, u64 wr_id,
3785 int nreq, u8 fence, u8 next_fence,
3786 u32 mlx5_opcode)
3787{
3788 u8 opmod = 0;
3789
3790 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3791 mlx5_opcode | ((u32)opmod << 24));
19098df2 3792 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3793 ctrl->fm_ce_se |= fence;
3794 qp->fm_cache = next_fence;
3795 if (unlikely(qp->wq_sig))
3796 ctrl->signature = wq_sig(ctrl);
3797
3798 qp->sq.wrid[idx] = wr_id;
3799 qp->sq.w_list[idx].opcode = mlx5_opcode;
3800 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3801 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3802 qp->sq.w_list[idx].next = qp->sq.cur_post;
3803}
3804
3805
e126ba97
EC		 3806int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3807 struct ib_send_wr **bad_wr)
3808{
3809 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3810 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3811 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3812 struct mlx5_ib_qp *qp;
e6631814 3813 struct mlx5_ib_mr *mr;
e126ba97
EC		 3814 struct mlx5_wqe_data_seg *dpseg;
3815 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3816 struct mlx5_bf *bf;
e126ba97 3817 int uninitialized_var(size);
d16e91da 3818 void *qend;
e126ba97 3819 unsigned long flags;
e126ba97
EC		 3820 unsigned idx;
3821 int err = 0;
3822 int inl = 0;
3823 int num_sge;
3824 void *seg;
3825 int nreq;
3826 int i;
3827 u8 next_fence = 0;
e126ba97
EC		 3828 u8 fence;
3829
d16e91da
HE		 3830 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3831 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3832
3833 qp = to_mqp(ibqp);
5fe9dec0 3834 bf = &qp->bf;
d16e91da
HE		 3835 qend = qp->sq.qend;
3836
e126ba97
EC		 3837 spin_lock_irqsave(&qp->sq.lock, flags);
3838
89ea94a7
MG		 3839 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3840 err = -EIO;
3841 *bad_wr = wr;
3842 nreq = 0;
3843 goto out;
3844 }
3845
e126ba97 3846 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3847 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3848 mlx5_ib_warn(dev, "\n");
3849 err = -EINVAL;
3850 *bad_wr = wr;
3851 goto out;
3852 }
3853
6e5eadac
SG		 3854 fence = qp->fm_cache;
3855 num_sge = wr->num_sge;
3856 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3857 mlx5_ib_warn(dev, "\n");
24be409b 3858 err = -EINVAL;
e126ba97
EC		 3859 *bad_wr = wr;
3860 goto out;
3861 }
3862
6e5eadac
SG		 3863 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3864 if (err) {
e126ba97
EC		 3865 mlx5_ib_warn(dev, "\n");
3866 err = -ENOMEM;
3867 *bad_wr = wr;
3868 goto out;
3869 }
3870
e126ba97
EC		 3871 switch (ibqp->qp_type) {
3872 case IB_QPT_XRC_INI:
3873 xrc = seg;
e126ba97
EC		 3874 seg += sizeof(*xrc);
3875 size += sizeof(*xrc) / 16;
3876 /* fall through */
3877 case IB_QPT_RC:
3878 switch (wr->opcode) {
3879 case IB_WR_RDMA_READ:
3880 case IB_WR_RDMA_WRITE:
3881 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3882 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3883 rdma_wr(wr)->rkey);
f241e749 3884 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3885 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3886 break;
3887
3888 case IB_WR_ATOMIC_CMP_AND_SWP:
3889 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3890 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3891 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3892 err = -ENOSYS;
3893 *bad_wr = wr;
3894 goto out;
e126ba97
EC		 3895
3896 case IB_WR_LOCAL_INV:
3897 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3898 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3899 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3900 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3901 num_sge = 0;
3902 break;
3903
8a187ee5
SG		 3904 case IB_WR_REG_MR:
3905 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3906 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3907 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3908 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3909 if (err) {
3910 *bad_wr = wr;
3911 goto out;
3912 }
3913 num_sge = 0;
3914 break;
3915
e6631814
SG		 3916 case IB_WR_REG_SIG_MR:
3917 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3918 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3919
3920 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3921 err = set_sig_umr_wr(wr, qp, &seg, &size);
3922 if (err) {
3923 mlx5_ib_warn(dev, "\n");
3924 *bad_wr = wr;
3925 goto out;
3926 }
3927
3928 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3929 nreq, get_fence(fence, wr),
3930 next_fence, MLX5_OPCODE_UMR);
3931 /*
3932 * SET_PSV WQEs are not signaled and solicited
3933 * on error
3934 */
3935 wr->send_flags &= ~IB_SEND_SIGNALED;
3936 wr->send_flags |= IB_SEND_SOLICITED;
3937 err = begin_wqe(qp, &seg, &ctrl, wr,
3938 &idx, &size, nreq);
3939 if (err) {
3940 mlx5_ib_warn(dev, "\n");
3941 err = -ENOMEM;
3942 *bad_wr = wr;
3943 goto out;
3944 }
3945
e622f2f4 3946 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3947 mr->sig->psv_memory.psv_idx, &seg,
3948 &size);
3949 if (err) {
3950 mlx5_ib_warn(dev, "\n");
3951 *bad_wr = wr;
3952 goto out;
3953 }
3954
3955 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3956 nreq, get_fence(fence, wr),
3957 next_fence, MLX5_OPCODE_SET_PSV);
3958 err = begin_wqe(qp, &seg, &ctrl, wr,
3959 &idx, &size, nreq);
3960 if (err) {
3961 mlx5_ib_warn(dev, "\n");
3962 err = -ENOMEM;
3963 *bad_wr = wr;
3964 goto out;
3965 }
3966
3967 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3968 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3969 mr->sig->psv_wire.psv_idx, &seg,
3970 &size);
3971 if (err) {
3972 mlx5_ib_warn(dev, "\n");
3973 *bad_wr = wr;
3974 goto out;
3975 }
3976
3977 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3978 nreq, get_fence(fence, wr),
3979 next_fence, MLX5_OPCODE_SET_PSV);
3980 num_sge = 0;
3981 goto skip_psv;
3982
e126ba97
EC		 3983 default:
3984 break;
3985 }
3986 break;
3987
3988 case IB_QPT_UC:
3989 switch (wr->opcode) {
3990 case IB_WR_RDMA_WRITE:
3991 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3992 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3993 rdma_wr(wr)->rkey);
e126ba97
EC		 3994 seg += sizeof(struct mlx5_wqe_raddr_seg);
3995 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3996 break;
3997
3998 default:
3999 break;
4000 }
4001 break;
4002
e126ba97 4003 case IB_QPT_SMI:
1e0e50b6
MG		 4004 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4005 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4006 err = -EPERM;
4007 *bad_wr = wr;
4008 goto out;
4009 }
d16e91da 4010 case MLX5_IB_QPT_HW_GSI:
e126ba97 4011 set_datagram_seg(seg, wr);
f241e749 4012 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4013 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4014 if (unlikely((seg == qend)))
4015 seg = mlx5_get_send_wqe(qp, 0);
4016 break;
f0313965
ES		 4017 case IB_QPT_UD:
4018 set_datagram_seg(seg, wr);
4019 seg += sizeof(struct mlx5_wqe_datagram_seg);
4020 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4021
4022 if (unlikely((seg == qend)))
4023 seg = mlx5_get_send_wqe(qp, 0);
4024
4025 /* handle qp that supports ud offload */
4026 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4027 struct mlx5_wqe_eth_pad *pad;
e126ba97 4028
f0313965
ES		 4029 pad = seg;
4030 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4031 seg += sizeof(struct mlx5_wqe_eth_pad);
4032 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4033
4034 seg = set_eth_seg(seg, wr, qend, qp, &size);
4035
4036 if (unlikely((seg == qend)))
4037 seg = mlx5_get_send_wqe(qp, 0);
4038 }
4039 break;
e126ba97
EC		 4040 case MLX5_IB_QPT_REG_UMR:
4041 if (wr->opcode != MLX5_IB_WR_UMR) {
4042 err = -EINVAL;
4043 mlx5_ib_warn(dev, "bad opcode\n");
4044 goto out;
4045 }
4046 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4047 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4048 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4049 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4050 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4051 if (unlikely((seg == qend)))
4052 seg = mlx5_get_send_wqe(qp, 0);
4053 set_reg_mkey_segment(seg, wr);
4054 seg += sizeof(struct mlx5_mkey_seg);
4055 size += sizeof(struct mlx5_mkey_seg) / 16;
4056 if (unlikely((seg == qend)))
4057 seg = mlx5_get_send_wqe(qp, 0);
4058 break;
4059
4060 default:
4061 break;
4062 }
4063
4064 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4065 int uninitialized_var(sz);
4066
4067 err = set_data_inl_seg(qp, wr, seg, &sz);
4068 if (unlikely(err)) {
4069 mlx5_ib_warn(dev, "\n");
4070 *bad_wr = wr;
4071 goto out;
4072 }
4073 inl = 1;
4074 size += sz;
4075 } else {
4076 dpseg = seg;
4077 for (i = 0; i < num_sge; i++) {
4078 if (unlikely(dpseg == qend)) {
4079 seg = mlx5_get_send_wqe(qp, 0);
4080 dpseg = seg;
4081 }
4082 if (likely(wr->sg_list[i].length)) {
4083 set_data_ptr_seg(dpseg, wr->sg_list + i);
4084 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4085 dpseg++;
4086 }
4087 }
4088 }
4089
6e5eadac
SG		 4090 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4091 get_fence(fence, wr), next_fence,
4092 mlx5_ib_opcode[wr->opcode]);
e6631814 4093skip_psv:
e126ba97
EC		 4094 if (0)
4095 dump_wqe(qp, idx, size);
4096 }
4097
4098out:
4099 if (likely(nreq)) {
4100 qp->sq.head += nreq;
4101
4102 /* Make sure that descriptors are written before
4103 * updating doorbell record and ringing the doorbell
4104 */
4105 wmb();
4106
4107 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4108
ada388f7
EC		 4109 /* Make sure doorbell record is visible to the HCA before
4110 * we hit doorbell */
4111 wmb();
4112
5fe9dec0
EC		 4113 /* currently we support only regular doorbells */
4114 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4115 /* Make sure doorbells don't leak out of SQ spinlock
4116 * and reach the HCA out of order.
4117 */
4118 mmiowb();
e126ba97 4119 bf->offset ^= bf->buf_size;
e126ba97
EC		 4120 }
4121
4122 spin_unlock_irqrestore(&qp->sq.lock, flags);
4123
4124 return err;
4125}
4126
4127static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4128{
4129 sig->signature = calc_sig(sig, size);
4130}
4131
4132int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4133 struct ib_recv_wr **bad_wr)
4134{
4135 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4136 struct mlx5_wqe_data_seg *scat;
4137 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4138 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4139 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4140 unsigned long flags;
4141 int err = 0;
4142 int nreq;
4143 int ind;
4144 int i;
4145
d16e91da
HE		 4146 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4147 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4148
e126ba97
EC		 4149 spin_lock_irqsave(&qp->rq.lock, flags);
4150
89ea94a7
MG		 4151 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4152 err = -EIO;
4153 *bad_wr = wr;
4154 nreq = 0;
4155 goto out;
4156 }
4157
e126ba97
EC		 4158 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4159
4160 for (nreq = 0; wr; nreq++, wr = wr->next) {
4161 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4162 err = -ENOMEM;
4163 *bad_wr = wr;
4164 goto out;
4165 }
4166
4167 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4168 err = -EINVAL;
4169 *bad_wr = wr;
4170 goto out;
4171 }
4172
4173 scat = get_recv_wqe(qp, ind);
4174 if (qp->wq_sig)
4175 scat++;
4176
4177 for (i = 0; i < wr->num_sge; i++)
4178 set_data_ptr_seg(scat + i, wr->sg_list + i);
4179
4180 if (i < qp->rq.max_gs) {
4181 scat[i].byte_count = 0;
4182 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4183 scat[i].addr = 0;
4184 }
4185
4186 if (qp->wq_sig) {
4187 sig = (struct mlx5_rwqe_sig *)scat;
4188 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4189 }
4190
4191 qp->rq.wrid[ind] = wr->wr_id;
4192
4193 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4194 }
4195
4196out:
4197 if (likely(nreq)) {
4198 qp->rq.head += nreq;
4199
4200 /* Make sure that descriptors are written before
4201 * doorbell record.
4202 */
4203 wmb();
4204
4205 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4206 }
4207
4208 spin_unlock_irqrestore(&qp->rq.lock, flags);
4209
4210 return err;
4211}
4212
4213static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4214{
4215 switch (mlx5_state) {
4216 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4217 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4218 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4219 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4220 case MLX5_QP_STATE_SQ_DRAINING:
4221 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4222 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4223 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4224 default: return -1;
4225 }
4226}
4227
4228static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4229{
4230 switch (mlx5_mig_state) {
4231 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4232 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4233 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4234 default: return -1;
4235 }
4236}
4237
4238static int to_ib_qp_access_flags(int mlx5_flags)
4239{
4240 int ib_flags = 0;
4241
4242 if (mlx5_flags & MLX5_QP_BIT_RRE)
4243 ib_flags |= IB_ACCESS_REMOTE_READ;
4244 if (mlx5_flags & MLX5_QP_BIT_RWE)
4245 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4246 if (mlx5_flags & MLX5_QP_BIT_RAE)
4247 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4248
4249 return ib_flags;
4250}
4251
38349389
DC		 4252static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4253 struct rdma_ah_attr *ib_ah_attr,
4254 struct mlx5_qp_path *path)
e126ba97 4255{
9603b61d 4256 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4257
4258 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4259 ib_ah_attr->port_num = path->port;
4260
c7a08ac7 4261 if (ib_ah_attr->port_num == 0 ||
938fe83c 4262 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4263 return;
4264
2811ba51 4265 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4266
4267 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4268 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4269 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4270 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4271 if (ib_ah_attr->ah_flags) {
4272 ib_ah_attr->grh.sgid_index = path->mgid_index;
4273 ib_ah_attr->grh.hop_limit = path->hop_limit;
4274 ib_ah_attr->grh.traffic_class =
4275 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4276 ib_ah_attr->grh.flow_label =
4277 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4278 memcpy(ib_ah_attr->grh.dgid.raw,
4279 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4280 }
4281}
4282
6d2f89df 4283static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4284 struct mlx5_ib_sq *sq,
4285 u8 *sq_state)
4286{
4287 void *out;
4288 void *sqc;
4289 int inlen;
4290 int err;
4291
4292 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4293 out = mlx5_vzalloc(inlen);
4294 if (!out)
4295 return -ENOMEM;
4296
4297 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4298 if (err)
4299 goto out;
4300
4301 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4302 *sq_state = MLX5_GET(sqc, sqc, state);
4303 sq->state = *sq_state;
4304
4305out:
4306 kvfree(out);
4307 return err;
4308}
4309
4310static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4311 struct mlx5_ib_rq *rq,
4312 u8 *rq_state)
4313{
4314 void *out;
4315 void *rqc;
4316 int inlen;
4317 int err;
4318
4319 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4320 out = mlx5_vzalloc(inlen);
4321 if (!out)
4322 return -ENOMEM;
4323
4324 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4325 if (err)
4326 goto out;
4327
4328 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4329 *rq_state = MLX5_GET(rqc, rqc, state);
4330 rq->state = *rq_state;
4331
4332out:
4333 kvfree(out);
4334 return err;
4335}
4336
4337static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4338 struct mlx5_ib_qp *qp, u8 *qp_state)
4339{
4340 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4341 [MLX5_RQC_STATE_RST] = {
4342 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4343 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4344 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4345 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4346 },
4347 [MLX5_RQC_STATE_RDY] = {
4348 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4349 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4350 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4351 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4352 },
4353 [MLX5_RQC_STATE_ERR] = {
4354 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4355 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4356 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4357 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4358 },
4359 [MLX5_RQ_STATE_NA] = {
4360 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4361 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4362 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4363 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4364 },
4365 };
4366
4367 *qp_state = sqrq_trans[rq_state][sq_state];
4368
4369 if (*qp_state == MLX5_QP_STATE_BAD) {
4370 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4371 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4372 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4373 return -EINVAL;
4374 }
4375
4376 if (*qp_state == MLX5_QP_STATE)
4377 *qp_state = qp->state;
4378
4379 return 0;
4380}
4381
4382static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4383 struct mlx5_ib_qp *qp,
4384 u8 *raw_packet_qp_state)
4385{
4386 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4387 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4388 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4389 int err;
4390 u8 sq_state = MLX5_SQ_STATE_NA;
4391 u8 rq_state = MLX5_RQ_STATE_NA;
4392
4393 if (qp->sq.wqe_cnt) {
4394 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4395 if (err)
4396 return err;
4397 }
4398
4399 if (qp->rq.wqe_cnt) {
4400 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4401 if (err)
4402 return err;
4403 }
4404
4405 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4406 raw_packet_qp_state);
4407}
4408
4409static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4410 struct ib_qp_attr *qp_attr)
e126ba97 4411{
09a7d9ec 4412 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4413 struct mlx5_qp_context *context;
4414 int mlx5_state;
09a7d9ec 4415 u32 *outb;
e126ba97
EC		 4416 int err = 0;
4417
09a7d9ec 4418 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4419 if (!outb)
4420 return -ENOMEM;
4421
19098df2 4422 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4423 outlen);
e126ba97 4424 if (err)
6d2f89df 4425 goto out;
e126ba97 4426
09a7d9ec
SM		 4427 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4428 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4429
e126ba97
EC		 4430 mlx5_state = be32_to_cpu(context->flags) >> 28;
4431
4432 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4433 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4434 qp_attr->path_mig_state =
4435 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4436 qp_attr->qkey = be32_to_cpu(context->qkey);
4437 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4438 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4439 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4440 qp_attr->qp_access_flags =
4441 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4442
4443 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4444 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4445 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4446 qp_attr->alt_pkey_index =
4447 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4448 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4449 }
4450
d3ae2bde 4451 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4452 qp_attr->port_num = context->pri_path.port;
4453
4454 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4455 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4456
4457 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4458
4459 qp_attr->max_dest_rd_atomic =
4460 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4461 qp_attr->min_rnr_timer =
4462 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4463 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4464 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4465 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4466 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4467
4468out:
4469 kfree(outb);
4470 return err;
4471}
4472
4473int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4474 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4475{
4476 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4477 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4478 int err = 0;
4479 u8 raw_packet_qp_state;
4480
28d61370
YH		 4481 if (ibqp->rwq_ind_tbl)
4482 return -ENOSYS;
4483
d16e91da
HE		 4484 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4485 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4486 qp_init_attr);
4487
6d2f89df 4488 mutex_lock(&qp->mutex);
4489
4490 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4491 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4492 if (err)
4493 goto out;
4494 qp->state = raw_packet_qp_state;
4495 qp_attr->port_num = 1;
4496 } else {
4497 err = query_qp_attr(dev, qp, qp_attr);
4498 if (err)
4499 goto out;
4500 }
4501
4502 qp_attr->qp_state = qp->state;
e126ba97
EC		 4503 qp_attr->cur_qp_state = qp_attr->qp_state;
4504 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4505 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4506
4507 if (!ibqp->uobject) {
0540d814 4508 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4509 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4510 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4511 } else {
4512 qp_attr->cap.max_send_wr = 0;
4513 qp_attr->cap.max_send_sge = 0;
4514 }
4515
0540d814
NO		 4516 qp_init_attr->qp_type = ibqp->qp_type;
4517 qp_init_attr->recv_cq = ibqp->recv_cq;
4518 qp_init_attr->send_cq = ibqp->send_cq;
4519 qp_init_attr->srq = ibqp->srq;
4520 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4521
4522 qp_init_attr->cap = qp_attr->cap;
4523
4524 qp_init_attr->create_flags = 0;
4525 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4526 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4527
051f2630
LR		 4528 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4529 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4530 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4531 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4532 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4533 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4534 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4535 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4536
e126ba97
EC		 4537 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4538 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4539
e126ba97
EC		 4540out:
4541 mutex_unlock(&qp->mutex);
4542 return err;
4543}
4544
4545struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4546 struct ib_ucontext *context,
4547 struct ib_udata *udata)
4548{
4549 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4550 struct mlx5_ib_xrcd *xrcd;
4551 int err;
4552
938fe83c 4553 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4554 return ERR_PTR(-ENOSYS);
4555
4556 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4557 if (!xrcd)
4558 return ERR_PTR(-ENOMEM);
4559
9603b61d 4560 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4561 if (err) {
4562 kfree(xrcd);
4563 return ERR_PTR(-ENOMEM);
4564 }
4565
4566 return &xrcd->ibxrcd;
4567}
4568
4569int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4570{
4571 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4572 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4573 int err;
4574
9603b61d 4575 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4576 if (err) {
4577 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4578 return err;
4579 }
4580
4581 kfree(xrcd);
4582
4583 return 0;
4584}
79b20a6c 4585
350d0e4c
YH		 4586static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4587{
4588 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4589 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4590 struct ib_event event;
4591
4592 if (rwq->ibwq.event_handler) {
4593 event.device = rwq->ibwq.device;
4594 event.element.wq = &rwq->ibwq;
4595 switch (type) {
4596 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4597 event.event = IB_EVENT_WQ_FATAL;
4598 break;
4599 default:
4600 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4601 return;
4602 }
4603
4604 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4605 }
4606}
4607
79b20a6c
YH		 4608static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4609 struct ib_wq_init_attr *init_attr)
4610{
4611 struct mlx5_ib_dev *dev;
4be6da1e 4612 int has_net_offloads;
79b20a6c
YH		 4613 __be64 *rq_pas0;
4614 void *in;
4615 void *rqc;
4616 void *wq;
4617 int inlen;
4618 int err;
4619
4620 dev = to_mdev(pd->device);
4621
4622 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4623 in = mlx5_vzalloc(inlen);
4624 if (!in)
4625 return -ENOMEM;
4626
4627 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4628 MLX5_SET(rqc, rqc, mem_rq_type,
4629 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4630 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4631 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4632 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4633 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4634 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4635 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4636 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4637 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4638 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4639 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4640 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4641 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4642 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4643 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4644 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4645 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4646 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4647 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4648 err = -EOPNOTSUPP;
4649 goto out;
4650 }
4651 } else {
4652 MLX5_SET(rqc, rqc, vsd, 1);
4653 }
4be6da1e
NO		 4654 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4655 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4656 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4657 err = -EOPNOTSUPP;
4658 goto out;
4659 }
4660 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4661 }
79b20a6c
YH		 4662 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4663 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4664 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
b1f74a84 4665out:
79b20a6c
YH		 4666 kvfree(in);
4667 return err;
4668}
4669
4670static int set_user_rq_size(struct mlx5_ib_dev *dev,
4671 struct ib_wq_init_attr *wq_init_attr,
4672 struct mlx5_ib_create_wq *ucmd,
4673 struct mlx5_ib_rwq *rwq)
4674{
4675 /* Sanity check RQ size before proceeding */
4676 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4677 return -EINVAL;
4678
4679 if (!ucmd->rq_wqe_count)
4680 return -EINVAL;
4681
4682 rwq->wqe_count = ucmd->rq_wqe_count;
4683 rwq->wqe_shift = ucmd->rq_wqe_shift;
4684 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4685 rwq->log_rq_stride = rwq->wqe_shift;
4686 rwq->log_rq_size = ilog2(rwq->wqe_count);
4687 return 0;
4688}
4689
4690static int prepare_user_rq(struct ib_pd *pd,
4691 struct ib_wq_init_attr *init_attr,
4692 struct ib_udata *udata,
4693 struct mlx5_ib_rwq *rwq)
4694{
4695 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4696 struct mlx5_ib_create_wq ucmd = {};
4697 int err;
4698 size_t required_cmd_sz;
4699
4700 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4701 if (udata->inlen < required_cmd_sz) {
4702 mlx5_ib_dbg(dev, "invalid inlen\n");
4703 return -EINVAL;
4704 }
4705
4706 if (udata->inlen > sizeof(ucmd) &&
4707 !ib_is_udata_cleared(udata, sizeof(ucmd),
4708 udata->inlen - sizeof(ucmd))) {
4709 mlx5_ib_dbg(dev, "inlen is not supported\n");
4710 return -EOPNOTSUPP;
4711 }
4712
4713 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4714 mlx5_ib_dbg(dev, "copy failed\n");
4715 return -EFAULT;
4716 }
4717
4718 if (ucmd.comp_mask) {
4719 mlx5_ib_dbg(dev, "invalid comp mask\n");
4720 return -EOPNOTSUPP;
4721 }
4722
4723 if (ucmd.reserved) {
4724 mlx5_ib_dbg(dev, "invalid reserved\n");
4725 return -EOPNOTSUPP;
4726 }
4727
4728 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4729 if (err) {
4730 mlx5_ib_dbg(dev, "err %d\n", err);
4731 return err;
4732 }
4733
4734 err = create_user_rq(dev, pd, rwq, &ucmd);
4735 if (err) {
4736 mlx5_ib_dbg(dev, "err %d\n", err);
4737 if (err)
4738 return err;
4739 }
4740
4741 rwq->user_index = ucmd.user_index;
4742 return 0;
4743}
4744
4745struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4746 struct ib_wq_init_attr *init_attr,
4747 struct ib_udata *udata)
4748{
4749 struct mlx5_ib_dev *dev;
4750 struct mlx5_ib_rwq *rwq;
4751 struct mlx5_ib_create_wq_resp resp = {};
4752 size_t min_resp_len;
4753 int err;
4754
4755 if (!udata)
4756 return ERR_PTR(-ENOSYS);
4757
4758 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4759 if (udata->outlen && udata->outlen < min_resp_len)
4760 return ERR_PTR(-EINVAL);
4761
4762 dev = to_mdev(pd->device);
4763 switch (init_attr->wq_type) {
4764 case IB_WQT_RQ:
4765 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4766 if (!rwq)
4767 return ERR_PTR(-ENOMEM);
4768 err = prepare_user_rq(pd, init_attr, udata, rwq);
4769 if (err)
4770 goto err;
4771 err = create_rq(rwq, pd, init_attr);
4772 if (err)
4773 goto err_user_rq;
4774 break;
4775 default:
4776 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4777 init_attr->wq_type);
4778 return ERR_PTR(-EINVAL);
4779 }
4780
350d0e4c 4781 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4782 rwq->ibwq.state = IB_WQS_RESET;
4783 if (udata->outlen) {
4784 resp.response_length = offsetof(typeof(resp), response_length) +
4785 sizeof(resp.response_length);
4786 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4787 if (err)
4788 goto err_copy;
4789 }
4790
350d0e4c
YH		 4791 rwq->core_qp.event = mlx5_ib_wq_event;
4792 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4793 return &rwq->ibwq;
4794
4795err_copy:
350d0e4c 4796 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4797err_user_rq:
4798 destroy_user_rq(pd, rwq);
4799err:
4800 kfree(rwq);
4801 return ERR_PTR(err);
4802}
4803
4804int mlx5_ib_destroy_wq(struct ib_wq *wq)
4805{
4806 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4807 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4808
350d0e4c 4809 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4810 destroy_user_rq(wq->pd, rwq);
4811 kfree(rwq);
4812
4813 return 0;
4814}
4815
c5f90929
YH		 4816struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4817 struct ib_rwq_ind_table_init_attr *init_attr,
4818 struct ib_udata *udata)
4819{
4820 struct mlx5_ib_dev *dev = to_mdev(device);
4821 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4822 int sz = 1 << init_attr->log_ind_tbl_size;
4823 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4824 size_t min_resp_len;
4825 int inlen;
4826 int err;
4827 int i;
4828 u32 *in;
4829 void *rqtc;
4830
4831 if (udata->inlen > 0 &&
4832 !ib_is_udata_cleared(udata, 0,
4833 udata->inlen))
4834 return ERR_PTR(-EOPNOTSUPP);
4835
efd7f400
MG		 4836 if (init_attr->log_ind_tbl_size >
4837 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4838 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4839 init_attr->log_ind_tbl_size,
4840 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4841 return ERR_PTR(-EINVAL);
4842 }
4843
c5f90929
YH		 4844 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4845 if (udata->outlen && udata->outlen < min_resp_len)
4846 return ERR_PTR(-EINVAL);
4847
4848 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4849 if (!rwq_ind_tbl)
4850 return ERR_PTR(-ENOMEM);
4851
4852 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4853 in = mlx5_vzalloc(inlen);
4854 if (!in) {
4855 err = -ENOMEM;
4856 goto err;
4857 }
4858
4859 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4860
4861 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4862 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4863
4864 for (i = 0; i < sz; i++)
4865 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4866
4867 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4868 kvfree(in);
4869
4870 if (err)
4871 goto err;
4872
4873 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4874 if (udata->outlen) {
4875 resp.response_length = offsetof(typeof(resp), response_length) +
4876 sizeof(resp.response_length);
4877 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4878 if (err)
4879 goto err_copy;
4880 }
4881
4882 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4883
4884err_copy:
4885 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4886err:
4887 kfree(rwq_ind_tbl);
4888 return ERR_PTR(err);
4889}
4890
4891int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4892{
4893 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4894 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4895
4896 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4897
4898 kfree(rwq_ind_tbl);
4899 return 0;
4900}
4901
79b20a6c
YH		 4902int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4903 u32 wq_attr_mask, struct ib_udata *udata)
4904{
4905 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4906 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4907 struct mlx5_ib_modify_wq ucmd = {};
4908 size_t required_cmd_sz;
4909 int curr_wq_state;
4910 int wq_state;
4911 int inlen;
4912 int err;
4913 void *rqc;
4914 void *in;
4915
4916 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4917 if (udata->inlen < required_cmd_sz)
4918 return -EINVAL;
4919
4920 if (udata->inlen > sizeof(ucmd) &&
4921 !ib_is_udata_cleared(udata, sizeof(ucmd),
4922 udata->inlen - sizeof(ucmd)))
4923 return -EOPNOTSUPP;
4924
4925 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4926 return -EFAULT;
4927
4928 if (ucmd.comp_mask || ucmd.reserved)
4929 return -EOPNOTSUPP;
4930
4931 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4932 in = mlx5_vzalloc(inlen);
4933 if (!in)
4934 return -ENOMEM;
4935
4936 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4937
4938 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4939 wq_attr->curr_wq_state : wq->state;
4940 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4941 wq_attr->wq_state : curr_wq_state;
4942 if (curr_wq_state == IB_WQS_ERR)
4943 curr_wq_state = MLX5_RQC_STATE_ERR;
4944 if (wq_state == IB_WQS_ERR)
4945 wq_state = MLX5_RQC_STATE_ERR;
4946 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4947 MLX5_SET(rqc, rqc, state, wq_state);
4948
b1f74a84
NO		 4949 if (wq_attr_mask & IB_WQ_FLAGS) {
4950 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4951 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
4952 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4953 mlx5_ib_dbg(dev, "VLAN offloads are not "
4954 "supported\n");
4955 err = -EOPNOTSUPP;
4956 goto out;
4957 }
4958 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4959 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
4960 MLX5_SET(rqc, rqc, vsd,
4961 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4962 }
4963 }
4964
23a6964e
MD		 4965 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4966 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4967 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4968 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 4969 MLX5_SET(rqc, rqc, counter_set_id,
4970 dev->port->cnts.set_id);
23a6964e
MD		 4971 } else
4972 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4973 dev->ib_dev.name);
4974 }
4975
350d0e4c 4976 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 4977 if (!err)
4978 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4979
b1f74a84
NO		 4980out:
4981 kvfree(in);
79b20a6c
YH		 4982 return err;
4983}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git