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IB/mlx5: Fix reported max SGE calculation
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39/* not supported currently */
40static int wq_signature;
41
42enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44};
45
46enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51};
52
53enum {
54 MLX5_IB_SQ_STRIDE = 6,
55 MLX5_IB_CACHE_LINE_SIZE = 64,
56};
57
58static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73};
74
f0313965
ES		 75struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77};
e126ba97 78
eb49ab0c
AV		 79enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81};
82
0680efa2
AV		 83struct mlx5_modify_raw_qp_param {
84 u16 operation;
eb49ab0c
AV		 85
86 u32 set_mask; /* raw_qp_set_mask_map */
87 u8 rq_q_ctr_id;
0680efa2
AV		 88};
89
89ea94a7
MG		 90static void get_cqs(enum ib_qp_type qp_type,
91 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
92 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
93
e126ba97
EC		 94static int is_qp0(enum ib_qp_type qp_type)
95{
96 return qp_type == IB_QPT_SMI;
97}
98
e126ba97
EC		 99static int is_sqp(enum ib_qp_type qp_type)
100{
101 return is_qp0(qp_type) || is_qp1(qp_type);
102}
103
104static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
105{
106 return mlx5_buf_offset(&qp->buf, offset);
107}
108
109static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
110{
111 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
112}
113
114void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
115{
116 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
117}
118
c1395a2a
HE		 119/**
120 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
121 *
122 * @qp: QP to copy from.
123 * @send: copy from the send queue when non-zero, use the receive queue
124 * otherwise.
125 * @wqe_index: index to start copying from. For send work queues, the
126 * wqe_index is in units of MLX5_SEND_WQE_BB.
127 * For receive work queue, it is the number of work queue
128 * element in the queue.
129 * @buffer: destination buffer.
130 * @length: maximum number of bytes to copy.
131 *
132 * Copies at least a single WQE, but may copy more data.
133 *
134 * Return: the number of bytes copied, or an error code.
135 */
136int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 137 void *buffer, u32 length,
138 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 139{
140 struct ib_device *ibdev = qp->ibqp.device;
141 struct mlx5_ib_dev *dev = to_mdev(ibdev);
142 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
143 size_t offset;
144 size_t wq_end;
19098df2 145 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 146 u32 first_copy_length;
147 int wqe_length;
148 int ret;
149
150 if (wq->wqe_cnt == 0) {
151 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
152 qp->ibqp.qp_type);
153 return -EINVAL;
154 }
155
156 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
157 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
158
159 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
160 return -EINVAL;
161
162 if (offset > umem->length ||
163 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
164 return -EINVAL;
165
166 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
167 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
168 if (ret)
169 return ret;
170
171 if (send) {
172 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
173 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
174
175 wqe_length = ds * MLX5_WQE_DS_UNITS;
176 } else {
177 wqe_length = 1 << wq->wqe_shift;
178 }
179
180 if (wqe_length <= first_copy_length)
181 return first_copy_length;
182
183 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
184 wqe_length - first_copy_length);
185 if (ret)
186 return ret;
187
188 return wqe_length;
189}
190
e126ba97
EC		 191static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
192{
193 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
194 struct ib_event event;
195
19098df2 196 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
197 /* This event is only valid for trans_qps */
198 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
199 }
e126ba97
EC		 200
201 if (ibqp->event_handler) {
202 event.device = ibqp->device;
203 event.element.qp = ibqp;
204 switch (type) {
205 case MLX5_EVENT_TYPE_PATH_MIG:
206 event.event = IB_EVENT_PATH_MIG;
207 break;
208 case MLX5_EVENT_TYPE_COMM_EST:
209 event.event = IB_EVENT_COMM_EST;
210 break;
211 case MLX5_EVENT_TYPE_SQ_DRAINED:
212 event.event = IB_EVENT_SQ_DRAINED;
213 break;
214 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
215 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
216 break;
217 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
218 event.event = IB_EVENT_QP_FATAL;
219 break;
220 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
221 event.event = IB_EVENT_PATH_MIG_ERR;
222 break;
223 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
224 event.event = IB_EVENT_QP_REQ_ERR;
225 break;
226 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
227 event.event = IB_EVENT_QP_ACCESS_ERR;
228 break;
229 default:
230 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
231 return;
232 }
233
234 ibqp->event_handler(&event, ibqp->qp_context);
235 }
236}
237
238static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
239 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
240{
241 int wqe_size;
242 int wq_size;
243
244 /* Sanity check RQ size before proceeding */
938fe83c 245 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 246 return -EINVAL;
247
248 if (!has_rq) {
249 qp->rq.max_gs = 0;
250 qp->rq.wqe_cnt = 0;
251 qp->rq.wqe_shift = 0;
0540d814
NO		 252 cap->max_recv_wr = 0;
253 cap->max_recv_sge = 0;
e126ba97
EC		 254 } else {
255 if (ucmd) {
256 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
257 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
258 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
259 qp->rq.max_post = qp->rq.wqe_cnt;
260 } else {
261 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
262 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
263 wqe_size = roundup_pow_of_two(wqe_size);
264 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
265 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
266 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 267 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 268 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
269 wqe_size,
938fe83c
SM		 270 MLX5_CAP_GEN(dev->mdev,
271 max_wqe_sz_rq));
e126ba97
EC		 272 return -EINVAL;
273 }
274 qp->rq.wqe_shift = ilog2(wqe_size);
275 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
276 qp->rq.max_post = qp->rq.wqe_cnt;
277 }
278 }
279
280 return 0;
281}
282
f0313965 283static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 284{
618af384 285 int size = 0;
e126ba97 286
f0313965 287 switch (attr->qp_type) {
e126ba97 288 case IB_QPT_XRC_INI:
b125a54b 289 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 290 /* fall through */
291 case IB_QPT_RC:
292 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 293 max(sizeof(struct mlx5_wqe_atomic_seg) +
294 sizeof(struct mlx5_wqe_raddr_seg),
295 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
296 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 297 break;
298
b125a54b
EC		 299 case IB_QPT_XRC_TGT:
300 return 0;
301
e126ba97 302 case IB_QPT_UC:
b125a54b 303 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 304 max(sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 307 break;
308
309 case IB_QPT_UD:
f0313965
ES		 310 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
311 size += sizeof(struct mlx5_wqe_eth_pad) +
312 sizeof(struct mlx5_wqe_eth_seg);
313 /* fall through */
e126ba97 314 case IB_QPT_SMI:
d16e91da 315 case MLX5_IB_QPT_HW_GSI:
b125a54b 316 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 317 sizeof(struct mlx5_wqe_datagram_seg);
318 break;
319
320 case MLX5_IB_QPT_REG_UMR:
b125a54b 321 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 322 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
323 sizeof(struct mlx5_mkey_seg);
324 break;
325
326 default:
327 return -EINVAL;
328 }
329
330 return size;
331}
332
333static int calc_send_wqe(struct ib_qp_init_attr *attr)
334{
335 int inl_size = 0;
336 int size;
337
f0313965 338 size = sq_overhead(attr);
e126ba97
EC		 339 if (size < 0)
340 return size;
341
342 if (attr->cap.max_inline_data) {
343 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
344 attr->cap.max_inline_data;
345 }
346
347 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 348 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
349 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
350 return MLX5_SIG_WQE_SIZE;
351 else
352 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 353}
354
288c01b7
EC		 355static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
356{
357 int max_sge;
358
359 if (attr->qp_type == IB_QPT_RC)
360 max_sge = (min_t(int, wqe_size, 512) -
361 sizeof(struct mlx5_wqe_ctrl_seg) -
362 sizeof(struct mlx5_wqe_raddr_seg)) /
363 sizeof(struct mlx5_wqe_data_seg);
364 else if (attr->qp_type == IB_QPT_XRC_INI)
365 max_sge = (min_t(int, wqe_size, 512) -
366 sizeof(struct mlx5_wqe_ctrl_seg) -
367 sizeof(struct mlx5_wqe_xrc_seg) -
368 sizeof(struct mlx5_wqe_raddr_seg)) /
369 sizeof(struct mlx5_wqe_data_seg);
370 else
371 max_sge = (wqe_size - sq_overhead(attr)) /
372 sizeof(struct mlx5_wqe_data_seg);
373
374 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
375 sizeof(struct mlx5_wqe_data_seg));
376}
377
e126ba97
EC		 378static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
379 struct mlx5_ib_qp *qp)
380{
381 int wqe_size;
382 int wq_size;
383
384 if (!attr->cap.max_send_wr)
385 return 0;
386
387 wqe_size = calc_send_wqe(attr);
388 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
389 if (wqe_size < 0)
390 return wqe_size;
391
938fe83c 392 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 393 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 394 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 395 return -EINVAL;
396 }
397
f0313965
ES		 398 qp->max_inline_data = wqe_size - sq_overhead(attr) -
399 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 400 attr->cap.max_inline_data = qp->max_inline_data;
401
e1e66cc2
SG		 402 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
403 qp->signature_en = true;
404
e126ba97
EC		 405 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
406 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 407 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 408 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 409 qp->sq.wqe_cnt,
410 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 411 return -ENOMEM;
412 }
e126ba97 413 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 414 qp->sq.max_gs = get_send_sge(attr, wqe_size);
415 if (qp->sq.max_gs < attr->cap.max_send_sge)
416 return -ENOMEM;
417
418 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 419 qp->sq.max_post = wq_size / wqe_size;
420 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 421
422 return wq_size;
423}
424
425static int set_user_buf_size(struct mlx5_ib_dev *dev,
426 struct mlx5_ib_qp *qp,
19098df2 427 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 428 struct mlx5_ib_qp_base *base,
429 struct ib_qp_init_attr *attr)
e126ba97
EC		 430{
431 int desc_sz = 1 << qp->sq.wqe_shift;
432
938fe83c 433 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 434 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 435 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 436 return -EINVAL;
437 }
438
439 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
440 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
441 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
442 return -EINVAL;
443 }
444
445 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
446
938fe83c 447 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 448 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 449 qp->sq.wqe_cnt,
450 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 451 return -EINVAL;
452 }
453
0fb2ed66 454 if (attr->qp_type == IB_QPT_RAW_PACKET) {
455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
457 } else {
458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
459 (qp->sq.wqe_cnt << 6);
460 }
e126ba97
EC		 461
462 return 0;
463}
464
465static int qp_has_rq(struct ib_qp_init_attr *attr)
466{
467 if (attr->qp_type == IB_QPT_XRC_INI ||
468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
469 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
470 !attr->cap.max_recv_wr)
471 return 0;
472
473 return 1;
474}
475
c1be5232
EC		 476static int first_med_uuar(void)
477{
478 return 1;
479}
480
481static int next_uuar(int n)
482{
483 n++;
484
485 while (((n % 4) & 2))
486 n++;
487
488 return n;
489}
490
491static int num_med_uuar(struct mlx5_uuar_info *uuari)
492{
493 int n;
494
495 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
496 uuari->num_low_latency_uuars - 1;
497
498 return n >= 0 ? n : 0;
499}
500
501static int max_uuari(struct mlx5_uuar_info *uuari)
502{
503 return uuari->num_uars * 4;
504}
505
506static int first_hi_uuar(struct mlx5_uuar_info *uuari)
507{
508 int med;
509 int i;
510 int t;
511
512 med = num_med_uuar(uuari);
513 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
514 t++;
515 if (t == med)
516 return next_uuar(i);
517 }
518
519 return 0;
520}
521
e126ba97
EC		 522static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
523{
e126ba97
EC		 524 int i;
525
c1be5232 526 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 527 if (!test_bit(i, uuari->bitmap)) {
528 set_bit(i, uuari->bitmap);
529 uuari->count[i]++;
530 return i;
531 }
532 }
533
534 return -ENOMEM;
535}
536
537static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
538{
c1be5232 539 int minidx = first_med_uuar();
e126ba97
EC		 540 int i;
541
c1be5232 542 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 543 if (uuari->count[i] < uuari->count[minidx])
544 minidx = i;
545 }
546
547 uuari->count[minidx]++;
548 return minidx;
549}
550
551static int alloc_uuar(struct mlx5_uuar_info *uuari,
552 enum mlx5_ib_latency_class lat)
553{
554 int uuarn = -EINVAL;
555
556 mutex_lock(&uuari->lock);
557 switch (lat) {
558 case MLX5_IB_LATENCY_CLASS_LOW:
559 uuarn = 0;
560 uuari->count[uuarn]++;
561 break;
562
563 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 564 if (uuari->ver < 2)
565 uuarn = -ENOMEM;
566 else
567 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 568 break;
569
570 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 571 if (uuari->ver < 2)
572 uuarn = -ENOMEM;
573 else
574 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 575 break;
576
577 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
578 uuarn = 2;
579 break;
580 }
581 mutex_unlock(&uuari->lock);
582
583 return uuarn;
584}
585
586static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
587{
588 clear_bit(uuarn, uuari->bitmap);
589 --uuari->count[uuarn];
590}
591
592static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
593{
594 clear_bit(uuarn, uuari->bitmap);
595 --uuari->count[uuarn];
596}
597
598static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
599{
600 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
601 int high_uuar = nuuars - uuari->num_low_latency_uuars;
602
603 mutex_lock(&uuari->lock);
604 if (uuarn == 0) {
605 --uuari->count[uuarn];
606 goto out;
607 }
608
609 if (uuarn < high_uuar) {
610 free_med_class_uuar(uuari, uuarn);
611 goto out;
612 }
613
614 free_high_class_uuar(uuari, uuarn);
615
616out:
617 mutex_unlock(&uuari->lock);
618}
619
620static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
621{
622 switch (state) {
623 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
624 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
625 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
626 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
627 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
628 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
629 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
630 default: return -1;
631 }
632}
633
634static int to_mlx5_st(enum ib_qp_type type)
635{
636 switch (type) {
637 case IB_QPT_RC: return MLX5_QP_ST_RC;
638 case IB_QPT_UC: return MLX5_QP_ST_UC;
639 case IB_QPT_UD: return MLX5_QP_ST_UD;
640 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
641 case IB_QPT_XRC_INI:
642 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
643 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 644 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 645 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 646 case IB_QPT_RAW_PACKET:
0fb2ed66 647 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 648 case IB_QPT_MAX:
649 default: return -EINVAL;
650 }
651}
652
89ea94a7
MG		 653static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
654 struct mlx5_ib_cq *recv_cq);
655static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
656 struct mlx5_ib_cq *recv_cq);
657
e126ba97
EC		 658static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
659{
660 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
661}
662
19098df2 663static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
664 struct ib_pd *pd,
665 unsigned long addr, size_t size,
666 struct ib_umem **umem,
667 int *npages, int *page_shift, int *ncont,
668 u32 *offset)
669{
670 int err;
671
672 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
673 if (IS_ERR(*umem)) {
674 mlx5_ib_dbg(dev, "umem_get failed\n");
675 return PTR_ERR(*umem);
676 }
677
678 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
679
680 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
681 if (err) {
682 mlx5_ib_warn(dev, "bad offset\n");
683 goto err_umem;
684 }
685
686 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
687 addr, size, *npages, *page_shift, *ncont, *offset);
688
689 return 0;
690
691err_umem:
692 ib_umem_release(*umem);
693 *umem = NULL;
694
695 return err;
696}
697
79b20a6c
YH		 698static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
699{
700 struct mlx5_ib_ucontext *context;
701
702 context = to_mucontext(pd->uobject->context);
703 mlx5_ib_db_unmap_user(context, &rwq->db);
704 if (rwq->umem)
705 ib_umem_release(rwq->umem);
706}
707
708static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
709 struct mlx5_ib_rwq *rwq,
710 struct mlx5_ib_create_wq *ucmd)
711{
712 struct mlx5_ib_ucontext *context;
713 int page_shift = 0;
714 int npages;
715 u32 offset = 0;
716 int ncont = 0;
717 int err;
718
719 if (!ucmd->buf_addr)
720 return -EINVAL;
721
722 context = to_mucontext(pd->uobject->context);
723 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
724 rwq->buf_size, 0, 0);
725 if (IS_ERR(rwq->umem)) {
726 mlx5_ib_dbg(dev, "umem_get failed\n");
727 err = PTR_ERR(rwq->umem);
728 return err;
729 }
730
731 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
732 &ncont, NULL);
733 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
734 &rwq->rq_page_offset);
735 if (err) {
736 mlx5_ib_warn(dev, "bad offset\n");
737 goto err_umem;
738 }
739
740 rwq->rq_num_pas = ncont;
741 rwq->page_shift = page_shift;
742 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
743 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
744
745 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
746 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
747 npages, page_shift, ncont, offset);
748
749 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
750 if (err) {
751 mlx5_ib_dbg(dev, "map failed\n");
752 goto err_umem;
753 }
754
755 rwq->create_type = MLX5_WQ_USER;
756 return 0;
757
758err_umem:
759 ib_umem_release(rwq->umem);
760 return err;
761}
762
e126ba97
EC		 763static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
764 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 765 struct ib_qp_init_attr *attr,
09a7d9ec 766 u32 **in,
19098df2 767 struct mlx5_ib_create_qp_resp *resp, int *inlen,
768 struct mlx5_ib_qp_base *base)
e126ba97
EC		 769{
770 struct mlx5_ib_ucontext *context;
771 struct mlx5_ib_create_qp ucmd;
19098df2 772 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 773 int page_shift = 0;
e126ba97
EC		 774 int uar_index;
775 int npages;
9e9c47d0 776 u32 offset = 0;
e126ba97 777 int uuarn;
9e9c47d0 778 int ncont = 0;
09a7d9ec
SM		 779 __be64 *pas;
780 void *qpc;
e126ba97
EC		 781 int err;
782
783 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
784 if (err) {
785 mlx5_ib_dbg(dev, "copy failed\n");
786 return err;
787 }
788
789 context = to_mucontext(pd->uobject->context);
790 /*
791 * TBD: should come from the verbs when we have the API
792 */
051f2630
LR		 793 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
794 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
795 uuarn = MLX5_CROSS_CHANNEL_UUAR;
796 else {
797 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 798 if (uuarn < 0) {
051f2630
LR		 799 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
800 mlx5_ib_dbg(dev, "reverting to medium latency\n");
801 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 802 if (uuarn < 0) {
051f2630
LR		 803 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
804 mlx5_ib_dbg(dev, "reverting to high latency\n");
805 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
806 if (uuarn < 0) {
807 mlx5_ib_warn(dev, "uuar allocation failed\n");
808 return uuarn;
809 }
c1be5232 810 }
e126ba97
EC		 811 }
812 }
813
814 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
815 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
816
48fea837
HE		 817 qp->rq.offset = 0;
818 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
819 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
820
0fb2ed66 821 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 822 if (err)
823 goto err_uuar;
824
19098df2 825 if (ucmd.buf_addr && ubuffer->buf_size) {
826 ubuffer->buf_addr = ucmd.buf_addr;
827 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
828 ubuffer->buf_size,
829 &ubuffer->umem, &npages, &page_shift,
830 &ncont, &offset);
831 if (err)
9e9c47d0 832 goto err_uuar;
9e9c47d0 833 } else {
19098df2 834 ubuffer->umem = NULL;
e126ba97 835 }
e126ba97 836
09a7d9ec
SM		 837 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
838 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 839 *in = mlx5_vzalloc(*inlen);
840 if (!*in) {
841 err = -ENOMEM;
842 goto err_umem;
843 }
09a7d9ec
SM		 844
845 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 846 if (ubuffer->umem)
09a7d9ec
SM		 847 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
848
849 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
850
851 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
852 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 853
09a7d9ec 854 MLX5_SET(qpc, qpc, uar_page, uar_index);
e126ba97
EC		 855 resp->uuar_index = uuarn;
856 qp->uuarn = uuarn;
857
858 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
859 if (err) {
860 mlx5_ib_dbg(dev, "map failed\n");
861 goto err_free;
862 }
863
864 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
865 if (err) {
866 mlx5_ib_dbg(dev, "copy failed\n");
867 goto err_unmap;
868 }
869 qp->create_type = MLX5_QP_USER;
870
871 return 0;
872
873err_unmap:
874 mlx5_ib_db_unmap_user(context, &qp->db);
875
876err_free:
479163f4 877 kvfree(*in);
e126ba97
EC		 878
879err_umem:
19098df2 880 if (ubuffer->umem)
881 ib_umem_release(ubuffer->umem);
e126ba97
EC		 882
883err_uuar:
884 free_uuar(&context->uuari, uuarn);
885 return err;
886}
887
19098df2 888static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
889 struct mlx5_ib_qp_base *base)
e126ba97
EC		 890{
891 struct mlx5_ib_ucontext *context;
892
893 context = to_mucontext(pd->uobject->context);
894 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 895 if (base->ubuffer.umem)
896 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 897 free_uuar(&context->uuari, qp->uuarn);
898}
899
900static int create_kernel_qp(struct mlx5_ib_dev *dev,
901 struct ib_qp_init_attr *init_attr,
902 struct mlx5_ib_qp *qp,
09a7d9ec 903 u32 **in, int *inlen,
19098df2 904 struct mlx5_ib_qp_base *base)
e126ba97
EC		 905{
906 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
907 struct mlx5_uuar_info *uuari;
908 int uar_index;
09a7d9ec 909 void *qpc;
e126ba97
EC		 910 int uuarn;
911 int err;
912
9603b61d 913 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 914 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
915 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 916 IB_QP_CREATE_IPOIB_UD_LSO |
917 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 918 return -EINVAL;
e126ba97
EC		 919
920 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
921 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
922
923 uuarn = alloc_uuar(uuari, lc);
924 if (uuarn < 0) {
925 mlx5_ib_dbg(dev, "\n");
926 return -ENOMEM;
927 }
928
929 qp->bf = &uuari->bfs[uuarn];
930 uar_index = qp->bf->uar->index;
931
932 err = calc_sq_size(dev, init_attr, qp);
933 if (err < 0) {
934 mlx5_ib_dbg(dev, "err %d\n", err);
935 goto err_uuar;
936 }
937
938 qp->rq.offset = 0;
939 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 940 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 941
19098df2 942 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 943 if (err) {
944 mlx5_ib_dbg(dev, "err %d\n", err);
945 goto err_uuar;
946 }
947
948 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 949 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
950 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 951 *in = mlx5_vzalloc(*inlen);
952 if (!*in) {
953 err = -ENOMEM;
954 goto err_buf;
955 }
09a7d9ec
SM		 956
957 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
958 MLX5_SET(qpc, qpc, uar_page, uar_index);
959 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
960
e126ba97 961 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 962 MLX5_SET(qpc, qpc, fre, 1);
963 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 964
b11a4f9c 965 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 966 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 967 qp->flags |= MLX5_IB_QP_SQPN_QP1;
968 }
969
09a7d9ec
SM		 970 mlx5_fill_page_array(&qp->buf,
971 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 972
9603b61d 973 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 974 if (err) {
975 mlx5_ib_dbg(dev, "err %d\n", err);
976 goto err_free;
977 }
978
e126ba97
EC		 979 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
980 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
981 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
982 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
983 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
984
985 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
986 !qp->sq.w_list || !qp->sq.wqe_head) {
987 err = -ENOMEM;
988 goto err_wrid;
989 }
990 qp->create_type = MLX5_QP_KERNEL;
991
992 return 0;
993
994err_wrid:
9603b61d 995 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 996 kfree(qp->sq.wqe_head);
997 kfree(qp->sq.w_list);
998 kfree(qp->sq.wrid);
999 kfree(qp->sq.wr_data);
1000 kfree(qp->rq.wrid);
1001
1002err_free:
479163f4 1003 kvfree(*in);
e126ba97
EC		 1004
1005err_buf:
9603b61d 1006 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1007
1008err_uuar:
9603b61d 1009 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 1010 return err;
1011}
1012
1013static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1014{
9603b61d 1015 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1016 kfree(qp->sq.wqe_head);
1017 kfree(qp->sq.w_list);
1018 kfree(qp->sq.wrid);
1019 kfree(qp->sq.wr_data);
1020 kfree(qp->rq.wrid);
9603b61d
JM		 1021 mlx5_buf_free(dev->mdev, &qp->buf);
1022 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 1023}
1024
09a7d9ec 1025static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1026{
1027 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1028 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1029 return MLX5_SRQ_RQ;
e126ba97 1030 else if (!qp->has_rq)
09a7d9ec 1031 return MLX5_ZERO_LEN_RQ;
e126ba97 1032 else
09a7d9ec 1033 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1034}
1035
1036static int is_connected(enum ib_qp_type qp_type)
1037{
1038 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1039 return 1;
1040
1041 return 0;
1042}
1043
0fb2ed66 1044static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1045 struct mlx5_ib_sq *sq, u32 tdn)
1046{
c4f287c4 1047 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1048 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1049
0fb2ed66 1050 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1051 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1052}
1053
1054static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1055 struct mlx5_ib_sq *sq)
1056{
1057 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1058}
1059
1060static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1061 struct mlx5_ib_sq *sq, void *qpin,
1062 struct ib_pd *pd)
1063{
1064 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1065 __be64 *pas;
1066 void *in;
1067 void *sqc;
1068 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1069 void *wq;
1070 int inlen;
1071 int err;
1072 int page_shift = 0;
1073 int npages;
1074 int ncont = 0;
1075 u32 offset = 0;
1076
1077 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1078 &sq->ubuffer.umem, &npages, &page_shift,
1079 &ncont, &offset);
1080 if (err)
1081 return err;
1082
1083 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1084 in = mlx5_vzalloc(inlen);
1085 if (!in) {
1086 err = -ENOMEM;
1087 goto err_umem;
1088 }
1089
1090 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1091 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1092 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1093 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1094 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1095 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1096 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1097
1098 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1099 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1100 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1101 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1102 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1103 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1104 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1105 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106 MLX5_SET(wq, wq, page_offset, offset);
1107
1108 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1109 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1110
1111 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1112
1113 kvfree(in);
1114
1115 if (err)
1116 goto err_umem;
1117
1118 return 0;
1119
1120err_umem:
1121 ib_umem_release(sq->ubuffer.umem);
1122 sq->ubuffer.umem = NULL;
1123
1124 return err;
1125}
1126
1127static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1128 struct mlx5_ib_sq *sq)
1129{
1130 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1131 ib_umem_release(sq->ubuffer.umem);
1132}
1133
1134static int get_rq_pas_size(void *qpc)
1135{
1136 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1137 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1138 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1139 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1140 u32 po_quanta = 1 << (log_page_size - 6);
1141 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1142 u32 page_size = 1 << log_page_size;
1143 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1144 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1145
1146 return rq_num_pas * sizeof(u64);
1147}
1148
1149static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1150 struct mlx5_ib_rq *rq, void *qpin)
1151{
358e42ea 1152 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1153 __be64 *pas;
1154 __be64 *qp_pas;
1155 void *in;
1156 void *rqc;
1157 void *wq;
1158 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1159 int inlen;
1160 int err;
1161 u32 rq_pas_size = get_rq_pas_size(qpc);
1162
1163 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1164 in = mlx5_vzalloc(inlen);
1165 if (!in)
1166 return -ENOMEM;
1167
1168 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1169 MLX5_SET(rqc, rqc, vsd, 1);
1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1175
358e42ea
MD		 1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1177 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1178
0fb2ed66 1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1182 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1189
1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1192 memcpy(pas, qp_pas, rq_pas_size);
1193
1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1195
1196 kvfree(in);
1197
1198 return err;
1199}
1200
1201static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1202 struct mlx5_ib_rq *rq)
1203{
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1205}
1206
1207static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208 struct mlx5_ib_rq *rq, u32 tdn)
1209{
1210 u32 *in;
1211 void *tirc;
1212 int inlen;
1213 int err;
1214
1215 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1216 in = mlx5_vzalloc(inlen);
1217 if (!in)
1218 return -ENOMEM;
1219
1220 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1221 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1222 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1223 MLX5_SET(tirc, tirc, transport_domain, tdn);
1224
1225 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1226
1227 kvfree(in);
1228
1229 return err;
1230}
1231
1232static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1234{
1235 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1236}
1237
1238static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1239 u32 *in,
0fb2ed66 1240 struct ib_pd *pd)
1241{
1242 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1243 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1244 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1245 struct ib_uobject *uobj = pd->uobject;
1246 struct ib_ucontext *ucontext = uobj->context;
1247 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1248 int err;
1249 u32 tdn = mucontext->tdn;
1250
1251 if (qp->sq.wqe_cnt) {
1252 err = create_raw_packet_qp_tis(dev, sq, tdn);
1253 if (err)
1254 return err;
1255
1256 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1257 if (err)
1258 goto err_destroy_tis;
1259
1260 sq->base.container_mibqp = qp;
1261 }
1262
1263 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1264 rq->base.container_mibqp = qp;
1265
0fb2ed66 1266 err = create_raw_packet_qp_rq(dev, rq, in);
1267 if (err)
1268 goto err_destroy_sq;
1269
0fb2ed66 1270
1271 err = create_raw_packet_qp_tir(dev, rq, tdn);
1272 if (err)
1273 goto err_destroy_rq;
1274 }
1275
1276 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1277 rq->base.mqp.qpn;
1278
1279 return 0;
1280
1281err_destroy_rq:
1282 destroy_raw_packet_qp_rq(dev, rq);
1283err_destroy_sq:
1284 if (!qp->sq.wqe_cnt)
1285 return err;
1286 destroy_raw_packet_qp_sq(dev, sq);
1287err_destroy_tis:
1288 destroy_raw_packet_qp_tis(dev, sq);
1289
1290 return err;
1291}
1292
1293static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1294 struct mlx5_ib_qp *qp)
1295{
1296 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1297 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1298 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1299
1300 if (qp->rq.wqe_cnt) {
1301 destroy_raw_packet_qp_tir(dev, rq);
1302 destroy_raw_packet_qp_rq(dev, rq);
1303 }
1304
1305 if (qp->sq.wqe_cnt) {
1306 destroy_raw_packet_qp_sq(dev, sq);
1307 destroy_raw_packet_qp_tis(dev, sq);
1308 }
1309}
1310
1311static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1312 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1313{
1314 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1315 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1316
1317 sq->sq = &qp->sq;
1318 rq->rq = &qp->rq;
1319 sq->doorbell = &qp->db;
1320 rq->doorbell = &qp->db;
1321}
1322
28d61370
YH		 1323static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1324{
1325 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1326}
1327
1328static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1329 struct ib_pd *pd,
1330 struct ib_qp_init_attr *init_attr,
1331 struct ib_udata *udata)
1332{
1333 struct ib_uobject *uobj = pd->uobject;
1334 struct ib_ucontext *ucontext = uobj->context;
1335 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1336 struct mlx5_ib_create_qp_resp resp = {};
1337 int inlen;
1338 int err;
1339 u32 *in;
1340 void *tirc;
1341 void *hfso;
1342 u32 selected_fields = 0;
1343 size_t min_resp_len;
1344 u32 tdn = mucontext->tdn;
1345 struct mlx5_ib_create_qp_rss ucmd = {};
1346 size_t required_cmd_sz;
1347
1348 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1349 return -EOPNOTSUPP;
1350
1351 if (init_attr->create_flags || init_attr->send_cq)
1352 return -EINVAL;
1353
1354 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1355 if (udata->outlen < min_resp_len)
1356 return -EINVAL;
1357
1358 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1359 if (udata->inlen < required_cmd_sz) {
1360 mlx5_ib_dbg(dev, "invalid inlen\n");
1361 return -EINVAL;
1362 }
1363
1364 if (udata->inlen > sizeof(ucmd) &&
1365 !ib_is_udata_cleared(udata, sizeof(ucmd),
1366 udata->inlen - sizeof(ucmd))) {
1367 mlx5_ib_dbg(dev, "inlen is not supported\n");
1368 return -EOPNOTSUPP;
1369 }
1370
1371 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1372 mlx5_ib_dbg(dev, "copy failed\n");
1373 return -EFAULT;
1374 }
1375
1376 if (ucmd.comp_mask) {
1377 mlx5_ib_dbg(dev, "invalid comp mask\n");
1378 return -EOPNOTSUPP;
1379 }
1380
1381 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1382 mlx5_ib_dbg(dev, "invalid reserved\n");
1383 return -EOPNOTSUPP;
1384 }
1385
1386 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1387 if (err) {
1388 mlx5_ib_dbg(dev, "copy failed\n");
1389 return -EINVAL;
1390 }
1391
1392 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1393 in = mlx5_vzalloc(inlen);
1394 if (!in)
1395 return -ENOMEM;
1396
1397 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1398 MLX5_SET(tirc, tirc, disp_type,
1399 MLX5_TIRC_DISP_TYPE_INDIRECT);
1400 MLX5_SET(tirc, tirc, indirect_table,
1401 init_attr->rwq_ind_tbl->ind_tbl_num);
1402 MLX5_SET(tirc, tirc, transport_domain, tdn);
1403
1404 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1405 switch (ucmd.rx_hash_function) {
1406 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1407 {
1408 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1409 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1410
1411 if (len != ucmd.rx_key_len) {
1412 err = -EINVAL;
1413 goto err;
1414 }
1415
1416 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1417 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1418 memcpy(rss_key, ucmd.rx_hash_key, len);
1419 break;
1420 }
1421 default:
1422 err = -EOPNOTSUPP;
1423 goto err;
1424 }
1425
1426 if (!ucmd.rx_hash_fields_mask) {
1427 /* special case when this TIR serves as steering entry without hashing */
1428 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1429 goto create_tir;
1430 err = -EINVAL;
1431 goto err;
1432 }
1433
1434 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1435 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1436 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1437 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1438 err = -EINVAL;
1439 goto err;
1440 }
1441
1442 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1443 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1444 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1445 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1446 MLX5_L3_PROT_TYPE_IPV4);
1447 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1448 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1449 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1450 MLX5_L3_PROT_TYPE_IPV6);
1451
1452 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1453 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1454 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1455 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1456 err = -EINVAL;
1457 goto err;
1458 }
1459
1460 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1461 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1462 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1463 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1464 MLX5_L4_PROT_TYPE_TCP);
1465 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1466 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1467 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1468 MLX5_L4_PROT_TYPE_UDP);
1469
1470 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1471 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1472 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1473
1474 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1475 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1476 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1477
1478 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1479 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1480 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1481
1482 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1483 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1484 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1485
1486 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1487
1488create_tir:
1489 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1490
1491 if (err)
1492 goto err;
1493
1494 kvfree(in);
1495 /* qpn is reserved for that QP */
1496 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1497 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1498 return 0;
1499
1500err:
1501 kvfree(in);
1502 return err;
1503}
1504
e126ba97
EC		 1505static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1506 struct ib_qp_init_attr *init_attr,
1507 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1508{
1509 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1510 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1511 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1512 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1513 struct mlx5_ib_cq *send_cq;
1514 struct mlx5_ib_cq *recv_cq;
1515 unsigned long flags;
cfb5e088 1516 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1517 struct mlx5_ib_create_qp ucmd;
1518 struct mlx5_ib_qp_base *base;
cfb5e088 1519 void *qpc;
09a7d9ec
SM		 1520 u32 *in;
1521 int err;
e126ba97 1522
0fb2ed66 1523 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1524 &qp->raw_packet_qp.rq.base :
1525 &qp->trans_qp.base;
1526
1527 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1528 mlx5_ib_odp_create_qp(qp);
6aec21f6 1529
e126ba97
EC		 1530 mutex_init(&qp->mutex);
1531 spin_lock_init(&qp->sq.lock);
1532 spin_lock_init(&qp->rq.lock);
1533
28d61370
YH		 1534 if (init_attr->rwq_ind_tbl) {
1535 if (!udata)
1536 return -ENOSYS;
1537
1538 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1539 return err;
1540 }
1541
f360d88a 1542 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1543 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1544 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1545 return -EINVAL;
1546 } else {
1547 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1548 }
1549 }
1550
051f2630
LR		 1551 if (init_attr->create_flags &
1552 (IB_QP_CREATE_CROSS_CHANNEL |
1553 IB_QP_CREATE_MANAGED_SEND |
1554 IB_QP_CREATE_MANAGED_RECV)) {
1555 if (!MLX5_CAP_GEN(mdev, cd)) {
1556 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1557 return -EINVAL;
1558 }
1559 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1560 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1561 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1562 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1563 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1564 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1565 }
f0313965
ES		 1566
1567 if (init_attr->qp_type == IB_QPT_UD &&
1568 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1569 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1570 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1571 return -EOPNOTSUPP;
1572 }
1573
358e42ea
MD		 1574 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1575 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1576 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1577 return -EOPNOTSUPP;
1578 }
1579 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1580 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1581 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1582 return -EOPNOTSUPP;
1583 }
1584 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1585 }
1586
e126ba97
EC		 1587 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1588 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1589
1590 if (pd && pd->uobject) {
1591 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1592 mlx5_ib_dbg(dev, "copy failed\n");
1593 return -EFAULT;
1594 }
1595
cfb5e088
HA		 1596 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1597 &ucmd, udata->inlen, &uidx);
1598 if (err)
1599 return err;
1600
e126ba97
EC		 1601 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1602 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1603 } else {
1604 qp->wq_sig = !!wq_signature;
1605 }
1606
1607 qp->has_rq = qp_has_rq(init_attr);
1608 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1609 qp, (pd && pd->uobject) ? &ucmd : NULL);
1610 if (err) {
1611 mlx5_ib_dbg(dev, "err %d\n", err);
1612 return err;
1613 }
1614
1615 if (pd) {
1616 if (pd->uobject) {
938fe83c
SM		 1617 __u32 max_wqes =
1618 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1619 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1620 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1621 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1622 mlx5_ib_dbg(dev, "invalid rq params\n");
1623 return -EINVAL;
1624 }
938fe83c 1625 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1626 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1627 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1628 return -EINVAL;
1629 }
b11a4f9c
HE		 1630 if (init_attr->create_flags &
1631 mlx5_ib_create_qp_sqpn_qp1()) {
1632 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1633 return -EINVAL;
1634 }
0fb2ed66 1635 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1636 &resp, &inlen, base);
e126ba97
EC		 1637 if (err)
1638 mlx5_ib_dbg(dev, "err %d\n", err);
1639 } else {
19098df2 1640 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1641 base);
e126ba97
EC		 1642 if (err)
1643 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1644 }
1645
1646 if (err)
1647 return err;
1648 } else {
09a7d9ec 1649 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1650 if (!in)
1651 return -ENOMEM;
1652
1653 qp->create_type = MLX5_QP_EMPTY;
1654 }
1655
1656 if (is_sqp(init_attr->qp_type))
1657 qp->port = init_attr->port_num;
1658
09a7d9ec
SM		 1659 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1660
1661 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1662 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1663
1664 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1665 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1666 else
09a7d9ec
SM		 1667 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1668
e126ba97
EC		 1669
1670 if (qp->wq_sig)
09a7d9ec 1671 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1672
f360d88a 1673 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1674 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1675
051f2630 1676 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1677 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1678 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1679 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1680 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1681 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1682
e126ba97
EC		 1683 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1684 int rcqe_sz;
1685 int scqe_sz;
1686
1687 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1688 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1689
1690 if (rcqe_sz == 128)
09a7d9ec 1691 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1692 else
09a7d9ec 1693 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1694
1695 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1696 if (scqe_sz == 128)
09a7d9ec 1697 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1698 else
09a7d9ec 1699 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1700 }
1701 }
1702
1703 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1704 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1705 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1706 }
1707
09a7d9ec 1708 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1709
1710 if (qp->sq.wqe_cnt)
09a7d9ec 1711 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1712 else
09a7d9ec 1713 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1714
1715 /* Set default resources */
1716 switch (init_attr->qp_type) {
1717 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1718 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1719 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1720 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1721 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1722 break;
1723 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1724 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1725 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1726 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1727 break;
1728 default:
1729 if (init_attr->srq) {
09a7d9ec
SM		 1730 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1731 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1732 } else {
09a7d9ec
SM		 1733 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1734 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1735 }
1736 }
1737
1738 if (init_attr->send_cq)
09a7d9ec 1739 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1740
1741 if (init_attr->recv_cq)
09a7d9ec 1742 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1743
09a7d9ec 1744 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1745
09a7d9ec
SM		 1746 /* 0xffffff means we ask to work with cqe version 0 */
1747 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1748 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1749
f0313965
ES		 1750 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1751 if (init_attr->qp_type == IB_QPT_UD &&
1752 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1753 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1754 qp->flags |= MLX5_IB_QP_LSO;
1755 }
cfb5e088 1756
0fb2ed66 1757 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1758 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1759 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1760 err = create_raw_packet_qp(dev, qp, in, pd);
1761 } else {
1762 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1763 }
1764
e126ba97
EC		 1765 if (err) {
1766 mlx5_ib_dbg(dev, "create qp failed\n");
1767 goto err_create;
1768 }
1769
479163f4 1770 kvfree(in);
e126ba97 1771
19098df2 1772 base->container_mibqp = qp;
1773 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1774
89ea94a7
MG		 1775 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1776 &send_cq, &recv_cq);
1777 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1778 mlx5_ib_lock_cqs(send_cq, recv_cq);
1779 /* Maintain device to QPs access, needed for further handling via reset
1780 * flow
1781 */
1782 list_add_tail(&qp->qps_list, &dev->qp_list);
1783 /* Maintain CQ to QPs access, needed for further handling via reset flow
1784 */
1785 if (send_cq)
1786 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1787 if (recv_cq)
1788 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1789 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1790 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1791
e126ba97
EC		 1792 return 0;
1793
1794err_create:
1795 if (qp->create_type == MLX5_QP_USER)
19098df2 1796 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1797 else if (qp->create_type == MLX5_QP_KERNEL)
1798 destroy_qp_kernel(dev, qp);
1799
479163f4 1800 kvfree(in);
e126ba97
EC		 1801 return err;
1802}
1803
1804static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1805 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1806{
1807 if (send_cq) {
1808 if (recv_cq) {
1809 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1810 spin_lock(&send_cq->lock);
e126ba97
EC		 1811 spin_lock_nested(&recv_cq->lock,
1812 SINGLE_DEPTH_NESTING);
1813 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1814 spin_lock(&send_cq->lock);
e126ba97
EC		 1815 __acquire(&recv_cq->lock);
1816 } else {
89ea94a7 1817 spin_lock(&recv_cq->lock);
e126ba97
EC		 1818 spin_lock_nested(&send_cq->lock,
1819 SINGLE_DEPTH_NESTING);
1820 }
1821 } else {
89ea94a7 1822 spin_lock(&send_cq->lock);
6a4f139a 1823 __acquire(&recv_cq->lock);
e126ba97
EC		 1824 }
1825 } else if (recv_cq) {
89ea94a7 1826 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1827 __acquire(&send_cq->lock);
1828 } else {
1829 __acquire(&send_cq->lock);
1830 __acquire(&recv_cq->lock);
e126ba97
EC		 1831 }
1832}
1833
1834static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1835 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1836{
1837 if (send_cq) {
1838 if (recv_cq) {
1839 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1840 spin_unlock(&recv_cq->lock);
89ea94a7 1841 spin_unlock(&send_cq->lock);
e126ba97
EC		 1842 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1843 __release(&recv_cq->lock);
89ea94a7 1844 spin_unlock(&send_cq->lock);
e126ba97
EC		 1845 } else {
1846 spin_unlock(&send_cq->lock);
89ea94a7 1847 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1848 }
1849 } else {
6a4f139a 1850 __release(&recv_cq->lock);
89ea94a7 1851 spin_unlock(&send_cq->lock);
e126ba97
EC		 1852 }
1853 } else if (recv_cq) {
6a4f139a 1854 __release(&send_cq->lock);
89ea94a7 1855 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1856 } else {
1857 __release(&recv_cq->lock);
1858 __release(&send_cq->lock);
e126ba97
EC		 1859 }
1860}
1861
1862static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1863{
1864 return to_mpd(qp->ibqp.pd);
1865}
1866
89ea94a7
MG		 1867static void get_cqs(enum ib_qp_type qp_type,
1868 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1869 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1870{
89ea94a7 1871 switch (qp_type) {
e126ba97
EC		 1872 case IB_QPT_XRC_TGT:
1873 *send_cq = NULL;
1874 *recv_cq = NULL;
1875 break;
1876 case MLX5_IB_QPT_REG_UMR:
1877 case IB_QPT_XRC_INI:
89ea94a7 1878 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1879 *recv_cq = NULL;
1880 break;
1881
1882 case IB_QPT_SMI:
d16e91da 1883 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1884 case IB_QPT_RC:
1885 case IB_QPT_UC:
1886 case IB_QPT_UD:
1887 case IB_QPT_RAW_IPV6:
1888 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1889 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1890 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1891 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1892 break;
1893
e126ba97
EC		 1894 case IB_QPT_MAX:
1895 default:
1896 *send_cq = NULL;
1897 *recv_cq = NULL;
1898 break;
1899 }
1900}
1901
ad5f8e96 1902static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1903 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1904 u8 lag_tx_affinity);
ad5f8e96 1905
e126ba97
EC		 1906static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1907{
1908 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1909 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1910 unsigned long flags;
e126ba97
EC		 1911 int err;
1912
28d61370
YH		 1913 if (qp->ibqp.rwq_ind_tbl) {
1914 destroy_rss_raw_qp_tir(dev, qp);
1915 return;
1916 }
1917
0fb2ed66 1918 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1919 &qp->raw_packet_qp.rq.base :
1920 &qp->trans_qp.base;
1921
6aec21f6 1922 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1923 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1924 mlx5_ib_qp_disable_pagefaults(qp);
1925 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1926 MLX5_CMD_OP_2RST_QP, 0,
1927 NULL, &base->mqp);
ad5f8e96 1928 } else {
0680efa2
AV		 1929 struct mlx5_modify_raw_qp_param raw_qp_param = {
1930 .operation = MLX5_CMD_OP_2RST_QP
1931 };
1932
13eab21f 1933 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1934 }
1935 if (err)
427c1e7b 1936 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1937 base->mqp.qpn);
6aec21f6 1938 }
e126ba97 1939
89ea94a7
MG		 1940 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1941 &send_cq, &recv_cq);
1942
1943 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1944 mlx5_ib_lock_cqs(send_cq, recv_cq);
1945 /* del from lists under both locks above to protect reset flow paths */
1946 list_del(&qp->qps_list);
1947 if (send_cq)
1948 list_del(&qp->cq_send_list);
1949
1950 if (recv_cq)
1951 list_del(&qp->cq_recv_list);
e126ba97
EC		 1952
1953 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1954 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1955 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1956 if (send_cq != recv_cq)
19098df2 1957 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1958 NULL);
e126ba97 1959 }
89ea94a7
MG		 1960 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1961 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1962
0fb2ed66 1963 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1964 destroy_raw_packet_qp(dev, qp);
1965 } else {
1966 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1967 if (err)
1968 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1969 base->mqp.qpn);
1970 }
e126ba97 1971
e126ba97
EC		 1972 if (qp->create_type == MLX5_QP_KERNEL)
1973 destroy_qp_kernel(dev, qp);
1974 else if (qp->create_type == MLX5_QP_USER)
19098df2 1975 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1976}
1977
1978static const char *ib_qp_type_str(enum ib_qp_type type)
1979{
1980 switch (type) {
1981 case IB_QPT_SMI:
1982 return "IB_QPT_SMI";
1983 case IB_QPT_GSI:
1984 return "IB_QPT_GSI";
1985 case IB_QPT_RC:
1986 return "IB_QPT_RC";
1987 case IB_QPT_UC:
1988 return "IB_QPT_UC";
1989 case IB_QPT_UD:
1990 return "IB_QPT_UD";
1991 case IB_QPT_RAW_IPV6:
1992 return "IB_QPT_RAW_IPV6";
1993 case IB_QPT_RAW_ETHERTYPE:
1994 return "IB_QPT_RAW_ETHERTYPE";
1995 case IB_QPT_XRC_INI:
1996 return "IB_QPT_XRC_INI";
1997 case IB_QPT_XRC_TGT:
1998 return "IB_QPT_XRC_TGT";
1999 case IB_QPT_RAW_PACKET:
2000 return "IB_QPT_RAW_PACKET";
2001 case MLX5_IB_QPT_REG_UMR:
2002 return "MLX5_IB_QPT_REG_UMR";
2003 case IB_QPT_MAX:
2004 default:
2005 return "Invalid QP type";
2006 }
2007}
2008
2009struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2010 struct ib_qp_init_attr *init_attr,
2011 struct ib_udata *udata)
2012{
2013 struct mlx5_ib_dev *dev;
2014 struct mlx5_ib_qp *qp;
2015 u16 xrcdn = 0;
2016 int err;
2017
2018 if (pd) {
2019 dev = to_mdev(pd->device);
0fb2ed66 2020
2021 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2022 if (!pd->uobject) {
2023 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2024 return ERR_PTR(-EINVAL);
2025 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2026 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2027 return ERR_PTR(-EINVAL);
2028 }
2029 }
09f16cf5
MD		 2030 } else {
2031 /* being cautious here */
2032 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2033 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2034 pr_warn("%s: no PD for transport %s\n", __func__,
2035 ib_qp_type_str(init_attr->qp_type));
2036 return ERR_PTR(-EINVAL);
2037 }
2038 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2039 }
2040
2041 switch (init_attr->qp_type) {
2042 case IB_QPT_XRC_TGT:
2043 case IB_QPT_XRC_INI:
938fe83c 2044 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2045 mlx5_ib_dbg(dev, "XRC not supported\n");
2046 return ERR_PTR(-ENOSYS);
2047 }
2048 init_attr->recv_cq = NULL;
2049 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2050 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2051 init_attr->send_cq = NULL;
2052 }
2053
2054 /* fall through */
0fb2ed66 2055 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2056 case IB_QPT_RC:
2057 case IB_QPT_UC:
2058 case IB_QPT_UD:
2059 case IB_QPT_SMI:
d16e91da 2060 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2061 case MLX5_IB_QPT_REG_UMR:
2062 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2063 if (!qp)
2064 return ERR_PTR(-ENOMEM);
2065
2066 err = create_qp_common(dev, pd, init_attr, udata, qp);
2067 if (err) {
2068 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2069 kfree(qp);
2070 return ERR_PTR(err);
2071 }
2072
2073 if (is_qp0(init_attr->qp_type))
2074 qp->ibqp.qp_num = 0;
2075 else if (is_qp1(init_attr->qp_type))
2076 qp->ibqp.qp_num = 1;
2077 else
19098df2 2078 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2079
2080 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2081 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2082 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 2083 to_mcq(init_attr->send_cq)->mcq.cqn);
2084
19098df2 2085 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2086
2087 break;
2088
d16e91da
HE		 2089 case IB_QPT_GSI:
2090 return mlx5_ib_gsi_create_qp(pd, init_attr);
2091
e126ba97
EC		 2092 case IB_QPT_RAW_IPV6:
2093 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2094 case IB_QPT_MAX:
2095 default:
2096 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2097 init_attr->qp_type);
2098 /* Don't support raw QPs */
2099 return ERR_PTR(-EINVAL);
2100 }
2101
2102 return &qp->ibqp;
2103}
2104
2105int mlx5_ib_destroy_qp(struct ib_qp *qp)
2106{
2107 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2108 struct mlx5_ib_qp *mqp = to_mqp(qp);
2109
d16e91da
HE		 2110 if (unlikely(qp->qp_type == IB_QPT_GSI))
2111 return mlx5_ib_gsi_destroy_qp(qp);
2112
e126ba97
EC		 2113 destroy_qp_common(dev, mqp);
2114
2115 kfree(mqp);
2116
2117 return 0;
2118}
2119
2120static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2121 int attr_mask)
2122{
2123 u32 hw_access_flags = 0;
2124 u8 dest_rd_atomic;
2125 u32 access_flags;
2126
2127 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2128 dest_rd_atomic = attr->max_dest_rd_atomic;
2129 else
19098df2 2130 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2131
2132 if (attr_mask & IB_QP_ACCESS_FLAGS)
2133 access_flags = attr->qp_access_flags;
2134 else
19098df2 2135 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2136
2137 if (!dest_rd_atomic)
2138 access_flags &= IB_ACCESS_REMOTE_WRITE;
2139
2140 if (access_flags & IB_ACCESS_REMOTE_READ)
2141 hw_access_flags |= MLX5_QP_BIT_RRE;
2142 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2143 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2144 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2145 hw_access_flags |= MLX5_QP_BIT_RWE;
2146
2147 return cpu_to_be32(hw_access_flags);
2148}
2149
2150enum {
2151 MLX5_PATH_FLAG_FL = 1 << 0,
2152 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2153 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2154};
2155
2156static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2157{
2158 if (rate == IB_RATE_PORT_CURRENT) {
2159 return 0;
2160 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2161 return -EINVAL;
2162 } else {
2163 while (rate != IB_RATE_2_5_GBPS &&
2164 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2165 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2166 --rate;
2167 }
2168
2169 return rate + MLX5_STAT_RATE_OFFSET;
2170}
2171
75850d0b 2172static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2173 struct mlx5_ib_sq *sq, u8 sl)
2174{
2175 void *in;
2176 void *tisc;
2177 int inlen;
2178 int err;
2179
2180 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2181 in = mlx5_vzalloc(inlen);
2182 if (!in)
2183 return -ENOMEM;
2184
2185 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2186
2187 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2188 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2189
2190 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2191
2192 kvfree(in);
2193
2194 return err;
2195}
2196
13eab21f
AH		 2197static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2198 struct mlx5_ib_sq *sq, u8 tx_affinity)
2199{
2200 void *in;
2201 void *tisc;
2202 int inlen;
2203 int err;
2204
2205 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2206 in = mlx5_vzalloc(inlen);
2207 if (!in)
2208 return -ENOMEM;
2209
2210 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2211
2212 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2213 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2214
2215 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2216
2217 kvfree(in);
2218
2219 return err;
2220}
2221
75850d0b 2222static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2223 const struct ib_ah_attr *ah,
e126ba97 2224 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2225 u32 path_flags, const struct ib_qp_attr *attr,
2226 bool alt)
e126ba97 2227{
2811ba51 2228 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 2229 int err;
2230
e126ba97 2231 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2232 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2233 attr->pkey_index);
e126ba97 2234
e126ba97 2235 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2236 if (ah->grh.sgid_index >=
2237 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2238 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2239 ah->grh.sgid_index,
2240 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2241 return -EINVAL;
2242 }
2811ba51
AS		 2243 }
2244
2245 if (ll == IB_LINK_LAYER_ETHERNET) {
2246 if (!(ah->ah_flags & IB_AH_GRH))
2247 return -EINVAL;
2248 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2249 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2250 ah->grh.sgid_index);
2251 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2252 } else {
d3ae2bde
NO		 2253 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2254 path->fl_free_ar |=
2255 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2256 path->rlid = cpu_to_be16(ah->dlid);
2257 path->grh_mlid = ah->src_path_bits & 0x7f;
2258 if (ah->ah_flags & IB_AH_GRH)
2259 path->grh_mlid |= 1 << 7;
2260 path->dci_cfi_prio_sl = ah->sl & 0xf;
2261 }
2262
2263 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2264 path->mgid_index = ah->grh.sgid_index;
2265 path->hop_limit = ah->grh.hop_limit;
2266 path->tclass_flowlabel =
2267 cpu_to_be32((ah->grh.traffic_class << 20) |
2268 (ah->grh.flow_label));
2269 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2270 }
2271
2272 err = ib_rate_to_mlx5(dev, ah->static_rate);
2273 if (err < 0)
2274 return err;
2275 path->static_rate = err;
2276 path->port = port;
2277
e126ba97 2278 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2279 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2280
75850d0b 2281 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2282 return modify_raw_packet_eth_prio(dev->mdev,
2283 &qp->raw_packet_qp.sq,
2284 ah->sl & 0xf);
2285
e126ba97
EC		 2286 return 0;
2287}
2288
2289static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2290 [MLX5_QP_STATE_INIT] = {
2291 [MLX5_QP_STATE_INIT] = {
2292 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2293 MLX5_QP_OPTPAR_RAE |
2294 MLX5_QP_OPTPAR_RWE |
2295 MLX5_QP_OPTPAR_PKEY_INDEX |
2296 MLX5_QP_OPTPAR_PRI_PORT,
2297 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2298 MLX5_QP_OPTPAR_PKEY_INDEX |
2299 MLX5_QP_OPTPAR_PRI_PORT,
2300 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2301 MLX5_QP_OPTPAR_Q_KEY |
2302 MLX5_QP_OPTPAR_PRI_PORT,
2303 },
2304 [MLX5_QP_STATE_RTR] = {
2305 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2306 MLX5_QP_OPTPAR_RRE |
2307 MLX5_QP_OPTPAR_RAE |
2308 MLX5_QP_OPTPAR_RWE |
2309 MLX5_QP_OPTPAR_PKEY_INDEX,
2310 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2311 MLX5_QP_OPTPAR_RWE |
2312 MLX5_QP_OPTPAR_PKEY_INDEX,
2313 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2314 MLX5_QP_OPTPAR_Q_KEY,
2315 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2316 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2317 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2318 MLX5_QP_OPTPAR_RRE |
2319 MLX5_QP_OPTPAR_RAE |
2320 MLX5_QP_OPTPAR_RWE |
2321 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2322 },
2323 },
2324 [MLX5_QP_STATE_RTR] = {
2325 [MLX5_QP_STATE_RTS] = {
2326 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2327 MLX5_QP_OPTPAR_RRE |
2328 MLX5_QP_OPTPAR_RAE |
2329 MLX5_QP_OPTPAR_RWE |
2330 MLX5_QP_OPTPAR_PM_STATE |
2331 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2332 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2333 MLX5_QP_OPTPAR_RWE |
2334 MLX5_QP_OPTPAR_PM_STATE,
2335 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2336 },
2337 },
2338 [MLX5_QP_STATE_RTS] = {
2339 [MLX5_QP_STATE_RTS] = {
2340 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2341 MLX5_QP_OPTPAR_RAE |
2342 MLX5_QP_OPTPAR_RWE |
2343 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2344 MLX5_QP_OPTPAR_PM_STATE |
2345 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2346 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2347 MLX5_QP_OPTPAR_PM_STATE |
2348 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2349 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2350 MLX5_QP_OPTPAR_SRQN |
2351 MLX5_QP_OPTPAR_CQN_RCV,
2352 },
2353 },
2354 [MLX5_QP_STATE_SQER] = {
2355 [MLX5_QP_STATE_RTS] = {
2356 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2357 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2358 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2359 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2360 MLX5_QP_OPTPAR_RWE |
2361 MLX5_QP_OPTPAR_RAE |
2362 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2363 },
2364 },
2365};
2366
2367static int ib_nr_to_mlx5_nr(int ib_mask)
2368{
2369 switch (ib_mask) {
2370 case IB_QP_STATE:
2371 return 0;
2372 case IB_QP_CUR_STATE:
2373 return 0;
2374 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2375 return 0;
2376 case IB_QP_ACCESS_FLAGS:
2377 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2378 MLX5_QP_OPTPAR_RAE;
2379 case IB_QP_PKEY_INDEX:
2380 return MLX5_QP_OPTPAR_PKEY_INDEX;
2381 case IB_QP_PORT:
2382 return MLX5_QP_OPTPAR_PRI_PORT;
2383 case IB_QP_QKEY:
2384 return MLX5_QP_OPTPAR_Q_KEY;
2385 case IB_QP_AV:
2386 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2387 MLX5_QP_OPTPAR_PRI_PORT;
2388 case IB_QP_PATH_MTU:
2389 return 0;
2390 case IB_QP_TIMEOUT:
2391 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2392 case IB_QP_RETRY_CNT:
2393 return MLX5_QP_OPTPAR_RETRY_COUNT;
2394 case IB_QP_RNR_RETRY:
2395 return MLX5_QP_OPTPAR_RNR_RETRY;
2396 case IB_QP_RQ_PSN:
2397 return 0;
2398 case IB_QP_MAX_QP_RD_ATOMIC:
2399 return MLX5_QP_OPTPAR_SRA_MAX;
2400 case IB_QP_ALT_PATH:
2401 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2402 case IB_QP_MIN_RNR_TIMER:
2403 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2404 case IB_QP_SQ_PSN:
2405 return 0;
2406 case IB_QP_MAX_DEST_RD_ATOMIC:
2407 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2408 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2409 case IB_QP_PATH_MIG_STATE:
2410 return MLX5_QP_OPTPAR_PM_STATE;
2411 case IB_QP_CAP:
2412 return 0;
2413 case IB_QP_DEST_QPN:
2414 return 0;
2415 }
2416 return 0;
2417}
2418
2419static int ib_mask_to_mlx5_opt(int ib_mask)
2420{
2421 int result = 0;
2422 int i;
2423
2424 for (i = 0; i < 8 * sizeof(int); i++) {
2425 if ((1 << i) & ib_mask)
2426 result |= ib_nr_to_mlx5_nr(1 << i);
2427 }
2428
2429 return result;
2430}
2431
eb49ab0c
AV		 2432static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2433 struct mlx5_ib_rq *rq, int new_state,
2434 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2435{
2436 void *in;
2437 void *rqc;
2438 int inlen;
2439 int err;
2440
2441 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2442 in = mlx5_vzalloc(inlen);
2443 if (!in)
2444 return -ENOMEM;
2445
2446 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2447
2448 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2449 MLX5_SET(rqc, rqc, state, new_state);
2450
eb49ab0c
AV		 2451 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2452 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2453 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2454 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2455 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2456 } else
2457 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2458 dev->ib_dev.name);
2459 }
2460
2461 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2462 if (err)
2463 goto out;
2464
2465 rq->state = new_state;
2466
2467out:
2468 kvfree(in);
2469 return err;
2470}
2471
2472static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2473 struct mlx5_ib_sq *sq, int new_state)
2474{
2475 void *in;
2476 void *sqc;
2477 int inlen;
2478 int err;
2479
2480 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2481 in = mlx5_vzalloc(inlen);
2482 if (!in)
2483 return -ENOMEM;
2484
2485 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2486
2487 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2488 MLX5_SET(sqc, sqc, state, new_state);
2489
2490 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2491 if (err)
2492 goto out;
2493
2494 sq->state = new_state;
2495
2496out:
2497 kvfree(in);
2498 return err;
2499}
2500
2501static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2502 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2503 u8 tx_affinity)
ad5f8e96 2504{
2505 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2506 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2507 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2508 int rq_state;
2509 int sq_state;
2510 int err;
2511
0680efa2 2512 switch (raw_qp_param->operation) {
ad5f8e96 2513 case MLX5_CMD_OP_RST2INIT_QP:
2514 rq_state = MLX5_RQC_STATE_RDY;
2515 sq_state = MLX5_SQC_STATE_RDY;
2516 break;
2517 case MLX5_CMD_OP_2ERR_QP:
2518 rq_state = MLX5_RQC_STATE_ERR;
2519 sq_state = MLX5_SQC_STATE_ERR;
2520 break;
2521 case MLX5_CMD_OP_2RST_QP:
2522 rq_state = MLX5_RQC_STATE_RST;
2523 sq_state = MLX5_SQC_STATE_RST;
2524 break;
2525 case MLX5_CMD_OP_INIT2INIT_QP:
2526 case MLX5_CMD_OP_INIT2RTR_QP:
2527 case MLX5_CMD_OP_RTR2RTS_QP:
2528 case MLX5_CMD_OP_RTS2RTS_QP:
eb49ab0c
AV		 2529 if (raw_qp_param->set_mask)
2530 return -EINVAL;
2531 else
2532 return 0;
ad5f8e96 2533 default:
2534 WARN_ON(1);
2535 return -EINVAL;
2536 }
2537
2538 if (qp->rq.wqe_cnt) {
eb49ab0c 2539 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2540 if (err)
2541 return err;
2542 }
2543
13eab21f
AH		 2544 if (qp->sq.wqe_cnt) {
2545 if (tx_affinity) {
2546 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2547 tx_affinity);
2548 if (err)
2549 return err;
2550 }
2551
ad5f8e96 2552 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
13eab21f 2553 }
ad5f8e96 2554
2555 return 0;
2556}
2557
e126ba97
EC		 2558static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2559 const struct ib_qp_attr *attr, int attr_mask,
2560 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2561{
427c1e7b 2562 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2563 [MLX5_QP_STATE_RST] = {
2564 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2565 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2566 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2567 },
2568 [MLX5_QP_STATE_INIT] = {
2569 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2570 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2571 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2572 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2573 },
2574 [MLX5_QP_STATE_RTR] = {
2575 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2576 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2577 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2578 },
2579 [MLX5_QP_STATE_RTS] = {
2580 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2581 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2582 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2583 },
2584 [MLX5_QP_STATE_SQD] = {
2585 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2586 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2587 },
2588 [MLX5_QP_STATE_SQER] = {
2589 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2590 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2591 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2592 },
2593 [MLX5_QP_STATE_ERR] = {
2594 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2595 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2596 }
2597 };
2598
e126ba97
EC		 2599 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2600 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2601 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2602 struct mlx5_ib_cq *send_cq, *recv_cq;
2603 struct mlx5_qp_context *context;
e126ba97 2604 struct mlx5_ib_pd *pd;
eb49ab0c 2605 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2606 enum mlx5_qp_state mlx5_cur, mlx5_new;
2607 enum mlx5_qp_optpar optpar;
2608 int sqd_event;
2609 int mlx5_st;
2610 int err;
427c1e7b 2611 u16 op;
13eab21f 2612 u8 tx_affinity = 0;
e126ba97 2613
1a412fb1
SM		 2614 context = kzalloc(sizeof(*context), GFP_KERNEL);
2615 if (!context)
e126ba97
EC		 2616 return -ENOMEM;
2617
e126ba97 2618 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2619 if (err < 0) {
2620 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2621 goto out;
158abf86 2622 }
e126ba97
EC		 2623
2624 context->flags = cpu_to_be32(err << 16);
2625
2626 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2627 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2628 } else {
2629 switch (attr->path_mig_state) {
2630 case IB_MIG_MIGRATED:
2631 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2632 break;
2633 case IB_MIG_REARM:
2634 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2635 break;
2636 case IB_MIG_ARMED:
2637 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2638 break;
2639 }
2640 }
2641
13eab21f
AH		 2642 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2643 if ((ibqp->qp_type == IB_QPT_RC) ||
2644 (ibqp->qp_type == IB_QPT_UD &&
2645 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2646 (ibqp->qp_type == IB_QPT_UC) ||
2647 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2648 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2649 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2650 if (mlx5_lag_is_active(dev->mdev)) {
2651 tx_affinity = (unsigned int)atomic_add_return(1,
2652 &dev->roce.next_port) %
2653 MLX5_MAX_PORTS + 1;
2654 context->flags |= cpu_to_be32(tx_affinity << 24);
2655 }
2656 }
2657 }
2658
d16e91da 2659 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2660 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2661 } else if (ibqp->qp_type == IB_QPT_UD ||
2662 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2663 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2664 } else if (attr_mask & IB_QP_PATH_MTU) {
2665 if (attr->path_mtu < IB_MTU_256 ||
2666 attr->path_mtu > IB_MTU_4096) {
2667 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2668 err = -EINVAL;
2669 goto out;
2670 }
938fe83c
SM		 2671 context->mtu_msgmax = (attr->path_mtu << 5) |
2672 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2673 }
2674
2675 if (attr_mask & IB_QP_DEST_QPN)
2676 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2677
2678 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2679 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2680
2681 /* todo implement counter_index functionality */
2682
2683 if (is_sqp(ibqp->qp_type))
2684 context->pri_path.port = qp->port;
2685
2686 if (attr_mask & IB_QP_PORT)
2687 context->pri_path.port = attr->port_num;
2688
2689 if (attr_mask & IB_QP_AV) {
75850d0b 2690 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2691 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2692 attr_mask, 0, attr, false);
e126ba97
EC		 2693 if (err)
2694 goto out;
2695 }
2696
2697 if (attr_mask & IB_QP_TIMEOUT)
2698 context->pri_path.ackto_lt |= attr->timeout << 3;
2699
2700 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2701 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2702 &context->alt_path,
f879ee8d
AS		 2703 attr->alt_port_num,
2704 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2705 0, attr, true);
e126ba97
EC		 2706 if (err)
2707 goto out;
2708 }
2709
2710 pd = get_pd(qp);
89ea94a7
MG		 2711 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2712 &send_cq, &recv_cq);
e126ba97
EC		 2713
2714 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2715 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2716 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2717 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2718
2719 if (attr_mask & IB_QP_RNR_RETRY)
2720 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2721
2722 if (attr_mask & IB_QP_RETRY_CNT)
2723 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2724
2725 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2726 if (attr->max_rd_atomic)
2727 context->params1 |=
2728 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2729 }
2730
2731 if (attr_mask & IB_QP_SQ_PSN)
2732 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2733
2734 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2735 if (attr->max_dest_rd_atomic)
2736 context->params2 |=
2737 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2738 }
2739
2740 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2741 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2742
2743 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2744 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2745
2746 if (attr_mask & IB_QP_RQ_PSN)
2747 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2748
2749 if (attr_mask & IB_QP_QKEY)
2750 context->qkey = cpu_to_be32(attr->qkey);
2751
2752 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2753 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2754
2755 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2756 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2757 sqd_event = 1;
2758 else
2759 sqd_event = 0;
2760
0837e86a
MB		 2761 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2762 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2763 qp->port) - 1;
eb49ab0c 2764 mibport = &dev->port[port_num];
0837e86a 2765 context->qp_counter_set_usr_page |=
321a9e3e 2766 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
0837e86a
MB		 2767 }
2768
e126ba97
EC		 2769 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2770 context->sq_crq_size |= cpu_to_be16(1 << 4);
2771
b11a4f9c
HE		 2772 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2773 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2774
2775 mlx5_cur = to_mlx5_state(cur_state);
2776 mlx5_new = to_mlx5_state(new_state);
2777 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2778 if (mlx5_st < 0)
e126ba97
EC		 2779 goto out;
2780
6aec21f6
HE		 2781 /* If moving to a reset or error state, we must disable page faults on
2782 * this QP and flush all current page faults. Otherwise a stale page
2783 * fault may attempt to work on this QP after it is reset and moved
2784 * again to RTS, and may cause the driver and the device to get out of
2785 * sync. */
2786 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2787 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2788 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2789 mlx5_ib_qp_disable_pagefaults(qp);
2790
427c1e7b 2791 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2792 !optab[mlx5_cur][mlx5_new])
2793 goto out;
2794
2795 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2796 optpar = ib_mask_to_mlx5_opt(attr_mask);
2797 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2798
0680efa2
AV		 2799 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2800 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2801
2802 raw_qp_param.operation = op;
eb49ab0c
AV		 2803 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2804 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2805 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2806 }
13eab21f 2807 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2808 } else {
1a412fb1 2809 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2810 &base->mqp);
0680efa2
AV		 2811 }
2812
e126ba97
EC		 2813 if (err)
2814 goto out;
2815
ad5f8e96 2816 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2817 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2818 mlx5_ib_qp_enable_pagefaults(qp);
2819
e126ba97
EC		 2820 qp->state = new_state;
2821
2822 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2823 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2824 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2825 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2826 if (attr_mask & IB_QP_PORT)
2827 qp->port = attr->port_num;
2828 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2829 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2830
2831 /*
2832 * If we moved a kernel QP to RESET, clean up all old CQ
2833 * entries and reinitialize the QP.
2834 */
2835 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2836 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2837 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2838 if (send_cq != recv_cq)
19098df2 2839 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2840
2841 qp->rq.head = 0;
2842 qp->rq.tail = 0;
2843 qp->sq.head = 0;
2844 qp->sq.tail = 0;
2845 qp->sq.cur_post = 0;
2846 qp->sq.last_poll = 0;
2847 qp->db.db[MLX5_RCV_DBR] = 0;
2848 qp->db.db[MLX5_SND_DBR] = 0;
2849 }
2850
2851out:
1a412fb1 2852 kfree(context);
e126ba97
EC		 2853 return err;
2854}
2855
2856int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2857 int attr_mask, struct ib_udata *udata)
2858{
2859 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2860 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2861 enum ib_qp_type qp_type;
e126ba97
EC		 2862 enum ib_qp_state cur_state, new_state;
2863 int err = -EINVAL;
2864 int port;
2811ba51 2865 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2866
28d61370
YH		 2867 if (ibqp->rwq_ind_tbl)
2868 return -ENOSYS;
2869
d16e91da
HE		 2870 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2871 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2872
2873 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2874 IB_QPT_GSI : ibqp->qp_type;
2875
e126ba97
EC		 2876 mutex_lock(&qp->mutex);
2877
2878 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2879 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2880
2811ba51
AS		 2881 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2882 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2883 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2884 }
2885
d16e91da
HE		 2886 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2887 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2888 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2889 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2890 goto out;
158abf86 2891 }
e126ba97
EC		 2892
2893 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2894 (attr->port_num == 0 ||
158abf86
HE		 2895 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2896 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2897 attr->port_num, dev->num_ports);
e126ba97 2898 goto out;
158abf86 2899 }
e126ba97
EC		 2900
2901 if (attr_mask & IB_QP_PKEY_INDEX) {
2902 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2903 if (attr->pkey_index >=
158abf86
HE		 2904 dev->mdev->port_caps[port - 1].pkey_table_len) {
2905 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2906 attr->pkey_index);
e126ba97 2907 goto out;
158abf86 2908 }
e126ba97
EC		 2909 }
2910
2911 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2912 attr->max_rd_atomic >
158abf86
HE		 2913 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2914 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2915 attr->max_rd_atomic);
e126ba97 2916 goto out;
158abf86 2917 }
e126ba97
EC		 2918
2919 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2920 attr->max_dest_rd_atomic >
158abf86
HE		 2921 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2922 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2923 attr->max_dest_rd_atomic);
e126ba97 2924 goto out;
158abf86 2925 }
e126ba97
EC		 2926
2927 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2928 err = 0;
2929 goto out;
2930 }
2931
2932 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2933
2934out:
2935 mutex_unlock(&qp->mutex);
2936 return err;
2937}
2938
2939static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2940{
2941 struct mlx5_ib_cq *cq;
2942 unsigned cur;
2943
2944 cur = wq->head - wq->tail;
2945 if (likely(cur + nreq < wq->max_post))
2946 return 0;
2947
2948 cq = to_mcq(ib_cq);
2949 spin_lock(&cq->lock);
2950 cur = wq->head - wq->tail;
2951 spin_unlock(&cq->lock);
2952
2953 return cur + nreq >= wq->max_post;
2954}
2955
2956static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2957 u64 remote_addr, u32 rkey)
2958{
2959 rseg->raddr = cpu_to_be64(remote_addr);
2960 rseg->rkey = cpu_to_be32(rkey);
2961 rseg->reserved = 0;
2962}
2963
f0313965
ES		 2964static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2965 struct ib_send_wr *wr, void *qend,
2966 struct mlx5_ib_qp *qp, int *size)
2967{
2968 void *seg = eseg;
2969
2970 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2971
2972 if (wr->send_flags & IB_SEND_IP_CSUM)
2973 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2974 MLX5_ETH_WQE_L4_CSUM;
2975
2976 seg += sizeof(struct mlx5_wqe_eth_seg);
2977 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2978
2979 if (wr->opcode == IB_WR_LSO) {
2980 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2981 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2982 u64 left, leftlen, copysz;
2983 void *pdata = ud_wr->header;
2984
2985 left = ud_wr->hlen;
2986 eseg->mss = cpu_to_be16(ud_wr->mss);
2987 eseg->inline_hdr_sz = cpu_to_be16(left);
2988
2989 /*
2990 * check if there is space till the end of queue, if yes,
2991 * copy all in one shot, otherwise copy till the end of queue,
2992 * rollback and than the copy the left
2993 */
2994 leftlen = qend - (void *)eseg->inline_hdr_start;
2995 copysz = min_t(u64, leftlen, left);
2996
2997 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2998
2999 if (likely(copysz > size_of_inl_hdr_start)) {
3000 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3001 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3002 }
3003
3004 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3005 seg = mlx5_get_send_wqe(qp, 0);
3006 left -= copysz;
3007 pdata += copysz;
3008 memcpy(seg, pdata, left);
3009 seg += ALIGN(left, 16);
3010 *size += ALIGN(left, 16) / 16;
3011 }
3012 }
3013
3014 return seg;
3015}
3016
e126ba97
EC		 3017static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3018 struct ib_send_wr *wr)
3019{
e622f2f4
CH		 3020 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3021 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3022 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3023}
3024
3025static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3026{
3027 dseg->byte_count = cpu_to_be32(sg->length);
3028 dseg->lkey = cpu_to_be32(sg->lkey);
3029 dseg->addr = cpu_to_be64(sg->addr);
3030}
3031
3032static __be16 get_klm_octo(int npages)
3033{
3034 return cpu_to_be16(ALIGN(npages, 8) / 2);
3035}
3036
3037static __be64 frwr_mkey_mask(void)
3038{
3039 u64 result;
3040
3041 result = MLX5_MKEY_MASK_LEN |
3042 MLX5_MKEY_MASK_PAGE_SIZE |
3043 MLX5_MKEY_MASK_START_ADDR |
3044 MLX5_MKEY_MASK_EN_RINVAL |
3045 MLX5_MKEY_MASK_KEY |
3046 MLX5_MKEY_MASK_LR |
3047 MLX5_MKEY_MASK_LW |
3048 MLX5_MKEY_MASK_RR |
3049 MLX5_MKEY_MASK_RW |
3050 MLX5_MKEY_MASK_A |
3051 MLX5_MKEY_MASK_SMALL_FENCE |
3052 MLX5_MKEY_MASK_FREE;
3053
3054 return cpu_to_be64(result);
3055}
3056
e6631814
SG		 3057static __be64 sig_mkey_mask(void)
3058{
3059 u64 result;
3060
3061 result = MLX5_MKEY_MASK_LEN |
3062 MLX5_MKEY_MASK_PAGE_SIZE |
3063 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3064 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3065 MLX5_MKEY_MASK_EN_RINVAL |
3066 MLX5_MKEY_MASK_KEY |
3067 MLX5_MKEY_MASK_LR |
3068 MLX5_MKEY_MASK_LW |
3069 MLX5_MKEY_MASK_RR |
3070 MLX5_MKEY_MASK_RW |
3071 MLX5_MKEY_MASK_SMALL_FENCE |
3072 MLX5_MKEY_MASK_FREE |
3073 MLX5_MKEY_MASK_BSF_EN;
3074
3075 return cpu_to_be64(result);
3076}
3077
8a187ee5
SG		 3078static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3079 struct mlx5_ib_mr *mr)
3080{
3081 int ndescs = mr->ndescs;
3082
3083 memset(umr, 0, sizeof(*umr));
b005d316 3084
ec22eb53 3085 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3086 /* KLMs take twice the size of MTTs */
3087 ndescs *= 2;
3088
8a187ee5
SG		 3089 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3090 umr->klm_octowords = get_klm_octo(ndescs);
3091 umr->mkey_mask = frwr_mkey_mask();
3092}
3093
dd01e66a 3094static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3095{
3096 memset(umr, 0, sizeof(*umr));
dd01e66a 3097 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3098 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3099}
3100
578e7264 3101static __be64 get_umr_reg_mr_mask(int atomic)
968e78dd
HE		 3102{
3103 u64 result;
3104
3105 result = MLX5_MKEY_MASK_LEN |
3106 MLX5_MKEY_MASK_PAGE_SIZE |
3107 MLX5_MKEY_MASK_START_ADDR |
3108 MLX5_MKEY_MASK_PD |
3109 MLX5_MKEY_MASK_LR |
3110 MLX5_MKEY_MASK_LW |
3111 MLX5_MKEY_MASK_KEY |
3112 MLX5_MKEY_MASK_RR |
3113 MLX5_MKEY_MASK_RW |
968e78dd
HE		 3114 MLX5_MKEY_MASK_FREE;
3115
578e7264
MG		 3116 if (atomic)
3117 result |= MLX5_MKEY_MASK_A;
3118
968e78dd
HE		 3119 return cpu_to_be64(result);
3120}
3121
3122static __be64 get_umr_unreg_mr_mask(void)
3123{
3124 u64 result;
3125
3126 result = MLX5_MKEY_MASK_FREE;
3127
3128 return cpu_to_be64(result);
3129}
3130
3131static __be64 get_umr_update_mtt_mask(void)
3132{
3133 u64 result;
3134
3135 result = MLX5_MKEY_MASK_FREE;
3136
3137 return cpu_to_be64(result);
3138}
3139
56e11d62
NO		 3140static __be64 get_umr_update_translation_mask(void)
3141{
3142 u64 result;
3143
3144 result = MLX5_MKEY_MASK_LEN |
3145 MLX5_MKEY_MASK_PAGE_SIZE |
3146 MLX5_MKEY_MASK_START_ADDR |
3147 MLX5_MKEY_MASK_KEY |
3148 MLX5_MKEY_MASK_FREE;
3149
3150 return cpu_to_be64(result);
3151}
3152
3153static __be64 get_umr_update_access_mask(void)
3154{
3155 u64 result;
3156
3157 result = MLX5_MKEY_MASK_LW |
3158 MLX5_MKEY_MASK_RR |
3159 MLX5_MKEY_MASK_RW |
3160 MLX5_MKEY_MASK_A |
3161 MLX5_MKEY_MASK_KEY |
3162 MLX5_MKEY_MASK_FREE;
3163
3164 return cpu_to_be64(result);
3165}
3166
3167static __be64 get_umr_update_pd_mask(void)
3168{
3169 u64 result;
3170
3171 result = MLX5_MKEY_MASK_PD |
3172 MLX5_MKEY_MASK_KEY |
3173 MLX5_MKEY_MASK_FREE;
3174
3175 return cpu_to_be64(result);
3176}
3177
e126ba97 3178static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3179 struct ib_send_wr *wr, int atomic)
e126ba97 3180{
e622f2f4 3181 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3182
3183 memset(umr, 0, sizeof(*umr));
3184
968e78dd
HE		 3185 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3186 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3187 else
3188 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3189
e126ba97 3190 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 3191 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 3192 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3193 umr->mkey_mask = get_umr_update_mtt_mask();
3194 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3195 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 3196 }
56e11d62
NO		 3197 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3198 umr->mkey_mask |= get_umr_update_translation_mask();
3199 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3200 umr->mkey_mask |= get_umr_update_access_mask();
3201 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3202 umr->mkey_mask |= get_umr_update_pd_mask();
3203 if (!umr->mkey_mask)
578e7264 3204 umr->mkey_mask = get_umr_reg_mr_mask(atomic);
e126ba97 3205 } else {
968e78dd 3206 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 3207 }
3208
3209 if (!wr->num_sge)
968e78dd 3210 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3211}
3212
3213static u8 get_umr_flags(int acc)
3214{
3215 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3216 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3217 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3218 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3219 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3220}
3221
8a187ee5
SG		 3222static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3223 struct mlx5_ib_mr *mr,
3224 u32 key, int access)
3225{
3226 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3227
3228 memset(seg, 0, sizeof(*seg));
b005d316 3229
ec22eb53 3230 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3231 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3232 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3233 /* KLMs take twice the size of MTTs */
3234 ndescs *= 2;
3235
3236 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3237 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3238 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3239 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3240 seg->len = cpu_to_be64(mr->ibmr.length);
3241 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3242}
3243
dd01e66a 3244static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3245{
3246 memset(seg, 0, sizeof(*seg));
dd01e66a 3247 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3248}
3249
3250static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3251{
e622f2f4 3252 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3253
e126ba97
EC		 3254 memset(seg, 0, sizeof(*seg));
3255 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 3256 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3257 return;
3258 }
3259
968e78dd
HE		 3260 seg->flags = convert_access(umrwr->access_flags);
3261 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 3262 if (umrwr->pd)
3263 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 3264 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3265 }
3266 seg->len = cpu_to_be64(umrwr->length);
3267 seg->log2_page_size = umrwr->page_shift;
746b5583 3268 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3269 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3270}
3271
8a187ee5
SG		 3272static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3273 struct mlx5_ib_mr *mr,
3274 struct mlx5_ib_pd *pd)
3275{
3276 int bcount = mr->desc_size * mr->ndescs;
3277
3278 dseg->addr = cpu_to_be64(mr->desc_map);
3279 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3280 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3281}
3282
e126ba97
EC		 3283static __be32 send_ieth(struct ib_send_wr *wr)
3284{
3285 switch (wr->opcode) {
3286 case IB_WR_SEND_WITH_IMM:
3287 case IB_WR_RDMA_WRITE_WITH_IMM:
3288 return wr->ex.imm_data;
3289
3290 case IB_WR_SEND_WITH_INV:
3291 return cpu_to_be32(wr->ex.invalidate_rkey);
3292
3293 default:
3294 return 0;
3295 }
3296}
3297
3298static u8 calc_sig(void *wqe, int size)
3299{
3300 u8 *p = wqe;
3301 u8 res = 0;
3302 int i;
3303
3304 for (i = 0; i < size; i++)
3305 res ^= p[i];
3306
3307 return ~res;
3308}
3309
3310static u8 wq_sig(void *wqe)
3311{
3312 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3313}
3314
3315static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3316 void *wqe, int *sz)
3317{
3318 struct mlx5_wqe_inline_seg *seg;
3319 void *qend = qp->sq.qend;
3320 void *addr;
3321 int inl = 0;
3322 int copy;
3323 int len;
3324 int i;
3325
3326 seg = wqe;
3327 wqe += sizeof(*seg);
3328 for (i = 0; i < wr->num_sge; i++) {
3329 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3330 len = wr->sg_list[i].length;
3331 inl += len;
3332
3333 if (unlikely(inl > qp->max_inline_data))
3334 return -ENOMEM;
3335
3336 if (unlikely(wqe + len > qend)) {
3337 copy = qend - wqe;
3338 memcpy(wqe, addr, copy);
3339 addr += copy;
3340 len -= copy;
3341 wqe = mlx5_get_send_wqe(qp, 0);
3342 }
3343 memcpy(wqe, addr, len);
3344 wqe += len;
3345 }
3346
3347 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3348
3349 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3350
3351 return 0;
3352}
3353
e6631814
SG		 3354static u16 prot_field_size(enum ib_signature_type type)
3355{
3356 switch (type) {
3357 case IB_SIG_TYPE_T10_DIF:
3358 return MLX5_DIF_SIZE;
3359 default:
3360 return 0;
3361 }
3362}
3363
3364static u8 bs_selector(int block_size)
3365{
3366 switch (block_size) {
3367 case 512: return 0x1;
3368 case 520: return 0x2;
3369 case 4096: return 0x3;
3370 case 4160: return 0x4;
3371 case 1073741824: return 0x5;
3372 default: return 0;
3373 }
3374}
3375
78eda2bb
SG		 3376static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3377 struct mlx5_bsf_inl *inl)
e6631814 3378{
142537f4
SG		 3379 /* Valid inline section and allow BSF refresh */
3380 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3381 MLX5_BSF_REFRESH_DIF);
3382 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3383 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3384 /* repeating block */
3385 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3386 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3387 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3388
78eda2bb
SG		 3389 if (domain->sig.dif.ref_remap)
3390 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3391
78eda2bb
SG		 3392 if (domain->sig.dif.app_escape) {
3393 if (domain->sig.dif.ref_escape)
3394 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3395 else
3396 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3397 }
3398
78eda2bb
SG		 3399 inl->dif_app_bitmask_check =
3400 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3401}
3402
3403static int mlx5_set_bsf(struct ib_mr *sig_mr,
3404 struct ib_sig_attrs *sig_attrs,
3405 struct mlx5_bsf *bsf, u32 data_size)
3406{
3407 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3408 struct mlx5_bsf_basic *basic = &bsf->basic;
3409 struct ib_sig_domain *mem = &sig_attrs->mem;
3410 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3411
c7f44fbd 3412 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3413
3414 /* Basic + Extended + Inline */
3415 basic->bsf_size_sbs = 1 << 7;
3416 /* Input domain check byte mask */
3417 basic->check_byte_mask = sig_attrs->check_mask;
3418 basic->raw_data_size = cpu_to_be32(data_size);
3419
3420 /* Memory domain */
e6631814 3421 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3422 case IB_SIG_TYPE_NONE:
3423 break;
e6631814 3424 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3425 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3426 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3427 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3428 break;
3429 default:
3430 return -EINVAL;
3431 }
e6631814 3432
78eda2bb
SG		 3433 /* Wire domain */
3434 switch (sig_attrs->wire.sig_type) {
3435 case IB_SIG_TYPE_NONE:
3436 break;
3437 case IB_SIG_TYPE_T10_DIF:
e6631814 3438 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3439 mem->sig_type == wire->sig_type) {
e6631814 3440 /* Same block structure */
142537f4 3441 basic->bsf_size_sbs |= 1 << 4;
e6631814 3442 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3443 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3444 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3445 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3446 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3447 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3448 } else
3449 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3450
142537f4 3451 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3452 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3453 break;
e6631814
SG		 3454 default:
3455 return -EINVAL;
3456 }
3457
3458 return 0;
3459}
3460
e622f2f4
CH		 3461static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3462 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3463{
e622f2f4
CH		 3464 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3465 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3466 struct mlx5_bsf *bsf;
e622f2f4
CH		 3467 u32 data_len = wr->wr.sg_list->length;
3468 u32 data_key = wr->wr.sg_list->lkey;
3469 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3470 int ret;
3471 int wqe_size;
3472
e622f2f4
CH		 3473 if (!wr->prot ||
3474 (data_key == wr->prot->lkey &&
3475 data_va == wr->prot->addr &&
3476 data_len == wr->prot->length)) {
e6631814
SG		 3477 /**
3478 * Source domain doesn't contain signature information
5c273b16 3479 * or data and protection are interleaved in memory.
e6631814
SG		 3480 * So need construct:
3481 * ------------------
3482 * | data_klm |
3483 * ------------------
3484 * | BSF |
3485 * ------------------
3486 **/
3487 struct mlx5_klm *data_klm = *seg;
3488
3489 data_klm->bcount = cpu_to_be32(data_len);
3490 data_klm->key = cpu_to_be32(data_key);
3491 data_klm->va = cpu_to_be64(data_va);
3492 wqe_size = ALIGN(sizeof(*data_klm), 64);
3493 } else {
3494 /**
3495 * Source domain contains signature information
3496 * So need construct a strided block format:
3497 * ---------------------------
3498 * | stride_block_ctrl |
3499 * ---------------------------
3500 * | data_klm |
3501 * ---------------------------
3502 * | prot_klm |
3503 * ---------------------------
3504 * | BSF |
3505 * ---------------------------
3506 **/
3507 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3508 struct mlx5_stride_block_entry *data_sentry;
3509 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3510 u32 prot_key = wr->prot->lkey;
3511 u64 prot_va = wr->prot->addr;
e6631814
SG		 3512 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3513 int prot_size;
3514
3515 sblock_ctrl = *seg;
3516 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3517 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3518
3519 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3520 if (!prot_size) {
3521 pr_err("Bad block size given: %u\n", block_size);
3522 return -EINVAL;
3523 }
3524 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3525 prot_size);
3526 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3527 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3528 sblock_ctrl->num_entries = cpu_to_be16(2);
3529
3530 data_sentry->bcount = cpu_to_be16(block_size);
3531 data_sentry->key = cpu_to_be32(data_key);
3532 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3533 data_sentry->stride = cpu_to_be16(block_size);
3534
e6631814
SG		 3535 prot_sentry->bcount = cpu_to_be16(prot_size);
3536 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3537 prot_sentry->va = cpu_to_be64(prot_va);
3538 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3539
e6631814
SG		 3540 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3541 sizeof(*prot_sentry), 64);
3542 }
3543
3544 *seg += wqe_size;
3545 *size += wqe_size / 16;
3546 if (unlikely((*seg == qp->sq.qend)))
3547 *seg = mlx5_get_send_wqe(qp, 0);
3548
3549 bsf = *seg;
3550 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3551 if (ret)
3552 return -EINVAL;
3553
3554 *seg += sizeof(*bsf);
3555 *size += sizeof(*bsf) / 16;
3556 if (unlikely((*seg == qp->sq.qend)))
3557 *seg = mlx5_get_send_wqe(qp, 0);
3558
3559 return 0;
3560}
3561
3562static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3563 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3564 u32 length, u32 pdn)
3565{
e622f2f4 3566 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3567 u32 sig_key = sig_mr->rkey;
d5436ba0 3568 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3569
3570 memset(seg, 0, sizeof(*seg));
3571
e622f2f4 3572 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3573 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3574 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3575 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3576 MLX5_MKEY_BSF_EN | pdn);
3577 seg->len = cpu_to_be64(length);
3578 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3579 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3580}
3581
3582static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3583 u32 nelements)
e6631814
SG		 3584{
3585 memset(umr, 0, sizeof(*umr));
3586
3587 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3588 umr->klm_octowords = get_klm_octo(nelements);
3589 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3590 umr->mkey_mask = sig_mkey_mask();
3591}
3592
3593
e622f2f4 3594static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3595 void **seg, int *size)
3596{
e622f2f4
CH		 3597 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3598 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3599 u32 pdn = get_pd(qp)->pdn;
3600 u32 klm_oct_size;
3601 int region_len, ret;
3602
e622f2f4
CH		 3603 if (unlikely(wr->wr.num_sge != 1) ||
3604 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3605 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3606 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3607 return -EINVAL;
3608
3609 /* length of the protected region, data + protection */
e622f2f4
CH		 3610 region_len = wr->wr.sg_list->length;
3611 if (wr->prot &&
3612 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3613 wr->prot->addr != wr->wr.sg_list->addr ||
3614 wr->prot->length != wr->wr.sg_list->length))
3615 region_len += wr->prot->length;
e6631814
SG		 3616
3617 /**
3618 * KLM octoword size - if protection was provided
3619 * then we use strided block format (3 octowords),
3620 * else we use single KLM (1 octoword)
3621 **/
e622f2f4 3622 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3623
e622f2f4 3624 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3625 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3626 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3627 if (unlikely((*seg == qp->sq.qend)))
3628 *seg = mlx5_get_send_wqe(qp, 0);
3629
3630 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3631 *seg += sizeof(struct mlx5_mkey_seg);
3632 *size += sizeof(struct mlx5_mkey_seg) / 16;
3633 if (unlikely((*seg == qp->sq.qend)))
3634 *seg = mlx5_get_send_wqe(qp, 0);
3635
3636 ret = set_sig_data_segment(wr, qp, seg, size);
3637 if (ret)
3638 return ret;
3639
d5436ba0 3640 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3641 return 0;
3642}
3643
3644static int set_psv_wr(struct ib_sig_domain *domain,
3645 u32 psv_idx, void **seg, int *size)
3646{
3647 struct mlx5_seg_set_psv *psv_seg = *seg;
3648
3649 memset(psv_seg, 0, sizeof(*psv_seg));
3650 psv_seg->psv_num = cpu_to_be32(psv_idx);
3651 switch (domain->sig_type) {
78eda2bb
SG		 3652 case IB_SIG_TYPE_NONE:
3653 break;
e6631814
SG		 3654 case IB_SIG_TYPE_T10_DIF:
3655 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3656 domain->sig.dif.app_tag);
3657 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3658 break;
e6631814
SG		 3659 default:
3660 pr_err("Bad signature type given.\n");
3661 return 1;
3662 }
3663
78eda2bb
SG		 3664 *seg += sizeof(*psv_seg);
3665 *size += sizeof(*psv_seg) / 16;
3666
e6631814
SG		 3667 return 0;
3668}
3669
8a187ee5
SG		 3670static int set_reg_wr(struct mlx5_ib_qp *qp,
3671 struct ib_reg_wr *wr,
3672 void **seg, int *size)
3673{
3674 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3675 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3676
3677 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3678 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3679 "Invalid IB_SEND_INLINE send flag\n");
3680 return -EINVAL;
3681 }
3682
3683 set_reg_umr_seg(*seg, mr);
3684 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3685 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3686 if (unlikely((*seg == qp->sq.qend)))
3687 *seg = mlx5_get_send_wqe(qp, 0);
3688
3689 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3690 *seg += sizeof(struct mlx5_mkey_seg);
3691 *size += sizeof(struct mlx5_mkey_seg) / 16;
3692 if (unlikely((*seg == qp->sq.qend)))
3693 *seg = mlx5_get_send_wqe(qp, 0);
3694
3695 set_reg_data_seg(*seg, mr, pd);
3696 *seg += sizeof(struct mlx5_wqe_data_seg);
3697 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3698
3699 return 0;
3700}
3701
dd01e66a 3702static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3703{
dd01e66a 3704 set_linv_umr_seg(*seg);
e126ba97
EC		 3705 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3706 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3707 if (unlikely((*seg == qp->sq.qend)))
3708 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3709 set_linv_mkey_seg(*seg);
e126ba97
EC		 3710 *seg += sizeof(struct mlx5_mkey_seg);
3711 *size += sizeof(struct mlx5_mkey_seg) / 16;
3712 if (unlikely((*seg == qp->sq.qend)))
3713 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3714}
3715
3716static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3717{
3718 __be32 *p = NULL;
3719 int tidx = idx;
3720 int i, j;
3721
3722 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3723 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3724 if ((i & 0xf) == 0) {
3725 void *buf = mlx5_get_send_wqe(qp, tidx);
3726 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3727 p = buf;
3728 j = 0;
3729 }
3730 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3731 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3732 be32_to_cpu(p[j + 3]));
3733 }
3734}
3735
3736static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3737 unsigned bytecnt, struct mlx5_ib_qp *qp)
3738{
3739 while (bytecnt > 0) {
3740 __iowrite64_copy(dst++, src++, 8);
3741 __iowrite64_copy(dst++, src++, 8);
3742 __iowrite64_copy(dst++, src++, 8);
3743 __iowrite64_copy(dst++, src++, 8);
3744 __iowrite64_copy(dst++, src++, 8);
3745 __iowrite64_copy(dst++, src++, 8);
3746 __iowrite64_copy(dst++, src++, 8);
3747 __iowrite64_copy(dst++, src++, 8);
3748 bytecnt -= 64;
3749 if (unlikely(src == qp->sq.qend))
3750 src = mlx5_get_send_wqe(qp, 0);
3751 }
3752}
3753
3754static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3755{
3756 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3757 wr->send_flags & IB_SEND_FENCE))
3758 return MLX5_FENCE_MODE_STRONG_ORDERING;
3759
3760 if (unlikely(fence)) {
3761 if (wr->send_flags & IB_SEND_FENCE)
3762 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3763 else
3764 return fence;
c9b25495
EC		 3765 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3766 return MLX5_FENCE_MODE_FENCE;
e126ba97 3767 }
c9b25495
EC		 3768
3769 return 0;
e126ba97
EC		 3770}
3771
6e5eadac
SG		 3772static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3773 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3774 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3775 int *size, int nreq)
3776{
b2a232d2
LR		 3777 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3778 return -ENOMEM;
6e5eadac
SG		 3779
3780 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3781 *seg = mlx5_get_send_wqe(qp, *idx);
3782 *ctrl = *seg;
3783 *(uint32_t *)(*seg + 8) = 0;
3784 (*ctrl)->imm = send_ieth(wr);
3785 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3786 (wr->send_flags & IB_SEND_SIGNALED ?
3787 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3788 (wr->send_flags & IB_SEND_SOLICITED ?
3789 MLX5_WQE_CTRL_SOLICITED : 0);
3790
3791 *seg += sizeof(**ctrl);
3792 *size = sizeof(**ctrl) / 16;
3793
b2a232d2 3794 return 0;
6e5eadac
SG		 3795}
3796
3797static void finish_wqe(struct mlx5_ib_qp *qp,
3798 struct mlx5_wqe_ctrl_seg *ctrl,
3799 u8 size, unsigned idx, u64 wr_id,
3800 int nreq, u8 fence, u8 next_fence,
3801 u32 mlx5_opcode)
3802{
3803 u8 opmod = 0;
3804
3805 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3806 mlx5_opcode | ((u32)opmod << 24));
19098df2 3807 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3808 ctrl->fm_ce_se |= fence;
3809 qp->fm_cache = next_fence;
3810 if (unlikely(qp->wq_sig))
3811 ctrl->signature = wq_sig(ctrl);
3812
3813 qp->sq.wrid[idx] = wr_id;
3814 qp->sq.w_list[idx].opcode = mlx5_opcode;
3815 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3816 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3817 qp->sq.w_list[idx].next = qp->sq.cur_post;
3818}
3819
3820
e126ba97
EC		 3821int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3822 struct ib_send_wr **bad_wr)
3823{
3824 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3825 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3826 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3827 struct mlx5_ib_qp *qp;
e6631814 3828 struct mlx5_ib_mr *mr;
e126ba97
EC		 3829 struct mlx5_wqe_data_seg *dpseg;
3830 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3831 struct mlx5_bf *bf;
e126ba97 3832 int uninitialized_var(size);
d16e91da 3833 void *qend;
e126ba97 3834 unsigned long flags;
e126ba97
EC		 3835 unsigned idx;
3836 int err = 0;
3837 int inl = 0;
3838 int num_sge;
3839 void *seg;
3840 int nreq;
3841 int i;
3842 u8 next_fence = 0;
e126ba97
EC		 3843 u8 fence;
3844
d16e91da
HE		 3845 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3846 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3847
3848 qp = to_mqp(ibqp);
3849 bf = qp->bf;
3850 qend = qp->sq.qend;
3851
e126ba97
EC		 3852 spin_lock_irqsave(&qp->sq.lock, flags);
3853
89ea94a7
MG		 3854 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3855 err = -EIO;
3856 *bad_wr = wr;
3857 nreq = 0;
3858 goto out;
3859 }
3860
e126ba97 3861 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3862 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3863 mlx5_ib_warn(dev, "\n");
3864 err = -EINVAL;
3865 *bad_wr = wr;
3866 goto out;
3867 }
3868
6e5eadac
SG		 3869 fence = qp->fm_cache;
3870 num_sge = wr->num_sge;
3871 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3872 mlx5_ib_warn(dev, "\n");
24be409b 3873 err = -EINVAL;
e126ba97
EC		 3874 *bad_wr = wr;
3875 goto out;
3876 }
3877
6e5eadac
SG		 3878 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3879 if (err) {
e126ba97
EC		 3880 mlx5_ib_warn(dev, "\n");
3881 err = -ENOMEM;
3882 *bad_wr = wr;
3883 goto out;
3884 }
3885
e126ba97
EC		 3886 switch (ibqp->qp_type) {
3887 case IB_QPT_XRC_INI:
3888 xrc = seg;
e126ba97
EC		 3889 seg += sizeof(*xrc);
3890 size += sizeof(*xrc) / 16;
3891 /* fall through */
3892 case IB_QPT_RC:
3893 switch (wr->opcode) {
3894 case IB_WR_RDMA_READ:
3895 case IB_WR_RDMA_WRITE:
3896 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3897 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3898 rdma_wr(wr)->rkey);
f241e749 3899 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3900 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3901 break;
3902
3903 case IB_WR_ATOMIC_CMP_AND_SWP:
3904 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3905 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3906 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3907 err = -ENOSYS;
3908 *bad_wr = wr;
3909 goto out;
e126ba97
EC		 3910
3911 case IB_WR_LOCAL_INV:
3912 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3913 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3914 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3915 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3916 num_sge = 0;
3917 break;
3918
8a187ee5
SG		 3919 case IB_WR_REG_MR:
3920 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3921 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3922 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3923 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3924 if (err) {
3925 *bad_wr = wr;
3926 goto out;
3927 }
3928 num_sge = 0;
3929 break;
3930
e6631814
SG		 3931 case IB_WR_REG_SIG_MR:
3932 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3933 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3934
3935 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3936 err = set_sig_umr_wr(wr, qp, &seg, &size);
3937 if (err) {
3938 mlx5_ib_warn(dev, "\n");
3939 *bad_wr = wr;
3940 goto out;
3941 }
3942
3943 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3944 nreq, get_fence(fence, wr),
3945 next_fence, MLX5_OPCODE_UMR);
3946 /*
3947 * SET_PSV WQEs are not signaled and solicited
3948 * on error
3949 */
3950 wr->send_flags &= ~IB_SEND_SIGNALED;
3951 wr->send_flags |= IB_SEND_SOLICITED;
3952 err = begin_wqe(qp, &seg, &ctrl, wr,
3953 &idx, &size, nreq);
3954 if (err) {
3955 mlx5_ib_warn(dev, "\n");
3956 err = -ENOMEM;
3957 *bad_wr = wr;
3958 goto out;
3959 }
3960
e622f2f4 3961 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3962 mr->sig->psv_memory.psv_idx, &seg,
3963 &size);
3964 if (err) {
3965 mlx5_ib_warn(dev, "\n");
3966 *bad_wr = wr;
3967 goto out;
3968 }
3969
3970 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3971 nreq, get_fence(fence, wr),
3972 next_fence, MLX5_OPCODE_SET_PSV);
3973 err = begin_wqe(qp, &seg, &ctrl, wr,
3974 &idx, &size, nreq);
3975 if (err) {
3976 mlx5_ib_warn(dev, "\n");
3977 err = -ENOMEM;
3978 *bad_wr = wr;
3979 goto out;
3980 }
3981
3982 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3983 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3984 mr->sig->psv_wire.psv_idx, &seg,
3985 &size);
3986 if (err) {
3987 mlx5_ib_warn(dev, "\n");
3988 *bad_wr = wr;
3989 goto out;
3990 }
3991
3992 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3993 nreq, get_fence(fence, wr),
3994 next_fence, MLX5_OPCODE_SET_PSV);
3995 num_sge = 0;
3996 goto skip_psv;
3997
e126ba97
EC		 3998 default:
3999 break;
4000 }
4001 break;
4002
4003 case IB_QPT_UC:
4004 switch (wr->opcode) {
4005 case IB_WR_RDMA_WRITE:
4006 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4007 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4008 rdma_wr(wr)->rkey);
e126ba97
EC		 4009 seg += sizeof(struct mlx5_wqe_raddr_seg);
4010 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4011 break;
4012
4013 default:
4014 break;
4015 }
4016 break;
4017
e126ba97 4018 case IB_QPT_SMI:
d16e91da 4019 case MLX5_IB_QPT_HW_GSI:
e126ba97 4020 set_datagram_seg(seg, wr);
f241e749 4021 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4022 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4023 if (unlikely((seg == qend)))
4024 seg = mlx5_get_send_wqe(qp, 0);
4025 break;
f0313965
ES		 4026 case IB_QPT_UD:
4027 set_datagram_seg(seg, wr);
4028 seg += sizeof(struct mlx5_wqe_datagram_seg);
4029 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4030
4031 if (unlikely((seg == qend)))
4032 seg = mlx5_get_send_wqe(qp, 0);
4033
4034 /* handle qp that supports ud offload */
4035 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4036 struct mlx5_wqe_eth_pad *pad;
e126ba97 4037
f0313965
ES		 4038 pad = seg;
4039 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4040 seg += sizeof(struct mlx5_wqe_eth_pad);
4041 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4042
4043 seg = set_eth_seg(seg, wr, qend, qp, &size);
4044
4045 if (unlikely((seg == qend)))
4046 seg = mlx5_get_send_wqe(qp, 0);
4047 }
4048 break;
e126ba97
EC		 4049 case MLX5_IB_QPT_REG_UMR:
4050 if (wr->opcode != MLX5_IB_WR_UMR) {
4051 err = -EINVAL;
4052 mlx5_ib_warn(dev, "bad opcode\n");
4053 goto out;
4054 }
4055 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4056 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4057 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4058 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4059 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4060 if (unlikely((seg == qend)))
4061 seg = mlx5_get_send_wqe(qp, 0);
4062 set_reg_mkey_segment(seg, wr);
4063 seg += sizeof(struct mlx5_mkey_seg);
4064 size += sizeof(struct mlx5_mkey_seg) / 16;
4065 if (unlikely((seg == qend)))
4066 seg = mlx5_get_send_wqe(qp, 0);
4067 break;
4068
4069 default:
4070 break;
4071 }
4072
4073 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4074 int uninitialized_var(sz);
4075
4076 err = set_data_inl_seg(qp, wr, seg, &sz);
4077 if (unlikely(err)) {
4078 mlx5_ib_warn(dev, "\n");
4079 *bad_wr = wr;
4080 goto out;
4081 }
4082 inl = 1;
4083 size += sz;
4084 } else {
4085 dpseg = seg;
4086 for (i = 0; i < num_sge; i++) {
4087 if (unlikely(dpseg == qend)) {
4088 seg = mlx5_get_send_wqe(qp, 0);
4089 dpseg = seg;
4090 }
4091 if (likely(wr->sg_list[i].length)) {
4092 set_data_ptr_seg(dpseg, wr->sg_list + i);
4093 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4094 dpseg++;
4095 }
4096 }
4097 }
4098
6e5eadac
SG		 4099 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4100 get_fence(fence, wr), next_fence,
4101 mlx5_ib_opcode[wr->opcode]);
e6631814 4102skip_psv:
e126ba97
EC		 4103 if (0)
4104 dump_wqe(qp, idx, size);
4105 }
4106
4107out:
4108 if (likely(nreq)) {
4109 qp->sq.head += nreq;
4110
4111 /* Make sure that descriptors are written before
4112 * updating doorbell record and ringing the doorbell
4113 */
4114 wmb();
4115
4116 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4117
ada388f7
EC		 4118 /* Make sure doorbell record is visible to the HCA before
4119 * we hit doorbell */
4120 wmb();
4121
e126ba97
EC		 4122 if (bf->need_lock)
4123 spin_lock(&bf->lock);
6a4f139a
EC		 4124 else
4125 __acquire(&bf->lock);
e126ba97
EC		 4126
4127 /* TBD enable WC */
4128 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4129 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4130 /* wc_wmb(); */
4131 } else {
4132 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4133 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4134 /* Make sure doorbells don't leak out of SQ spinlock
4135 * and reach the HCA out of order.
4136 */
4137 mmiowb();
4138 }
4139 bf->offset ^= bf->buf_size;
4140 if (bf->need_lock)
4141 spin_unlock(&bf->lock);
6a4f139a
EC		 4142 else
4143 __release(&bf->lock);
e126ba97
EC		 4144 }
4145
4146 spin_unlock_irqrestore(&qp->sq.lock, flags);
4147
4148 return err;
4149}
4150
4151static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4152{
4153 sig->signature = calc_sig(sig, size);
4154}
4155
4156int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4157 struct ib_recv_wr **bad_wr)
4158{
4159 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4160 struct mlx5_wqe_data_seg *scat;
4161 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4162 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4163 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4164 unsigned long flags;
4165 int err = 0;
4166 int nreq;
4167 int ind;
4168 int i;
4169
d16e91da
HE		 4170 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4171 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4172
e126ba97
EC		 4173 spin_lock_irqsave(&qp->rq.lock, flags);
4174
89ea94a7
MG		 4175 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4176 err = -EIO;
4177 *bad_wr = wr;
4178 nreq = 0;
4179 goto out;
4180 }
4181
e126ba97
EC		 4182 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4183
4184 for (nreq = 0; wr; nreq++, wr = wr->next) {
4185 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4186 err = -ENOMEM;
4187 *bad_wr = wr;
4188 goto out;
4189 }
4190
4191 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4192 err = -EINVAL;
4193 *bad_wr = wr;
4194 goto out;
4195 }
4196
4197 scat = get_recv_wqe(qp, ind);
4198 if (qp->wq_sig)
4199 scat++;
4200
4201 for (i = 0; i < wr->num_sge; i++)
4202 set_data_ptr_seg(scat + i, wr->sg_list + i);
4203
4204 if (i < qp->rq.max_gs) {
4205 scat[i].byte_count = 0;
4206 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4207 scat[i].addr = 0;
4208 }
4209
4210 if (qp->wq_sig) {
4211 sig = (struct mlx5_rwqe_sig *)scat;
4212 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4213 }
4214
4215 qp->rq.wrid[ind] = wr->wr_id;
4216
4217 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4218 }
4219
4220out:
4221 if (likely(nreq)) {
4222 qp->rq.head += nreq;
4223
4224 /* Make sure that descriptors are written before
4225 * doorbell record.
4226 */
4227 wmb();
4228
4229 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4230 }
4231
4232 spin_unlock_irqrestore(&qp->rq.lock, flags);
4233
4234 return err;
4235}
4236
4237static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4238{
4239 switch (mlx5_state) {
4240 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4241 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4242 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4243 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4244 case MLX5_QP_STATE_SQ_DRAINING:
4245 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4246 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4247 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4248 default: return -1;
4249 }
4250}
4251
4252static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4253{
4254 switch (mlx5_mig_state) {
4255 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4256 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4257 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4258 default: return -1;
4259 }
4260}
4261
4262static int to_ib_qp_access_flags(int mlx5_flags)
4263{
4264 int ib_flags = 0;
4265
4266 if (mlx5_flags & MLX5_QP_BIT_RRE)
4267 ib_flags |= IB_ACCESS_REMOTE_READ;
4268 if (mlx5_flags & MLX5_QP_BIT_RWE)
4269 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4270 if (mlx5_flags & MLX5_QP_BIT_RAE)
4271 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4272
4273 return ib_flags;
4274}
4275
4276static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4277 struct mlx5_qp_path *path)
4278{
9603b61d 4279 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4280
4281 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4282 ib_ah_attr->port_num = path->port;
4283
c7a08ac7 4284 if (ib_ah_attr->port_num == 0 ||
938fe83c 4285 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4286 return;
4287
2811ba51 4288 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4289
4290 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4291 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4292 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4293 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4294 if (ib_ah_attr->ah_flags) {
4295 ib_ah_attr->grh.sgid_index = path->mgid_index;
4296 ib_ah_attr->grh.hop_limit = path->hop_limit;
4297 ib_ah_attr->grh.traffic_class =
4298 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4299 ib_ah_attr->grh.flow_label =
4300 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4301 memcpy(ib_ah_attr->grh.dgid.raw,
4302 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4303 }
4304}
4305
6d2f89df 4306static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4307 struct mlx5_ib_sq *sq,
4308 u8 *sq_state)
4309{
4310 void *out;
4311 void *sqc;
4312 int inlen;
4313 int err;
4314
4315 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4316 out = mlx5_vzalloc(inlen);
4317 if (!out)
4318 return -ENOMEM;
4319
4320 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4321 if (err)
4322 goto out;
4323
4324 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4325 *sq_state = MLX5_GET(sqc, sqc, state);
4326 sq->state = *sq_state;
4327
4328out:
4329 kvfree(out);
4330 return err;
4331}
4332
4333static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4334 struct mlx5_ib_rq *rq,
4335 u8 *rq_state)
4336{
4337 void *out;
4338 void *rqc;
4339 int inlen;
4340 int err;
4341
4342 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4343 out = mlx5_vzalloc(inlen);
4344 if (!out)
4345 return -ENOMEM;
4346
4347 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4348 if (err)
4349 goto out;
4350
4351 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4352 *rq_state = MLX5_GET(rqc, rqc, state);
4353 rq->state = *rq_state;
4354
4355out:
4356 kvfree(out);
4357 return err;
4358}
4359
4360static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4361 struct mlx5_ib_qp *qp, u8 *qp_state)
4362{
4363 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4364 [MLX5_RQC_STATE_RST] = {
4365 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4366 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4367 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4368 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4369 },
4370 [MLX5_RQC_STATE_RDY] = {
4371 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4372 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4373 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4374 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4375 },
4376 [MLX5_RQC_STATE_ERR] = {
4377 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4378 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4379 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4380 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4381 },
4382 [MLX5_RQ_STATE_NA] = {
4383 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4384 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4385 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4386 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4387 },
4388 };
4389
4390 *qp_state = sqrq_trans[rq_state][sq_state];
4391
4392 if (*qp_state == MLX5_QP_STATE_BAD) {
4393 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4394 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4395 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4396 return -EINVAL;
4397 }
4398
4399 if (*qp_state == MLX5_QP_STATE)
4400 *qp_state = qp->state;
4401
4402 return 0;
4403}
4404
4405static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4406 struct mlx5_ib_qp *qp,
4407 u8 *raw_packet_qp_state)
4408{
4409 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4410 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4411 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4412 int err;
4413 u8 sq_state = MLX5_SQ_STATE_NA;
4414 u8 rq_state = MLX5_RQ_STATE_NA;
4415
4416 if (qp->sq.wqe_cnt) {
4417 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4418 if (err)
4419 return err;
4420 }
4421
4422 if (qp->rq.wqe_cnt) {
4423 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4424 if (err)
4425 return err;
4426 }
4427
4428 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4429 raw_packet_qp_state);
4430}
4431
4432static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4433 struct ib_qp_attr *qp_attr)
e126ba97 4434{
09a7d9ec 4435 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4436 struct mlx5_qp_context *context;
4437 int mlx5_state;
09a7d9ec 4438 u32 *outb;
e126ba97
EC		 4439 int err = 0;
4440
09a7d9ec 4441 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4442 if (!outb)
4443 return -ENOMEM;
4444
19098df2 4445 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4446 outlen);
e126ba97 4447 if (err)
6d2f89df 4448 goto out;
e126ba97 4449
09a7d9ec
SM		 4450 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4451 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4452
e126ba97
EC		 4453 mlx5_state = be32_to_cpu(context->flags) >> 28;
4454
4455 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4456 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4457 qp_attr->path_mig_state =
4458 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4459 qp_attr->qkey = be32_to_cpu(context->qkey);
4460 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4461 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4462 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4463 qp_attr->qp_access_flags =
4464 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4465
4466 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4467 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4468 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4469 qp_attr->alt_pkey_index =
4470 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4471 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4472 }
4473
d3ae2bde 4474 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4475 qp_attr->port_num = context->pri_path.port;
4476
4477 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4478 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4479
4480 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4481
4482 qp_attr->max_dest_rd_atomic =
4483 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4484 qp_attr->min_rnr_timer =
4485 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4486 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4487 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4488 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4489 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4490
4491out:
4492 kfree(outb);
4493 return err;
4494}
4495
4496int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4497 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4498{
4499 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4500 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4501 int err = 0;
4502 u8 raw_packet_qp_state;
4503
28d61370
YH		 4504 if (ibqp->rwq_ind_tbl)
4505 return -ENOSYS;
4506
d16e91da
HE		 4507 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4508 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4509 qp_init_attr);
4510
6d2f89df 4511#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4512 /*
4513 * Wait for any outstanding page faults, in case the user frees memory
4514 * based upon this query's result.
4515 */
4516 flush_workqueue(mlx5_ib_page_fault_wq);
4517#endif
4518
4519 mutex_lock(&qp->mutex);
4520
4521 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4522 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4523 if (err)
4524 goto out;
4525 qp->state = raw_packet_qp_state;
4526 qp_attr->port_num = 1;
4527 } else {
4528 err = query_qp_attr(dev, qp, qp_attr);
4529 if (err)
4530 goto out;
4531 }
4532
4533 qp_attr->qp_state = qp->state;
e126ba97
EC		 4534 qp_attr->cur_qp_state = qp_attr->qp_state;
4535 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4536 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4537
4538 if (!ibqp->uobject) {
0540d814 4539 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4540 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4541 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4542 } else {
4543 qp_attr->cap.max_send_wr = 0;
4544 qp_attr->cap.max_send_sge = 0;
4545 }
4546
0540d814
NO		 4547 qp_init_attr->qp_type = ibqp->qp_type;
4548 qp_init_attr->recv_cq = ibqp->recv_cq;
4549 qp_init_attr->send_cq = ibqp->send_cq;
4550 qp_init_attr->srq = ibqp->srq;
4551 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4552
4553 qp_init_attr->cap = qp_attr->cap;
4554
4555 qp_init_attr->create_flags = 0;
4556 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4557 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4558
051f2630
LR		 4559 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4560 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4561 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4562 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4563 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4564 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4565 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4566 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4567
e126ba97
EC		 4568 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4569 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4570
e126ba97
EC		 4571out:
4572 mutex_unlock(&qp->mutex);
4573 return err;
4574}
4575
4576struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4577 struct ib_ucontext *context,
4578 struct ib_udata *udata)
4579{
4580 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4581 struct mlx5_ib_xrcd *xrcd;
4582 int err;
4583
938fe83c 4584 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4585 return ERR_PTR(-ENOSYS);
4586
4587 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4588 if (!xrcd)
4589 return ERR_PTR(-ENOMEM);
4590
9603b61d 4591 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4592 if (err) {
4593 kfree(xrcd);
4594 return ERR_PTR(-ENOMEM);
4595 }
4596
4597 return &xrcd->ibxrcd;
4598}
4599
4600int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4601{
4602 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4603 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4604 int err;
4605
9603b61d 4606 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4607 if (err) {
4608 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4609 return err;
4610 }
4611
4612 kfree(xrcd);
4613
4614 return 0;
4615}
79b20a6c 4616
350d0e4c
YH		 4617static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4618{
4619 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4620 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4621 struct ib_event event;
4622
4623 if (rwq->ibwq.event_handler) {
4624 event.device = rwq->ibwq.device;
4625 event.element.wq = &rwq->ibwq;
4626 switch (type) {
4627 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4628 event.event = IB_EVENT_WQ_FATAL;
4629 break;
4630 default:
4631 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4632 return;
4633 }
4634
4635 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4636 }
4637}
4638
79b20a6c
YH		 4639static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4640 struct ib_wq_init_attr *init_attr)
4641{
4642 struct mlx5_ib_dev *dev;
4643 __be64 *rq_pas0;
4644 void *in;
4645 void *rqc;
4646 void *wq;
4647 int inlen;
4648 int err;
4649
4650 dev = to_mdev(pd->device);
4651
4652 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4653 in = mlx5_vzalloc(inlen);
4654 if (!in)
4655 return -ENOMEM;
4656
4657 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4658 MLX5_SET(rqc, rqc, mem_rq_type,
4659 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4660 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4661 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4662 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4663 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4664 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4665 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4666 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4667 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4668 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4669 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4670 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4671 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4672 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4673 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4674 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4675 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4676 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
79b20a6c
YH		 4677 kvfree(in);
4678 return err;
4679}
4680
4681static int set_user_rq_size(struct mlx5_ib_dev *dev,
4682 struct ib_wq_init_attr *wq_init_attr,
4683 struct mlx5_ib_create_wq *ucmd,
4684 struct mlx5_ib_rwq *rwq)
4685{
4686 /* Sanity check RQ size before proceeding */
4687 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4688 return -EINVAL;
4689
4690 if (!ucmd->rq_wqe_count)
4691 return -EINVAL;
4692
4693 rwq->wqe_count = ucmd->rq_wqe_count;
4694 rwq->wqe_shift = ucmd->rq_wqe_shift;
4695 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4696 rwq->log_rq_stride = rwq->wqe_shift;
4697 rwq->log_rq_size = ilog2(rwq->wqe_count);
4698 return 0;
4699}
4700
4701static int prepare_user_rq(struct ib_pd *pd,
4702 struct ib_wq_init_attr *init_attr,
4703 struct ib_udata *udata,
4704 struct mlx5_ib_rwq *rwq)
4705{
4706 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4707 struct mlx5_ib_create_wq ucmd = {};
4708 int err;
4709 size_t required_cmd_sz;
4710
4711 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4712 if (udata->inlen < required_cmd_sz) {
4713 mlx5_ib_dbg(dev, "invalid inlen\n");
4714 return -EINVAL;
4715 }
4716
4717 if (udata->inlen > sizeof(ucmd) &&
4718 !ib_is_udata_cleared(udata, sizeof(ucmd),
4719 udata->inlen - sizeof(ucmd))) {
4720 mlx5_ib_dbg(dev, "inlen is not supported\n");
4721 return -EOPNOTSUPP;
4722 }
4723
4724 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4725 mlx5_ib_dbg(dev, "copy failed\n");
4726 return -EFAULT;
4727 }
4728
4729 if (ucmd.comp_mask) {
4730 mlx5_ib_dbg(dev, "invalid comp mask\n");
4731 return -EOPNOTSUPP;
4732 }
4733
4734 if (ucmd.reserved) {
4735 mlx5_ib_dbg(dev, "invalid reserved\n");
4736 return -EOPNOTSUPP;
4737 }
4738
4739 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4740 if (err) {
4741 mlx5_ib_dbg(dev, "err %d\n", err);
4742 return err;
4743 }
4744
4745 err = create_user_rq(dev, pd, rwq, &ucmd);
4746 if (err) {
4747 mlx5_ib_dbg(dev, "err %d\n", err);
4748 if (err)
4749 return err;
4750 }
4751
4752 rwq->user_index = ucmd.user_index;
4753 return 0;
4754}
4755
4756struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4757 struct ib_wq_init_attr *init_attr,
4758 struct ib_udata *udata)
4759{
4760 struct mlx5_ib_dev *dev;
4761 struct mlx5_ib_rwq *rwq;
4762 struct mlx5_ib_create_wq_resp resp = {};
4763 size_t min_resp_len;
4764 int err;
4765
4766 if (!udata)
4767 return ERR_PTR(-ENOSYS);
4768
4769 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4770 if (udata->outlen && udata->outlen < min_resp_len)
4771 return ERR_PTR(-EINVAL);
4772
4773 dev = to_mdev(pd->device);
4774 switch (init_attr->wq_type) {
4775 case IB_WQT_RQ:
4776 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4777 if (!rwq)
4778 return ERR_PTR(-ENOMEM);
4779 err = prepare_user_rq(pd, init_attr, udata, rwq);
4780 if (err)
4781 goto err;
4782 err = create_rq(rwq, pd, init_attr);
4783 if (err)
4784 goto err_user_rq;
4785 break;
4786 default:
4787 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4788 init_attr->wq_type);
4789 return ERR_PTR(-EINVAL);
4790 }
4791
350d0e4c 4792 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4793 rwq->ibwq.state = IB_WQS_RESET;
4794 if (udata->outlen) {
4795 resp.response_length = offsetof(typeof(resp), response_length) +
4796 sizeof(resp.response_length);
4797 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4798 if (err)
4799 goto err_copy;
4800 }
4801
350d0e4c
YH		 4802 rwq->core_qp.event = mlx5_ib_wq_event;
4803 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4804 return &rwq->ibwq;
4805
4806err_copy:
350d0e4c 4807 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4808err_user_rq:
4809 destroy_user_rq(pd, rwq);
4810err:
4811 kfree(rwq);
4812 return ERR_PTR(err);
4813}
4814
4815int mlx5_ib_destroy_wq(struct ib_wq *wq)
4816{
4817 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4818 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4819
350d0e4c 4820 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4821 destroy_user_rq(wq->pd, rwq);
4822 kfree(rwq);
4823
4824 return 0;
4825}
4826
c5f90929
YH		 4827struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4828 struct ib_rwq_ind_table_init_attr *init_attr,
4829 struct ib_udata *udata)
4830{
4831 struct mlx5_ib_dev *dev = to_mdev(device);
4832 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4833 int sz = 1 << init_attr->log_ind_tbl_size;
4834 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4835 size_t min_resp_len;
4836 int inlen;
4837 int err;
4838 int i;
4839 u32 *in;
4840 void *rqtc;
4841
4842 if (udata->inlen > 0 &&
4843 !ib_is_udata_cleared(udata, 0,
4844 udata->inlen))
4845 return ERR_PTR(-EOPNOTSUPP);
4846
4847 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4848 if (udata->outlen && udata->outlen < min_resp_len)
4849 return ERR_PTR(-EINVAL);
4850
4851 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4852 if (!rwq_ind_tbl)
4853 return ERR_PTR(-ENOMEM);
4854
4855 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4856 in = mlx5_vzalloc(inlen);
4857 if (!in) {
4858 err = -ENOMEM;
4859 goto err;
4860 }
4861
4862 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4863
4864 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4865 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4866
4867 for (i = 0; i < sz; i++)
4868 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4869
4870 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4871 kvfree(in);
4872
4873 if (err)
4874 goto err;
4875
4876 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4877 if (udata->outlen) {
4878 resp.response_length = offsetof(typeof(resp), response_length) +
4879 sizeof(resp.response_length);
4880 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4881 if (err)
4882 goto err_copy;
4883 }
4884
4885 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4886
4887err_copy:
4888 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4889err:
4890 kfree(rwq_ind_tbl);
4891 return ERR_PTR(err);
4892}
4893
4894int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4895{
4896 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4897 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4898
4899 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4900
4901 kfree(rwq_ind_tbl);
4902 return 0;
4903}
4904
79b20a6c
YH		 4905int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4906 u32 wq_attr_mask, struct ib_udata *udata)
4907{
4908 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4909 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4910 struct mlx5_ib_modify_wq ucmd = {};
4911 size_t required_cmd_sz;
4912 int curr_wq_state;
4913 int wq_state;
4914 int inlen;
4915 int err;
4916 void *rqc;
4917 void *in;
4918
4919 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4920 if (udata->inlen < required_cmd_sz)
4921 return -EINVAL;
4922
4923 if (udata->inlen > sizeof(ucmd) &&
4924 !ib_is_udata_cleared(udata, sizeof(ucmd),
4925 udata->inlen - sizeof(ucmd)))
4926 return -EOPNOTSUPP;
4927
4928 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4929 return -EFAULT;
4930
4931 if (ucmd.comp_mask || ucmd.reserved)
4932 return -EOPNOTSUPP;
4933
4934 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4935 in = mlx5_vzalloc(inlen);
4936 if (!in)
4937 return -ENOMEM;
4938
4939 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4940
4941 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4942 wq_attr->curr_wq_state : wq->state;
4943 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4944 wq_attr->wq_state : curr_wq_state;
4945 if (curr_wq_state == IB_WQS_ERR)
4946 curr_wq_state = MLX5_RQC_STATE_ERR;
4947 if (wq_state == IB_WQS_ERR)
4948 wq_state = MLX5_RQC_STATE_ERR;
4949 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4950 MLX5_SET(rqc, rqc, state, wq_state);
4951
350d0e4c 4952 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 4953 kvfree(in);
4954 if (!err)
4955 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4956
4957 return err;
4958}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git