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RDMA/mlx5: Fix integer overflow while resizing CQ
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
e126ba97
EC		 39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 56};
57
58static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73};
74
f0313965
ES		 75struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77};
e126ba97 78
eb49ab0c
AV		 79enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 82};
83
0680efa2
AV		 84struct mlx5_modify_raw_qp_param {
85 u16 operation;
eb49ab0c
AV		 86
87 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 88 u32 rate_limit;
eb49ab0c 89 u8 rq_q_ctr_id;
0680efa2
AV		 90};
91
89ea94a7
MG		 92static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
e126ba97
EC		 96static int is_qp0(enum ib_qp_type qp_type)
97{
98 return qp_type == IB_QPT_SMI;
99}
100
e126ba97
EC		 101static int is_sqp(enum ib_qp_type qp_type)
102{
103 return is_qp0(qp_type) || is_qp1(qp_type);
104}
105
106static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107{
108 return mlx5_buf_offset(&qp->buf, offset);
109}
110
111static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112{
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114}
115
116void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117{
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119}
120
c1395a2a
HE		 121/**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 141{
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
19098df2 147 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191}
192
e126ba97
EC		 193static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194{
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
19098df2 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
e126ba97
EC		 202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238}
239
240static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242{
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
938fe83c 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
0540d814
NO		 254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
e126ba97
EC		 256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
938fe83c
SM		 272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
e126ba97
EC		 274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283}
284
f0313965 285static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 286{
618af384 287 int size = 0;
e126ba97 288
f0313965 289 switch (attr->qp_type) {
e126ba97 290 case IB_QPT_XRC_INI:
b125a54b 291 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 299 break;
300
b125a54b
EC		 301 case IB_QPT_XRC_TGT:
302 return 0;
303
e126ba97 304 case IB_QPT_UC:
b125a54b 305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 309 break;
310
311 case IB_QPT_UD:
f0313965
ES		 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
e126ba97 316 case IB_QPT_SMI:
d16e91da 317 case MLX5_IB_QPT_HW_GSI:
b125a54b 318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
b125a54b 323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333}
334
335static int calc_send_wqe(struct ib_qp_init_attr *attr)
336{
337 int inl_size = 0;
338 int size;
339
f0313965 340 size = sq_overhead(attr);
e126ba97
EC		 341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 355}
356
288c01b7
EC		 357static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358{
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378}
379
e126ba97
EC		 380static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382{
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
938fe83c 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 397 return -EINVAL;
398 }
399
f0313965
ES		 400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 402 attr->cap.max_inline_data = qp->max_inline_data;
403
e1e66cc2
SG		 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
e126ba97
EC		 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 414 return -ENOMEM;
415 }
e126ba97 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 424
425 return wq_size;
426}
427
428static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
19098df2 430 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
e126ba97
EC		 433{
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
938fe83c 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
938fe83c 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 454 return -EINVAL;
455 }
456
c2e53b2c
YH		 457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
e126ba97
EC		 465
466 return 0;
467}
468
469static int qp_has_rq(struct ib_qp_init_attr *attr)
470{
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478}
479
2f5ff264 480static int first_med_bfreg(void)
c1be5232
EC		 481{
482 return 1;
483}
484
0b80c14f
EC		 485enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492};
493
b037c29a
EC		 494static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495{
31a78a5a 496 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 497}
498
499static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 501{
502 int n;
503
b037c29a
EC		 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 506
507 return n >= 0 ? n : 0;
508}
509
b037c29a
EC		 510static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 512{
513 int med;
c1be5232 514
b037c29a
EC		 515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
c1be5232
EC		 517}
518
b037c29a
EC		 519static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
e126ba97 521{
e126ba97
EC		 522 int i;
523
b037c29a
EC		 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
2f5ff264 526 bfregi->count[i]++;
e126ba97
EC		 527 return i;
528 }
529 }
530
531 return -ENOMEM;
532}
533
b037c29a
EC		 534static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
e126ba97 536{
2f5ff264 537 int minidx = first_med_bfreg();
e126ba97
EC		 538 int i;
539
b037c29a 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 541 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 542 minidx = i;
0b80c14f
EC		 543 if (!bfregi->count[minidx])
544 break;
e126ba97
EC		 545 }
546
2f5ff264 547 bfregi->count[minidx]++;
e126ba97
EC		 548 return minidx;
549}
550
b037c29a
EC		 551static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
2f5ff264 553 enum mlx5_ib_latency_class lat)
e126ba97 554{
2f5ff264 555 int bfregn = -EINVAL;
e126ba97 556
2f5ff264 557 mutex_lock(&bfregi->lock);
e126ba97
EC		 558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 561 bfregn = 0;
562 bfregi->count[bfregn]++;
e126ba97
EC		 563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
78c0f98c 568 else
b037c29a 569 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
78c0f98c 575 else
b037c29a 576 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 577 break;
578 }
2f5ff264 579 mutex_unlock(&bfregi->lock);
e126ba97 580
2f5ff264 581 return bfregn;
e126ba97
EC		 582}
583
4ed131d0 584void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 585{
2f5ff264 586 mutex_lock(&bfregi->lock);
b037c29a 587 bfregi->count[bfregn]--;
2f5ff264 588 mutex_unlock(&bfregi->lock);
e126ba97
EC		 589}
590
591static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592{
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603}
604
605static int to_mlx5_st(enum ib_qp_type type)
606{
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 616 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 617 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 618 case IB_QPT_RAW_PACKET:
0fb2ed66 619 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 620 case IB_QPT_MAX:
621 default: return -EINVAL;
622 }
623}
624
89ea94a7
MG		 625static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
626 struct mlx5_ib_cq *recv_cq);
627static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
628 struct mlx5_ib_cq *recv_cq);
629
b037c29a 630static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1ee47ab3
YH		 631 struct mlx5_bfreg_info *bfregi, int bfregn,
632 bool dyn_bfreg)
e126ba97 633{
b037c29a
EC		 634 int bfregs_per_sys_page;
635 int index_of_sys_page;
636 int offset;
637
638 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
639 MLX5_NON_FP_BFREGS_PER_UAR;
640 index_of_sys_page = bfregn / bfregs_per_sys_page;
641
1ee47ab3
YH		 642 if (dyn_bfreg) {
643 index_of_sys_page += bfregi->num_static_sys_pages;
644 if (bfregn > bfregi->num_dyn_bfregs ||
645 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
646 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
647 return -EINVAL;
648 }
649 }
b037c29a 650
1ee47ab3 651 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 652 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 653}
654
19098df2 655static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
656 struct ib_pd *pd,
657 unsigned long addr, size_t size,
658 struct ib_umem **umem,
659 int *npages, int *page_shift, int *ncont,
660 u32 *offset)
661{
662 int err;
663
664 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
665 if (IS_ERR(*umem)) {
666 mlx5_ib_dbg(dev, "umem_get failed\n");
667 return PTR_ERR(*umem);
668 }
669
762f899a 670 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 671
672 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
673 if (err) {
674 mlx5_ib_warn(dev, "bad offset\n");
675 goto err_umem;
676 }
677
678 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
679 addr, size, *npages, *page_shift, *ncont, *offset);
680
681 return 0;
682
683err_umem:
684 ib_umem_release(*umem);
685 *umem = NULL;
686
687 return err;
688}
689
fe248c3a
MG		 690static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
691 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 692{
693 struct mlx5_ib_ucontext *context;
694
fe248c3a
MG		 695 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
696 atomic_dec(&dev->delay_drop.rqs_cnt);
697
79b20a6c
YH		 698 context = to_mucontext(pd->uobject->context);
699 mlx5_ib_db_unmap_user(context, &rwq->db);
700 if (rwq->umem)
701 ib_umem_release(rwq->umem);
702}
703
704static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
705 struct mlx5_ib_rwq *rwq,
706 struct mlx5_ib_create_wq *ucmd)
707{
708 struct mlx5_ib_ucontext *context;
709 int page_shift = 0;
710 int npages;
711 u32 offset = 0;
712 int ncont = 0;
713 int err;
714
715 if (!ucmd->buf_addr)
716 return -EINVAL;
717
718 context = to_mucontext(pd->uobject->context);
719 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
720 rwq->buf_size, 0, 0);
721 if (IS_ERR(rwq->umem)) {
722 mlx5_ib_dbg(dev, "umem_get failed\n");
723 err = PTR_ERR(rwq->umem);
724 return err;
725 }
726
762f899a 727 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 728 &ncont, NULL);
729 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
730 &rwq->rq_page_offset);
731 if (err) {
732 mlx5_ib_warn(dev, "bad offset\n");
733 goto err_umem;
734 }
735
736 rwq->rq_num_pas = ncont;
737 rwq->page_shift = page_shift;
738 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
739 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
740
741 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
742 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
743 npages, page_shift, ncont, offset);
744
745 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
746 if (err) {
747 mlx5_ib_dbg(dev, "map failed\n");
748 goto err_umem;
749 }
750
751 rwq->create_type = MLX5_WQ_USER;
752 return 0;
753
754err_umem:
755 ib_umem_release(rwq->umem);
756 return err;
757}
758
b037c29a
EC		 759static int adjust_bfregn(struct mlx5_ib_dev *dev,
760 struct mlx5_bfreg_info *bfregi, int bfregn)
761{
762 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
763 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
764}
765
e126ba97
EC		 766static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
767 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 768 struct ib_qp_init_attr *attr,
09a7d9ec 769 u32 **in,
19098df2 770 struct mlx5_ib_create_qp_resp *resp, int *inlen,
771 struct mlx5_ib_qp_base *base)
e126ba97
EC		 772{
773 struct mlx5_ib_ucontext *context;
774 struct mlx5_ib_create_qp ucmd;
19098df2 775 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 776 int page_shift = 0;
1ee47ab3 777 int uar_index = 0;
e126ba97 778 int npages;
9e9c47d0 779 u32 offset = 0;
2f5ff264 780 int bfregn;
9e9c47d0 781 int ncont = 0;
09a7d9ec
SM		 782 __be64 *pas;
783 void *qpc;
e126ba97
EC		 784 int err;
785
786 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
787 if (err) {
788 mlx5_ib_dbg(dev, "copy failed\n");
789 return err;
790 }
791
792 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 793 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
794 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
795 ucmd.bfreg_index, true);
796 if (uar_index < 0)
797 return uar_index;
798
799 bfregn = MLX5_IB_INVALID_BFREG;
800 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
801 /*
802 * TBD: should come from the verbs when we have the API
803 */
051f2630 804 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 805 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 806 }
051f2630 807 else {
b037c29a 808 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 809 if (bfregn < 0) {
810 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 811 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 812 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 813 if (bfregn < 0) {
814 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 815 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 816 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 817 if (bfregn < 0) {
818 mlx5_ib_warn(dev, "bfreg allocation failed\n");
819 return bfregn;
051f2630 820 }
c1be5232 821 }
e126ba97
EC		 822 }
823 }
824
2f5ff264 825 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 826 if (bfregn != MLX5_IB_INVALID_BFREG)
827 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
828 false);
e126ba97 829
48fea837
HE		 830 qp->rq.offset = 0;
831 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
832 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
833
0fb2ed66 834 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 835 if (err)
2f5ff264 836 goto err_bfreg;
e126ba97 837
19098df2 838 if (ucmd.buf_addr && ubuffer->buf_size) {
839 ubuffer->buf_addr = ucmd.buf_addr;
840 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
841 ubuffer->buf_size,
842 &ubuffer->umem, &npages, &page_shift,
843 &ncont, &offset);
844 if (err)
2f5ff264 845 goto err_bfreg;
9e9c47d0 846 } else {
19098df2 847 ubuffer->umem = NULL;
e126ba97 848 }
e126ba97 849
09a7d9ec
SM		 850 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
851 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 852 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 853 if (!*in) {
854 err = -ENOMEM;
855 goto err_umem;
856 }
09a7d9ec
SM		 857
858 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 859 if (ubuffer->umem)
09a7d9ec
SM		 860 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
861
862 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
863
864 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
865 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 866
09a7d9ec 867 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 868 if (bfregn != MLX5_IB_INVALID_BFREG)
869 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
870 else
871 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 872 qp->bfregn = bfregn;
e126ba97
EC		 873
874 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
875 if (err) {
876 mlx5_ib_dbg(dev, "map failed\n");
877 goto err_free;
878 }
879
880 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
881 if (err) {
882 mlx5_ib_dbg(dev, "copy failed\n");
883 goto err_unmap;
884 }
885 qp->create_type = MLX5_QP_USER;
886
887 return 0;
888
889err_unmap:
890 mlx5_ib_db_unmap_user(context, &qp->db);
891
892err_free:
479163f4 893 kvfree(*in);
e126ba97
EC		 894
895err_umem:
19098df2 896 if (ubuffer->umem)
897 ib_umem_release(ubuffer->umem);
e126ba97 898
2f5ff264 899err_bfreg:
1ee47ab3
YH		 900 if (bfregn != MLX5_IB_INVALID_BFREG)
901 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 902 return err;
903}
904
b037c29a
EC		 905static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
906 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 907{
908 struct mlx5_ib_ucontext *context;
909
910 context = to_mucontext(pd->uobject->context);
911 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 912 if (base->ubuffer.umem)
913 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 914
915 /*
916 * Free only the BFREGs which are handled by the kernel.
917 * BFREGs of UARs allocated dynamically are handled by user.
918 */
919 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
920 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 921}
922
923static int create_kernel_qp(struct mlx5_ib_dev *dev,
924 struct ib_qp_init_attr *init_attr,
925 struct mlx5_ib_qp *qp,
09a7d9ec 926 u32 **in, int *inlen,
19098df2 927 struct mlx5_ib_qp_base *base)
e126ba97 928{
e126ba97 929 int uar_index;
09a7d9ec 930 void *qpc;
e126ba97
EC		 931 int err;
932
f0313965
ES		 933 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
934 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 935 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 936 IB_QP_CREATE_NETIF_QP |
b11a4f9c 937 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 938 return -EINVAL;
e126ba97
EC		 939
940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 941 qp->bf.bfreg = &dev->fp_bfreg;
942 else
943 qp->bf.bfreg = &dev->bfreg;
e126ba97 944
d8030b0d
EC		 945 /* We need to divide by two since each register is comprised of
946 * two buffers of identical size, namely odd and even
947 */
948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 949 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 950
951 err = calc_sq_size(dev, init_attr, qp);
952 if (err < 0) {
953 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 954 return err;
e126ba97
EC		 955 }
956
957 qp->rq.offset = 0;
958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 960
19098df2 961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 962 if (err) {
963 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 964 return err;
e126ba97
EC		 965 }
966
967 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 968 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
969 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 970 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 971 if (!*in) {
972 err = -ENOMEM;
973 goto err_buf;
974 }
09a7d9ec
SM		 975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977 MLX5_SET(qpc, qpc, uar_page, uar_index);
978 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979
e126ba97 980 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 981 MLX5_SET(qpc, qpc, fre, 1);
982 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 983
b11a4f9c 984 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 985 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 986 qp->flags |= MLX5_IB_QP_SQPN_QP1;
987 }
988
09a7d9ec
SM		 989 mlx5_fill_page_array(&qp->buf,
990 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 991
9603b61d 992 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 993 if (err) {
994 mlx5_ib_dbg(dev, "err %d\n", err);
995 goto err_free;
996 }
997
b5883008
LD		 998 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
999 sizeof(*qp->sq.wrid), GFP_KERNEL);
1000 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1001 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1002 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1003 sizeof(*qp->rq.wrid), GFP_KERNEL);
1004 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1005 sizeof(*qp->sq.w_list), GFP_KERNEL);
1006 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1007 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1008
1009 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1010 !qp->sq.w_list || !qp->sq.wqe_head) {
1011 err = -ENOMEM;
1012 goto err_wrid;
1013 }
1014 qp->create_type = MLX5_QP_KERNEL;
1015
1016 return 0;
1017
1018err_wrid:
b5883008
LD		 1019 kvfree(qp->sq.wqe_head);
1020 kvfree(qp->sq.w_list);
1021 kvfree(qp->sq.wrid);
1022 kvfree(qp->sq.wr_data);
1023 kvfree(qp->rq.wrid);
f4044dac 1024 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1025
1026err_free:
479163f4 1027 kvfree(*in);
e126ba97
EC		 1028
1029err_buf:
9603b61d 1030 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1031 return err;
1032}
1033
1034static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1035{
b5883008
LD		 1036 kvfree(qp->sq.wqe_head);
1037 kvfree(qp->sq.w_list);
1038 kvfree(qp->sq.wrid);
1039 kvfree(qp->sq.wr_data);
1040 kvfree(qp->rq.wrid);
f4044dac 1041 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1042 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1043}
1044
09a7d9ec 1045static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1046{
1047 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1048 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1049 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1050 return MLX5_SRQ_RQ;
e126ba97 1051 else if (!qp->has_rq)
09a7d9ec 1052 return MLX5_ZERO_LEN_RQ;
e126ba97 1053 else
09a7d9ec 1054 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1055}
1056
1057static int is_connected(enum ib_qp_type qp_type)
1058{
1059 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1060 return 1;
1061
1062 return 0;
1063}
1064
0fb2ed66 1065static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1066 struct mlx5_ib_qp *qp,
0fb2ed66 1067 struct mlx5_ib_sq *sq, u32 tdn)
1068{
c4f287c4 1069 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1070 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1071
0fb2ed66 1072 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1073 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1074 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1075
0fb2ed66 1076 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1077}
1078
1079static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080 struct mlx5_ib_sq *sq)
1081{
1082 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1083}
1084
1085static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1086 struct mlx5_ib_sq *sq, void *qpin,
1087 struct ib_pd *pd)
1088{
1089 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1090 __be64 *pas;
1091 void *in;
1092 void *sqc;
1093 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1094 void *wq;
1095 int inlen;
1096 int err;
1097 int page_shift = 0;
1098 int npages;
1099 int ncont = 0;
1100 u32 offset = 0;
1101
1102 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1103 &sq->ubuffer.umem, &npages, &page_shift,
1104 &ncont, &offset);
1105 if (err)
1106 return err;
1107
1108 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1109 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1110 if (!in) {
1111 err = -ENOMEM;
1112 goto err_umem;
1113 }
1114
1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1117 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1118 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1119 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1120 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1121 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1122 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1123 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1124 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1125 MLX5_CAP_ETH(dev->mdev, swp))
1126 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1127
1128 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1129 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1130 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1131 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1132 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1134 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1135 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1136 MLX5_SET(wq, wq, page_offset, offset);
1137
1138 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1139 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1140
1141 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1142
1143 kvfree(in);
1144
1145 if (err)
1146 goto err_umem;
1147
1148 return 0;
1149
1150err_umem:
1151 ib_umem_release(sq->ubuffer.umem);
1152 sq->ubuffer.umem = NULL;
1153
1154 return err;
1155}
1156
1157static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1158 struct mlx5_ib_sq *sq)
1159{
1160 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1161 ib_umem_release(sq->ubuffer.umem);
1162}
1163
1164static int get_rq_pas_size(void *qpc)
1165{
1166 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1167 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1168 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1169 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1170 u32 po_quanta = 1 << (log_page_size - 6);
1171 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1172 u32 page_size = 1 << log_page_size;
1173 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1174 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1175
1176 return rq_num_pas * sizeof(u64);
1177}
1178
1179static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1180 struct mlx5_ib_rq *rq, void *qpin)
1181{
358e42ea 1182 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1183 __be64 *pas;
1184 __be64 *qp_pas;
1185 void *in;
1186 void *rqc;
1187 void *wq;
1188 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1189 int inlen;
1190 int err;
1191 u32 rq_pas_size = get_rq_pas_size(qpc);
1192
1193 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1194 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1195 if (!in)
1196 return -ENOMEM;
1197
1198 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1199 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1200 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1201 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1202 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1203 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1204 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1205 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1206
358e42ea
MD		 1207 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1208 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1209
0fb2ed66 1210 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1211 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1212 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1213 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1214 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1215 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1216 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1217 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1218 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1219 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1220
1221 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1222 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1223 memcpy(pas, qp_pas, rq_pas_size);
1224
1225 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1226
1227 kvfree(in);
1228
1229 return err;
1230}
1231
1232static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1234{
1235 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1236}
1237
f95ef6cb
MG		 1238static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1239{
1240 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1241 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1242 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1243}
1244
0fb2ed66 1245static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb
MG		 1246 struct mlx5_ib_rq *rq, u32 tdn,
1247 bool tunnel_offload_en)
0fb2ed66 1248{
1249 u32 *in;
1250 void *tirc;
1251 int inlen;
1252 int err;
1253
1254 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1255 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1256 if (!in)
1257 return -ENOMEM;
1258
1259 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1260 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1261 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1262 MLX5_SET(tirc, tirc, transport_domain, tdn);
f95ef6cb
MG		 1263 if (tunnel_offload_en)
1264 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1265
1266 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1267
1268 kvfree(in);
1269
1270 return err;
1271}
1272
1273static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_rq *rq)
1275{
1276 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1277}
1278
1279static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1280 u32 *in,
0fb2ed66 1281 struct ib_pd *pd)
1282{
1283 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1284 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1285 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1286 struct ib_uobject *uobj = pd->uobject;
1287 struct ib_ucontext *ucontext = uobj->context;
1288 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1289 int err;
1290 u32 tdn = mucontext->tdn;
1291
1292 if (qp->sq.wqe_cnt) {
c2e53b2c 1293 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1294 if (err)
1295 return err;
1296
1297 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1298 if (err)
1299 goto err_destroy_tis;
1300
1301 sq->base.container_mibqp = qp;
1d31e9c0 1302 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1303 }
1304
1305 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1306 rq->base.container_mibqp = qp;
1307
e4cc4fa7
NO		 1308 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1309 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1310 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1311 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
0fb2ed66 1312 err = create_raw_packet_qp_rq(dev, rq, in);
1313 if (err)
1314 goto err_destroy_sq;
1315
0fb2ed66 1316
f95ef6cb
MG		 1317 err = create_raw_packet_qp_tir(dev, rq, tdn,
1318 qp->tunnel_offload_en);
0fb2ed66 1319 if (err)
1320 goto err_destroy_rq;
1321 }
1322
1323 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1324 rq->base.mqp.qpn;
1325
1326 return 0;
1327
1328err_destroy_rq:
1329 destroy_raw_packet_qp_rq(dev, rq);
1330err_destroy_sq:
1331 if (!qp->sq.wqe_cnt)
1332 return err;
1333 destroy_raw_packet_qp_sq(dev, sq);
1334err_destroy_tis:
1335 destroy_raw_packet_qp_tis(dev, sq);
1336
1337 return err;
1338}
1339
1340static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1341 struct mlx5_ib_qp *qp)
1342{
1343 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1344 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1345 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1346
1347 if (qp->rq.wqe_cnt) {
1348 destroy_raw_packet_qp_tir(dev, rq);
1349 destroy_raw_packet_qp_rq(dev, rq);
1350 }
1351
1352 if (qp->sq.wqe_cnt) {
1353 destroy_raw_packet_qp_sq(dev, sq);
1354 destroy_raw_packet_qp_tis(dev, sq);
1355 }
1356}
1357
1358static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1359 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1360{
1361 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1362 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1363
1364 sq->sq = &qp->sq;
1365 rq->rq = &qp->rq;
1366 sq->doorbell = &qp->db;
1367 rq->doorbell = &qp->db;
1368}
1369
28d61370
YH		 1370static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1371{
1372 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1373}
1374
1375static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1376 struct ib_pd *pd,
1377 struct ib_qp_init_attr *init_attr,
1378 struct ib_udata *udata)
1379{
1380 struct ib_uobject *uobj = pd->uobject;
1381 struct ib_ucontext *ucontext = uobj->context;
1382 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1383 struct mlx5_ib_create_qp_resp resp = {};
1384 int inlen;
1385 int err;
1386 u32 *in;
1387 void *tirc;
1388 void *hfso;
1389 u32 selected_fields = 0;
1390 size_t min_resp_len;
1391 u32 tdn = mucontext->tdn;
1392 struct mlx5_ib_create_qp_rss ucmd = {};
1393 size_t required_cmd_sz;
1394
1395 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1396 return -EOPNOTSUPP;
1397
1398 if (init_attr->create_flags || init_attr->send_cq)
1399 return -EINVAL;
1400
2f5ff264 1401 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1402 if (udata->outlen < min_resp_len)
1403 return -EINVAL;
1404
f95ef6cb 1405 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1406 if (udata->inlen < required_cmd_sz) {
1407 mlx5_ib_dbg(dev, "invalid inlen\n");
1408 return -EINVAL;
1409 }
1410
1411 if (udata->inlen > sizeof(ucmd) &&
1412 !ib_is_udata_cleared(udata, sizeof(ucmd),
1413 udata->inlen - sizeof(ucmd))) {
1414 mlx5_ib_dbg(dev, "inlen is not supported\n");
1415 return -EOPNOTSUPP;
1416 }
1417
1418 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1419 mlx5_ib_dbg(dev, "copy failed\n");
1420 return -EFAULT;
1421 }
1422
1423 if (ucmd.comp_mask) {
1424 mlx5_ib_dbg(dev, "invalid comp mask\n");
1425 return -EOPNOTSUPP;
1426 }
1427
f95ef6cb
MG		 1428 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1429 mlx5_ib_dbg(dev, "invalid flags\n");
1430 return -EOPNOTSUPP;
1431 }
1432
1433 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1434 !tunnel_offload_supported(dev->mdev)) {
1435 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1436 return -EOPNOTSUPP;
1437 }
1438
309fa347
MG		 1439 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1440 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1441 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1442 return -EOPNOTSUPP;
1443 }
1444
28d61370
YH		 1445 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1446 if (err) {
1447 mlx5_ib_dbg(dev, "copy failed\n");
1448 return -EINVAL;
1449 }
1450
1451 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1452 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1453 if (!in)
1454 return -ENOMEM;
1455
1456 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1457 MLX5_SET(tirc, tirc, disp_type,
1458 MLX5_TIRC_DISP_TYPE_INDIRECT);
1459 MLX5_SET(tirc, tirc, indirect_table,
1460 init_attr->rwq_ind_tbl->ind_tbl_num);
1461 MLX5_SET(tirc, tirc, transport_domain, tdn);
1462
1463 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1464
1465 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1466 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1467
309fa347
MG		 1468 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1469 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1470 else
1471 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1472
28d61370
YH		 1473 switch (ucmd.rx_hash_function) {
1474 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1475 {
1476 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1477 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1478
1479 if (len != ucmd.rx_key_len) {
1480 err = -EINVAL;
1481 goto err;
1482 }
1483
1484 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1485 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1486 memcpy(rss_key, ucmd.rx_hash_key, len);
1487 break;
1488 }
1489 default:
1490 err = -EOPNOTSUPP;
1491 goto err;
1492 }
1493
1494 if (!ucmd.rx_hash_fields_mask) {
1495 /* special case when this TIR serves as steering entry without hashing */
1496 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1497 goto create_tir;
1498 err = -EINVAL;
1499 goto err;
1500 }
1501
1502 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1504 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1505 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1506 err = -EINVAL;
1507 goto err;
1508 }
1509
1510 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1513 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1514 MLX5_L3_PROT_TYPE_IPV4);
1515 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1517 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1518 MLX5_L3_PROT_TYPE_IPV6);
1519
1520 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1521 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1522 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1523 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1524 err = -EINVAL;
1525 goto err;
1526 }
1527
1528 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1529 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1530 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1531 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1532 MLX5_L4_PROT_TYPE_TCP);
1533 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1534 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1535 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1536 MLX5_L4_PROT_TYPE_UDP);
1537
1538 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1540 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1541
1542 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1544 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1545
1546 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1548 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1549
1550 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1552 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1553
1554 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1555
1556create_tir:
1557 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1558
1559 if (err)
1560 goto err;
1561
1562 kvfree(in);
1563 /* qpn is reserved for that QP */
1564 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1565 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1566 return 0;
1567
1568err:
1569 kvfree(in);
1570 return err;
1571}
1572
e126ba97
EC		 1573static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1574 struct ib_qp_init_attr *init_attr,
1575 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1576{
1577 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1578 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1579 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1580 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1581 struct mlx5_ib_cq *send_cq;
1582 struct mlx5_ib_cq *recv_cq;
1583 unsigned long flags;
cfb5e088 1584 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1585 struct mlx5_ib_create_qp ucmd;
1586 struct mlx5_ib_qp_base *base;
e7b169f3 1587 int mlx5_st;
cfb5e088 1588 void *qpc;
09a7d9ec
SM		 1589 u32 *in;
1590 int err;
e126ba97
EC		 1591
1592 mutex_init(&qp->mutex);
1593 spin_lock_init(&qp->sq.lock);
1594 spin_lock_init(&qp->rq.lock);
1595
e7b169f3
NO		 1596 mlx5_st = to_mlx5_st(init_attr->qp_type);
1597 if (mlx5_st < 0)
1598 return -EINVAL;
1599
28d61370
YH		 1600 if (init_attr->rwq_ind_tbl) {
1601 if (!udata)
1602 return -ENOSYS;
1603
1604 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1605 return err;
1606 }
1607
f360d88a 1608 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1609 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1610 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1611 return -EINVAL;
1612 } else {
1613 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1614 }
1615 }
1616
051f2630
LR		 1617 if (init_attr->create_flags &
1618 (IB_QP_CREATE_CROSS_CHANNEL |
1619 IB_QP_CREATE_MANAGED_SEND |
1620 IB_QP_CREATE_MANAGED_RECV)) {
1621 if (!MLX5_CAP_GEN(mdev, cd)) {
1622 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1623 return -EINVAL;
1624 }
1625 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1626 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1627 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1628 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1629 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1630 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1631 }
f0313965
ES		 1632
1633 if (init_attr->qp_type == IB_QPT_UD &&
1634 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1635 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1636 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1637 return -EOPNOTSUPP;
1638 }
1639
358e42ea
MD		 1640 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1641 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1642 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1643 return -EOPNOTSUPP;
1644 }
1645 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1646 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1647 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1648 return -EOPNOTSUPP;
1649 }
1650 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1651 }
1652
e126ba97
EC		 1653 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1654 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1655
e4cc4fa7
NO		 1656 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1657 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1658 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1659 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1660 return -EOPNOTSUPP;
1661 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1662 }
1663
e126ba97
EC		 1664 if (pd && pd->uobject) {
1665 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1666 mlx5_ib_dbg(dev, "copy failed\n");
1667 return -EFAULT;
1668 }
1669
cfb5e088
HA		 1670 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1671 &ucmd, udata->inlen, &uidx);
1672 if (err)
1673 return err;
1674
e126ba97
EC		 1675 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1676 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1677 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1678 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1679 !tunnel_offload_supported(mdev)) {
1680 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1681 return -EOPNOTSUPP;
1682 }
1683 qp->tunnel_offload_en = true;
1684 }
c2e53b2c
YH		 1685
1686 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1687 if (init_attr->qp_type != IB_QPT_UD ||
1688 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1689 MLX5_CAP_PORT_TYPE_IB) ||
1690 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1691 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1692 return -EOPNOTSUPP;
1693 }
1694
1695 qp->flags |= MLX5_IB_QP_UNDERLAY;
1696 qp->underlay_qpn = init_attr->source_qpn;
1697 }
e126ba97
EC		 1698 } else {
1699 qp->wq_sig = !!wq_signature;
1700 }
1701
c2e53b2c
YH		 1702 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1703 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1704 &qp->raw_packet_qp.rq.base :
1705 &qp->trans_qp.base;
1706
e126ba97
EC		 1707 qp->has_rq = qp_has_rq(init_attr);
1708 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1709 qp, (pd && pd->uobject) ? &ucmd : NULL);
1710 if (err) {
1711 mlx5_ib_dbg(dev, "err %d\n", err);
1712 return err;
1713 }
1714
1715 if (pd) {
1716 if (pd->uobject) {
938fe83c
SM		 1717 __u32 max_wqes =
1718 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1719 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1720 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1721 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1722 mlx5_ib_dbg(dev, "invalid rq params\n");
1723 return -EINVAL;
1724 }
938fe83c 1725 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1726 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1727 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1728 return -EINVAL;
1729 }
b11a4f9c
HE		 1730 if (init_attr->create_flags &
1731 mlx5_ib_create_qp_sqpn_qp1()) {
1732 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1733 return -EINVAL;
1734 }
0fb2ed66 1735 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1736 &resp, &inlen, base);
e126ba97
EC		 1737 if (err)
1738 mlx5_ib_dbg(dev, "err %d\n", err);
1739 } else {
19098df2 1740 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1741 base);
e126ba97
EC		 1742 if (err)
1743 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1744 }
1745
1746 if (err)
1747 return err;
1748 } else {
1b9a07ee 1749 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1750 if (!in)
1751 return -ENOMEM;
1752
1753 qp->create_type = MLX5_QP_EMPTY;
1754 }
1755
1756 if (is_sqp(init_attr->qp_type))
1757 qp->port = init_attr->port_num;
1758
09a7d9ec
SM		 1759 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1760
e7b169f3 1761 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1762 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1763
1764 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1765 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1766 else
09a7d9ec
SM		 1767 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1768
e126ba97
EC		 1769
1770 if (qp->wq_sig)
09a7d9ec 1771 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1772
f360d88a 1773 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1774 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1775
051f2630 1776 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1777 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1778 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1779 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1780 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1781 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1782
e126ba97
EC		 1783 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1784 int rcqe_sz;
1785 int scqe_sz;
1786
1787 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1788 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1789
1790 if (rcqe_sz == 128)
09a7d9ec 1791 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1792 else
09a7d9ec 1793 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1794
1795 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1796 if (scqe_sz == 128)
09a7d9ec 1797 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1798 else
09a7d9ec 1799 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1800 }
1801 }
1802
1803 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1804 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1805 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1806 }
1807
09a7d9ec 1808 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1809
3fd3307e 1810 if (qp->sq.wqe_cnt) {
09a7d9ec 1811 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1812 } else {
09a7d9ec 1813 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1814 if (init_attr->srq &&
1815 init_attr->srq->srq_type == IB_SRQT_TM)
1816 MLX5_SET(qpc, qpc, offload_type,
1817 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1818 }
e126ba97
EC		 1819
1820 /* Set default resources */
1821 switch (init_attr->qp_type) {
1822 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1823 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1824 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1825 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1826 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1827 break;
1828 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1829 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1830 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1831 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1832 break;
1833 default:
1834 if (init_attr->srq) {
09a7d9ec
SM		 1835 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1836 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1837 } else {
09a7d9ec
SM		 1838 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1839 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1840 }
1841 }
1842
1843 if (init_attr->send_cq)
09a7d9ec 1844 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1845
1846 if (init_attr->recv_cq)
09a7d9ec 1847 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1848
09a7d9ec 1849 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1850
09a7d9ec
SM		 1851 /* 0xffffff means we ask to work with cqe version 0 */
1852 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1853 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1854
f0313965
ES		 1855 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1856 if (init_attr->qp_type == IB_QPT_UD &&
1857 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1858 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1859 qp->flags |= MLX5_IB_QP_LSO;
1860 }
cfb5e088 1861
b1383aa6
NO		 1862 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1863 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1864 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1865 err = -EOPNOTSUPP;
1866 goto err;
1867 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1868 MLX5_SET(qpc, qpc, end_padding_mode,
1869 MLX5_WQ_END_PAD_MODE_ALIGN);
1870 } else {
1871 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1872 }
1873 }
1874
c2e53b2c
YH		 1875 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1876 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1877 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1878 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1879 err = create_raw_packet_qp(dev, qp, in, pd);
1880 } else {
1881 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1882 }
1883
e126ba97
EC		 1884 if (err) {
1885 mlx5_ib_dbg(dev, "create qp failed\n");
1886 goto err_create;
1887 }
1888
479163f4 1889 kvfree(in);
e126ba97 1890
19098df2 1891 base->container_mibqp = qp;
1892 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1893
89ea94a7
MG		 1894 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1895 &send_cq, &recv_cq);
1896 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1897 mlx5_ib_lock_cqs(send_cq, recv_cq);
1898 /* Maintain device to QPs access, needed for further handling via reset
1899 * flow
1900 */
1901 list_add_tail(&qp->qps_list, &dev->qp_list);
1902 /* Maintain CQ to QPs access, needed for further handling via reset flow
1903 */
1904 if (send_cq)
1905 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1906 if (recv_cq)
1907 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1908 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1909 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1910
e126ba97
EC		 1911 return 0;
1912
1913err_create:
1914 if (qp->create_type == MLX5_QP_USER)
b037c29a 1915 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1916 else if (qp->create_type == MLX5_QP_KERNEL)
1917 destroy_qp_kernel(dev, qp);
1918
b1383aa6 1919err:
479163f4 1920 kvfree(in);
e126ba97
EC		 1921 return err;
1922}
1923
1924static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1925 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1926{
1927 if (send_cq) {
1928 if (recv_cq) {
1929 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1930 spin_lock(&send_cq->lock);
e126ba97
EC		 1931 spin_lock_nested(&recv_cq->lock,
1932 SINGLE_DEPTH_NESTING);
1933 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1934 spin_lock(&send_cq->lock);
e126ba97
EC		 1935 __acquire(&recv_cq->lock);
1936 } else {
89ea94a7 1937 spin_lock(&recv_cq->lock);
e126ba97
EC		 1938 spin_lock_nested(&send_cq->lock,
1939 SINGLE_DEPTH_NESTING);
1940 }
1941 } else {
89ea94a7 1942 spin_lock(&send_cq->lock);
6a4f139a 1943 __acquire(&recv_cq->lock);
e126ba97
EC		 1944 }
1945 } else if (recv_cq) {
89ea94a7 1946 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1947 __acquire(&send_cq->lock);
1948 } else {
1949 __acquire(&send_cq->lock);
1950 __acquire(&recv_cq->lock);
e126ba97
EC		 1951 }
1952}
1953
1954static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1955 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1956{
1957 if (send_cq) {
1958 if (recv_cq) {
1959 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1960 spin_unlock(&recv_cq->lock);
89ea94a7 1961 spin_unlock(&send_cq->lock);
e126ba97
EC		 1962 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1963 __release(&recv_cq->lock);
89ea94a7 1964 spin_unlock(&send_cq->lock);
e126ba97
EC		 1965 } else {
1966 spin_unlock(&send_cq->lock);
89ea94a7 1967 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1968 }
1969 } else {
6a4f139a 1970 __release(&recv_cq->lock);
89ea94a7 1971 spin_unlock(&send_cq->lock);
e126ba97
EC		 1972 }
1973 } else if (recv_cq) {
6a4f139a 1974 __release(&send_cq->lock);
89ea94a7 1975 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1976 } else {
1977 __release(&recv_cq->lock);
1978 __release(&send_cq->lock);
e126ba97
EC		 1979 }
1980}
1981
1982static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1983{
1984 return to_mpd(qp->ibqp.pd);
1985}
1986
89ea94a7
MG		 1987static void get_cqs(enum ib_qp_type qp_type,
1988 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1989 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1990{
89ea94a7 1991 switch (qp_type) {
e126ba97
EC		 1992 case IB_QPT_XRC_TGT:
1993 *send_cq = NULL;
1994 *recv_cq = NULL;
1995 break;
1996 case MLX5_IB_QPT_REG_UMR:
1997 case IB_QPT_XRC_INI:
89ea94a7 1998 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1999 *recv_cq = NULL;
2000 break;
2001
2002 case IB_QPT_SMI:
d16e91da 2003 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2004 case IB_QPT_RC:
2005 case IB_QPT_UC:
2006 case IB_QPT_UD:
2007 case IB_QPT_RAW_IPV6:
2008 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2009 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2010 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2011 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2012 break;
2013
e126ba97
EC		 2014 case IB_QPT_MAX:
2015 default:
2016 *send_cq = NULL;
2017 *recv_cq = NULL;
2018 break;
2019 }
2020}
2021
ad5f8e96 2022static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2023 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2024 u8 lag_tx_affinity);
ad5f8e96 2025
e126ba97
EC		 2026static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2027{
2028 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2029 struct mlx5_ib_qp_base *base;
89ea94a7 2030 unsigned long flags;
e126ba97
EC		 2031 int err;
2032
28d61370
YH		 2033 if (qp->ibqp.rwq_ind_tbl) {
2034 destroy_rss_raw_qp_tir(dev, qp);
2035 return;
2036 }
2037
c2e53b2c
YH		 2038 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2039 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2040 &qp->raw_packet_qp.rq.base :
2041 &qp->trans_qp.base;
2042
6aec21f6 2043 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2044 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2045 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2046 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2047 MLX5_CMD_OP_2RST_QP, 0,
2048 NULL, &base->mqp);
ad5f8e96 2049 } else {
0680efa2
AV		 2050 struct mlx5_modify_raw_qp_param raw_qp_param = {
2051 .operation = MLX5_CMD_OP_2RST_QP
2052 };
2053
13eab21f 2054 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2055 }
2056 if (err)
427c1e7b 2057 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2058 base->mqp.qpn);
6aec21f6 2059 }
e126ba97 2060
89ea94a7
MG		 2061 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2062 &send_cq, &recv_cq);
2063
2064 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2065 mlx5_ib_lock_cqs(send_cq, recv_cq);
2066 /* del from lists under both locks above to protect reset flow paths */
2067 list_del(&qp->qps_list);
2068 if (send_cq)
2069 list_del(&qp->cq_send_list);
2070
2071 if (recv_cq)
2072 list_del(&qp->cq_recv_list);
e126ba97
EC		 2073
2074 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2075 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2076 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2077 if (send_cq != recv_cq)
19098df2 2078 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2079 NULL);
e126ba97 2080 }
89ea94a7
MG		 2081 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2082 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2083
c2e53b2c
YH		 2084 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2085 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2086 destroy_raw_packet_qp(dev, qp);
2087 } else {
2088 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2089 if (err)
2090 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2091 base->mqp.qpn);
2092 }
e126ba97 2093
e126ba97
EC		 2094 if (qp->create_type == MLX5_QP_KERNEL)
2095 destroy_qp_kernel(dev, qp);
2096 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2097 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2098}
2099
2100static const char *ib_qp_type_str(enum ib_qp_type type)
2101{
2102 switch (type) {
2103 case IB_QPT_SMI:
2104 return "IB_QPT_SMI";
2105 case IB_QPT_GSI:
2106 return "IB_QPT_GSI";
2107 case IB_QPT_RC:
2108 return "IB_QPT_RC";
2109 case IB_QPT_UC:
2110 return "IB_QPT_UC";
2111 case IB_QPT_UD:
2112 return "IB_QPT_UD";
2113 case IB_QPT_RAW_IPV6:
2114 return "IB_QPT_RAW_IPV6";
2115 case IB_QPT_RAW_ETHERTYPE:
2116 return "IB_QPT_RAW_ETHERTYPE";
2117 case IB_QPT_XRC_INI:
2118 return "IB_QPT_XRC_INI";
2119 case IB_QPT_XRC_TGT:
2120 return "IB_QPT_XRC_TGT";
2121 case IB_QPT_RAW_PACKET:
2122 return "IB_QPT_RAW_PACKET";
2123 case MLX5_IB_QPT_REG_UMR:
2124 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2125 case IB_QPT_DRIVER:
2126 return "IB_QPT_DRIVER";
e126ba97
EC		 2127 case IB_QPT_MAX:
2128 default:
2129 return "Invalid QP type";
2130 }
2131}
2132
b4aaa1f0
MS		 2133static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2134 struct ib_qp_init_attr *attr,
2135 struct mlx5_ib_create_qp *ucmd)
2136{
2137 struct mlx5_ib_dev *dev;
2138 struct mlx5_ib_qp *qp;
2139 int err = 0;
2140 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2141 void *dctc;
2142
2143 if (!attr->srq || !attr->recv_cq)
2144 return ERR_PTR(-EINVAL);
2145
2146 dev = to_mdev(pd->device);
2147
2148 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2149 ucmd, sizeof(*ucmd), &uidx);
2150 if (err)
2151 return ERR_PTR(err);
2152
2153 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2154 if (!qp)
2155 return ERR_PTR(-ENOMEM);
2156
2157 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2158 if (!qp->dct.in) {
2159 err = -ENOMEM;
2160 goto err_free;
2161 }
2162
2163 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2164 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2165 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2166 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2167 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2168 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2169 MLX5_SET(dctc, dctc, user_index, uidx);
2170
2171 qp->state = IB_QPS_RESET;
2172
2173 return &qp->ibqp;
2174err_free:
2175 kfree(qp);
2176 return ERR_PTR(err);
2177}
2178
2179static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2180 struct ib_qp_init_attr *init_attr,
2181 struct mlx5_ib_create_qp *ucmd,
2182 struct ib_udata *udata)
2183{
2184 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2185 int err;
2186
2187 if (!udata)
2188 return -EINVAL;
2189
2190 if (udata->inlen < sizeof(*ucmd)) {
2191 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2192 return -EINVAL;
2193 }
2194 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2195 if (err)
2196 return err;
2197
2198 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2199 init_attr->qp_type = MLX5_IB_QPT_DCI;
2200 } else {
2201 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2202 init_attr->qp_type = MLX5_IB_QPT_DCT;
2203 } else {
2204 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2205 return -EINVAL;
2206 }
2207 }
2208
2209 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2210 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2211 return -EOPNOTSUPP;
2212 }
2213
2214 return 0;
2215}
2216
e126ba97 2217struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2218 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2219 struct ib_udata *udata)
2220{
2221 struct mlx5_ib_dev *dev;
2222 struct mlx5_ib_qp *qp;
2223 u16 xrcdn = 0;
2224 int err;
b4aaa1f0
MS		 2225 struct ib_qp_init_attr mlx_init_attr;
2226 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2227
2228 if (pd) {
2229 dev = to_mdev(pd->device);
0fb2ed66 2230
2231 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2232 if (!pd->uobject) {
2233 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2234 return ERR_PTR(-EINVAL);
2235 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2236 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2237 return ERR_PTR(-EINVAL);
2238 }
2239 }
09f16cf5
MD		 2240 } else {
2241 /* being cautious here */
2242 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2243 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2244 pr_warn("%s: no PD for transport %s\n", __func__,
2245 ib_qp_type_str(init_attr->qp_type));
2246 return ERR_PTR(-EINVAL);
2247 }
2248 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2249 }
2250
b4aaa1f0
MS		 2251 if (init_attr->qp_type == IB_QPT_DRIVER) {
2252 struct mlx5_ib_create_qp ucmd;
2253
2254 init_attr = &mlx_init_attr;
2255 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2256 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2257 if (err)
2258 return ERR_PTR(err);
c32a4f29
MS		 2259
2260 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2261 if (init_attr->cap.max_recv_wr ||
2262 init_attr->cap.max_recv_sge) {
2263 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2264 return ERR_PTR(-EINVAL);
2265 }
776a3906
MS		 2266 } else {
2267 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2268 }
b4aaa1f0
MS		 2269 }
2270
e126ba97
EC		 2271 switch (init_attr->qp_type) {
2272 case IB_QPT_XRC_TGT:
2273 case IB_QPT_XRC_INI:
938fe83c 2274 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2275 mlx5_ib_dbg(dev, "XRC not supported\n");
2276 return ERR_PTR(-ENOSYS);
2277 }
2278 init_attr->recv_cq = NULL;
2279 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2280 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2281 init_attr->send_cq = NULL;
2282 }
2283
2284 /* fall through */
0fb2ed66 2285 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2286 case IB_QPT_RC:
2287 case IB_QPT_UC:
2288 case IB_QPT_UD:
2289 case IB_QPT_SMI:
d16e91da 2290 case MLX5_IB_QPT_HW_GSI:
e126ba97 2291 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2292 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2293 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2294 if (!qp)
2295 return ERR_PTR(-ENOMEM);
2296
2297 err = create_qp_common(dev, pd, init_attr, udata, qp);
2298 if (err) {
2299 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2300 kfree(qp);
2301 return ERR_PTR(err);
2302 }
2303
2304 if (is_qp0(init_attr->qp_type))
2305 qp->ibqp.qp_num = 0;
2306 else if (is_qp1(init_attr->qp_type))
2307 qp->ibqp.qp_num = 1;
2308 else
19098df2 2309 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2310
2311 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2312 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2313 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2314 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2315
19098df2 2316 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2317
2318 break;
2319
d16e91da
HE		 2320 case IB_QPT_GSI:
2321 return mlx5_ib_gsi_create_qp(pd, init_attr);
2322
e126ba97
EC		 2323 case IB_QPT_RAW_IPV6:
2324 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2325 case IB_QPT_MAX:
2326 default:
2327 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2328 init_attr->qp_type);
2329 /* Don't support raw QPs */
2330 return ERR_PTR(-EINVAL);
2331 }
2332
b4aaa1f0
MS		 2333 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2334 qp->qp_sub_type = init_attr->qp_type;
2335
e126ba97
EC		 2336 return &qp->ibqp;
2337}
2338
776a3906
MS		 2339static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2340{
2341 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2342
2343 if (mqp->state == IB_QPS_RTR) {
2344 int err;
2345
2346 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2347 if (err) {
2348 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2349 return err;
2350 }
2351 }
2352
2353 kfree(mqp->dct.in);
2354 kfree(mqp);
2355 return 0;
2356}
2357
e126ba97
EC		 2358int mlx5_ib_destroy_qp(struct ib_qp *qp)
2359{
2360 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2361 struct mlx5_ib_qp *mqp = to_mqp(qp);
2362
d16e91da
HE		 2363 if (unlikely(qp->qp_type == IB_QPT_GSI))
2364 return mlx5_ib_gsi_destroy_qp(qp);
2365
776a3906
MS		 2366 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2367 return mlx5_ib_destroy_dct(mqp);
2368
e126ba97
EC		 2369 destroy_qp_common(dev, mqp);
2370
2371 kfree(mqp);
2372
2373 return 0;
2374}
2375
2376static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2377 int attr_mask)
2378{
2379 u32 hw_access_flags = 0;
2380 u8 dest_rd_atomic;
2381 u32 access_flags;
2382
2383 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2384 dest_rd_atomic = attr->max_dest_rd_atomic;
2385 else
19098df2 2386 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2387
2388 if (attr_mask & IB_QP_ACCESS_FLAGS)
2389 access_flags = attr->qp_access_flags;
2390 else
19098df2 2391 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2392
2393 if (!dest_rd_atomic)
2394 access_flags &= IB_ACCESS_REMOTE_WRITE;
2395
2396 if (access_flags & IB_ACCESS_REMOTE_READ)
2397 hw_access_flags |= MLX5_QP_BIT_RRE;
2398 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2399 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2400 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2401 hw_access_flags |= MLX5_QP_BIT_RWE;
2402
2403 return cpu_to_be32(hw_access_flags);
2404}
2405
2406enum {
2407 MLX5_PATH_FLAG_FL = 1 << 0,
2408 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2409 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2410};
2411
2412static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2413{
2414 if (rate == IB_RATE_PORT_CURRENT) {
2415 return 0;
2416 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2417 return -EINVAL;
2418 } else {
2419 while (rate != IB_RATE_2_5_GBPS &&
2420 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2421 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2422 --rate;
2423 }
2424
2425 return rate + MLX5_STAT_RATE_OFFSET;
2426}
2427
75850d0b 2428static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2429 struct mlx5_ib_sq *sq, u8 sl)
2430{
2431 void *in;
2432 void *tisc;
2433 int inlen;
2434 int err;
2435
2436 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2437 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2438 if (!in)
2439 return -ENOMEM;
2440
2441 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2442
2443 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2444 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2445
2446 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2447
2448 kvfree(in);
2449
2450 return err;
2451}
2452
13eab21f
AH		 2453static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2454 struct mlx5_ib_sq *sq, u8 tx_affinity)
2455{
2456 void *in;
2457 void *tisc;
2458 int inlen;
2459 int err;
2460
2461 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2462 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2463 if (!in)
2464 return -ENOMEM;
2465
2466 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2467
2468 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2469 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2470
2471 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2472
2473 kvfree(in);
2474
2475 return err;
2476}
2477
75850d0b 2478static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2479 const struct rdma_ah_attr *ah,
e126ba97 2480 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2481 u32 path_flags, const struct ib_qp_attr *attr,
2482 bool alt)
e126ba97 2483{
d8966fcd 2484 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2485 int err;
ed88451e 2486 enum ib_gid_type gid_type;
d8966fcd
DC		 2487 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2488 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2489
e126ba97 2490 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2491 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2492 attr->pkey_index);
e126ba97 2493
d8966fcd
DC		 2494 if (ah_flags & IB_AH_GRH) {
2495 if (grh->sgid_index >=
938fe83c 2496 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2497 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2498 grh->sgid_index,
938fe83c 2499 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2500 return -EINVAL;
2501 }
2811ba51 2502 }
44c58487
DC		 2503
2504 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2505 if (!(ah_flags & IB_AH_GRH))
2811ba51 2506 return -EINVAL;
d8966fcd 2507 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2508 &gid_type);
2509 if (err)
2510 return err;
44c58487 2511 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2512 if (qp->ibqp.qp_type == IB_QPT_RC ||
2513 qp->ibqp.qp_type == IB_QPT_UC ||
2514 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2515 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2516 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2517 grh->sgid_index);
d8966fcd 2518 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2519 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2520 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2521 } else {
d3ae2bde
NO		 2522 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2523 path->fl_free_ar |=
2524 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2525 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2526 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2527 if (ah_flags & IB_AH_GRH)
2811ba51 2528 path->grh_mlid |= 1 << 7;
d8966fcd 2529 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2530 }
2531
d8966fcd
DC		 2532 if (ah_flags & IB_AH_GRH) {
2533 path->mgid_index = grh->sgid_index;
2534 path->hop_limit = grh->hop_limit;
e126ba97 2535 path->tclass_flowlabel =
d8966fcd
DC		 2536 cpu_to_be32((grh->traffic_class << 20) |
2537 (grh->flow_label));
2538 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2539 }
2540
d8966fcd 2541 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2542 if (err < 0)
2543 return err;
2544 path->static_rate = err;
2545 path->port = port;
2546
e126ba97 2547 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2548 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2549
75850d0b 2550 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2551 return modify_raw_packet_eth_prio(dev->mdev,
2552 &qp->raw_packet_qp.sq,
d8966fcd 2553 sl & 0xf);
75850d0b 2554
e126ba97
EC		 2555 return 0;
2556}
2557
2558static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2559 [MLX5_QP_STATE_INIT] = {
2560 [MLX5_QP_STATE_INIT] = {
2561 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2562 MLX5_QP_OPTPAR_RAE |
2563 MLX5_QP_OPTPAR_RWE |
2564 MLX5_QP_OPTPAR_PKEY_INDEX |
2565 MLX5_QP_OPTPAR_PRI_PORT,
2566 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2567 MLX5_QP_OPTPAR_PKEY_INDEX |
2568 MLX5_QP_OPTPAR_PRI_PORT,
2569 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2570 MLX5_QP_OPTPAR_Q_KEY |
2571 MLX5_QP_OPTPAR_PRI_PORT,
2572 },
2573 [MLX5_QP_STATE_RTR] = {
2574 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2575 MLX5_QP_OPTPAR_RRE |
2576 MLX5_QP_OPTPAR_RAE |
2577 MLX5_QP_OPTPAR_RWE |
2578 MLX5_QP_OPTPAR_PKEY_INDEX,
2579 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2580 MLX5_QP_OPTPAR_RWE |
2581 MLX5_QP_OPTPAR_PKEY_INDEX,
2582 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2583 MLX5_QP_OPTPAR_Q_KEY,
2584 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2585 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2586 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2587 MLX5_QP_OPTPAR_RRE |
2588 MLX5_QP_OPTPAR_RAE |
2589 MLX5_QP_OPTPAR_RWE |
2590 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2591 },
2592 },
2593 [MLX5_QP_STATE_RTR] = {
2594 [MLX5_QP_STATE_RTS] = {
2595 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2596 MLX5_QP_OPTPAR_RRE |
2597 MLX5_QP_OPTPAR_RAE |
2598 MLX5_QP_OPTPAR_RWE |
2599 MLX5_QP_OPTPAR_PM_STATE |
2600 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2601 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2602 MLX5_QP_OPTPAR_RWE |
2603 MLX5_QP_OPTPAR_PM_STATE,
2604 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2605 },
2606 },
2607 [MLX5_QP_STATE_RTS] = {
2608 [MLX5_QP_STATE_RTS] = {
2609 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2610 MLX5_QP_OPTPAR_RAE |
2611 MLX5_QP_OPTPAR_RWE |
2612 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2613 MLX5_QP_OPTPAR_PM_STATE |
2614 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2615 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2616 MLX5_QP_OPTPAR_PM_STATE |
2617 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2618 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2619 MLX5_QP_OPTPAR_SRQN |
2620 MLX5_QP_OPTPAR_CQN_RCV,
2621 },
2622 },
2623 [MLX5_QP_STATE_SQER] = {
2624 [MLX5_QP_STATE_RTS] = {
2625 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2626 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2627 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2628 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2629 MLX5_QP_OPTPAR_RWE |
2630 MLX5_QP_OPTPAR_RAE |
2631 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2632 },
2633 },
2634};
2635
2636static int ib_nr_to_mlx5_nr(int ib_mask)
2637{
2638 switch (ib_mask) {
2639 case IB_QP_STATE:
2640 return 0;
2641 case IB_QP_CUR_STATE:
2642 return 0;
2643 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2644 return 0;
2645 case IB_QP_ACCESS_FLAGS:
2646 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2647 MLX5_QP_OPTPAR_RAE;
2648 case IB_QP_PKEY_INDEX:
2649 return MLX5_QP_OPTPAR_PKEY_INDEX;
2650 case IB_QP_PORT:
2651 return MLX5_QP_OPTPAR_PRI_PORT;
2652 case IB_QP_QKEY:
2653 return MLX5_QP_OPTPAR_Q_KEY;
2654 case IB_QP_AV:
2655 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2656 MLX5_QP_OPTPAR_PRI_PORT;
2657 case IB_QP_PATH_MTU:
2658 return 0;
2659 case IB_QP_TIMEOUT:
2660 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2661 case IB_QP_RETRY_CNT:
2662 return MLX5_QP_OPTPAR_RETRY_COUNT;
2663 case IB_QP_RNR_RETRY:
2664 return MLX5_QP_OPTPAR_RNR_RETRY;
2665 case IB_QP_RQ_PSN:
2666 return 0;
2667 case IB_QP_MAX_QP_RD_ATOMIC:
2668 return MLX5_QP_OPTPAR_SRA_MAX;
2669 case IB_QP_ALT_PATH:
2670 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2671 case IB_QP_MIN_RNR_TIMER:
2672 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2673 case IB_QP_SQ_PSN:
2674 return 0;
2675 case IB_QP_MAX_DEST_RD_ATOMIC:
2676 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2677 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2678 case IB_QP_PATH_MIG_STATE:
2679 return MLX5_QP_OPTPAR_PM_STATE;
2680 case IB_QP_CAP:
2681 return 0;
2682 case IB_QP_DEST_QPN:
2683 return 0;
2684 }
2685 return 0;
2686}
2687
2688static int ib_mask_to_mlx5_opt(int ib_mask)
2689{
2690 int result = 0;
2691 int i;
2692
2693 for (i = 0; i < 8 * sizeof(int); i++) {
2694 if ((1 << i) & ib_mask)
2695 result |= ib_nr_to_mlx5_nr(1 << i);
2696 }
2697
2698 return result;
2699}
2700
eb49ab0c
AV		 2701static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2702 struct mlx5_ib_rq *rq, int new_state,
2703 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2704{
2705 void *in;
2706 void *rqc;
2707 int inlen;
2708 int err;
2709
2710 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2711 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2712 if (!in)
2713 return -ENOMEM;
2714
2715 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2716
2717 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2718 MLX5_SET(rqc, rqc, state, new_state);
2719
eb49ab0c
AV		 2720 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2721 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2722 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2723 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2724 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2725 } else
2726 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2727 dev->ib_dev.name);
2728 }
2729
2730 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2731 if (err)
2732 goto out;
2733
2734 rq->state = new_state;
2735
2736out:
2737 kvfree(in);
2738 return err;
2739}
2740
2741static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2742 struct mlx5_ib_sq *sq,
2743 int new_state,
2744 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2745{
7d29f349
BW		 2746 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2747 u32 old_rate = ibqp->rate_limit;
2748 u32 new_rate = old_rate;
2749 u16 rl_index = 0;
ad5f8e96 2750 void *in;
2751 void *sqc;
2752 int inlen;
2753 int err;
2754
2755 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2756 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2757 if (!in)
2758 return -ENOMEM;
2759
2760 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2761
2762 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2763 MLX5_SET(sqc, sqc, state, new_state);
2764
7d29f349
BW		 2765 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2766 if (new_state != MLX5_SQC_STATE_RDY)
2767 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2768 __func__);
2769 else
2770 new_rate = raw_qp_param->rate_limit;
2771 }
2772
2773 if (old_rate != new_rate) {
2774 if (new_rate) {
2775 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2776 if (err) {
2777 pr_err("Failed configuring rate %u: %d\n",
2778 new_rate, err);
2779 goto out;
2780 }
2781 }
2782
2783 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2784 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2785 }
2786
ad5f8e96 2787 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2788 if (err) {
2789 /* Remove new rate from table if failed */
2790 if (new_rate &&
2791 old_rate != new_rate)
2792 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2793 goto out;
7d29f349
BW		 2794 }
2795
2796 /* Only remove the old rate after new rate was set */
2797 if ((old_rate &&
2798 (old_rate != new_rate)) ||
2799 (new_state != MLX5_SQC_STATE_RDY))
2800 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2801
7d29f349 2802 ibqp->rate_limit = new_rate;
ad5f8e96 2803 sq->state = new_state;
2804
2805out:
2806 kvfree(in);
2807 return err;
2808}
2809
2810static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2811 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2812 u8 tx_affinity)
ad5f8e96 2813{
2814 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2815 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2816 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2817 int modify_rq = !!qp->rq.wqe_cnt;
2818 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2819 int rq_state;
2820 int sq_state;
2821 int err;
2822
0680efa2 2823 switch (raw_qp_param->operation) {
ad5f8e96 2824 case MLX5_CMD_OP_RST2INIT_QP:
2825 rq_state = MLX5_RQC_STATE_RDY;
2826 sq_state = MLX5_SQC_STATE_RDY;
2827 break;
2828 case MLX5_CMD_OP_2ERR_QP:
2829 rq_state = MLX5_RQC_STATE_ERR;
2830 sq_state = MLX5_SQC_STATE_ERR;
2831 break;
2832 case MLX5_CMD_OP_2RST_QP:
2833 rq_state = MLX5_RQC_STATE_RST;
2834 sq_state = MLX5_SQC_STATE_RST;
2835 break;
ad5f8e96 2836 case MLX5_CMD_OP_RTR2RTS_QP:
2837 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2838 if (raw_qp_param->set_mask ==
2839 MLX5_RAW_QP_RATE_LIMIT) {
2840 modify_rq = 0;
2841 sq_state = sq->state;
2842 } else {
2843 return raw_qp_param->set_mask ? -EINVAL : 0;
2844 }
2845 break;
2846 case MLX5_CMD_OP_INIT2INIT_QP:
2847 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2848 if (raw_qp_param->set_mask)
2849 return -EINVAL;
2850 else
2851 return 0;
ad5f8e96 2852 default:
2853 WARN_ON(1);
2854 return -EINVAL;
2855 }
2856
7d29f349
BW		 2857 if (modify_rq) {
2858 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2859 if (err)
2860 return err;
2861 }
2862
7d29f349 2863 if (modify_sq) {
13eab21f
AH		 2864 if (tx_affinity) {
2865 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2866 tx_affinity);
2867 if (err)
2868 return err;
2869 }
2870
7d29f349 2871 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2872 }
ad5f8e96 2873
2874 return 0;
2875}
2876
e126ba97
EC		 2877static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2878 const struct ib_qp_attr *attr, int attr_mask,
2879 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2880{
427c1e7b 2881 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2882 [MLX5_QP_STATE_RST] = {
2883 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2884 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2885 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2886 },
2887 [MLX5_QP_STATE_INIT] = {
2888 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2889 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2890 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2891 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2892 },
2893 [MLX5_QP_STATE_RTR] = {
2894 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2895 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2896 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2897 },
2898 [MLX5_QP_STATE_RTS] = {
2899 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2900 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2901 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2902 },
2903 [MLX5_QP_STATE_SQD] = {
2904 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2905 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2906 },
2907 [MLX5_QP_STATE_SQER] = {
2908 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2909 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2910 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2911 },
2912 [MLX5_QP_STATE_ERR] = {
2913 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2914 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2915 }
2916 };
2917
e126ba97
EC		 2918 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2919 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2920 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2921 struct mlx5_ib_cq *send_cq, *recv_cq;
2922 struct mlx5_qp_context *context;
e126ba97 2923 struct mlx5_ib_pd *pd;
eb49ab0c 2924 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2925 enum mlx5_qp_state mlx5_cur, mlx5_new;
2926 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2927 int mlx5_st;
2928 int err;
427c1e7b 2929 u16 op;
13eab21f 2930 u8 tx_affinity = 0;
e126ba97 2931
1a412fb1
SM		 2932 context = kzalloc(sizeof(*context), GFP_KERNEL);
2933 if (!context)
e126ba97
EC		 2934 return -ENOMEM;
2935
c32a4f29
MS		 2936 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2937 qp->qp_sub_type : ibqp->qp_type);
158abf86
HE		 2938 if (err < 0) {
2939 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2940 goto out;
158abf86 2941 }
e126ba97
EC		 2942
2943 context->flags = cpu_to_be32(err << 16);
2944
2945 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2946 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2947 } else {
2948 switch (attr->path_mig_state) {
2949 case IB_MIG_MIGRATED:
2950 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2951 break;
2952 case IB_MIG_REARM:
2953 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2954 break;
2955 case IB_MIG_ARMED:
2956 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2957 break;
2958 }
2959 }
2960
13eab21f
AH		 2961 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2962 if ((ibqp->qp_type == IB_QPT_RC) ||
2963 (ibqp->qp_type == IB_QPT_UD &&
2964 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2965 (ibqp->qp_type == IB_QPT_UC) ||
2966 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2967 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2968 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2969 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 2970 u8 p = mlx5_core_native_port_num(dev->mdev);
13eab21f 2971 tx_affinity = (unsigned int)atomic_add_return(1,
7fd8aefb 2972 &dev->roce[p].next_port) %
13eab21f
AH		 2973 MLX5_MAX_PORTS + 1;
2974 context->flags |= cpu_to_be32(tx_affinity << 24);
2975 }
2976 }
2977 }
2978
d16e91da 2979 if (is_sqp(ibqp->qp_type)) {
e126ba97 2980 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 2981 } else if ((ibqp->qp_type == IB_QPT_UD &&
2982 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 2983 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2984 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2985 } else if (attr_mask & IB_QP_PATH_MTU) {
2986 if (attr->path_mtu < IB_MTU_256 ||
2987 attr->path_mtu > IB_MTU_4096) {
2988 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2989 err = -EINVAL;
2990 goto out;
2991 }
938fe83c
SM		 2992 context->mtu_msgmax = (attr->path_mtu << 5) |
2993 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2994 }
2995
2996 if (attr_mask & IB_QP_DEST_QPN)
2997 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2998
2999 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3000 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3001
3002 /* todo implement counter_index functionality */
3003
3004 if (is_sqp(ibqp->qp_type))
3005 context->pri_path.port = qp->port;
3006
3007 if (attr_mask & IB_QP_PORT)
3008 context->pri_path.port = attr->port_num;
3009
3010 if (attr_mask & IB_QP_AV) {
75850d0b 3011 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3012 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3013 attr_mask, 0, attr, false);
e126ba97
EC		 3014 if (err)
3015 goto out;
3016 }
3017
3018 if (attr_mask & IB_QP_TIMEOUT)
3019 context->pri_path.ackto_lt |= attr->timeout << 3;
3020
3021 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3022 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3023 &context->alt_path,
f879ee8d
AS		 3024 attr->alt_port_num,
3025 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3026 0, attr, true);
e126ba97
EC		 3027 if (err)
3028 goto out;
3029 }
3030
3031 pd = get_pd(qp);
89ea94a7
MG		 3032 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3033 &send_cq, &recv_cq);
e126ba97
EC		 3034
3035 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3036 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3037 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3038 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3039
3040 if (attr_mask & IB_QP_RNR_RETRY)
3041 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3042
3043 if (attr_mask & IB_QP_RETRY_CNT)
3044 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3045
3046 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3047 if (attr->max_rd_atomic)
3048 context->params1 |=
3049 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3050 }
3051
3052 if (attr_mask & IB_QP_SQ_PSN)
3053 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3054
3055 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3056 if (attr->max_dest_rd_atomic)
3057 context->params2 |=
3058 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3059 }
3060
3061 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3062 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3063
3064 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3065 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3066
3067 if (attr_mask & IB_QP_RQ_PSN)
3068 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3069
3070 if (attr_mask & IB_QP_QKEY)
3071 context->qkey = cpu_to_be32(attr->qkey);
3072
3073 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3074 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3075
0837e86a
MB		 3076 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3077 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3078 qp->port) - 1;
c2e53b2c
YH		 3079
3080 /* Underlay port should be used - index 0 function per port */
3081 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3082 port_num = 0;
3083
eb49ab0c 3084 mibport = &dev->port[port_num];
0837e86a 3085 context->qp_counter_set_usr_page |=
e1f24a79 3086 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3087 }
3088
e126ba97
EC		 3089 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3090 context->sq_crq_size |= cpu_to_be16(1 << 4);
3091
b11a4f9c
HE		 3092 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3093 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3094
3095 mlx5_cur = to_mlx5_state(cur_state);
3096 mlx5_new = to_mlx5_state(new_state);
c32a4f29
MS		 3097 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3098 qp->qp_sub_type : ibqp->qp_type);
07c9113f 3099 if (mlx5_st < 0)
e126ba97
EC		 3100 goto out;
3101
427c1e7b 3102 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3103 !optab[mlx5_cur][mlx5_new]) {
3104 err = -EINVAL;
427c1e7b 3105 goto out;
5d414b17 3106 }
427c1e7b 3107
3108 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3109 optpar = ib_mask_to_mlx5_opt(attr_mask);
3110 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3111
c2e53b2c
YH		 3112 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3113 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3114 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3115
3116 raw_qp_param.operation = op;
eb49ab0c 3117 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3118 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3119 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3120 }
7d29f349
BW		 3121
3122 if (attr_mask & IB_QP_RATE_LIMIT) {
3123 raw_qp_param.rate_limit = attr->rate_limit;
3124 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3125 }
3126
13eab21f 3127 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3128 } else {
1a412fb1 3129 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3130 &base->mqp);
0680efa2
AV		 3131 }
3132
e126ba97
EC		 3133 if (err)
3134 goto out;
3135
3136 qp->state = new_state;
3137
3138 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3139 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3140 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3141 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3142 if (attr_mask & IB_QP_PORT)
3143 qp->port = attr->port_num;
3144 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3145 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3146
3147 /*
3148 * If we moved a kernel QP to RESET, clean up all old CQ
3149 * entries and reinitialize the QP.
3150 */
3151 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 3152 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3153 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3154 if (send_cq != recv_cq)
19098df2 3155 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3156
3157 qp->rq.head = 0;
3158 qp->rq.tail = 0;
3159 qp->sq.head = 0;
3160 qp->sq.tail = 0;
3161 qp->sq.cur_post = 0;
3162 qp->sq.last_poll = 0;
3163 qp->db.db[MLX5_RCV_DBR] = 0;
3164 qp->db.db[MLX5_SND_DBR] = 0;
3165 }
3166
3167out:
1a412fb1 3168 kfree(context);
e126ba97
EC		 3169 return err;
3170}
3171
c32a4f29
MS		 3172static inline bool is_valid_mask(int mask, int req, int opt)
3173{
3174 if ((mask & req) != req)
3175 return false;
3176
3177 if (mask & ~(req | opt))
3178 return false;
3179
3180 return true;
3181}
3182
3183/* check valid transition for driver QP types
3184 * for now the only QP type that this function supports is DCI
3185 */
3186static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3187 enum ib_qp_attr_mask attr_mask)
3188{
3189 int req = IB_QP_STATE;
3190 int opt = 0;
3191
3192 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3193 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3194 return is_valid_mask(attr_mask, req, opt);
3195 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3196 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3197 return is_valid_mask(attr_mask, req, opt);
3198 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3199 req |= IB_QP_PATH_MTU;
3200 opt = IB_QP_PKEY_INDEX;
3201 return is_valid_mask(attr_mask, req, opt);
3202 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3203 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3204 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3205 opt = IB_QP_MIN_RNR_TIMER;
3206 return is_valid_mask(attr_mask, req, opt);
3207 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3208 opt = IB_QP_MIN_RNR_TIMER;
3209 return is_valid_mask(attr_mask, req, opt);
3210 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3211 return is_valid_mask(attr_mask, req, opt);
3212 }
3213 return false;
3214}
3215
776a3906
MS		 3216/* mlx5_ib_modify_dct: modify a DCT QP
3217 * valid transitions are:
3218 * RESET to INIT: must set access_flags, pkey_index and port
3219 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3220 * mtu, gid_index and hop_limit
3221 * Other transitions and attributes are illegal
3222 */
3223static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3224 int attr_mask, struct ib_udata *udata)
3225{
3226 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3227 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3228 enum ib_qp_state cur_state, new_state;
3229 int err = 0;
3230 int required = IB_QP_STATE;
3231 void *dctc;
3232
3233 if (!(attr_mask & IB_QP_STATE))
3234 return -EINVAL;
3235
3236 cur_state = qp->state;
3237 new_state = attr->qp_state;
3238
3239 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3240 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3241 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3242 if (!is_valid_mask(attr_mask, required, 0))
3243 return -EINVAL;
3244
3245 if (attr->port_num == 0 ||
3246 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3247 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3248 attr->port_num, dev->num_ports);
3249 return -EINVAL;
3250 }
3251 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3252 MLX5_SET(dctc, dctc, rre, 1);
3253 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3254 MLX5_SET(dctc, dctc, rwe, 1);
3255 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3256 if (!mlx5_ib_dc_atomic_is_supported(dev))
3257 return -EOPNOTSUPP;
3258 MLX5_SET(dctc, dctc, rae, 1);
3259 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3260 }
3261 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3262 MLX5_SET(dctc, dctc, port, attr->port_num);
3263 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3264
3265 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3266 struct mlx5_ib_modify_qp_resp resp = {};
3267 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3268 sizeof(resp.dctn);
3269
3270 if (udata->outlen < min_resp_len)
3271 return -EINVAL;
3272 resp.response_length = min_resp_len;
3273
3274 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3275 if (!is_valid_mask(attr_mask, required, 0))
3276 return -EINVAL;
3277 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3278 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3279 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3280 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3281 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3282 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3283
3284 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3285 MLX5_ST_SZ_BYTES(create_dct_in));
3286 if (err)
3287 return err;
3288 resp.dctn = qp->dct.mdct.mqp.qpn;
3289 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3290 if (err) {
3291 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3292 return err;
3293 }
3294 } else {
3295 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3296 return -EINVAL;
3297 }
3298 if (err)
3299 qp->state = IB_QPS_ERR;
3300 else
3301 qp->state = new_state;
3302 return err;
3303}
3304
e126ba97
EC		 3305int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3306 int attr_mask, struct ib_udata *udata)
3307{
3308 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3309 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 3310 enum ib_qp_type qp_type;
e126ba97
EC		 3311 enum ib_qp_state cur_state, new_state;
3312 int err = -EINVAL;
3313 int port;
2811ba51 3314 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3315
28d61370
YH		 3316 if (ibqp->rwq_ind_tbl)
3317 return -ENOSYS;
3318
d16e91da
HE		 3319 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3320 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3321
c32a4f29
MS		 3322 if (ibqp->qp_type == IB_QPT_DRIVER)
3323 qp_type = qp->qp_sub_type;
3324 else
3325 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3326 IB_QPT_GSI : ibqp->qp_type;
3327
776a3906
MS		 3328 if (qp_type == MLX5_IB_QPT_DCT)
3329 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3330
e126ba97
EC		 3331 mutex_lock(&qp->mutex);
3332
3333 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3334 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3335
2811ba51
AS		 3336 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3337 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3338 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3339 }
3340
c2e53b2c
YH		 3341 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3342 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3343 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3344 attr_mask);
3345 goto out;
3346 }
3347 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3348 qp_type != MLX5_IB_QPT_DCI &&
3349 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3350 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3351 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3352 goto out;
c32a4f29
MS		 3353 } else if (qp_type == MLX5_IB_QPT_DCI &&
3354 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3355 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3356 cur_state, new_state, qp_type, attr_mask);
3357 goto out;
158abf86 3358 }
e126ba97
EC		 3359
3360 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3361 (attr->port_num == 0 ||
508562d6 3362 attr->port_num > dev->num_ports)) {
158abf86
HE		 3363 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3364 attr->port_num, dev->num_ports);
e126ba97 3365 goto out;
158abf86 3366 }
e126ba97
EC		 3367
3368 if (attr_mask & IB_QP_PKEY_INDEX) {
3369 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3370 if (attr->pkey_index >=
158abf86
HE		 3371 dev->mdev->port_caps[port - 1].pkey_table_len) {
3372 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3373 attr->pkey_index);
e126ba97 3374 goto out;
158abf86 3375 }
e126ba97
EC		 3376 }
3377
3378 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3379 attr->max_rd_atomic >
158abf86
HE		 3380 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3381 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3382 attr->max_rd_atomic);
e126ba97 3383 goto out;
158abf86 3384 }
e126ba97
EC		 3385
3386 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3387 attr->max_dest_rd_atomic >
158abf86
HE		 3388 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3389 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3390 attr->max_dest_rd_atomic);
e126ba97 3391 goto out;
158abf86 3392 }
e126ba97
EC		 3393
3394 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3395 err = 0;
3396 goto out;
3397 }
3398
3399 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3400
3401out:
3402 mutex_unlock(&qp->mutex);
3403 return err;
3404}
3405
3406static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3407{
3408 struct mlx5_ib_cq *cq;
3409 unsigned cur;
3410
3411 cur = wq->head - wq->tail;
3412 if (likely(cur + nreq < wq->max_post))
3413 return 0;
3414
3415 cq = to_mcq(ib_cq);
3416 spin_lock(&cq->lock);
3417 cur = wq->head - wq->tail;
3418 spin_unlock(&cq->lock);
3419
3420 return cur + nreq >= wq->max_post;
3421}
3422
3423static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3424 u64 remote_addr, u32 rkey)
3425{
3426 rseg->raddr = cpu_to_be64(remote_addr);
3427 rseg->rkey = cpu_to_be32(rkey);
3428 rseg->reserved = 0;
3429}
3430
f0313965
ES		 3431static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3432 struct ib_send_wr *wr, void *qend,
3433 struct mlx5_ib_qp *qp, int *size)
3434{
3435 void *seg = eseg;
3436
3437 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3438
3439 if (wr->send_flags & IB_SEND_IP_CSUM)
3440 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3441 MLX5_ETH_WQE_L4_CSUM;
3442
3443 seg += sizeof(struct mlx5_wqe_eth_seg);
3444 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3445
3446 if (wr->opcode == IB_WR_LSO) {
3447 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3448 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3449 u64 left, leftlen, copysz;
3450 void *pdata = ud_wr->header;
3451
3452 left = ud_wr->hlen;
3453 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3454 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3455
3456 /*
3457 * check if there is space till the end of queue, if yes,
3458 * copy all in one shot, otherwise copy till the end of queue,
3459 * rollback and than the copy the left
3460 */
2b31f7ae 3461 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3462 copysz = min_t(u64, leftlen, left);
3463
3464 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3465
3466 if (likely(copysz > size_of_inl_hdr_start)) {
3467 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3468 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3469 }
3470
3471 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3472 seg = mlx5_get_send_wqe(qp, 0);
3473 left -= copysz;
3474 pdata += copysz;
3475 memcpy(seg, pdata, left);
3476 seg += ALIGN(left, 16);
3477 *size += ALIGN(left, 16) / 16;
3478 }
3479 }
3480
3481 return seg;
3482}
3483
e126ba97
EC		 3484static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3485 struct ib_send_wr *wr)
3486{
e622f2f4
CH		 3487 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3488 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3489 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3490}
3491
3492static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3493{
3494 dseg->byte_count = cpu_to_be32(sg->length);
3495 dseg->lkey = cpu_to_be32(sg->lkey);
3496 dseg->addr = cpu_to_be64(sg->addr);
3497}
3498
31616255 3499static u64 get_xlt_octo(u64 bytes)
e126ba97 3500{
31616255
AK		 3501 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3502 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3503}
3504
3505static __be64 frwr_mkey_mask(void)
3506{
3507 u64 result;
3508
3509 result = MLX5_MKEY_MASK_LEN |
3510 MLX5_MKEY_MASK_PAGE_SIZE |
3511 MLX5_MKEY_MASK_START_ADDR |
3512 MLX5_MKEY_MASK_EN_RINVAL |
3513 MLX5_MKEY_MASK_KEY |
3514 MLX5_MKEY_MASK_LR |
3515 MLX5_MKEY_MASK_LW |
3516 MLX5_MKEY_MASK_RR |
3517 MLX5_MKEY_MASK_RW |
3518 MLX5_MKEY_MASK_A |
3519 MLX5_MKEY_MASK_SMALL_FENCE |
3520 MLX5_MKEY_MASK_FREE;
3521
3522 return cpu_to_be64(result);
3523}
3524
e6631814
SG		 3525static __be64 sig_mkey_mask(void)
3526{
3527 u64 result;
3528
3529 result = MLX5_MKEY_MASK_LEN |
3530 MLX5_MKEY_MASK_PAGE_SIZE |
3531 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3532 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3533 MLX5_MKEY_MASK_EN_RINVAL |
3534 MLX5_MKEY_MASK_KEY |
3535 MLX5_MKEY_MASK_LR |
3536 MLX5_MKEY_MASK_LW |
3537 MLX5_MKEY_MASK_RR |
3538 MLX5_MKEY_MASK_RW |
3539 MLX5_MKEY_MASK_SMALL_FENCE |
3540 MLX5_MKEY_MASK_FREE |
3541 MLX5_MKEY_MASK_BSF_EN;
3542
3543 return cpu_to_be64(result);
3544}
3545
8a187ee5 3546static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3547 struct mlx5_ib_mr *mr)
8a187ee5 3548{
31616255 3549 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3550
3551 memset(umr, 0, sizeof(*umr));
b005d316 3552
8a187ee5 3553 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3554 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3555 umr->mkey_mask = frwr_mkey_mask();
3556}
3557
dd01e66a 3558static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3559{
3560 memset(umr, 0, sizeof(*umr));
dd01e66a 3561 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3562 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3563}
3564
31616255 3565static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3566{
3567 u64 result;
3568
31616255 3569 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3570 MLX5_MKEY_MASK_FREE;
3571
968e78dd
HE		 3572 return cpu_to_be64(result);
3573}
3574
31616255 3575static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3576{
3577 u64 result;
3578
3579 result = MLX5_MKEY_MASK_FREE;
3580
3581 return cpu_to_be64(result);
3582}
3583
56e11d62
NO		 3584static __be64 get_umr_update_translation_mask(void)
3585{
3586 u64 result;
3587
3588 result = MLX5_MKEY_MASK_LEN |
3589 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3590 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3591
3592 return cpu_to_be64(result);
3593}
3594
31616255 3595static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3596{
3597 u64 result;
3598
31616255
AK		 3599 result = MLX5_MKEY_MASK_LR |
3600 MLX5_MKEY_MASK_LW |
56e11d62 3601 MLX5_MKEY_MASK_RR |
31616255
AK		 3602 MLX5_MKEY_MASK_RW;
3603
3604 if (atomic)
3605 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3606
3607 return cpu_to_be64(result);
3608}
3609
3610static __be64 get_umr_update_pd_mask(void)
3611{
3612 u64 result;
3613
31616255 3614 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3615
3616 return cpu_to_be64(result);
3617}
3618
e126ba97 3619static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3620 struct ib_send_wr *wr, int atomic)
e126ba97 3621{
e622f2f4 3622 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3623
3624 memset(umr, 0, sizeof(*umr));
3625
968e78dd
HE		 3626 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3627 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3628 else
3629 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3630
31616255
AK		 3631 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3632 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3633 u64 offset = get_xlt_octo(umrwr->offset);
3634
3635 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3636 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3637 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3638 }
31616255
AK		 3639 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3640 umr->mkey_mask |= get_umr_update_translation_mask();
3641 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3642 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3643 umr->mkey_mask |= get_umr_update_pd_mask();
3644 }
3645 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3646 umr->mkey_mask |= get_umr_enable_mr_mask();
3647 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3648 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3649
3650 if (!wr->num_sge)
968e78dd 3651 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3652}
3653
3654static u8 get_umr_flags(int acc)
3655{
3656 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3657 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3658 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3659 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3660 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3661}
3662
8a187ee5
SG		 3663static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3664 struct mlx5_ib_mr *mr,
3665 u32 key, int access)
3666{
3667 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3668
3669 memset(seg, 0, sizeof(*seg));
b005d316 3670
ec22eb53 3671 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3672 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3673 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3674 /* KLMs take twice the size of MTTs */
3675 ndescs *= 2;
3676
3677 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3678 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3679 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3680 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3681 seg->len = cpu_to_be64(mr->ibmr.length);
3682 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3683}
3684
dd01e66a 3685static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3686{
3687 memset(seg, 0, sizeof(*seg));
dd01e66a 3688 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3689}
3690
3691static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3692{
e622f2f4 3693 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3694
e126ba97 3695 memset(seg, 0, sizeof(*seg));
31616255 3696 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3697 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3698
968e78dd 3699 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3700 if (umrwr->pd)
3701 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3702 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3703 !umrwr->length)
3704 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3705
3706 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3707 seg->len = cpu_to_be64(umrwr->length);
3708 seg->log2_page_size = umrwr->page_shift;
746b5583 3709 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3710 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3711}
3712
8a187ee5
SG		 3713static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3714 struct mlx5_ib_mr *mr,
3715 struct mlx5_ib_pd *pd)
3716{
3717 int bcount = mr->desc_size * mr->ndescs;
3718
3719 dseg->addr = cpu_to_be64(mr->desc_map);
3720 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3721 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3722}
3723
e126ba97
EC		 3724static __be32 send_ieth(struct ib_send_wr *wr)
3725{
3726 switch (wr->opcode) {
3727 case IB_WR_SEND_WITH_IMM:
3728 case IB_WR_RDMA_WRITE_WITH_IMM:
3729 return wr->ex.imm_data;
3730
3731 case IB_WR_SEND_WITH_INV:
3732 return cpu_to_be32(wr->ex.invalidate_rkey);
3733
3734 default:
3735 return 0;
3736 }
3737}
3738
3739static u8 calc_sig(void *wqe, int size)
3740{
3741 u8 *p = wqe;
3742 u8 res = 0;
3743 int i;
3744
3745 for (i = 0; i < size; i++)
3746 res ^= p[i];
3747
3748 return ~res;
3749}
3750
3751static u8 wq_sig(void *wqe)
3752{
3753 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3754}
3755
3756static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3757 void *wqe, int *sz)
3758{
3759 struct mlx5_wqe_inline_seg *seg;
3760 void *qend = qp->sq.qend;
3761 void *addr;
3762 int inl = 0;
3763 int copy;
3764 int len;
3765 int i;
3766
3767 seg = wqe;
3768 wqe += sizeof(*seg);
3769 for (i = 0; i < wr->num_sge; i++) {
3770 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3771 len = wr->sg_list[i].length;
3772 inl += len;
3773
3774 if (unlikely(inl > qp->max_inline_data))
3775 return -ENOMEM;
3776
3777 if (unlikely(wqe + len > qend)) {
3778 copy = qend - wqe;
3779 memcpy(wqe, addr, copy);
3780 addr += copy;
3781 len -= copy;
3782 wqe = mlx5_get_send_wqe(qp, 0);
3783 }
3784 memcpy(wqe, addr, len);
3785 wqe += len;
3786 }
3787
3788 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3789
3790 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3791
3792 return 0;
3793}
3794
e6631814
SG		 3795static u16 prot_field_size(enum ib_signature_type type)
3796{
3797 switch (type) {
3798 case IB_SIG_TYPE_T10_DIF:
3799 return MLX5_DIF_SIZE;
3800 default:
3801 return 0;
3802 }
3803}
3804
3805static u8 bs_selector(int block_size)
3806{
3807 switch (block_size) {
3808 case 512: return 0x1;
3809 case 520: return 0x2;
3810 case 4096: return 0x3;
3811 case 4160: return 0x4;
3812 case 1073741824: return 0x5;
3813 default: return 0;
3814 }
3815}
3816
78eda2bb
SG		 3817static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3818 struct mlx5_bsf_inl *inl)
e6631814 3819{
142537f4
SG		 3820 /* Valid inline section and allow BSF refresh */
3821 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3822 MLX5_BSF_REFRESH_DIF);
3823 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3824 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3825 /* repeating block */
3826 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3827 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3828 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3829
78eda2bb
SG		 3830 if (domain->sig.dif.ref_remap)
3831 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3832
78eda2bb
SG		 3833 if (domain->sig.dif.app_escape) {
3834 if (domain->sig.dif.ref_escape)
3835 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3836 else
3837 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3838 }
3839
78eda2bb
SG		 3840 inl->dif_app_bitmask_check =
3841 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3842}
3843
3844static int mlx5_set_bsf(struct ib_mr *sig_mr,
3845 struct ib_sig_attrs *sig_attrs,
3846 struct mlx5_bsf *bsf, u32 data_size)
3847{
3848 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3849 struct mlx5_bsf_basic *basic = &bsf->basic;
3850 struct ib_sig_domain *mem = &sig_attrs->mem;
3851 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3852
c7f44fbd 3853 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3854
3855 /* Basic + Extended + Inline */
3856 basic->bsf_size_sbs = 1 << 7;
3857 /* Input domain check byte mask */
3858 basic->check_byte_mask = sig_attrs->check_mask;
3859 basic->raw_data_size = cpu_to_be32(data_size);
3860
3861 /* Memory domain */
e6631814 3862 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3863 case IB_SIG_TYPE_NONE:
3864 break;
e6631814 3865 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3866 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3867 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3868 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3869 break;
3870 default:
3871 return -EINVAL;
3872 }
e6631814 3873
78eda2bb
SG		 3874 /* Wire domain */
3875 switch (sig_attrs->wire.sig_type) {
3876 case IB_SIG_TYPE_NONE:
3877 break;
3878 case IB_SIG_TYPE_T10_DIF:
e6631814 3879 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3880 mem->sig_type == wire->sig_type) {
e6631814 3881 /* Same block structure */
142537f4 3882 basic->bsf_size_sbs |= 1 << 4;
e6631814 3883 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3884 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3885 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3886 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3887 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3888 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3889 } else
3890 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3891
142537f4 3892 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3893 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3894 break;
e6631814
SG		 3895 default:
3896 return -EINVAL;
3897 }
3898
3899 return 0;
3900}
3901
e622f2f4
CH		 3902static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3903 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3904{
e622f2f4
CH		 3905 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3906 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3907 struct mlx5_bsf *bsf;
e622f2f4
CH		 3908 u32 data_len = wr->wr.sg_list->length;
3909 u32 data_key = wr->wr.sg_list->lkey;
3910 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3911 int ret;
3912 int wqe_size;
3913
e622f2f4
CH		 3914 if (!wr->prot ||
3915 (data_key == wr->prot->lkey &&
3916 data_va == wr->prot->addr &&
3917 data_len == wr->prot->length)) {
e6631814
SG		 3918 /**
3919 * Source domain doesn't contain signature information
5c273b16 3920 * or data and protection are interleaved in memory.
e6631814
SG		 3921 * So need construct:
3922 * ------------------
3923 * | data_klm |
3924 * ------------------
3925 * | BSF |
3926 * ------------------
3927 **/
3928 struct mlx5_klm *data_klm = *seg;
3929
3930 data_klm->bcount = cpu_to_be32(data_len);
3931 data_klm->key = cpu_to_be32(data_key);
3932 data_klm->va = cpu_to_be64(data_va);
3933 wqe_size = ALIGN(sizeof(*data_klm), 64);
3934 } else {
3935 /**
3936 * Source domain contains signature information
3937 * So need construct a strided block format:
3938 * ---------------------------
3939 * | stride_block_ctrl |
3940 * ---------------------------
3941 * | data_klm |
3942 * ---------------------------
3943 * | prot_klm |
3944 * ---------------------------
3945 * | BSF |
3946 * ---------------------------
3947 **/
3948 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3949 struct mlx5_stride_block_entry *data_sentry;
3950 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3951 u32 prot_key = wr->prot->lkey;
3952 u64 prot_va = wr->prot->addr;
e6631814
SG		 3953 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3954 int prot_size;
3955
3956 sblock_ctrl = *seg;
3957 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3958 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3959
3960 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3961 if (!prot_size) {
3962 pr_err("Bad block size given: %u\n", block_size);
3963 return -EINVAL;
3964 }
3965 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3966 prot_size);
3967 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3968 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3969 sblock_ctrl->num_entries = cpu_to_be16(2);
3970
3971 data_sentry->bcount = cpu_to_be16(block_size);
3972 data_sentry->key = cpu_to_be32(data_key);
3973 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3974 data_sentry->stride = cpu_to_be16(block_size);
3975
e6631814
SG		 3976 prot_sentry->bcount = cpu_to_be16(prot_size);
3977 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3978 prot_sentry->va = cpu_to_be64(prot_va);
3979 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3980
e6631814
SG		 3981 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3982 sizeof(*prot_sentry), 64);
3983 }
3984
3985 *seg += wqe_size;
3986 *size += wqe_size / 16;
3987 if (unlikely((*seg == qp->sq.qend)))
3988 *seg = mlx5_get_send_wqe(qp, 0);
3989
3990 bsf = *seg;
3991 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3992 if (ret)
3993 return -EINVAL;
3994
3995 *seg += sizeof(*bsf);
3996 *size += sizeof(*bsf) / 16;
3997 if (unlikely((*seg == qp->sq.qend)))
3998 *seg = mlx5_get_send_wqe(qp, 0);
3999
4000 return 0;
4001}
4002
4003static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 4004 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4005 u32 length, u32 pdn)
4006{
e622f2f4 4007 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4008 u32 sig_key = sig_mr->rkey;
d5436ba0 4009 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4010
4011 memset(seg, 0, sizeof(*seg));
4012
e622f2f4 4013 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4014 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4015 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4016 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4017 MLX5_MKEY_BSF_EN | pdn);
4018 seg->len = cpu_to_be64(length);
31616255 4019 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4020 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4021}
4022
4023static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4024 u32 size)
e6631814
SG		 4025{
4026 memset(umr, 0, sizeof(*umr));
4027
4028 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4029 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4030 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4031 umr->mkey_mask = sig_mkey_mask();
4032}
4033
4034
e622f2f4 4035static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 4036 void **seg, int *size)
4037{
e622f2f4
CH		 4038 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4039 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4040 u32 pdn = get_pd(qp)->pdn;
31616255 4041 u32 xlt_size;
e6631814
SG		 4042 int region_len, ret;
4043
e622f2f4
CH		 4044 if (unlikely(wr->wr.num_sge != 1) ||
4045 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4046 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4047 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4048 return -EINVAL;
4049
4050 /* length of the protected region, data + protection */
e622f2f4
CH		 4051 region_len = wr->wr.sg_list->length;
4052 if (wr->prot &&
4053 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4054 wr->prot->addr != wr->wr.sg_list->addr ||
4055 wr->prot->length != wr->wr.sg_list->length))
4056 region_len += wr->prot->length;
e6631814
SG		 4057
4058 /**
4059 * KLM octoword size - if protection was provided
4060 * then we use strided block format (3 octowords),
4061 * else we use single KLM (1 octoword)
4062 **/
31616255 4063 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4064
31616255 4065 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4066 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4067 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4068 if (unlikely((*seg == qp->sq.qend)))
4069 *seg = mlx5_get_send_wqe(qp, 0);
4070
31616255 4071 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4072 *seg += sizeof(struct mlx5_mkey_seg);
4073 *size += sizeof(struct mlx5_mkey_seg) / 16;
4074 if (unlikely((*seg == qp->sq.qend)))
4075 *seg = mlx5_get_send_wqe(qp, 0);
4076
4077 ret = set_sig_data_segment(wr, qp, seg, size);
4078 if (ret)
4079 return ret;
4080
d5436ba0 4081 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4082 return 0;
4083}
4084
4085static int set_psv_wr(struct ib_sig_domain *domain,
4086 u32 psv_idx, void **seg, int *size)
4087{
4088 struct mlx5_seg_set_psv *psv_seg = *seg;
4089
4090 memset(psv_seg, 0, sizeof(*psv_seg));
4091 psv_seg->psv_num = cpu_to_be32(psv_idx);
4092 switch (domain->sig_type) {
78eda2bb
SG		 4093 case IB_SIG_TYPE_NONE:
4094 break;
e6631814
SG		 4095 case IB_SIG_TYPE_T10_DIF:
4096 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4097 domain->sig.dif.app_tag);
4098 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4099 break;
e6631814 4100 default:
12bbf1ea
LR		 4101 pr_err("Bad signature type (%d) is given.\n",
4102 domain->sig_type);
4103 return -EINVAL;
e6631814
SG		 4104 }
4105
78eda2bb
SG		 4106 *seg += sizeof(*psv_seg);
4107 *size += sizeof(*psv_seg) / 16;
4108
e6631814
SG		 4109 return 0;
4110}
4111
8a187ee5
SG		 4112static int set_reg_wr(struct mlx5_ib_qp *qp,
4113 struct ib_reg_wr *wr,
4114 void **seg, int *size)
4115{
4116 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4117 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4118
4119 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4120 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4121 "Invalid IB_SEND_INLINE send flag\n");
4122 return -EINVAL;
4123 }
4124
4125 set_reg_umr_seg(*seg, mr);
4126 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4127 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4128 if (unlikely((*seg == qp->sq.qend)))
4129 *seg = mlx5_get_send_wqe(qp, 0);
4130
4131 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4132 *seg += sizeof(struct mlx5_mkey_seg);
4133 *size += sizeof(struct mlx5_mkey_seg) / 16;
4134 if (unlikely((*seg == qp->sq.qend)))
4135 *seg = mlx5_get_send_wqe(qp, 0);
4136
4137 set_reg_data_seg(*seg, mr, pd);
4138 *seg += sizeof(struct mlx5_wqe_data_seg);
4139 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4140
4141 return 0;
4142}
4143
dd01e66a 4144static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4145{
dd01e66a 4146 set_linv_umr_seg(*seg);
e126ba97
EC		 4147 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4148 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4149 if (unlikely((*seg == qp->sq.qend)))
4150 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4151 set_linv_mkey_seg(*seg);
e126ba97
EC		 4152 *seg += sizeof(struct mlx5_mkey_seg);
4153 *size += sizeof(struct mlx5_mkey_seg) / 16;
4154 if (unlikely((*seg == qp->sq.qend)))
4155 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4156}
4157
4158static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4159{
4160 __be32 *p = NULL;
4161 int tidx = idx;
4162 int i, j;
4163
4164 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4165 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4166 if ((i & 0xf) == 0) {
4167 void *buf = mlx5_get_send_wqe(qp, tidx);
4168 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4169 p = buf;
4170 j = 0;
4171 }
4172 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4173 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4174 be32_to_cpu(p[j + 3]));
4175 }
4176}
4177
6e5eadac
SG		 4178static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4179 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 4180 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 4181 int *size, int nreq)
4182{
b2a232d2
LR		 4183 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4184 return -ENOMEM;
6e5eadac
SG		 4185
4186 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4187 *seg = mlx5_get_send_wqe(qp, *idx);
4188 *ctrl = *seg;
4189 *(uint32_t *)(*seg + 8) = 0;
4190 (*ctrl)->imm = send_ieth(wr);
4191 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4192 (wr->send_flags & IB_SEND_SIGNALED ?
4193 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4194 (wr->send_flags & IB_SEND_SOLICITED ?
4195 MLX5_WQE_CTRL_SOLICITED : 0);
4196
4197 *seg += sizeof(**ctrl);
4198 *size = sizeof(**ctrl) / 16;
4199
b2a232d2 4200 return 0;
6e5eadac
SG		 4201}
4202
4203static void finish_wqe(struct mlx5_ib_qp *qp,
4204 struct mlx5_wqe_ctrl_seg *ctrl,
4205 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4206 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4207{
4208 u8 opmod = 0;
4209
4210 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4211 mlx5_opcode | ((u32)opmod << 24));
19098df2 4212 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4213 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4214 if (unlikely(qp->wq_sig))
4215 ctrl->signature = wq_sig(ctrl);
4216
4217 qp->sq.wrid[idx] = wr_id;
4218 qp->sq.w_list[idx].opcode = mlx5_opcode;
4219 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4220 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4221 qp->sq.w_list[idx].next = qp->sq.cur_post;
4222}
4223
4224
e126ba97
EC		 4225int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4226 struct ib_send_wr **bad_wr)
4227{
4228 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4229 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4230 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4231 struct mlx5_ib_qp *qp;
e6631814 4232 struct mlx5_ib_mr *mr;
e126ba97
EC		 4233 struct mlx5_wqe_data_seg *dpseg;
4234 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4235 struct mlx5_bf *bf;
e126ba97 4236 int uninitialized_var(size);
d16e91da 4237 void *qend;
e126ba97 4238 unsigned long flags;
e126ba97
EC		 4239 unsigned idx;
4240 int err = 0;
e126ba97
EC		 4241 int num_sge;
4242 void *seg;
4243 int nreq;
4244 int i;
4245 u8 next_fence = 0;
e126ba97
EC		 4246 u8 fence;
4247
d16e91da
HE		 4248 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4249 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4250
4251 qp = to_mqp(ibqp);
5fe9dec0 4252 bf = &qp->bf;
d16e91da
HE		 4253 qend = qp->sq.qend;
4254
e126ba97
EC		 4255 spin_lock_irqsave(&qp->sq.lock, flags);
4256
89ea94a7
MG		 4257 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4258 err = -EIO;
4259 *bad_wr = wr;
4260 nreq = 0;
4261 goto out;
4262 }
4263
e126ba97 4264 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4265 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4266 mlx5_ib_warn(dev, "\n");
4267 err = -EINVAL;
4268 *bad_wr = wr;
4269 goto out;
4270 }
4271
6e5eadac
SG		 4272 num_sge = wr->num_sge;
4273 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4274 mlx5_ib_warn(dev, "\n");
24be409b 4275 err = -EINVAL;
e126ba97
EC		 4276 *bad_wr = wr;
4277 goto out;
4278 }
4279
6e5eadac
SG		 4280 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4281 if (err) {
e126ba97
EC		 4282 mlx5_ib_warn(dev, "\n");
4283 err = -ENOMEM;
4284 *bad_wr = wr;
4285 goto out;
4286 }
4287
6e8484c5
MG		 4288 if (wr->opcode == IB_WR_LOCAL_INV ||
4289 wr->opcode == IB_WR_REG_MR) {
4290 fence = dev->umr_fence;
4291 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4292 } else if (wr->send_flags & IB_SEND_FENCE) {
4293 if (qp->next_fence)
4294 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4295 else
4296 fence = MLX5_FENCE_MODE_FENCE;
4297 } else {
4298 fence = qp->next_fence;
4299 }
4300
e126ba97
EC		 4301 switch (ibqp->qp_type) {
4302 case IB_QPT_XRC_INI:
4303 xrc = seg;
e126ba97
EC		 4304 seg += sizeof(*xrc);
4305 size += sizeof(*xrc) / 16;
4306 /* fall through */
4307 case IB_QPT_RC:
4308 switch (wr->opcode) {
4309 case IB_WR_RDMA_READ:
4310 case IB_WR_RDMA_WRITE:
4311 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4312 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4313 rdma_wr(wr)->rkey);
f241e749 4314 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4315 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4316 break;
4317
4318 case IB_WR_ATOMIC_CMP_AND_SWP:
4319 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4320 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4321 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4322 err = -ENOSYS;
4323 *bad_wr = wr;
4324 goto out;
e126ba97
EC		 4325
4326 case IB_WR_LOCAL_INV:
e126ba97
EC		 4327 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4328 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4329 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4330 num_sge = 0;
4331 break;
4332
8a187ee5 4333 case IB_WR_REG_MR:
8a187ee5
SG		 4334 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4335 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4336 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4337 if (err) {
4338 *bad_wr = wr;
4339 goto out;
4340 }
4341 num_sge = 0;
4342 break;
4343
e6631814
SG		 4344 case IB_WR_REG_SIG_MR:
4345 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4346 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4347
4348 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4349 err = set_sig_umr_wr(wr, qp, &seg, &size);
4350 if (err) {
4351 mlx5_ib_warn(dev, "\n");
4352 *bad_wr = wr;
4353 goto out;
4354 }
4355
6e8484c5
MG		 4356 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4357 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4358 /*
4359 * SET_PSV WQEs are not signaled and solicited
4360 * on error
4361 */
4362 wr->send_flags &= ~IB_SEND_SIGNALED;
4363 wr->send_flags |= IB_SEND_SOLICITED;
4364 err = begin_wqe(qp, &seg, &ctrl, wr,
4365 &idx, &size, nreq);
4366 if (err) {
4367 mlx5_ib_warn(dev, "\n");
4368 err = -ENOMEM;
4369 *bad_wr = wr;
4370 goto out;
4371 }
4372
e622f2f4 4373 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4374 mr->sig->psv_memory.psv_idx, &seg,
4375 &size);
4376 if (err) {
4377 mlx5_ib_warn(dev, "\n");
4378 *bad_wr = wr;
4379 goto out;
4380 }
4381
6e8484c5
MG		 4382 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4383 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 4384 err = begin_wqe(qp, &seg, &ctrl, wr,
4385 &idx, &size, nreq);
4386 if (err) {
4387 mlx5_ib_warn(dev, "\n");
4388 err = -ENOMEM;
4389 *bad_wr = wr;
4390 goto out;
4391 }
4392
e622f2f4 4393 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4394 mr->sig->psv_wire.psv_idx, &seg,
4395 &size);
4396 if (err) {
4397 mlx5_ib_warn(dev, "\n");
4398 *bad_wr = wr;
4399 goto out;
4400 }
4401
6e8484c5
MG		 4402 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4403 fence, MLX5_OPCODE_SET_PSV);
4404 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4405 num_sge = 0;
4406 goto skip_psv;
4407
e126ba97
EC		 4408 default:
4409 break;
4410 }
4411 break;
4412
4413 case IB_QPT_UC:
4414 switch (wr->opcode) {
4415 case IB_WR_RDMA_WRITE:
4416 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4417 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4418 rdma_wr(wr)->rkey);
e126ba97
EC		 4419 seg += sizeof(struct mlx5_wqe_raddr_seg);
4420 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4421 break;
4422
4423 default:
4424 break;
4425 }
4426 break;
4427
e126ba97 4428 case IB_QPT_SMI:
1e0e50b6
MG		 4429 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4430 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4431 err = -EPERM;
4432 *bad_wr = wr;
4433 goto out;
4434 }
f6b1ee34 4435 /* fall through */
d16e91da 4436 case MLX5_IB_QPT_HW_GSI:
e126ba97 4437 set_datagram_seg(seg, wr);
f241e749 4438 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4439 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4440 if (unlikely((seg == qend)))
4441 seg = mlx5_get_send_wqe(qp, 0);
4442 break;
f0313965
ES		 4443 case IB_QPT_UD:
4444 set_datagram_seg(seg, wr);
4445 seg += sizeof(struct mlx5_wqe_datagram_seg);
4446 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4447
4448 if (unlikely((seg == qend)))
4449 seg = mlx5_get_send_wqe(qp, 0);
4450
4451 /* handle qp that supports ud offload */
4452 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4453 struct mlx5_wqe_eth_pad *pad;
e126ba97 4454
f0313965
ES		 4455 pad = seg;
4456 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4457 seg += sizeof(struct mlx5_wqe_eth_pad);
4458 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4459
4460 seg = set_eth_seg(seg, wr, qend, qp, &size);
4461
4462 if (unlikely((seg == qend)))
4463 seg = mlx5_get_send_wqe(qp, 0);
4464 }
4465 break;
e126ba97
EC		 4466 case MLX5_IB_QPT_REG_UMR:
4467 if (wr->opcode != MLX5_IB_WR_UMR) {
4468 err = -EINVAL;
4469 mlx5_ib_warn(dev, "bad opcode\n");
4470 goto out;
4471 }
4472 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4473 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4474 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4475 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4476 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4477 if (unlikely((seg == qend)))
4478 seg = mlx5_get_send_wqe(qp, 0);
4479 set_reg_mkey_segment(seg, wr);
4480 seg += sizeof(struct mlx5_mkey_seg);
4481 size += sizeof(struct mlx5_mkey_seg) / 16;
4482 if (unlikely((seg == qend)))
4483 seg = mlx5_get_send_wqe(qp, 0);
4484 break;
4485
4486 default:
4487 break;
4488 }
4489
4490 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4491 int uninitialized_var(sz);
4492
4493 err = set_data_inl_seg(qp, wr, seg, &sz);
4494 if (unlikely(err)) {
4495 mlx5_ib_warn(dev, "\n");
4496 *bad_wr = wr;
4497 goto out;
4498 }
e126ba97
EC		 4499 size += sz;
4500 } else {
4501 dpseg = seg;
4502 for (i = 0; i < num_sge; i++) {
4503 if (unlikely(dpseg == qend)) {
4504 seg = mlx5_get_send_wqe(qp, 0);
4505 dpseg = seg;
4506 }
4507 if (likely(wr->sg_list[i].length)) {
4508 set_data_ptr_seg(dpseg, wr->sg_list + i);
4509 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4510 dpseg++;
4511 }
4512 }
4513 }
4514
6e8484c5
MG		 4515 qp->next_fence = next_fence;
4516 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4517 mlx5_ib_opcode[wr->opcode]);
e6631814 4518skip_psv:
e126ba97
EC		 4519 if (0)
4520 dump_wqe(qp, idx, size);
4521 }
4522
4523out:
4524 if (likely(nreq)) {
4525 qp->sq.head += nreq;
4526
4527 /* Make sure that descriptors are written before
4528 * updating doorbell record and ringing the doorbell
4529 */
4530 wmb();
4531
4532 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4533
ada388f7
EC		 4534 /* Make sure doorbell record is visible to the HCA before
4535 * we hit doorbell */
4536 wmb();
4537
5fe9dec0
EC		 4538 /* currently we support only regular doorbells */
4539 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4540 /* Make sure doorbells don't leak out of SQ spinlock
4541 * and reach the HCA out of order.
4542 */
4543 mmiowb();
e126ba97 4544 bf->offset ^= bf->buf_size;
e126ba97
EC		 4545 }
4546
4547 spin_unlock_irqrestore(&qp->sq.lock, flags);
4548
4549 return err;
4550}
4551
4552static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4553{
4554 sig->signature = calc_sig(sig, size);
4555}
4556
4557int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4558 struct ib_recv_wr **bad_wr)
4559{
4560 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4561 struct mlx5_wqe_data_seg *scat;
4562 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4563 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4564 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4565 unsigned long flags;
4566 int err = 0;
4567 int nreq;
4568 int ind;
4569 int i;
4570
d16e91da
HE		 4571 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4572 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4573
e126ba97
EC		 4574 spin_lock_irqsave(&qp->rq.lock, flags);
4575
89ea94a7
MG		 4576 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4577 err = -EIO;
4578 *bad_wr = wr;
4579 nreq = 0;
4580 goto out;
4581 }
4582
e126ba97
EC		 4583 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4584
4585 for (nreq = 0; wr; nreq++, wr = wr->next) {
4586 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4587 err = -ENOMEM;
4588 *bad_wr = wr;
4589 goto out;
4590 }
4591
4592 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4593 err = -EINVAL;
4594 *bad_wr = wr;
4595 goto out;
4596 }
4597
4598 scat = get_recv_wqe(qp, ind);
4599 if (qp->wq_sig)
4600 scat++;
4601
4602 for (i = 0; i < wr->num_sge; i++)
4603 set_data_ptr_seg(scat + i, wr->sg_list + i);
4604
4605 if (i < qp->rq.max_gs) {
4606 scat[i].byte_count = 0;
4607 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4608 scat[i].addr = 0;
4609 }
4610
4611 if (qp->wq_sig) {
4612 sig = (struct mlx5_rwqe_sig *)scat;
4613 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4614 }
4615
4616 qp->rq.wrid[ind] = wr->wr_id;
4617
4618 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4619 }
4620
4621out:
4622 if (likely(nreq)) {
4623 qp->rq.head += nreq;
4624
4625 /* Make sure that descriptors are written before
4626 * doorbell record.
4627 */
4628 wmb();
4629
4630 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4631 }
4632
4633 spin_unlock_irqrestore(&qp->rq.lock, flags);
4634
4635 return err;
4636}
4637
4638static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4639{
4640 switch (mlx5_state) {
4641 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4642 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4643 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4644 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4645 case MLX5_QP_STATE_SQ_DRAINING:
4646 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4647 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4648 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4649 default: return -1;
4650 }
4651}
4652
4653static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4654{
4655 switch (mlx5_mig_state) {
4656 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4657 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4658 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4659 default: return -1;
4660 }
4661}
4662
4663static int to_ib_qp_access_flags(int mlx5_flags)
4664{
4665 int ib_flags = 0;
4666
4667 if (mlx5_flags & MLX5_QP_BIT_RRE)
4668 ib_flags |= IB_ACCESS_REMOTE_READ;
4669 if (mlx5_flags & MLX5_QP_BIT_RWE)
4670 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4671 if (mlx5_flags & MLX5_QP_BIT_RAE)
4672 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4673
4674 return ib_flags;
4675}
4676
38349389 4677static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4678 struct rdma_ah_attr *ah_attr,
38349389 4679 struct mlx5_qp_path *path)
e126ba97 4680{
e126ba97 4681
d8966fcd 4682 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4683
e7996a9a 4684 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 4685 return;
4686
ae59c3f0
LR		 4687 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4688
d8966fcd
DC		 4689 rdma_ah_set_port_num(ah_attr, path->port);
4690 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4691
4692 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4693 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4694 rdma_ah_set_static_rate(ah_attr,
4695 path->static_rate ? path->static_rate - 5 : 0);
4696 if (path->grh_mlid & (1 << 7)) {
4697 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4698
4699 rdma_ah_set_grh(ah_attr, NULL,
4700 tc_fl & 0xfffff,
4701 path->mgid_index,
4702 path->hop_limit,
4703 (tc_fl >> 20) & 0xff);
4704 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4705 }
4706}
4707
6d2f89df 4708static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4709 struct mlx5_ib_sq *sq,
4710 u8 *sq_state)
4711{
4712 void *out;
4713 void *sqc;
4714 int inlen;
4715 int err;
4716
4717 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4718 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4719 if (!out)
4720 return -ENOMEM;
4721
4722 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4723 if (err)
4724 goto out;
4725
4726 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4727 *sq_state = MLX5_GET(sqc, sqc, state);
4728 sq->state = *sq_state;
4729
4730out:
4731 kvfree(out);
4732 return err;
4733}
4734
4735static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4736 struct mlx5_ib_rq *rq,
4737 u8 *rq_state)
4738{
4739 void *out;
4740 void *rqc;
4741 int inlen;
4742 int err;
4743
4744 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4745 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4746 if (!out)
4747 return -ENOMEM;
4748
4749 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4750 if (err)
4751 goto out;
4752
4753 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4754 *rq_state = MLX5_GET(rqc, rqc, state);
4755 rq->state = *rq_state;
4756
4757out:
4758 kvfree(out);
4759 return err;
4760}
4761
4762static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4763 struct mlx5_ib_qp *qp, u8 *qp_state)
4764{
4765 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4766 [MLX5_RQC_STATE_RST] = {
4767 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4768 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4769 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4770 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4771 },
4772 [MLX5_RQC_STATE_RDY] = {
4773 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4774 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4775 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4776 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4777 },
4778 [MLX5_RQC_STATE_ERR] = {
4779 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4780 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4781 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4782 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4783 },
4784 [MLX5_RQ_STATE_NA] = {
4785 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4786 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4787 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4788 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4789 },
4790 };
4791
4792 *qp_state = sqrq_trans[rq_state][sq_state];
4793
4794 if (*qp_state == MLX5_QP_STATE_BAD) {
4795 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4796 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4797 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4798 return -EINVAL;
4799 }
4800
4801 if (*qp_state == MLX5_QP_STATE)
4802 *qp_state = qp->state;
4803
4804 return 0;
4805}
4806
4807static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4808 struct mlx5_ib_qp *qp,
4809 u8 *raw_packet_qp_state)
4810{
4811 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4812 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4813 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4814 int err;
4815 u8 sq_state = MLX5_SQ_STATE_NA;
4816 u8 rq_state = MLX5_RQ_STATE_NA;
4817
4818 if (qp->sq.wqe_cnt) {
4819 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4820 if (err)
4821 return err;
4822 }
4823
4824 if (qp->rq.wqe_cnt) {
4825 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4826 if (err)
4827 return err;
4828 }
4829
4830 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4831 raw_packet_qp_state);
4832}
4833
4834static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4835 struct ib_qp_attr *qp_attr)
e126ba97 4836{
09a7d9ec 4837 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4838 struct mlx5_qp_context *context;
4839 int mlx5_state;
09a7d9ec 4840 u32 *outb;
e126ba97
EC		 4841 int err = 0;
4842
09a7d9ec 4843 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4844 if (!outb)
4845 return -ENOMEM;
4846
19098df2 4847 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4848 outlen);
e126ba97 4849 if (err)
6d2f89df 4850 goto out;
e126ba97 4851
09a7d9ec
SM		 4852 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4853 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4854
e126ba97
EC		 4855 mlx5_state = be32_to_cpu(context->flags) >> 28;
4856
4857 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4858 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4859 qp_attr->path_mig_state =
4860 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4861 qp_attr->qkey = be32_to_cpu(context->qkey);
4862 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4863 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4864 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4865 qp_attr->qp_access_flags =
4866 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4867
4868 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4869 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4870 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4871 qp_attr->alt_pkey_index =
4872 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4873 qp_attr->alt_port_num =
4874 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4875 }
4876
d3ae2bde 4877 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4878 qp_attr->port_num = context->pri_path.port;
4879
4880 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4881 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4882
4883 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4884
4885 qp_attr->max_dest_rd_atomic =
4886 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4887 qp_attr->min_rnr_timer =
4888 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4889 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4890 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4891 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4892 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4893
4894out:
4895 kfree(outb);
4896 return err;
4897}
4898
776a3906
MS		 4899static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4900 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4901 struct ib_qp_init_attr *qp_init_attr)
4902{
4903 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4904 u32 *out;
4905 u32 access_flags = 0;
4906 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4907 void *dctc;
4908 int err;
4909 int supported_mask = IB_QP_STATE |
4910 IB_QP_ACCESS_FLAGS |
4911 IB_QP_PORT |
4912 IB_QP_MIN_RNR_TIMER |
4913 IB_QP_AV |
4914 IB_QP_PATH_MTU |
4915 IB_QP_PKEY_INDEX;
4916
4917 if (qp_attr_mask & ~supported_mask)
4918 return -EINVAL;
4919 if (mqp->state != IB_QPS_RTR)
4920 return -EINVAL;
4921
4922 out = kzalloc(outlen, GFP_KERNEL);
4923 if (!out)
4924 return -ENOMEM;
4925
4926 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
4927 if (err)
4928 goto out;
4929
4930 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4931
4932 if (qp_attr_mask & IB_QP_STATE)
4933 qp_attr->qp_state = IB_QPS_RTR;
4934
4935 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4936 if (MLX5_GET(dctc, dctc, rre))
4937 access_flags |= IB_ACCESS_REMOTE_READ;
4938 if (MLX5_GET(dctc, dctc, rwe))
4939 access_flags |= IB_ACCESS_REMOTE_WRITE;
4940 if (MLX5_GET(dctc, dctc, rae))
4941 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4942 qp_attr->qp_access_flags = access_flags;
4943 }
4944
4945 if (qp_attr_mask & IB_QP_PORT)
4946 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4947 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4948 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4949 if (qp_attr_mask & IB_QP_AV) {
4950 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4951 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4952 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4953 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4954 }
4955 if (qp_attr_mask & IB_QP_PATH_MTU)
4956 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4957 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4958 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4959out:
4960 kfree(out);
4961 return err;
4962}
4963
6d2f89df 4964int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4965 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4966{
4967 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4968 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4969 int err = 0;
4970 u8 raw_packet_qp_state;
4971
28d61370
YH		 4972 if (ibqp->rwq_ind_tbl)
4973 return -ENOSYS;
4974
d16e91da
HE		 4975 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4976 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4977 qp_init_attr);
4978
c2e53b2c
YH		 4979 /* Not all of output fields are applicable, make sure to zero them */
4980 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4981 memset(qp_attr, 0, sizeof(*qp_attr));
4982
776a3906
MS		 4983 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
4984 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4985 qp_attr_mask, qp_init_attr);
4986
6d2f89df 4987 mutex_lock(&qp->mutex);
4988
c2e53b2c
YH		 4989 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4990 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 4991 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4992 if (err)
4993 goto out;
4994 qp->state = raw_packet_qp_state;
4995 qp_attr->port_num = 1;
4996 } else {
4997 err = query_qp_attr(dev, qp, qp_attr);
4998 if (err)
4999 goto out;
5000 }
5001
5002 qp_attr->qp_state = qp->state;
e126ba97
EC		 5003 qp_attr->cur_qp_state = qp_attr->qp_state;
5004 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5005 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5006
5007 if (!ibqp->uobject) {
0540d814 5008 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5009 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5010 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5011 } else {
5012 qp_attr->cap.max_send_wr = 0;
5013 qp_attr->cap.max_send_sge = 0;
5014 }
5015
0540d814
NO		 5016 qp_init_attr->qp_type = ibqp->qp_type;
5017 qp_init_attr->recv_cq = ibqp->recv_cq;
5018 qp_init_attr->send_cq = ibqp->send_cq;
5019 qp_init_attr->srq = ibqp->srq;
5020 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5021
5022 qp_init_attr->cap = qp_attr->cap;
5023
5024 qp_init_attr->create_flags = 0;
5025 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5026 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5027
051f2630
LR		 5028 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5029 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5030 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5031 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5032 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5033 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5034 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5035 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5036
e126ba97
EC		 5037 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5038 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5039
e126ba97
EC		 5040out:
5041 mutex_unlock(&qp->mutex);
5042 return err;
5043}
5044
5045struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5046 struct ib_ucontext *context,
5047 struct ib_udata *udata)
5048{
5049 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5050 struct mlx5_ib_xrcd *xrcd;
5051 int err;
5052
938fe83c 5053 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5054 return ERR_PTR(-ENOSYS);
5055
5056 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5057 if (!xrcd)
5058 return ERR_PTR(-ENOMEM);
5059
9603b61d 5060 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 5061 if (err) {
5062 kfree(xrcd);
5063 return ERR_PTR(-ENOMEM);
5064 }
5065
5066 return &xrcd->ibxrcd;
5067}
5068
5069int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5070{
5071 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5072 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5073 int err;
5074
9603b61d 5075 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
b081808a 5076 if (err)
e126ba97 5077 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5078
5079 kfree(xrcd);
e126ba97
EC		 5080 return 0;
5081}
79b20a6c 5082
350d0e4c
YH		 5083static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5084{
5085 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5086 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5087 struct ib_event event;
5088
5089 if (rwq->ibwq.event_handler) {
5090 event.device = rwq->ibwq.device;
5091 event.element.wq = &rwq->ibwq;
5092 switch (type) {
5093 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5094 event.event = IB_EVENT_WQ_FATAL;
5095 break;
5096 default:
5097 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5098 return;
5099 }
5100
5101 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5102 }
5103}
5104
03404e8a
MG		 5105static int set_delay_drop(struct mlx5_ib_dev *dev)
5106{
5107 int err = 0;
5108
5109 mutex_lock(&dev->delay_drop.lock);
5110 if (dev->delay_drop.activate)
5111 goto out;
5112
5113 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5114 if (err)
5115 goto out;
5116
5117 dev->delay_drop.activate = true;
5118out:
5119 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5120
5121 if (!err)
5122 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5123 return err;
5124}
5125
79b20a6c
YH		 5126static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5127 struct ib_wq_init_attr *init_attr)
5128{
5129 struct mlx5_ib_dev *dev;
4be6da1e 5130 int has_net_offloads;
79b20a6c
YH		 5131 __be64 *rq_pas0;
5132 void *in;
5133 void *rqc;
5134 void *wq;
5135 int inlen;
5136 int err;
5137
5138 dev = to_mdev(pd->device);
5139
5140 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5141 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5142 if (!in)
5143 return -ENOMEM;
5144
5145 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5146 MLX5_SET(rqc, rqc, mem_rq_type,
5147 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5148 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5149 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5150 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5151 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5152 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5153 MLX5_SET(wq, wq, wq_type,
5154 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5155 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5156 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5157 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5158 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5159 err = -EOPNOTSUPP;
5160 goto out;
5161 } else {
5162 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5163 }
5164 }
79b20a6c 5165 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5166 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5167 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5168 MLX5_SET(wq, wq, log_wqe_stride_size,
5169 rwq->single_stride_log_num_of_bytes -
5170 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5171 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5172 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5173 }
79b20a6c
YH		 5174 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5175 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5176 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5177 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5178 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5179 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5180 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5181 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5182 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5183 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5184 err = -EOPNOTSUPP;
5185 goto out;
5186 }
5187 } else {
5188 MLX5_SET(rqc, rqc, vsd, 1);
5189 }
4be6da1e
NO		 5190 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5191 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5192 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5193 err = -EOPNOTSUPP;
5194 goto out;
5195 }
5196 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5197 }
03404e8a
MG		 5198 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5199 if (!(dev->ib_dev.attrs.raw_packet_caps &
5200 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5201 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5202 err = -EOPNOTSUPP;
5203 goto out;
5204 }
5205 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5206 }
79b20a6c
YH		 5207 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5208 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5209 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5210 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5211 err = set_delay_drop(dev);
5212 if (err) {
5213 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5214 err);
5215 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5216 } else {
5217 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5218 }
5219 }
b1f74a84 5220out:
79b20a6c
YH		 5221 kvfree(in);
5222 return err;
5223}
5224
5225static int set_user_rq_size(struct mlx5_ib_dev *dev,
5226 struct ib_wq_init_attr *wq_init_attr,
5227 struct mlx5_ib_create_wq *ucmd,
5228 struct mlx5_ib_rwq *rwq)
5229{
5230 /* Sanity check RQ size before proceeding */
5231 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5232 return -EINVAL;
5233
5234 if (!ucmd->rq_wqe_count)
5235 return -EINVAL;
5236
5237 rwq->wqe_count = ucmd->rq_wqe_count;
5238 rwq->wqe_shift = ucmd->rq_wqe_shift;
5239 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5240 rwq->log_rq_stride = rwq->wqe_shift;
5241 rwq->log_rq_size = ilog2(rwq->wqe_count);
5242 return 0;
5243}
5244
5245static int prepare_user_rq(struct ib_pd *pd,
5246 struct ib_wq_init_attr *init_attr,
5247 struct ib_udata *udata,
5248 struct mlx5_ib_rwq *rwq)
5249{
5250 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5251 struct mlx5_ib_create_wq ucmd = {};
5252 int err;
5253 size_t required_cmd_sz;
5254
ccc87087
NO		 5255 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5256 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5257 if (udata->inlen < required_cmd_sz) {
5258 mlx5_ib_dbg(dev, "invalid inlen\n");
5259 return -EINVAL;
5260 }
5261
5262 if (udata->inlen > sizeof(ucmd) &&
5263 !ib_is_udata_cleared(udata, sizeof(ucmd),
5264 udata->inlen - sizeof(ucmd))) {
5265 mlx5_ib_dbg(dev, "inlen is not supported\n");
5266 return -EOPNOTSUPP;
5267 }
5268
5269 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5270 mlx5_ib_dbg(dev, "copy failed\n");
5271 return -EFAULT;
5272 }
5273
ccc87087 5274 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5275 mlx5_ib_dbg(dev, "invalid comp mask\n");
5276 return -EOPNOTSUPP;
ccc87087
NO		 5277 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5278 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5279 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5280 return -EOPNOTSUPP;
5281 }
5282 if ((ucmd.single_stride_log_num_of_bytes <
5283 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5284 (ucmd.single_stride_log_num_of_bytes >
5285 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5286 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5287 ucmd.single_stride_log_num_of_bytes,
5288 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5289 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5290 return -EINVAL;
5291 }
5292 if ((ucmd.single_wqe_log_num_of_strides >
5293 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5294 (ucmd.single_wqe_log_num_of_strides <
5295 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5296 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5297 ucmd.single_wqe_log_num_of_strides,
5298 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5299 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5300 return -EINVAL;
5301 }
5302 rwq->single_stride_log_num_of_bytes =
5303 ucmd.single_stride_log_num_of_bytes;
5304 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5305 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5306 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5307 }
5308
5309 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5310 if (err) {
5311 mlx5_ib_dbg(dev, "err %d\n", err);
5312 return err;
5313 }
5314
5315 err = create_user_rq(dev, pd, rwq, &ucmd);
5316 if (err) {
5317 mlx5_ib_dbg(dev, "err %d\n", err);
5318 if (err)
5319 return err;
5320 }
5321
5322 rwq->user_index = ucmd.user_index;
5323 return 0;
5324}
5325
5326struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5327 struct ib_wq_init_attr *init_attr,
5328 struct ib_udata *udata)
5329{
5330 struct mlx5_ib_dev *dev;
5331 struct mlx5_ib_rwq *rwq;
5332 struct mlx5_ib_create_wq_resp resp = {};
5333 size_t min_resp_len;
5334 int err;
5335
5336 if (!udata)
5337 return ERR_PTR(-ENOSYS);
5338
5339 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5340 if (udata->outlen && udata->outlen < min_resp_len)
5341 return ERR_PTR(-EINVAL);
5342
5343 dev = to_mdev(pd->device);
5344 switch (init_attr->wq_type) {
5345 case IB_WQT_RQ:
5346 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5347 if (!rwq)
5348 return ERR_PTR(-ENOMEM);
5349 err = prepare_user_rq(pd, init_attr, udata, rwq);
5350 if (err)
5351 goto err;
5352 err = create_rq(rwq, pd, init_attr);
5353 if (err)
5354 goto err_user_rq;
5355 break;
5356 default:
5357 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5358 init_attr->wq_type);
5359 return ERR_PTR(-EINVAL);
5360 }
5361
350d0e4c 5362 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5363 rwq->ibwq.state = IB_WQS_RESET;
5364 if (udata->outlen) {
5365 resp.response_length = offsetof(typeof(resp), response_length) +
5366 sizeof(resp.response_length);
5367 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5368 if (err)
5369 goto err_copy;
5370 }
5371
350d0e4c
YH		 5372 rwq->core_qp.event = mlx5_ib_wq_event;
5373 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5374 return &rwq->ibwq;
5375
5376err_copy:
350d0e4c 5377 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5378err_user_rq:
fe248c3a 5379 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5380err:
5381 kfree(rwq);
5382 return ERR_PTR(err);
5383}
5384
5385int mlx5_ib_destroy_wq(struct ib_wq *wq)
5386{
5387 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5388 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5389
350d0e4c 5390 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5391 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5392 kfree(rwq);
5393
5394 return 0;
5395}
5396
c5f90929
YH		 5397struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5398 struct ib_rwq_ind_table_init_attr *init_attr,
5399 struct ib_udata *udata)
5400{
5401 struct mlx5_ib_dev *dev = to_mdev(device);
5402 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5403 int sz = 1 << init_attr->log_ind_tbl_size;
5404 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5405 size_t min_resp_len;
5406 int inlen;
5407 int err;
5408 int i;
5409 u32 *in;
5410 void *rqtc;
5411
5412 if (udata->inlen > 0 &&
5413 !ib_is_udata_cleared(udata, 0,
5414 udata->inlen))
5415 return ERR_PTR(-EOPNOTSUPP);
5416
efd7f400
MG		 5417 if (init_attr->log_ind_tbl_size >
5418 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5419 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5420 init_attr->log_ind_tbl_size,
5421 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5422 return ERR_PTR(-EINVAL);
5423 }
5424
c5f90929
YH		 5425 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5426 if (udata->outlen && udata->outlen < min_resp_len)
5427 return ERR_PTR(-EINVAL);
5428
5429 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5430 if (!rwq_ind_tbl)
5431 return ERR_PTR(-ENOMEM);
5432
5433 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5434 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5435 if (!in) {
5436 err = -ENOMEM;
5437 goto err;
5438 }
5439
5440 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5441
5442 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5443 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5444
5445 for (i = 0; i < sz; i++)
5446 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5447
5448 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5449 kvfree(in);
5450
5451 if (err)
5452 goto err;
5453
5454 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5455 if (udata->outlen) {
5456 resp.response_length = offsetof(typeof(resp), response_length) +
5457 sizeof(resp.response_length);
5458 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5459 if (err)
5460 goto err_copy;
5461 }
5462
5463 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5464
5465err_copy:
5466 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5467err:
5468 kfree(rwq_ind_tbl);
5469 return ERR_PTR(err);
5470}
5471
5472int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5473{
5474 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5475 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5476
5477 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5478
5479 kfree(rwq_ind_tbl);
5480 return 0;
5481}
5482
79b20a6c
YH		 5483int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5484 u32 wq_attr_mask, struct ib_udata *udata)
5485{
5486 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5487 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5488 struct mlx5_ib_modify_wq ucmd = {};
5489 size_t required_cmd_sz;
5490 int curr_wq_state;
5491 int wq_state;
5492 int inlen;
5493 int err;
5494 void *rqc;
5495 void *in;
5496
5497 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5498 if (udata->inlen < required_cmd_sz)
5499 return -EINVAL;
5500
5501 if (udata->inlen > sizeof(ucmd) &&
5502 !ib_is_udata_cleared(udata, sizeof(ucmd),
5503 udata->inlen - sizeof(ucmd)))
5504 return -EOPNOTSUPP;
5505
5506 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5507 return -EFAULT;
5508
5509 if (ucmd.comp_mask || ucmd.reserved)
5510 return -EOPNOTSUPP;
5511
5512 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5513 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5514 if (!in)
5515 return -ENOMEM;
5516
5517 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5518
5519 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5520 wq_attr->curr_wq_state : wq->state;
5521 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5522 wq_attr->wq_state : curr_wq_state;
5523 if (curr_wq_state == IB_WQS_ERR)
5524 curr_wq_state = MLX5_RQC_STATE_ERR;
5525 if (wq_state == IB_WQS_ERR)
5526 wq_state = MLX5_RQC_STATE_ERR;
5527 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5528 MLX5_SET(rqc, rqc, state, wq_state);
5529
b1f74a84
NO		 5530 if (wq_attr_mask & IB_WQ_FLAGS) {
5531 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5532 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5533 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5534 mlx5_ib_dbg(dev, "VLAN offloads are not "
5535 "supported\n");
5536 err = -EOPNOTSUPP;
5537 goto out;
5538 }
5539 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5540 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5541 MLX5_SET(rqc, rqc, vsd,
5542 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5543 }
b1383aa6
NO		 5544
5545 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5546 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5547 err = -EOPNOTSUPP;
5548 goto out;
5549 }
b1f74a84
NO		 5550 }
5551
23a6964e
MD		 5552 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5553 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5554 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5555 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5556 MLX5_SET(rqc, rqc, counter_set_id,
5557 dev->port->cnts.set_id);
23a6964e
MD		 5558 } else
5559 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5560 dev->ib_dev.name);
5561 }
5562
350d0e4c 5563 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5564 if (!err)
5565 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5566
b1f74a84
NO		 5567out:
5568 kvfree(in);
79b20a6c
YH		 5569 return err;
5570}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git