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IB/mlx5: Add XRC initiator ODP support
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
443c1cf9 40#include "cmd.h"
e126ba97
EC		 41
42/* not supported currently */
43static int wq_signature;
44
45enum {
46 MLX5_IB_ACK_REQ_FREQ = 8,
47};
48
49enum {
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
54};
55
56enum {
57 MLX5_IB_SQ_STRIDE = 6,
064e5262 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
e126ba97
EC		 59};
60
61static const u32 mlx5_ib_opcode[] = {
62 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 63 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
76};
77
f0313965
ES		 78struct mlx5_wqe_eth_pad {
79 u8 rsvd0[16];
80};
e126ba97 81
eb49ab0c
AV		 82enum raw_qp_set_mask_map {
83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 85};
86
0680efa2
AV		 87struct mlx5_modify_raw_qp_param {
88 u16 operation;
eb49ab0c
AV		 89
90 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 91
92 struct mlx5_rate_limit rl;
93
eb49ab0c 94 u8 rq_q_ctr_id;
0680efa2
AV		 95};
96
89ea94a7
MG		 97static void get_cqs(enum ib_qp_type qp_type,
98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100
e126ba97
EC		 101static int is_qp0(enum ib_qp_type qp_type)
102{
103 return qp_type == IB_QPT_SMI;
104}
105
e126ba97
EC		 106static int is_sqp(enum ib_qp_type qp_type)
107{
108 return is_qp0(qp_type) || is_qp1(qp_type);
109}
110
c1395a2a
HE		 111/**
112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
113 *
114 * @qp: QP to copy from.
115 * @send: copy from the send queue when non-zero, use the receive queue
116 * otherwise.
117 * @wqe_index: index to start copying from. For send work queues, the
118 * wqe_index is in units of MLX5_SEND_WQE_BB.
119 * For receive work queue, it is the number of work queue
120 * element in the queue.
121 * @buffer: destination buffer.
122 * @length: maximum number of bytes to copy.
123 *
124 * Copies at least a single WQE, but may copy more data.
125 *
126 * Return: the number of bytes copied, or an error code.
127 */
128int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 129 void *buffer, u32 length,
130 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 131{
132 struct ib_device *ibdev = qp->ibqp.device;
133 struct mlx5_ib_dev *dev = to_mdev(ibdev);
134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
135 size_t offset;
136 size_t wq_end;
19098df2 137 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 138 u32 first_copy_length;
139 int wqe_length;
140 int ret;
141
142 if (wq->wqe_cnt == 0) {
143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
144 qp->ibqp.qp_type);
145 return -EINVAL;
146 }
147
148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
150
151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
152 return -EINVAL;
153
154 if (offset > umem->length ||
155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
156 return -EINVAL;
157
158 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
160 if (ret)
161 return ret;
162
163 if (send) {
164 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
166
167 wqe_length = ds * MLX5_WQE_DS_UNITS;
168 } else {
169 wqe_length = 1 << wq->wqe_shift;
170 }
171
172 if (wqe_length <= first_copy_length)
173 return first_copy_length;
174
175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
176 wqe_length - first_copy_length);
177 if (ret)
178 return ret;
179
180 return wqe_length;
181}
182
e126ba97
EC		 183static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
184{
185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
186 struct ib_event event;
187
19098df2 188 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
189 /* This event is only valid for trans_qps */
190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
191 }
e126ba97
EC		 192
193 if (ibqp->event_handler) {
194 event.device = ibqp->device;
195 event.element.qp = ibqp;
196 switch (type) {
197 case MLX5_EVENT_TYPE_PATH_MIG:
198 event.event = IB_EVENT_PATH_MIG;
199 break;
200 case MLX5_EVENT_TYPE_COMM_EST:
201 event.event = IB_EVENT_COMM_EST;
202 break;
203 case MLX5_EVENT_TYPE_SQ_DRAINED:
204 event.event = IB_EVENT_SQ_DRAINED;
205 break;
206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
207 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
208 break;
209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
210 event.event = IB_EVENT_QP_FATAL;
211 break;
212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
213 event.event = IB_EVENT_PATH_MIG_ERR;
214 break;
215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
216 event.event = IB_EVENT_QP_REQ_ERR;
217 break;
218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
219 event.event = IB_EVENT_QP_ACCESS_ERR;
220 break;
221 default:
222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
223 return;
224 }
225
226 ibqp->event_handler(&event, ibqp->qp_context);
227 }
228}
229
230static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
232{
233 int wqe_size;
234 int wq_size;
235
236 /* Sanity check RQ size before proceeding */
938fe83c 237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 238 return -EINVAL;
239
240 if (!has_rq) {
241 qp->rq.max_gs = 0;
242 qp->rq.wqe_cnt = 0;
243 qp->rq.wqe_shift = 0;
0540d814
NO		 244 cap->max_recv_wr = 0;
245 cap->max_recv_sge = 0;
e126ba97
EC		 246 } else {
247 if (ucmd) {
248 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
250 return -EINVAL;
e126ba97 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
002bf228
LR		 252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
253 return -EINVAL;
e126ba97
EC		 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
255 qp->rq.max_post = qp->rq.wqe_cnt;
256 } else {
257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
259 wqe_size = roundup_pow_of_two(wqe_size);
260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
262 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
265 wqe_size,
938fe83c
SM		 266 MLX5_CAP_GEN(dev->mdev,
267 max_wqe_sz_rq));
e126ba97
EC		 268 return -EINVAL;
269 }
270 qp->rq.wqe_shift = ilog2(wqe_size);
271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
272 qp->rq.max_post = qp->rq.wqe_cnt;
273 }
274 }
275
276 return 0;
277}
278
f0313965 279static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 280{
618af384 281 int size = 0;
e126ba97 282
f0313965 283 switch (attr->qp_type) {
e126ba97 284 case IB_QPT_XRC_INI:
b125a54b 285 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 286 /* fall through */
287 case IB_QPT_RC:
288 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 289 max(sizeof(struct mlx5_wqe_atomic_seg) +
290 sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 292 sizeof(struct mlx5_mkey_seg) +
293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
294 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 295 break;
296
b125a54b
EC		 297 case IB_QPT_XRC_TGT:
298 return 0;
299
e126ba97 300 case IB_QPT_UC:
b125a54b 301 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 302 max(sizeof(struct mlx5_wqe_raddr_seg),
303 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
304 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 305 break;
306
307 case IB_QPT_UD:
f0313965
ES		 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
309 size += sizeof(struct mlx5_wqe_eth_pad) +
310 sizeof(struct mlx5_wqe_eth_seg);
311 /* fall through */
e126ba97 312 case IB_QPT_SMI:
d16e91da 313 case MLX5_IB_QPT_HW_GSI:
b125a54b 314 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 315 sizeof(struct mlx5_wqe_datagram_seg);
316 break;
317
318 case MLX5_IB_QPT_REG_UMR:
b125a54b 319 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
321 sizeof(struct mlx5_mkey_seg);
322 break;
323
324 default:
325 return -EINVAL;
326 }
327
328 return size;
329}
330
331static int calc_send_wqe(struct ib_qp_init_attr *attr)
332{
333 int inl_size = 0;
334 int size;
335
f0313965 336 size = sq_overhead(attr);
e126ba97
EC		 337 if (size < 0)
338 return size;
339
340 if (attr->cap.max_inline_data) {
341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
342 attr->cap.max_inline_data;
343 }
344
345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
348 return MLX5_SIG_WQE_SIZE;
349 else
350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 351}
352
288c01b7
EC		 353static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
354{
355 int max_sge;
356
357 if (attr->qp_type == IB_QPT_RC)
358 max_sge = (min_t(int, wqe_size, 512) -
359 sizeof(struct mlx5_wqe_ctrl_seg) -
360 sizeof(struct mlx5_wqe_raddr_seg)) /
361 sizeof(struct mlx5_wqe_data_seg);
362 else if (attr->qp_type == IB_QPT_XRC_INI)
363 max_sge = (min_t(int, wqe_size, 512) -
364 sizeof(struct mlx5_wqe_ctrl_seg) -
365 sizeof(struct mlx5_wqe_xrc_seg) -
366 sizeof(struct mlx5_wqe_raddr_seg)) /
367 sizeof(struct mlx5_wqe_data_seg);
368 else
369 max_sge = (wqe_size - sq_overhead(attr)) /
370 sizeof(struct mlx5_wqe_data_seg);
371
372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
373 sizeof(struct mlx5_wqe_data_seg));
374}
375
e126ba97
EC		 376static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
377 struct mlx5_ib_qp *qp)
378{
379 int wqe_size;
380 int wq_size;
381
382 if (!attr->cap.max_send_wr)
383 return 0;
384
385 wqe_size = calc_send_wqe(attr);
386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
387 if (wqe_size < 0)
388 return wqe_size;
389
938fe83c 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 393 return -EINVAL;
394 }
395
f0313965
ES		 396 qp->max_inline_data = wqe_size - sq_overhead(attr) -
397 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 398 attr->cap.max_inline_data = qp->max_inline_data;
399
e1e66cc2
SG		 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
401 qp->signature_en = true;
402
e126ba97
EC		 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 408 qp->sq.wqe_cnt,
409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 410 return -ENOMEM;
411 }
e126ba97 412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 413 qp->sq.max_gs = get_send_sge(attr, wqe_size);
414 if (qp->sq.max_gs < attr->cap.max_send_sge)
415 return -ENOMEM;
416
417 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 418 qp->sq.max_post = wq_size / wqe_size;
419 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 420
421 return wq_size;
422}
423
424static int set_user_buf_size(struct mlx5_ib_dev *dev,
425 struct mlx5_ib_qp *qp,
19098df2 426 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 427 struct mlx5_ib_qp_base *base,
428 struct ib_qp_init_attr *attr)
e126ba97
EC		 429{
430 int desc_sz = 1 << qp->sq.wqe_shift;
431
938fe83c 432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 435 return -EINVAL;
436 }
437
438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
440 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
441 return -EINVAL;
442 }
443
444 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
445
938fe83c 446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 448 qp->sq.wqe_cnt,
449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 450 return -EINVAL;
451 }
452
c2e53b2c
YH		 453 if (attr->qp_type == IB_QPT_RAW_PACKET ||
454 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
457 } else {
458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
459 (qp->sq.wqe_cnt << 6);
460 }
e126ba97
EC		 461
462 return 0;
463}
464
465static int qp_has_rq(struct ib_qp_init_attr *attr)
466{
467 if (attr->qp_type == IB_QPT_XRC_INI ||
468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
469 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
470 !attr->cap.max_recv_wr)
471 return 0;
472
473 return 1;
474}
475
0b80c14f
EC		 476enum {
477 /* this is the first blue flame register in the array of bfregs assigned
478 * to a processes. Since we do not use it for blue flame but rather
479 * regular 64 bit doorbells, we do not need a lock for maintaiing
480 * "odd/even" order
481 */
482 NUM_NON_BLUE_FLAME_BFREGS = 1,
483};
484
b037c29a
EC		 485static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
486{
31a78a5a 487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 488}
489
490static int num_med_bfreg(struct mlx5_ib_dev *dev,
491 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 492{
493 int n;
494
b037c29a
EC		 495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
496 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 497
498 return n >= 0 ? n : 0;
499}
500
18b0362e
YH		 501static int first_med_bfreg(struct mlx5_ib_dev *dev,
502 struct mlx5_bfreg_info *bfregi)
503{
504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
505}
506
b037c29a
EC		 507static int first_hi_bfreg(struct mlx5_ib_dev *dev,
508 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 509{
510 int med;
c1be5232 511
b037c29a
EC		 512 med = num_med_bfreg(dev, bfregi);
513 return ++med;
c1be5232
EC		 514}
515
b037c29a
EC		 516static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
517 struct mlx5_bfreg_info *bfregi)
e126ba97 518{
e126ba97
EC		 519 int i;
520
b037c29a
EC		 521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
522 if (!bfregi->count[i]) {
2f5ff264 523 bfregi->count[i]++;
e126ba97
EC		 524 return i;
525 }
526 }
527
528 return -ENOMEM;
529}
530
b037c29a
EC		 531static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
532 struct mlx5_bfreg_info *bfregi)
e126ba97 533{
18b0362e 534 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 535 int i;
536
18b0362e
YH		 537 if (minidx < 0)
538 return minidx;
539
540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 541 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 542 minidx = i;
0b80c14f
EC		 543 if (!bfregi->count[minidx])
544 break;
e126ba97
EC		 545 }
546
2f5ff264 547 bfregi->count[minidx]++;
e126ba97
EC		 548 return minidx;
549}
550
b037c29a 551static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 552 struct mlx5_bfreg_info *bfregi)
e126ba97 553{
ffaf58de 554 int bfregn = -ENOMEM;
e126ba97 555
2f5ff264 556 mutex_lock(&bfregi->lock);
ffaf58de
LR		 557 if (bfregi->ver >= 2) {
558 bfregn = alloc_high_class_bfreg(dev, bfregi);
559 if (bfregn < 0)
560 bfregn = alloc_med_class_bfreg(dev, bfregi);
561 }
562
563 if (bfregn < 0) {
0b80c14f 564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 565 bfregn = 0;
566 bfregi->count[bfregn]++;
e126ba97 567 }
2f5ff264 568 mutex_unlock(&bfregi->lock);
e126ba97 569
2f5ff264 570 return bfregn;
e126ba97
EC		 571}
572
4ed131d0 573void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 574{
2f5ff264 575 mutex_lock(&bfregi->lock);
b037c29a 576 bfregi->count[bfregn]--;
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97
EC		 578}
579
580static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
581{
582 switch (state) {
583 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
590 default: return -1;
591 }
592}
593
594static int to_mlx5_st(enum ib_qp_type type)
595{
596 switch (type) {
597 case IB_QPT_RC: return MLX5_QP_ST_RC;
598 case IB_QPT_UC: return MLX5_QP_ST_UC;
599 case IB_QPT_UD: return MLX5_QP_ST_UD;
600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
601 case IB_QPT_XRC_INI:
602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
603 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 607 case IB_QPT_RAW_PACKET:
0fb2ed66 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 609 case IB_QPT_MAX:
610 default: return -EINVAL;
611 }
612}
613
89ea94a7
MG		 614static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
615 struct mlx5_ib_cq *recv_cq);
616static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
618
7c043e90 619int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 620 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 621 bool dyn_bfreg)
e126ba97 622{
05f58ceb
LR		 623 unsigned int bfregs_per_sys_page;
624 u32 index_of_sys_page;
625 u32 offset;
b037c29a
EC		 626
627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
628 MLX5_NON_FP_BFREGS_PER_UAR;
629 index_of_sys_page = bfregn / bfregs_per_sys_page;
630
1ee47ab3
YH		 631 if (dyn_bfreg) {
632 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 633
634 if (index_of_sys_page >= bfregi->num_sys_pages)
635 return -EINVAL;
636
1ee47ab3
YH		 637 if (bfregn > bfregi->num_dyn_bfregs ||
638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
640 return -EINVAL;
641 }
642 }
b037c29a 643
1ee47ab3 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 645 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 646}
647
b0ea0fa5 648static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
19098df2 649 unsigned long addr, size_t size,
b0ea0fa5
JG		 650 struct ib_umem **umem, int *npages, int *page_shift,
651 int *ncont, u32 *offset)
19098df2 652{
653 int err;
654
b0ea0fa5 655 *umem = ib_umem_get(udata, addr, size, 0, 0);
19098df2 656 if (IS_ERR(*umem)) {
657 mlx5_ib_dbg(dev, "umem_get failed\n");
658 return PTR_ERR(*umem);
659 }
660
762f899a 661 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 662
663 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
664 if (err) {
665 mlx5_ib_warn(dev, "bad offset\n");
666 goto err_umem;
667 }
668
669 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
670 addr, size, *npages, *page_shift, *ncont, *offset);
671
672 return 0;
673
674err_umem:
675 ib_umem_release(*umem);
676 *umem = NULL;
677
678 return err;
679}
680
fe248c3a
MG		 681static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
682 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 683{
684 struct mlx5_ib_ucontext *context;
685
fe248c3a
MG		 686 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
687 atomic_dec(&dev->delay_drop.rqs_cnt);
688
79b20a6c
YH		 689 context = to_mucontext(pd->uobject->context);
690 mlx5_ib_db_unmap_user(context, &rwq->db);
691 if (rwq->umem)
692 ib_umem_release(rwq->umem);
693}
694
695static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
b0ea0fa5 696 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
79b20a6c
YH		 697 struct mlx5_ib_create_wq *ucmd)
698{
79b20a6c
YH		 699 int page_shift = 0;
700 int npages;
701 u32 offset = 0;
702 int ncont = 0;
703 int err;
704
705 if (!ucmd->buf_addr)
706 return -EINVAL;
707
b0ea0fa5 708 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
79b20a6c
YH		 709 if (IS_ERR(rwq->umem)) {
710 mlx5_ib_dbg(dev, "umem_get failed\n");
711 err = PTR_ERR(rwq->umem);
712 return err;
713 }
714
762f899a 715 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 716 &ncont, NULL);
717 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
718 &rwq->rq_page_offset);
719 if (err) {
720 mlx5_ib_warn(dev, "bad offset\n");
721 goto err_umem;
722 }
723
724 rwq->rq_num_pas = ncont;
725 rwq->page_shift = page_shift;
726 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
727 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
728
729 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
730 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
731 npages, page_shift, ncont, offset);
732
b0ea0fa5
JG		 733 err = mlx5_ib_db_map_user(to_mucontext(pd->uobject->context), udata,
734 ucmd->db_addr, &rwq->db);
79b20a6c
YH		 735 if (err) {
736 mlx5_ib_dbg(dev, "map failed\n");
737 goto err_umem;
738 }
739
740 rwq->create_type = MLX5_WQ_USER;
741 return 0;
742
743err_umem:
744 ib_umem_release(rwq->umem);
745 return err;
746}
747
b037c29a
EC		 748static int adjust_bfregn(struct mlx5_ib_dev *dev,
749 struct mlx5_bfreg_info *bfregi, int bfregn)
750{
751 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
752 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
753}
754
e126ba97
EC		 755static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
756 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 757 struct ib_qp_init_attr *attr,
09a7d9ec 758 u32 **in,
19098df2 759 struct mlx5_ib_create_qp_resp *resp, int *inlen,
760 struct mlx5_ib_qp_base *base)
e126ba97
EC		 761{
762 struct mlx5_ib_ucontext *context;
763 struct mlx5_ib_create_qp ucmd;
19098df2 764 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 765 int page_shift = 0;
1ee47ab3 766 int uar_index = 0;
e126ba97 767 int npages;
9e9c47d0 768 u32 offset = 0;
2f5ff264 769 int bfregn;
9e9c47d0 770 int ncont = 0;
09a7d9ec
SM		 771 __be64 *pas;
772 void *qpc;
e126ba97 773 int err;
5aa3771d 774 u16 uid;
e126ba97
EC		 775
776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
777 if (err) {
778 mlx5_ib_dbg(dev, "copy failed\n");
779 return err;
780 }
781
782 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 783 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
784 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
785 ucmd.bfreg_index, true);
786 if (uar_index < 0)
787 return uar_index;
788
789 bfregn = MLX5_IB_INVALID_BFREG;
790 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
791 /*
792 * TBD: should come from the verbs when we have the API
793 */
051f2630 794 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 795 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 796 }
051f2630 797 else {
ffaf58de
LR		 798 bfregn = alloc_bfreg(dev, &context->bfregi);
799 if (bfregn < 0)
800 return bfregn;
e126ba97
EC		 801 }
802
2f5ff264 803 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 804 if (bfregn != MLX5_IB_INVALID_BFREG)
805 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
806 false);
e126ba97 807
48fea837
HE		 808 qp->rq.offset = 0;
809 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
810 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
811
0fb2ed66 812 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 813 if (err)
2f5ff264 814 goto err_bfreg;
e126ba97 815
19098df2 816 if (ucmd.buf_addr && ubuffer->buf_size) {
817 ubuffer->buf_addr = ucmd.buf_addr;
b0ea0fa5
JG		 818 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
819 ubuffer->buf_size, &ubuffer->umem,
820 &npages, &page_shift, &ncont, &offset);
19098df2 821 if (err)
2f5ff264 822 goto err_bfreg;
9e9c47d0 823 } else {
19098df2 824 ubuffer->umem = NULL;
e126ba97 825 }
e126ba97 826
09a7d9ec
SM		 827 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
828 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 829 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 830 if (!*in) {
831 err = -ENOMEM;
832 goto err_umem;
833 }
09a7d9ec 834
7422edce
YH		 835 uid = (attr->qp_type != IB_QPT_XRC_TGT &&
836 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
5aa3771d 837 MLX5_SET(create_qp_in, *in, uid, uid);
09a7d9ec 838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 839 if (ubuffer->umem)
09a7d9ec
SM		 840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
841
842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
843
844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
845 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 846
09a7d9ec 847 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 848 if (bfregn != MLX5_IB_INVALID_BFREG)
849 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
850 else
851 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 852 qp->bfregn = bfregn;
e126ba97 853
b0ea0fa5 854 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
e126ba97
EC		 855 if (err) {
856 mlx5_ib_dbg(dev, "map failed\n");
857 goto err_free;
858 }
859
41d902cb 860 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
e126ba97
EC		 861 if (err) {
862 mlx5_ib_dbg(dev, "copy failed\n");
863 goto err_unmap;
864 }
865 qp->create_type = MLX5_QP_USER;
866
867 return 0;
868
869err_unmap:
870 mlx5_ib_db_unmap_user(context, &qp->db);
871
872err_free:
479163f4 873 kvfree(*in);
e126ba97
EC		 874
875err_umem:
19098df2 876 if (ubuffer->umem)
877 ib_umem_release(ubuffer->umem);
e126ba97 878
2f5ff264 879err_bfreg:
1ee47ab3
YH		 880 if (bfregn != MLX5_IB_INVALID_BFREG)
881 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 882 return err;
883}
884
b037c29a
EC		 885static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
886 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 887{
888 struct mlx5_ib_ucontext *context;
889
890 context = to_mucontext(pd->uobject->context);
891 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 892 if (base->ubuffer.umem)
893 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 894
895 /*
896 * Free only the BFREGs which are handled by the kernel.
897 * BFREGs of UARs allocated dynamically are handled by user.
898 */
899 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
900 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 901}
902
34f4c955
GL		 903/* get_sq_edge - Get the next nearby edge.
904 *
905 * An 'edge' is defined as the first following address after the end
906 * of the fragment or the SQ. Accordingly, during the WQE construction
907 * which repetitively increases the pointer to write the next data, it
908 * simply should check if it gets to an edge.
909 *
910 * @sq - SQ buffer.
911 * @idx - Stride index in the SQ buffer.
912 *
913 * Return:
914 * The new edge.
915 */
916static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
917{
918 void *fragment_end;
919
920 fragment_end = mlx5_frag_buf_get_wqe
921 (&sq->fbc,
922 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
923
924 return fragment_end + MLX5_SEND_WQE_BB;
925}
926
e126ba97
EC		 927static int create_kernel_qp(struct mlx5_ib_dev *dev,
928 struct ib_qp_init_attr *init_attr,
929 struct mlx5_ib_qp *qp,
09a7d9ec 930 u32 **in, int *inlen,
19098df2 931 struct mlx5_ib_qp_base *base)
e126ba97 932{
e126ba97 933 int uar_index;
09a7d9ec 934 void *qpc;
e126ba97
EC		 935 int err;
936
f0313965
ES		 937 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
938 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 939 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 940 IB_QP_CREATE_NETIF_QP |
b11a4f9c 941 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 942 return -EINVAL;
e126ba97
EC		 943
944 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 945 qp->bf.bfreg = &dev->fp_bfreg;
946 else
947 qp->bf.bfreg = &dev->bfreg;
e126ba97 948
d8030b0d
EC		 949 /* We need to divide by two since each register is comprised of
950 * two buffers of identical size, namely odd and even
951 */
952 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 953 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 954
955 err = calc_sq_size(dev, init_attr, qp);
956 if (err < 0) {
957 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 958 return err;
e126ba97
EC		 959 }
960
961 qp->rq.offset = 0;
962 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 963 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 964
34f4c955
GL		 965 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
966 &qp->buf, dev->mdev->priv.numa_node);
e126ba97
EC		 967 if (err) {
968 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 969 return err;
e126ba97
EC		 970 }
971
34f4c955
GL		 972 if (qp->rq.wqe_cnt)
973 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
974 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
975
976 if (qp->sq.wqe_cnt) {
977 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
978 MLX5_SEND_WQE_BB;
979 mlx5_init_fbc_offset(qp->buf.frags +
980 (qp->sq.offset / PAGE_SIZE),
981 ilog2(MLX5_SEND_WQE_BB),
982 ilog2(qp->sq.wqe_cnt),
983 sq_strides_offset, &qp->sq.fbc);
984
985 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
986 }
987
09a7d9ec
SM		 988 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
989 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 990 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 991 if (!*in) {
992 err = -ENOMEM;
993 goto err_buf;
994 }
09a7d9ec
SM		 995
996 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
997 MLX5_SET(qpc, qpc, uar_page, uar_index);
998 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
999
e126ba97 1000 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 1001 MLX5_SET(qpc, qpc, fre, 1);
1002 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 1003
b11a4f9c 1004 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 1005 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 1006 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1007 }
1008
34f4c955
GL		 1009 mlx5_fill_page_frag_array(&qp->buf,
1010 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1011 *in, pas));
e126ba97 1012
9603b61d 1013 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 1014 if (err) {
1015 mlx5_ib_dbg(dev, "err %d\n", err);
1016 goto err_free;
1017 }
1018
b5883008
LD		 1019 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1020 sizeof(*qp->sq.wrid), GFP_KERNEL);
1021 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1022 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1023 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1024 sizeof(*qp->rq.wrid), GFP_KERNEL);
1025 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1026 sizeof(*qp->sq.w_list), GFP_KERNEL);
1027 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1028 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1029
1030 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1031 !qp->sq.w_list || !qp->sq.wqe_head) {
1032 err = -ENOMEM;
1033 goto err_wrid;
1034 }
1035 qp->create_type = MLX5_QP_KERNEL;
1036
1037 return 0;
1038
1039err_wrid:
b5883008
LD		 1040 kvfree(qp->sq.wqe_head);
1041 kvfree(qp->sq.w_list);
1042 kvfree(qp->sq.wrid);
1043 kvfree(qp->sq.wr_data);
1044 kvfree(qp->rq.wrid);
f4044dac 1045 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1046
1047err_free:
479163f4 1048 kvfree(*in);
e126ba97
EC		 1049
1050err_buf:
34f4c955 1051 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1052 return err;
1053}
1054
1055static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1056{
b5883008
LD		 1057 kvfree(qp->sq.wqe_head);
1058 kvfree(qp->sq.w_list);
1059 kvfree(qp->sq.wrid);
1060 kvfree(qp->sq.wr_data);
1061 kvfree(qp->rq.wrid);
f4044dac 1062 mlx5_db_free(dev->mdev, &qp->db);
34f4c955 1063 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1064}
1065
09a7d9ec 1066static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1067{
1068 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1069 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1070 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1071 return MLX5_SRQ_RQ;
e126ba97 1072 else if (!qp->has_rq)
09a7d9ec 1073 return MLX5_ZERO_LEN_RQ;
e126ba97 1074 else
09a7d9ec 1075 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1076}
1077
1078static int is_connected(enum ib_qp_type qp_type)
1079{
5d6ff1ba
YC		 1080 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1081 qp_type == MLX5_IB_QPT_DCI)
e126ba97
EC		 1082 return 1;
1083
1084 return 0;
1085}
1086
0fb2ed66 1087static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1088 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1089 struct mlx5_ib_sq *sq, u32 tdn,
1090 struct ib_pd *pd)
0fb2ed66 1091{
c4f287c4 1092 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1093 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1094
1cd6dbd3 1095 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1096 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1097 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1098 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1099
0fb2ed66 1100 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1101}
1102
1103static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1104 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1105{
1cd6dbd3 1106 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1107}
1108
b96c9dde
MB		 1109static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1110 struct mlx5_ib_sq *sq)
1111{
1112 if (sq->flow_rule)
1113 mlx5_del_flow_rules(sq->flow_rule);
1114}
1115
0fb2ed66 1116static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
b0ea0fa5 1117 struct ib_udata *udata,
0fb2ed66 1118 struct mlx5_ib_sq *sq, void *qpin,
1119 struct ib_pd *pd)
1120{
1121 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1122 __be64 *pas;
1123 void *in;
1124 void *sqc;
1125 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1126 void *wq;
1127 int inlen;
1128 int err;
1129 int page_shift = 0;
1130 int npages;
1131 int ncont = 0;
1132 u32 offset = 0;
1133
b0ea0fa5
JG		 1134 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1135 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1136 &offset);
0fb2ed66 1137 if (err)
1138 return err;
1139
1140 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1141 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1142 if (!in) {
1143 err = -ENOMEM;
1144 goto err_umem;
1145 }
1146
c14003f0 1147 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1148 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1149 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1150 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1151 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1152 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1153 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1154 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1155 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1156 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1157 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1158 MLX5_CAP_ETH(dev->mdev, swp))
1159 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1160
1161 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1162 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1163 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1164 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1165 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1166 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1167 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1168 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1169 MLX5_SET(wq, wq, page_offset, offset);
1170
1171 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1172 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1173
1174 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1175
1176 kvfree(in);
1177
1178 if (err)
1179 goto err_umem;
1180
b96c9dde
MB		 1181 err = create_flow_rule_vport_sq(dev, sq);
1182 if (err)
1183 goto err_flow;
1184
0fb2ed66 1185 return 0;
1186
b96c9dde
MB		 1187err_flow:
1188 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1189
0fb2ed66 1190err_umem:
1191 ib_umem_release(sq->ubuffer.umem);
1192 sq->ubuffer.umem = NULL;
1193
1194 return err;
1195}
1196
1197static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1198 struct mlx5_ib_sq *sq)
1199{
b96c9dde 1200 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1201 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1202 ib_umem_release(sq->ubuffer.umem);
1203}
1204
2c292dbb 1205static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1206{
1207 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1208 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1209 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1210 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1211 u32 po_quanta = 1 << (log_page_size - 6);
1212 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1213 u32 page_size = 1 << log_page_size;
1214 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1215 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1216
1217 return rq_num_pas * sizeof(u64);
1218}
1219
1220static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1221 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1222 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1223{
358e42ea 1224 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1225 __be64 *pas;
1226 __be64 *qp_pas;
1227 void *in;
1228 void *rqc;
1229 void *wq;
1230 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1231 size_t rq_pas_size = get_rq_pas_size(qpc);
1232 size_t inlen;
0fb2ed66 1233 int err;
2c292dbb
BP		 1234
1235 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1236 return -EINVAL;
0fb2ed66 1237
1238 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1239 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1240 if (!in)
1241 return -ENOMEM;
1242
34d57585 1243 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1244 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1245 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1246 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1247 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1248 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1249 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1250 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1251 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1252
358e42ea
MD		 1253 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1254 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1255
0fb2ed66 1256 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1257 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1258 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1259 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1260 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1261 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1262 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1263 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1264 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1265 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1266
1267 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1268 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1269 memcpy(pas, qp_pas, rq_pas_size);
1270
1271 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1272
1273 kvfree(in);
1274
1275 return err;
1276}
1277
1278static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1279 struct mlx5_ib_rq *rq)
1280{
1281 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1282}
1283
f95ef6cb
MG		 1284static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1285{
1286 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1287 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1288 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1289}
1290
0042f9e4
MB		 1291static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1292 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1293 u32 qp_flags_en,
1294 struct ib_pd *pd)
0042f9e4
MB		 1295{
1296 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1297 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1298 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1299 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1300}
1301
0fb2ed66 1302static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1303 struct mlx5_ib_rq *rq, u32 tdn,
443c1cf9
YH		 1304 u32 *qp_flags_en,
1305 struct ib_pd *pd)
0fb2ed66 1306{
175edba8 1307 u8 lb_flag = 0;
0fb2ed66 1308 u32 *in;
1309 void *tirc;
1310 int inlen;
1311 int err;
1312
1313 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1314 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1315 if (!in)
1316 return -ENOMEM;
1317
443c1cf9 1318 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1319 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1320 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1321 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1322 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1323 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1324 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1325
175edba8
MB		 1326 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1327 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1328
1329 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1330 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1331
1332 if (dev->rep) {
1333 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1334 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1335 }
1336
1337 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
ec9c2fb8 1338
0fb2ed66 1339 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1340
0042f9e4
MB		 1341 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1342 err = mlx5_ib_enable_lb(dev, false, true);
1343
1344 if (err)
443c1cf9 1345 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1346 }
0fb2ed66 1347 kvfree(in);
1348
1349 return err;
1350}
1351
0fb2ed66 1352static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1353 u32 *in, size_t inlen,
7f72052c
YH		 1354 struct ib_pd *pd,
1355 struct ib_udata *udata,
1356 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1357{
1358 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1359 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1360 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1361 struct ib_uobject *uobj = pd->uobject;
1362 struct ib_ucontext *ucontext = uobj->context;
1363 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1364 int err;
1365 u32 tdn = mucontext->tdn;
7f72052c 1366 u16 uid = to_mpd(pd)->uid;
0fb2ed66 1367
1368 if (qp->sq.wqe_cnt) {
1cd6dbd3 1369 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1370 if (err)
1371 return err;
1372
b0ea0fa5 1373 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
0fb2ed66 1374 if (err)
1375 goto err_destroy_tis;
1376
7f72052c
YH		 1377 if (uid) {
1378 resp->tisn = sq->tisn;
1379 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1380 resp->sqn = sq->base.mqp.qpn;
1381 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1382 }
1383
0fb2ed66 1384 sq->base.container_mibqp = qp;
1d31e9c0 1385 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1386 }
1387
1388 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1389 rq->base.container_mibqp = qp;
1390
e4cc4fa7
NO		 1391 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1392 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1393 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1394 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1395 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1396 if (err)
1397 goto err_destroy_sq;
1398
443c1cf9 1399 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
0fb2ed66 1400 if (err)
1401 goto err_destroy_rq;
7f72052c
YH		 1402
1403 if (uid) {
1404 resp->rqn = rq->base.mqp.qpn;
1405 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1406 resp->tirn = rq->tirn;
1407 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1408 }
0fb2ed66 1409 }
1410
1411 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1412 rq->base.mqp.qpn;
7f72052c
YH		 1413 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1414 if (err)
1415 goto err_destroy_tir;
0fb2ed66 1416
1417 return 0;
1418
7f72052c
YH		 1419err_destroy_tir:
1420 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
0fb2ed66 1421err_destroy_rq:
1422 destroy_raw_packet_qp_rq(dev, rq);
1423err_destroy_sq:
1424 if (!qp->sq.wqe_cnt)
1425 return err;
1426 destroy_raw_packet_qp_sq(dev, sq);
1427err_destroy_tis:
1cd6dbd3 1428 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1429
1430 return err;
1431}
1432
1433static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1434 struct mlx5_ib_qp *qp)
1435{
1436 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1437 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1438 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1439
1440 if (qp->rq.wqe_cnt) {
443c1cf9 1441 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1442 destroy_raw_packet_qp_rq(dev, rq);
1443 }
1444
1445 if (qp->sq.wqe_cnt) {
1446 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1447 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1448 }
1449}
1450
1451static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1452 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1453{
1454 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1455 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1456
1457 sq->sq = &qp->sq;
1458 rq->rq = &qp->rq;
1459 sq->doorbell = &qp->db;
1460 rq->doorbell = &qp->db;
1461}
1462
28d61370
YH		 1463static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1464{
0042f9e4
MB		 1465 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1466 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1467 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1468 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1469 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1470}
1471
1472static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1473 struct ib_pd *pd,
1474 struct ib_qp_init_attr *init_attr,
1475 struct ib_udata *udata)
1476{
1477 struct ib_uobject *uobj = pd->uobject;
1478 struct ib_ucontext *ucontext = uobj->context;
1479 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1480 struct mlx5_ib_create_qp_resp resp = {};
1481 int inlen;
1482 int err;
1483 u32 *in;
1484 void *tirc;
1485 void *hfso;
1486 u32 selected_fields = 0;
2d93fc85 1487 u32 outer_l4;
28d61370
YH		 1488 size_t min_resp_len;
1489 u32 tdn = mucontext->tdn;
1490 struct mlx5_ib_create_qp_rss ucmd = {};
1491 size_t required_cmd_sz;
175edba8 1492 u8 lb_flag = 0;
28d61370
YH		 1493
1494 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1495 return -EOPNOTSUPP;
1496
1497 if (init_attr->create_flags || init_attr->send_cq)
1498 return -EINVAL;
1499
2f5ff264 1500 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1501 if (udata->outlen < min_resp_len)
1502 return -EINVAL;
1503
f95ef6cb 1504 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1505 if (udata->inlen < required_cmd_sz) {
1506 mlx5_ib_dbg(dev, "invalid inlen\n");
1507 return -EINVAL;
1508 }
1509
1510 if (udata->inlen > sizeof(ucmd) &&
1511 !ib_is_udata_cleared(udata, sizeof(ucmd),
1512 udata->inlen - sizeof(ucmd))) {
1513 mlx5_ib_dbg(dev, "inlen is not supported\n");
1514 return -EOPNOTSUPP;
1515 }
1516
1517 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1518 mlx5_ib_dbg(dev, "copy failed\n");
1519 return -EFAULT;
1520 }
1521
1522 if (ucmd.comp_mask) {
1523 mlx5_ib_dbg(dev, "invalid comp mask\n");
1524 return -EOPNOTSUPP;
1525 }
1526
175edba8
MB		 1527 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1528 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1529 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
f95ef6cb
MG		 1530 mlx5_ib_dbg(dev, "invalid flags\n");
1531 return -EOPNOTSUPP;
1532 }
1533
1534 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1535 !tunnel_offload_supported(dev->mdev)) {
1536 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1537 return -EOPNOTSUPP;
1538 }
1539
309fa347
MG		 1540 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1541 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1542 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1543 return -EOPNOTSUPP;
1544 }
1545
175edba8
MB		 1546 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1547 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1548 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1549 }
1550
1551 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1552 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1553 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1554 }
1555
41d902cb 1556 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
28d61370
YH		 1557 if (err) {
1558 mlx5_ib_dbg(dev, "copy failed\n");
1559 return -EINVAL;
1560 }
1561
1562 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1563 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1564 if (!in)
1565 return -ENOMEM;
1566
443c1cf9 1567 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1568 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1569 MLX5_SET(tirc, tirc, disp_type,
1570 MLX5_TIRC_DISP_TYPE_INDIRECT);
1571 MLX5_SET(tirc, tirc, indirect_table,
1572 init_attr->rwq_ind_tbl->ind_tbl_num);
1573 MLX5_SET(tirc, tirc, transport_domain, tdn);
1574
1575 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1576
1577 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1578 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1579
175edba8
MB		 1580 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1581
309fa347
MG		 1582 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1583 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1584 else
1585 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1586
28d61370
YH		 1587 switch (ucmd.rx_hash_function) {
1588 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1589 {
1590 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1591 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1592
1593 if (len != ucmd.rx_key_len) {
1594 err = -EINVAL;
1595 goto err;
1596 }
1597
1598 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1599 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1600 memcpy(rss_key, ucmd.rx_hash_key, len);
1601 break;
1602 }
1603 default:
1604 err = -EOPNOTSUPP;
1605 goto err;
1606 }
1607
1608 if (!ucmd.rx_hash_fields_mask) {
1609 /* special case when this TIR serves as steering entry without hashing */
1610 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1611 goto create_tir;
1612 err = -EINVAL;
1613 goto err;
1614 }
1615
1616 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1617 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1618 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1619 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1620 err = -EINVAL;
1621 goto err;
1622 }
1623
1624 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1625 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1626 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1627 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1628 MLX5_L3_PROT_TYPE_IPV4);
1629 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1630 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1631 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1632 MLX5_L3_PROT_TYPE_IPV6);
1633
2d93fc85
MB		 1634 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1635 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1636 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1637 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1638 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1639
1640 /* Check that only one l4 protocol is set */
1641 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1642 err = -EINVAL;
1643 goto err;
1644 }
1645
1646 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1647 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1648 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1649 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1650 MLX5_L4_PROT_TYPE_TCP);
1651 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1652 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1653 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1654 MLX5_L4_PROT_TYPE_UDP);
1655
1656 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1657 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1658 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1659
1660 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1661 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1662 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1663
1664 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1665 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1666 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1667
1668 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1669 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1670 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1671
2d93fc85
MB		 1672 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1673 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1674
28d61370
YH		 1675 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1676
1677create_tir:
1678 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1679
0042f9e4
MB		 1680 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1681 err = mlx5_ib_enable_lb(dev, false, true);
1682
1683 if (err)
443c1cf9
YH		 1684 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1685 to_mpd(pd)->uid);
0042f9e4
MB		 1686 }
1687
28d61370
YH		 1688 if (err)
1689 goto err;
1690
7f72052c
YH		 1691 if (mucontext->devx_uid) {
1692 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1693 resp.tirn = qp->rss_qp.tirn;
1694 }
1695
1696 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1697 if (err)
1698 goto err_copy;
1699
28d61370
YH		 1700 kvfree(in);
1701 /* qpn is reserved for that QP */
1702 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1703 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1704 return 0;
1705
7f72052c
YH		 1706err_copy:
1707 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
28d61370
YH		 1708err:
1709 kvfree(in);
1710 return err;
1711}
1712
5d6ff1ba
YC		 1713static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1714 void *qpc)
1715{
1716 int rcqe_sz;
1717
1718 if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1719 return;
1720
1721 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1722
1723 if (rcqe_sz == 128) {
1724 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1725 return;
1726 }
1727
1728 if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1729 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1730}
1731
1732static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1733 struct ib_qp_init_attr *init_attr,
6f4bc0ea 1734 struct mlx5_ib_create_qp *ucmd,
5d6ff1ba
YC		 1735 void *qpc)
1736{
1737 enum ib_qp_type qpt = init_attr->qp_type;
1738 int scqe_sz;
6f4bc0ea 1739 bool allow_scat_cqe = 0;
5d6ff1ba
YC		 1740
1741 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1742 return;
1743
6f4bc0ea
YC		 1744 if (ucmd)
1745 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1746
1747 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
5d6ff1ba
YC		 1748 return;
1749
1750 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1751 if (scqe_sz == 128) {
1752 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1753 return;
1754 }
1755
1756 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1757 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1758 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1759}
1760
a60109dc
YC		 1761static int atomic_size_to_mode(int size_mask)
1762{
1763 /* driver does not support atomic_size > 256B
1764 * and does not know how to translate bigger sizes
1765 */
1766 int supported_size_mask = size_mask & 0x1ff;
1767 int log_max_size;
1768
1769 if (!supported_size_mask)
1770 return -EOPNOTSUPP;
1771
1772 log_max_size = __fls(supported_size_mask);
1773
1774 if (log_max_size > 3)
1775 return log_max_size;
1776
1777 return MLX5_ATOMIC_MODE_8B;
1778}
1779
1780static int get_atomic_mode(struct mlx5_ib_dev *dev,
1781 enum ib_qp_type qp_type)
1782{
1783 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1784 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1785 int atomic_mode = -EOPNOTSUPP;
1786 int atomic_size_mask;
1787
1788 if (!atomic)
1789 return -EOPNOTSUPP;
1790
1791 if (qp_type == MLX5_IB_QPT_DCT)
1792 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1793 else
1794 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1795
1796 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1797 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1798 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1799
1800 if (atomic_mode <= 0 &&
1801 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1802 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1803 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1804
1805 return atomic_mode;
1806}
1807
2e43bb31
YC		 1808static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1809{
1810 return (input & ~supported) == 0;
1811}
1812
e126ba97
EC		 1813static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1814 struct ib_qp_init_attr *init_attr,
1815 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1816{
1817 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1818 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1819 struct mlx5_core_dev *mdev = dev->mdev;
0625b4ba 1820 struct mlx5_ib_create_qp_resp resp = {};
89ea94a7
MG		 1821 struct mlx5_ib_cq *send_cq;
1822 struct mlx5_ib_cq *recv_cq;
1823 unsigned long flags;
cfb5e088 1824 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1825 struct mlx5_ib_create_qp ucmd;
1826 struct mlx5_ib_qp_base *base;
e7b169f3 1827 int mlx5_st;
cfb5e088 1828 void *qpc;
09a7d9ec
SM		 1829 u32 *in;
1830 int err;
e126ba97
EC		 1831
1832 mutex_init(&qp->mutex);
1833 spin_lock_init(&qp->sq.lock);
1834 spin_lock_init(&qp->rq.lock);
1835
e7b169f3
NO		 1836 mlx5_st = to_mlx5_st(init_attr->qp_type);
1837 if (mlx5_st < 0)
1838 return -EINVAL;
1839
28d61370
YH		 1840 if (init_attr->rwq_ind_tbl) {
1841 if (!udata)
1842 return -ENOSYS;
1843
1844 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1845 return err;
1846 }
1847
f360d88a 1848 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1849 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1850 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1851 return -EINVAL;
1852 } else {
1853 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1854 }
1855 }
1856
051f2630
LR		 1857 if (init_attr->create_flags &
1858 (IB_QP_CREATE_CROSS_CHANNEL |
1859 IB_QP_CREATE_MANAGED_SEND |
1860 IB_QP_CREATE_MANAGED_RECV)) {
1861 if (!MLX5_CAP_GEN(mdev, cd)) {
1862 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1863 return -EINVAL;
1864 }
1865 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1866 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1867 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1868 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1869 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1870 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1871 }
f0313965
ES		 1872
1873 if (init_attr->qp_type == IB_QPT_UD &&
1874 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1875 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1876 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1877 return -EOPNOTSUPP;
1878 }
1879
358e42ea
MD		 1880 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1881 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1882 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1883 return -EOPNOTSUPP;
1884 }
1885 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1886 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1887 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1888 return -EOPNOTSUPP;
1889 }
1890 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1891 }
1892
e126ba97
EC		 1893 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1894 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1895
e4cc4fa7
NO		 1896 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1897 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1898 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1899 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1900 return -EOPNOTSUPP;
1901 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1902 }
1903
e00b64f7 1904 if (udata) {
e126ba97
EC		 1905 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1906 mlx5_ib_dbg(dev, "copy failed\n");
1907 return -EFAULT;
1908 }
1909
2e43bb31
YC		 1910 if (!check_flags_mask(ucmd.flags,
1911 MLX5_QP_FLAG_SIGNATURE |
1912 MLX5_QP_FLAG_SCATTER_CQE |
1913 MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1914 MLX5_QP_FLAG_BFREG_INDEX |
1915 MLX5_QP_FLAG_TYPE_DCT |
6f4bc0ea 1916 MLX5_QP_FLAG_TYPE_DCI |
569c6651
DG		 1917 MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
1918 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE))
2e43bb31
YC		 1919 return -EINVAL;
1920
cfb5e088
HA		 1921 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1922 &ucmd, udata->inlen, &uidx);
1923 if (err)
1924 return err;
1925
e126ba97 1926 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
5d6ff1ba
YC		 1927 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1928 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1929 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1930 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1931 !tunnel_offload_supported(mdev)) {
1932 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1933 return -EOPNOTSUPP;
1934 }
175edba8
MB		 1935 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1936 }
1937
1938 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1939 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1940 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1941 return -EOPNOTSUPP;
1942 }
1943 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1944 }
1945
1946 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1947 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1948 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1949 return -EOPNOTSUPP;
1950 }
1951 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
f95ef6cb 1952 }
c2e53b2c 1953
569c6651
DG		 1954 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
1955 if (init_attr->qp_type != IB_QPT_RC ||
1956 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
1957 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
1958 return -EOPNOTSUPP;
1959 }
1960 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
1961 }
1962
c2e53b2c
YH		 1963 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1964 if (init_attr->qp_type != IB_QPT_UD ||
1965 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1966 MLX5_CAP_PORT_TYPE_IB) ||
1967 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1968 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1969 return -EOPNOTSUPP;
1970 }
1971
1972 qp->flags |= MLX5_IB_QP_UNDERLAY;
1973 qp->underlay_qpn = init_attr->source_qpn;
1974 }
e126ba97
EC		 1975 } else {
1976 qp->wq_sig = !!wq_signature;
1977 }
1978
c2e53b2c
YH		 1979 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1980 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1981 &qp->raw_packet_qp.rq.base :
1982 &qp->trans_qp.base;
1983
e126ba97
EC		 1984 qp->has_rq = qp_has_rq(init_attr);
1985 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
e00b64f7 1986 qp, udata ? &ucmd : NULL);
e126ba97
EC		 1987 if (err) {
1988 mlx5_ib_dbg(dev, "err %d\n", err);
1989 return err;
1990 }
1991
1992 if (pd) {
e00b64f7 1993 if (udata) {
938fe83c
SM		 1994 __u32 max_wqes =
1995 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1996 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1997 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1998 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1999 mlx5_ib_dbg(dev, "invalid rq params\n");
2000 return -EINVAL;
2001 }
938fe83c 2002 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 2003 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 2004 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 2005 return -EINVAL;
2006 }
b11a4f9c
HE		 2007 if (init_attr->create_flags &
2008 mlx5_ib_create_qp_sqpn_qp1()) {
2009 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2010 return -EINVAL;
2011 }
0fb2ed66 2012 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2013 &resp, &inlen, base);
e126ba97
EC		 2014 if (err)
2015 mlx5_ib_dbg(dev, "err %d\n", err);
2016 } else {
19098df2 2017 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2018 base);
e126ba97
EC		 2019 if (err)
2020 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 2021 }
2022
2023 if (err)
2024 return err;
2025 } else {
1b9a07ee 2026 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 2027 if (!in)
2028 return -ENOMEM;
2029
2030 qp->create_type = MLX5_QP_EMPTY;
2031 }
2032
2033 if (is_sqp(init_attr->qp_type))
2034 qp->port = init_attr->port_num;
2035
09a7d9ec
SM		 2036 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2037
e7b169f3 2038 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 2039 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 2040
2041 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 2042 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 2043 else
09a7d9ec
SM		 2044 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2045
e126ba97
EC		 2046
2047 if (qp->wq_sig)
09a7d9ec 2048 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 2049
f360d88a 2050 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 2051 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 2052
051f2630 2053 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 2054 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 2055 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 2056 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 2057 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 2058 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
569c6651
DG		 2059 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2060 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
e126ba97 2061 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
5d6ff1ba 2062 configure_responder_scat_cqe(init_attr, qpc);
6f4bc0ea 2063 configure_requester_scat_cqe(dev, init_attr,
e00b64f7 2064 udata ? &ucmd : NULL,
6f4bc0ea 2065 qpc);
e126ba97
EC		 2066 }
2067
2068 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 2069 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2070 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 2071 }
2072
09a7d9ec 2073 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 2074
3fd3307e 2075 if (qp->sq.wqe_cnt) {
09a7d9ec 2076 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 2077 } else {
09a7d9ec 2078 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 2079 if (init_attr->srq &&
2080 init_attr->srq->srq_type == IB_SRQT_TM)
2081 MLX5_SET(qpc, qpc, offload_type,
2082 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2083 }
e126ba97
EC		 2084
2085 /* Set default resources */
2086 switch (init_attr->qp_type) {
2087 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 2088 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2089 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2090 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2091 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 2092 break;
2093 case IB_QPT_XRC_INI:
09a7d9ec
SM		 2094 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2095 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2096 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 2097 break;
2098 default:
2099 if (init_attr->srq) {
09a7d9ec
SM		 2100 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2101 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 2102 } else {
09a7d9ec
SM		 2103 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2104 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 2105 }
2106 }
2107
2108 if (init_attr->send_cq)
09a7d9ec 2109 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 2110
2111 if (init_attr->recv_cq)
09a7d9ec 2112 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 2113
09a7d9ec 2114 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 2115
09a7d9ec
SM		 2116 /* 0xffffff means we ask to work with cqe version 0 */
2117 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 2118 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 2119
f0313965
ES		 2120 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2121 if (init_attr->qp_type == IB_QPT_UD &&
2122 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 2123 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2124 qp->flags |= MLX5_IB_QP_LSO;
2125 }
cfb5e088 2126
b1383aa6
NO		 2127 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2128 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2129 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2130 err = -EOPNOTSUPP;
2131 goto err;
2132 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2133 MLX5_SET(qpc, qpc, end_padding_mode,
2134 MLX5_WQ_END_PAD_MODE_ALIGN);
2135 } else {
2136 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2137 }
2138 }
2139
2c292dbb
BP		 2140 if (inlen < 0) {
2141 err = -EINVAL;
2142 goto err;
2143 }
2144
c2e53b2c
YH		 2145 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2146 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2147 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2148 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c
YH		 2149 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2150 &resp);
0fb2ed66 2151 } else {
2152 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2153 }
2154
e126ba97
EC		 2155 if (err) {
2156 mlx5_ib_dbg(dev, "create qp failed\n");
2157 goto err_create;
2158 }
2159
479163f4 2160 kvfree(in);
e126ba97 2161
19098df2 2162 base->container_mibqp = qp;
2163 base->mqp.event = mlx5_ib_qp_event;
e126ba97 2164
89ea94a7
MG		 2165 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2166 &send_cq, &recv_cq);
2167 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2168 mlx5_ib_lock_cqs(send_cq, recv_cq);
2169 /* Maintain device to QPs access, needed for further handling via reset
2170 * flow
2171 */
2172 list_add_tail(&qp->qps_list, &dev->qp_list);
2173 /* Maintain CQ to QPs access, needed for further handling via reset flow
2174 */
2175 if (send_cq)
2176 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2177 if (recv_cq)
2178 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2179 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2180 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2181
e126ba97
EC		 2182 return 0;
2183
2184err_create:
2185 if (qp->create_type == MLX5_QP_USER)
b037c29a 2186 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 2187 else if (qp->create_type == MLX5_QP_KERNEL)
2188 destroy_qp_kernel(dev, qp);
2189
b1383aa6 2190err:
479163f4 2191 kvfree(in);
e126ba97
EC		 2192 return err;
2193}
2194
2195static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2196 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2197{
2198 if (send_cq) {
2199 if (recv_cq) {
2200 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2201 spin_lock(&send_cq->lock);
e126ba97
EC		 2202 spin_lock_nested(&recv_cq->lock,
2203 SINGLE_DEPTH_NESTING);
2204 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2205 spin_lock(&send_cq->lock);
e126ba97
EC		 2206 __acquire(&recv_cq->lock);
2207 } else {
89ea94a7 2208 spin_lock(&recv_cq->lock);
e126ba97
EC		 2209 spin_lock_nested(&send_cq->lock,
2210 SINGLE_DEPTH_NESTING);
2211 }
2212 } else {
89ea94a7 2213 spin_lock(&send_cq->lock);
6a4f139a 2214 __acquire(&recv_cq->lock);
e126ba97
EC		 2215 }
2216 } else if (recv_cq) {
89ea94a7 2217 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2218 __acquire(&send_cq->lock);
2219 } else {
2220 __acquire(&send_cq->lock);
2221 __acquire(&recv_cq->lock);
e126ba97
EC		 2222 }
2223}
2224
2225static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2226 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2227{
2228 if (send_cq) {
2229 if (recv_cq) {
2230 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2231 spin_unlock(&recv_cq->lock);
89ea94a7 2232 spin_unlock(&send_cq->lock);
e126ba97
EC		 2233 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2234 __release(&recv_cq->lock);
89ea94a7 2235 spin_unlock(&send_cq->lock);
e126ba97
EC		 2236 } else {
2237 spin_unlock(&send_cq->lock);
89ea94a7 2238 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2239 }
2240 } else {
6a4f139a 2241 __release(&recv_cq->lock);
89ea94a7 2242 spin_unlock(&send_cq->lock);
e126ba97
EC		 2243 }
2244 } else if (recv_cq) {
6a4f139a 2245 __release(&send_cq->lock);
89ea94a7 2246 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2247 } else {
2248 __release(&recv_cq->lock);
2249 __release(&send_cq->lock);
e126ba97
EC		 2250 }
2251}
2252
2253static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2254{
2255 return to_mpd(qp->ibqp.pd);
2256}
2257
89ea94a7
MG		 2258static void get_cqs(enum ib_qp_type qp_type,
2259 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2260 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2261{
89ea94a7 2262 switch (qp_type) {
e126ba97
EC		 2263 case IB_QPT_XRC_TGT:
2264 *send_cq = NULL;
2265 *recv_cq = NULL;
2266 break;
2267 case MLX5_IB_QPT_REG_UMR:
2268 case IB_QPT_XRC_INI:
89ea94a7 2269 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2270 *recv_cq = NULL;
2271 break;
2272
2273 case IB_QPT_SMI:
d16e91da 2274 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2275 case IB_QPT_RC:
2276 case IB_QPT_UC:
2277 case IB_QPT_UD:
2278 case IB_QPT_RAW_IPV6:
2279 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2280 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2281 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2282 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2283 break;
2284
e126ba97
EC		 2285 case IB_QPT_MAX:
2286 default:
2287 *send_cq = NULL;
2288 *recv_cq = NULL;
2289 break;
2290 }
2291}
2292
ad5f8e96 2293static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2294 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2295 u8 lag_tx_affinity);
ad5f8e96 2296
e126ba97
EC		 2297static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2298{
2299 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2300 struct mlx5_ib_qp_base *base;
89ea94a7 2301 unsigned long flags;
e126ba97
EC		 2302 int err;
2303
28d61370
YH		 2304 if (qp->ibqp.rwq_ind_tbl) {
2305 destroy_rss_raw_qp_tir(dev, qp);
2306 return;
2307 }
2308
c2e53b2c
YH		 2309 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2310 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2311 &qp->raw_packet_qp.rq.base :
2312 &qp->trans_qp.base;
2313
6aec21f6 2314 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2315 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2316 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2317 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2318 MLX5_CMD_OP_2RST_QP, 0,
2319 NULL, &base->mqp);
ad5f8e96 2320 } else {
0680efa2
AV		 2321 struct mlx5_modify_raw_qp_param raw_qp_param = {
2322 .operation = MLX5_CMD_OP_2RST_QP
2323 };
2324
13eab21f 2325 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2326 }
2327 if (err)
427c1e7b 2328 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2329 base->mqp.qpn);
6aec21f6 2330 }
e126ba97 2331
89ea94a7
MG		 2332 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2333 &send_cq, &recv_cq);
2334
2335 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2336 mlx5_ib_lock_cqs(send_cq, recv_cq);
2337 /* del from lists under both locks above to protect reset flow paths */
2338 list_del(&qp->qps_list);
2339 if (send_cq)
2340 list_del(&qp->cq_send_list);
2341
2342 if (recv_cq)
2343 list_del(&qp->cq_recv_list);
e126ba97
EC		 2344
2345 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2346 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2347 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2348 if (send_cq != recv_cq)
19098df2 2349 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2350 NULL);
e126ba97 2351 }
89ea94a7
MG		 2352 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2353 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2354
c2e53b2c
YH		 2355 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2356 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2357 destroy_raw_packet_qp(dev, qp);
2358 } else {
2359 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2360 if (err)
2361 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2362 base->mqp.qpn);
2363 }
e126ba97 2364
e126ba97
EC		 2365 if (qp->create_type == MLX5_QP_KERNEL)
2366 destroy_qp_kernel(dev, qp);
2367 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2368 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2369}
2370
2371static const char *ib_qp_type_str(enum ib_qp_type type)
2372{
2373 switch (type) {
2374 case IB_QPT_SMI:
2375 return "IB_QPT_SMI";
2376 case IB_QPT_GSI:
2377 return "IB_QPT_GSI";
2378 case IB_QPT_RC:
2379 return "IB_QPT_RC";
2380 case IB_QPT_UC:
2381 return "IB_QPT_UC";
2382 case IB_QPT_UD:
2383 return "IB_QPT_UD";
2384 case IB_QPT_RAW_IPV6:
2385 return "IB_QPT_RAW_IPV6";
2386 case IB_QPT_RAW_ETHERTYPE:
2387 return "IB_QPT_RAW_ETHERTYPE";
2388 case IB_QPT_XRC_INI:
2389 return "IB_QPT_XRC_INI";
2390 case IB_QPT_XRC_TGT:
2391 return "IB_QPT_XRC_TGT";
2392 case IB_QPT_RAW_PACKET:
2393 return "IB_QPT_RAW_PACKET";
2394 case MLX5_IB_QPT_REG_UMR:
2395 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2396 case IB_QPT_DRIVER:
2397 return "IB_QPT_DRIVER";
e126ba97
EC		 2398 case IB_QPT_MAX:
2399 default:
2400 return "Invalid QP type";
2401 }
2402}
2403
b4aaa1f0
MS		 2404static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2405 struct ib_qp_init_attr *attr,
2406 struct mlx5_ib_create_qp *ucmd)
2407{
b4aaa1f0
MS		 2408 struct mlx5_ib_qp *qp;
2409 int err = 0;
2410 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2411 void *dctc;
2412
2413 if (!attr->srq || !attr->recv_cq)
2414 return ERR_PTR(-EINVAL);
2415
b4aaa1f0
MS		 2416 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2417 ucmd, sizeof(*ucmd), &uidx);
2418 if (err)
2419 return ERR_PTR(err);
2420
2421 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2422 if (!qp)
2423 return ERR_PTR(-ENOMEM);
2424
2425 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2426 if (!qp->dct.in) {
2427 err = -ENOMEM;
2428 goto err_free;
2429 }
2430
a01a5860 2431 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2432 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2433 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2434 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2435 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2436 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2437 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2438 MLX5_SET(dctc, dctc, user_index, uidx);
2439
5d6ff1ba
YC		 2440 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2441 configure_responder_scat_cqe(attr, dctc);
2442
b4aaa1f0
MS		 2443 qp->state = IB_QPS_RESET;
2444
2445 return &qp->ibqp;
2446err_free:
2447 kfree(qp);
2448 return ERR_PTR(err);
2449}
2450
2451static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2452 struct ib_qp_init_attr *init_attr,
2453 struct mlx5_ib_create_qp *ucmd,
2454 struct ib_udata *udata)
2455{
2456 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2457 int err;
2458
2459 if (!udata)
2460 return -EINVAL;
2461
2462 if (udata->inlen < sizeof(*ucmd)) {
2463 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2464 return -EINVAL;
2465 }
2466 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2467 if (err)
2468 return err;
2469
2470 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2471 init_attr->qp_type = MLX5_IB_QPT_DCI;
2472 } else {
2473 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2474 init_attr->qp_type = MLX5_IB_QPT_DCT;
2475 } else {
2476 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2477 return -EINVAL;
2478 }
2479 }
2480
2481 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2482 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2483 return -EOPNOTSUPP;
2484 }
2485
2486 return 0;
2487}
2488
e126ba97 2489struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2490 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2491 struct ib_udata *udata)
2492{
2493 struct mlx5_ib_dev *dev;
2494 struct mlx5_ib_qp *qp;
2495 u16 xrcdn = 0;
2496 int err;
b4aaa1f0
MS		 2497 struct ib_qp_init_attr mlx_init_attr;
2498 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2499
2500 if (pd) {
2501 dev = to_mdev(pd->device);
0fb2ed66 2502
2503 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
e00b64f7 2504 if (!udata) {
0fb2ed66 2505 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2506 return ERR_PTR(-EINVAL);
2507 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2508 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2509 return ERR_PTR(-EINVAL);
2510 }
2511 }
09f16cf5
MD		 2512 } else {
2513 /* being cautious here */
2514 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2515 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2516 pr_warn("%s: no PD for transport %s\n", __func__,
2517 ib_qp_type_str(init_attr->qp_type));
2518 return ERR_PTR(-EINVAL);
2519 }
2520 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2521 }
2522
b4aaa1f0
MS		 2523 if (init_attr->qp_type == IB_QPT_DRIVER) {
2524 struct mlx5_ib_create_qp ucmd;
2525
2526 init_attr = &mlx_init_attr;
2527 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2528 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2529 if (err)
2530 return ERR_PTR(err);
c32a4f29
MS		 2531
2532 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2533 if (init_attr->cap.max_recv_wr ||
2534 init_attr->cap.max_recv_sge) {
2535 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2536 return ERR_PTR(-EINVAL);
2537 }
776a3906
MS		 2538 } else {
2539 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2540 }
b4aaa1f0
MS		 2541 }
2542
e126ba97
EC		 2543 switch (init_attr->qp_type) {
2544 case IB_QPT_XRC_TGT:
2545 case IB_QPT_XRC_INI:
938fe83c 2546 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2547 mlx5_ib_dbg(dev, "XRC not supported\n");
2548 return ERR_PTR(-ENOSYS);
2549 }
2550 init_attr->recv_cq = NULL;
2551 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2552 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2553 init_attr->send_cq = NULL;
2554 }
2555
2556 /* fall through */
0fb2ed66 2557 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2558 case IB_QPT_RC:
2559 case IB_QPT_UC:
2560 case IB_QPT_UD:
2561 case IB_QPT_SMI:
d16e91da 2562 case MLX5_IB_QPT_HW_GSI:
e126ba97 2563 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2564 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2565 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2566 if (!qp)
2567 return ERR_PTR(-ENOMEM);
2568
2569 err = create_qp_common(dev, pd, init_attr, udata, qp);
2570 if (err) {
2571 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2572 kfree(qp);
2573 return ERR_PTR(err);
2574 }
2575
2576 if (is_qp0(init_attr->qp_type))
2577 qp->ibqp.qp_num = 0;
2578 else if (is_qp1(init_attr->qp_type))
2579 qp->ibqp.qp_num = 1;
2580 else
19098df2 2581 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2582
2583 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2584 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2585 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2586 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2587
19098df2 2588 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2589
2590 break;
2591
d16e91da
HE		 2592 case IB_QPT_GSI:
2593 return mlx5_ib_gsi_create_qp(pd, init_attr);
2594
e126ba97
EC		 2595 case IB_QPT_RAW_IPV6:
2596 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2597 case IB_QPT_MAX:
2598 default:
2599 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2600 init_attr->qp_type);
2601 /* Don't support raw QPs */
2602 return ERR_PTR(-EINVAL);
2603 }
2604
b4aaa1f0
MS		 2605 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2606 qp->qp_sub_type = init_attr->qp_type;
2607
e126ba97
EC		 2608 return &qp->ibqp;
2609}
2610
776a3906
MS		 2611static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2612{
2613 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2614
2615 if (mqp->state == IB_QPS_RTR) {
2616 int err;
2617
2618 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2619 if (err) {
2620 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2621 return err;
2622 }
2623 }
2624
2625 kfree(mqp->dct.in);
2626 kfree(mqp);
2627 return 0;
2628}
2629
e126ba97
EC		 2630int mlx5_ib_destroy_qp(struct ib_qp *qp)
2631{
2632 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2633 struct mlx5_ib_qp *mqp = to_mqp(qp);
2634
d16e91da
HE		 2635 if (unlikely(qp->qp_type == IB_QPT_GSI))
2636 return mlx5_ib_gsi_destroy_qp(qp);
2637
776a3906
MS		 2638 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2639 return mlx5_ib_destroy_dct(mqp);
2640
e126ba97
EC		 2641 destroy_qp_common(dev, mqp);
2642
2643 kfree(mqp);
2644
2645 return 0;
2646}
2647
a60109dc
YC		 2648static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2649 const struct ib_qp_attr *attr,
2650 int attr_mask, __be32 *hw_access_flags)
e126ba97 2651{
e126ba97
EC		 2652 u8 dest_rd_atomic;
2653 u32 access_flags;
2654
a60109dc
YC		 2655 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2656
e126ba97
EC		 2657 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2658 dest_rd_atomic = attr->max_dest_rd_atomic;
2659 else
19098df2 2660 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2661
2662 if (attr_mask & IB_QP_ACCESS_FLAGS)
2663 access_flags = attr->qp_access_flags;
2664 else
19098df2 2665 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2666
2667 if (!dest_rd_atomic)
2668 access_flags &= IB_ACCESS_REMOTE_WRITE;
2669
2670 if (access_flags & IB_ACCESS_REMOTE_READ)
a60109dc 2671 *hw_access_flags |= MLX5_QP_BIT_RRE;
13f8d9c1 2672 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 2673 int atomic_mode;
2674
2675 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2676 if (atomic_mode < 0)
2677 return -EOPNOTSUPP;
2678
2679 *hw_access_flags |= MLX5_QP_BIT_RAE;
2680 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2681 }
2682
e126ba97 2683 if (access_flags & IB_ACCESS_REMOTE_WRITE)
a60109dc
YC		 2684 *hw_access_flags |= MLX5_QP_BIT_RWE;
2685
2686 *hw_access_flags = cpu_to_be32(*hw_access_flags);
e126ba97 2687
a60109dc 2688 return 0;
e126ba97
EC		 2689}
2690
2691enum {
2692 MLX5_PATH_FLAG_FL = 1 << 0,
2693 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2694 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2695};
2696
2697static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2698{
4f32ac2e 2699 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 2700 return 0;
4f32ac2e 2701
a5a5d199 2702 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
e126ba97 2703 return -EINVAL;
e126ba97 2704
4f32ac2e
DG		 2705 while (rate != IB_RATE_PORT_CURRENT &&
2706 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2707 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2708 --rate;
2709
2710 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 2711}
2712
75850d0b 2713static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2714 struct mlx5_ib_sq *sq, u8 sl,
2715 struct ib_pd *pd)
75850d0b 2716{
2717 void *in;
2718 void *tisc;
2719 int inlen;
2720 int err;
2721
2722 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2723 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2724 if (!in)
2725 return -ENOMEM;
2726
2727 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 2728 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 2729
2730 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2731 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2732
2733 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2734
2735 kvfree(in);
2736
2737 return err;
2738}
2739
13eab21f 2740static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2741 struct mlx5_ib_sq *sq, u8 tx_affinity,
2742 struct ib_pd *pd)
13eab21f
AH		 2743{
2744 void *in;
2745 void *tisc;
2746 int inlen;
2747 int err;
2748
2749 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2750 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2751 if (!in)
2752 return -ENOMEM;
2753
2754 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 2755 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 2756
2757 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2758 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2759
2760 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2761
2762 kvfree(in);
2763
2764 return err;
2765}
2766
75850d0b 2767static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2768 const struct rdma_ah_attr *ah,
e126ba97 2769 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2770 u32 path_flags, const struct ib_qp_attr *attr,
2771 bool alt)
e126ba97 2772{
d8966fcd 2773 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2774 int err;
ed88451e 2775 enum ib_gid_type gid_type;
d8966fcd
DC		 2776 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2777 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2778
e126ba97 2779 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2780 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2781 attr->pkey_index);
e126ba97 2782
d8966fcd
DC		 2783 if (ah_flags & IB_AH_GRH) {
2784 if (grh->sgid_index >=
938fe83c 2785 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2786 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2787 grh->sgid_index,
938fe83c 2788 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2789 return -EINVAL;
2790 }
2811ba51 2791 }
44c58487
DC		 2792
2793 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2794 if (!(ah_flags & IB_AH_GRH))
2811ba51 2795 return -EINVAL;
47ec3866 2796
44c58487 2797 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2798 if (qp->ibqp.qp_type == IB_QPT_RC ||
2799 qp->ibqp.qp_type == IB_QPT_UC ||
2800 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2801 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
47ec3866
PP		 2802 path->udp_sport =
2803 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
d8966fcd 2804 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
47ec3866 2805 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 2806 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2807 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2808 } else {
d3ae2bde
NO		 2809 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2810 path->fl_free_ar |=
2811 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2812 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2813 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2814 if (ah_flags & IB_AH_GRH)
2811ba51 2815 path->grh_mlid |= 1 << 7;
d8966fcd 2816 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2817 }
2818
d8966fcd
DC		 2819 if (ah_flags & IB_AH_GRH) {
2820 path->mgid_index = grh->sgid_index;
2821 path->hop_limit = grh->hop_limit;
e126ba97 2822 path->tclass_flowlabel =
d8966fcd
DC		 2823 cpu_to_be32((grh->traffic_class << 20) |
2824 (grh->flow_label));
2825 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2826 }
2827
d8966fcd 2828 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2829 if (err < 0)
2830 return err;
2831 path->static_rate = err;
2832 path->port = port;
2833
e126ba97 2834 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2835 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2836
75850d0b 2837 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2838 return modify_raw_packet_eth_prio(dev->mdev,
2839 &qp->raw_packet_qp.sq,
1cd6dbd3 2840 sl & 0xf, qp->ibqp.pd);
75850d0b 2841
e126ba97
EC		 2842 return 0;
2843}
2844
2845static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2846 [MLX5_QP_STATE_INIT] = {
2847 [MLX5_QP_STATE_INIT] = {
2848 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2849 MLX5_QP_OPTPAR_RAE |
2850 MLX5_QP_OPTPAR_RWE |
2851 MLX5_QP_OPTPAR_PKEY_INDEX |
2852 MLX5_QP_OPTPAR_PRI_PORT,
2853 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2854 MLX5_QP_OPTPAR_PKEY_INDEX |
2855 MLX5_QP_OPTPAR_PRI_PORT,
2856 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2857 MLX5_QP_OPTPAR_Q_KEY |
2858 MLX5_QP_OPTPAR_PRI_PORT,
2859 },
2860 [MLX5_QP_STATE_RTR] = {
2861 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2862 MLX5_QP_OPTPAR_RRE |
2863 MLX5_QP_OPTPAR_RAE |
2864 MLX5_QP_OPTPAR_RWE |
2865 MLX5_QP_OPTPAR_PKEY_INDEX,
2866 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2867 MLX5_QP_OPTPAR_RWE |
2868 MLX5_QP_OPTPAR_PKEY_INDEX,
2869 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2870 MLX5_QP_OPTPAR_Q_KEY,
2871 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2872 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2873 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2874 MLX5_QP_OPTPAR_RRE |
2875 MLX5_QP_OPTPAR_RAE |
2876 MLX5_QP_OPTPAR_RWE |
2877 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2878 },
2879 },
2880 [MLX5_QP_STATE_RTR] = {
2881 [MLX5_QP_STATE_RTS] = {
2882 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2883 MLX5_QP_OPTPAR_RRE |
2884 MLX5_QP_OPTPAR_RAE |
2885 MLX5_QP_OPTPAR_RWE |
2886 MLX5_QP_OPTPAR_PM_STATE |
2887 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2888 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2889 MLX5_QP_OPTPAR_RWE |
2890 MLX5_QP_OPTPAR_PM_STATE,
2891 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2892 },
2893 },
2894 [MLX5_QP_STATE_RTS] = {
2895 [MLX5_QP_STATE_RTS] = {
2896 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2897 MLX5_QP_OPTPAR_RAE |
2898 MLX5_QP_OPTPAR_RWE |
2899 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2900 MLX5_QP_OPTPAR_PM_STATE |
2901 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2902 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2903 MLX5_QP_OPTPAR_PM_STATE |
2904 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2905 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2906 MLX5_QP_OPTPAR_SRQN |
2907 MLX5_QP_OPTPAR_CQN_RCV,
2908 },
2909 },
2910 [MLX5_QP_STATE_SQER] = {
2911 [MLX5_QP_STATE_RTS] = {
2912 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2913 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2914 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2915 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2916 MLX5_QP_OPTPAR_RWE |
2917 MLX5_QP_OPTPAR_RAE |
2918 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2919 },
2920 },
2921};
2922
2923static int ib_nr_to_mlx5_nr(int ib_mask)
2924{
2925 switch (ib_mask) {
2926 case IB_QP_STATE:
2927 return 0;
2928 case IB_QP_CUR_STATE:
2929 return 0;
2930 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2931 return 0;
2932 case IB_QP_ACCESS_FLAGS:
2933 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2934 MLX5_QP_OPTPAR_RAE;
2935 case IB_QP_PKEY_INDEX:
2936 return MLX5_QP_OPTPAR_PKEY_INDEX;
2937 case IB_QP_PORT:
2938 return MLX5_QP_OPTPAR_PRI_PORT;
2939 case IB_QP_QKEY:
2940 return MLX5_QP_OPTPAR_Q_KEY;
2941 case IB_QP_AV:
2942 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2943 MLX5_QP_OPTPAR_PRI_PORT;
2944 case IB_QP_PATH_MTU:
2945 return 0;
2946 case IB_QP_TIMEOUT:
2947 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2948 case IB_QP_RETRY_CNT:
2949 return MLX5_QP_OPTPAR_RETRY_COUNT;
2950 case IB_QP_RNR_RETRY:
2951 return MLX5_QP_OPTPAR_RNR_RETRY;
2952 case IB_QP_RQ_PSN:
2953 return 0;
2954 case IB_QP_MAX_QP_RD_ATOMIC:
2955 return MLX5_QP_OPTPAR_SRA_MAX;
2956 case IB_QP_ALT_PATH:
2957 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2958 case IB_QP_MIN_RNR_TIMER:
2959 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2960 case IB_QP_SQ_PSN:
2961 return 0;
2962 case IB_QP_MAX_DEST_RD_ATOMIC:
2963 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2964 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2965 case IB_QP_PATH_MIG_STATE:
2966 return MLX5_QP_OPTPAR_PM_STATE;
2967 case IB_QP_CAP:
2968 return 0;
2969 case IB_QP_DEST_QPN:
2970 return 0;
2971 }
2972 return 0;
2973}
2974
2975static int ib_mask_to_mlx5_opt(int ib_mask)
2976{
2977 int result = 0;
2978 int i;
2979
2980 for (i = 0; i < 8 * sizeof(int); i++) {
2981 if ((1 << i) & ib_mask)
2982 result |= ib_nr_to_mlx5_nr(1 << i);
2983 }
2984
2985 return result;
2986}
2987
34d57585
YH		 2988static int modify_raw_packet_qp_rq(
2989 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2990 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 2991{
2992 void *in;
2993 void *rqc;
2994 int inlen;
2995 int err;
2996
2997 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2998 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2999 if (!in)
3000 return -ENOMEM;
3001
3002 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 3003 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3004
3005 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3006 MLX5_SET(rqc, rqc, state, new_state);
3007
eb49ab0c
AV		 3008 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3009 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3010 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 3011 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 3012 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3013 } else
5a738b5d
JG		 3014 dev_info_once(
3015 &dev->ib_dev.dev,
3016 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 3017 }
3018
3019 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 3020 if (err)
3021 goto out;
3022
3023 rq->state = new_state;
3024
3025out:
3026 kvfree(in);
3027 return err;
3028}
3029
c14003f0
YH		 3030static int modify_raw_packet_qp_sq(
3031 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3032 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3033{
7d29f349 3034 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 3035 struct mlx5_rate_limit old_rl = ibqp->rl;
3036 struct mlx5_rate_limit new_rl = old_rl;
3037 bool new_rate_added = false;
7d29f349 3038 u16 rl_index = 0;
ad5f8e96 3039 void *in;
3040 void *sqc;
3041 int inlen;
3042 int err;
3043
3044 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 3045 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3046 if (!in)
3047 return -ENOMEM;
3048
c14003f0 3049 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3050 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3051
3052 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3053 MLX5_SET(sqc, sqc, state, new_state);
3054
7d29f349
BW		 3055 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3056 if (new_state != MLX5_SQC_STATE_RDY)
3057 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3058 __func__);
3059 else
61147f39 3060 new_rl = raw_qp_param->rl;
7d29f349
BW		 3061 }
3062
61147f39
BW		 3063 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3064 if (new_rl.rate) {
3065 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 3066 if (err) {
61147f39
BW		 3067 pr_err("Failed configuring rate limit(err %d): \
3068 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3069 err, new_rl.rate, new_rl.max_burst_sz,
3070 new_rl.typical_pkt_sz);
3071
7d29f349
BW		 3072 goto out;
3073 }
61147f39 3074 new_rate_added = true;
7d29f349
BW		 3075 }
3076
3077 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 3078 /* index 0 means no limit */
7d29f349
BW		 3079 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3080 }
3081
ad5f8e96 3082 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 3083 if (err) {
3084 /* Remove new rate from table if failed */
61147f39
BW		 3085 if (new_rate_added)
3086 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 3087 goto out;
7d29f349
BW		 3088 }
3089
3090 /* Only remove the old rate after new rate was set */
61147f39
BW		 3091 if ((old_rl.rate &&
3092 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
7d29f349 3093 (new_state != MLX5_SQC_STATE_RDY))
61147f39 3094 mlx5_rl_remove_rate(dev, &old_rl);
ad5f8e96 3095
61147f39 3096 ibqp->rl = new_rl;
ad5f8e96 3097 sq->state = new_state;
3098
3099out:
3100 kvfree(in);
3101 return err;
3102}
3103
3104static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 3105 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3106 u8 tx_affinity)
ad5f8e96 3107{
3108 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3109 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3110 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 3111 int modify_rq = !!qp->rq.wqe_cnt;
3112 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 3113 int rq_state;
3114 int sq_state;
3115 int err;
3116
0680efa2 3117 switch (raw_qp_param->operation) {
ad5f8e96 3118 case MLX5_CMD_OP_RST2INIT_QP:
3119 rq_state = MLX5_RQC_STATE_RDY;
3120 sq_state = MLX5_SQC_STATE_RDY;
3121 break;
3122 case MLX5_CMD_OP_2ERR_QP:
3123 rq_state = MLX5_RQC_STATE_ERR;
3124 sq_state = MLX5_SQC_STATE_ERR;
3125 break;
3126 case MLX5_CMD_OP_2RST_QP:
3127 rq_state = MLX5_RQC_STATE_RST;
3128 sq_state = MLX5_SQC_STATE_RST;
3129 break;
ad5f8e96 3130 case MLX5_CMD_OP_RTR2RTS_QP:
3131 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 3132 if (raw_qp_param->set_mask ==
3133 MLX5_RAW_QP_RATE_LIMIT) {
3134 modify_rq = 0;
3135 sq_state = sq->state;
3136 } else {
3137 return raw_qp_param->set_mask ? -EINVAL : 0;
3138 }
3139 break;
3140 case MLX5_CMD_OP_INIT2INIT_QP:
3141 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 3142 if (raw_qp_param->set_mask)
3143 return -EINVAL;
3144 else
3145 return 0;
ad5f8e96 3146 default:
3147 WARN_ON(1);
3148 return -EINVAL;
3149 }
3150
7d29f349 3151 if (modify_rq) {
34d57585
YH		 3152 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3153 qp->ibqp.pd);
ad5f8e96 3154 if (err)
3155 return err;
3156 }
3157
7d29f349 3158 if (modify_sq) {
13eab21f
AH		 3159 if (tx_affinity) {
3160 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3161 tx_affinity,
3162 qp->ibqp.pd);
13eab21f
AH		 3163 if (err)
3164 return err;
3165 }
3166
c14003f0
YH		 3167 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3168 raw_qp_param, qp->ibqp.pd);
13eab21f 3169 }
ad5f8e96 3170
3171 return 0;
3172}
3173
c6a21c38
MD		 3174static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3175 struct mlx5_ib_pd *pd,
3176 struct mlx5_ib_qp_base *qp_base,
3177 u8 port_num)
3178{
3179 struct mlx5_ib_ucontext *ucontext = NULL;
3180 unsigned int tx_port_affinity;
3181
3182 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3183 ucontext = to_mucontext(pd->ibpd.uobject->context);
3184
3185 if (ucontext) {
3186 tx_port_affinity = (unsigned int)atomic_add_return(
3187 1, &ucontext->tx_port_affinity) %
3188 MLX5_MAX_PORTS +
3189 1;
3190 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3191 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3192 } else {
3193 tx_port_affinity =
3194 (unsigned int)atomic_add_return(
3195 1, &dev->roce[port_num].tx_port_affinity) %
3196 MLX5_MAX_PORTS +
3197 1;
3198 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3199 tx_port_affinity, qp_base->mqp.qpn);
3200 }
3201
3202 return tx_port_affinity;
3203}
3204
e126ba97
EC		 3205static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3206 const struct ib_qp_attr *attr, int attr_mask,
61147f39
BW		 3207 enum ib_qp_state cur_state, enum ib_qp_state new_state,
3208 const struct mlx5_ib_modify_qp *ucmd)
e126ba97 3209{
427c1e7b 3210 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3211 [MLX5_QP_STATE_RST] = {
3212 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3213 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3214 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3215 },
3216 [MLX5_QP_STATE_INIT] = {
3217 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3218 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3219 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3220 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3221 },
3222 [MLX5_QP_STATE_RTR] = {
3223 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3224 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3225 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3226 },
3227 [MLX5_QP_STATE_RTS] = {
3228 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3229 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3230 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3231 },
3232 [MLX5_QP_STATE_SQD] = {
3233 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3234 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3235 },
3236 [MLX5_QP_STATE_SQER] = {
3237 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3238 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3239 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3240 },
3241 [MLX5_QP_STATE_ERR] = {
3242 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3243 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3244 }
3245 };
3246
e126ba97
EC		 3247 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3248 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3249 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 3250 struct mlx5_ib_cq *send_cq, *recv_cq;
3251 struct mlx5_qp_context *context;
e126ba97 3252 struct mlx5_ib_pd *pd;
eb49ab0c 3253 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 3254 enum mlx5_qp_state mlx5_cur, mlx5_new;
3255 enum mlx5_qp_optpar optpar;
e126ba97
EC		 3256 int mlx5_st;
3257 int err;
427c1e7b 3258 u16 op;
13eab21f 3259 u8 tx_affinity = 0;
e126ba97 3260
55de9a77
LR		 3261 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3262 qp->qp_sub_type : ibqp->qp_type);
3263 if (mlx5_st < 0)
3264 return -EINVAL;
3265
1a412fb1
SM		 3266 context = kzalloc(sizeof(*context), GFP_KERNEL);
3267 if (!context)
e126ba97
EC		 3268 return -ENOMEM;
3269
c6a21c38 3270 pd = get_pd(qp);
55de9a77 3271 context->flags = cpu_to_be32(mlx5_st << 16);
e126ba97
EC		 3272
3273 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3274 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3275 } else {
3276 switch (attr->path_mig_state) {
3277 case IB_MIG_MIGRATED:
3278 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3279 break;
3280 case IB_MIG_REARM:
3281 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3282 break;
3283 case IB_MIG_ARMED:
3284 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3285 break;
3286 }
3287 }
3288
13eab21f
AH		 3289 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3290 if ((ibqp->qp_type == IB_QPT_RC) ||
3291 (ibqp->qp_type == IB_QPT_UD &&
3292 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3293 (ibqp->qp_type == IB_QPT_UC) ||
3294 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3295 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3296 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
7c34ec19 3297 if (dev->lag_active) {
7fd8aefb 3298 u8 p = mlx5_core_native_port_num(dev->mdev);
c6a21c38 3299 tx_affinity = get_tx_affinity(dev, pd, base, p);
13eab21f
AH		 3300 context->flags |= cpu_to_be32(tx_affinity << 24);
3301 }
3302 }
3303 }
3304
d16e91da 3305 if (is_sqp(ibqp->qp_type)) {
e126ba97 3306 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 3307 } else if ((ibqp->qp_type == IB_QPT_UD &&
3308 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 3309 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3310 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3311 } else if (attr_mask & IB_QP_PATH_MTU) {
3312 if (attr->path_mtu < IB_MTU_256 ||
3313 attr->path_mtu > IB_MTU_4096) {
3314 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3315 err = -EINVAL;
3316 goto out;
3317 }
938fe83c
SM		 3318 context->mtu_msgmax = (attr->path_mtu << 5) |
3319 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3320 }
3321
3322 if (attr_mask & IB_QP_DEST_QPN)
3323 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3324
3325 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3326 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3327
3328 /* todo implement counter_index functionality */
3329
3330 if (is_sqp(ibqp->qp_type))
3331 context->pri_path.port = qp->port;
3332
3333 if (attr_mask & IB_QP_PORT)
3334 context->pri_path.port = attr->port_num;
3335
3336 if (attr_mask & IB_QP_AV) {
75850d0b 3337 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3338 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3339 attr_mask, 0, attr, false);
e126ba97
EC		 3340 if (err)
3341 goto out;
3342 }
3343
3344 if (attr_mask & IB_QP_TIMEOUT)
3345 context->pri_path.ackto_lt |= attr->timeout << 3;
3346
3347 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3348 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3349 &context->alt_path,
f879ee8d
AS		 3350 attr->alt_port_num,
3351 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3352 0, attr, true);
e126ba97
EC		 3353 if (err)
3354 goto out;
3355 }
3356
89ea94a7
MG		 3357 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3358 &send_cq, &recv_cq);
e126ba97
EC		 3359
3360 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3361 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3362 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3363 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3364
3365 if (attr_mask & IB_QP_RNR_RETRY)
3366 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3367
3368 if (attr_mask & IB_QP_RETRY_CNT)
3369 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3370
3371 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3372 if (attr->max_rd_atomic)
3373 context->params1 |=
3374 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3375 }
3376
3377 if (attr_mask & IB_QP_SQ_PSN)
3378 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3379
3380 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3381 if (attr->max_dest_rd_atomic)
3382 context->params2 |=
3383 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3384 }
3385
a60109dc
YC		 3386 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3387 __be32 access_flags = 0;
3388
3389 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3390 if (err)
3391 goto out;
3392
3393 context->params2 |= access_flags;
3394 }
e126ba97
EC		 3395
3396 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3397 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3398
3399 if (attr_mask & IB_QP_RQ_PSN)
3400 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3401
3402 if (attr_mask & IB_QP_QKEY)
3403 context->qkey = cpu_to_be32(attr->qkey);
3404
3405 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3406 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3407
0837e86a
MB		 3408 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3409 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3410 qp->port) - 1;
c2e53b2c
YH		 3411
3412 /* Underlay port should be used - index 0 function per port */
3413 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3414 port_num = 0;
3415
eb49ab0c 3416 mibport = &dev->port[port_num];
0837e86a 3417 context->qp_counter_set_usr_page |=
e1f24a79 3418 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3419 }
3420
e126ba97
EC		 3421 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3422 context->sq_crq_size |= cpu_to_be16(1 << 4);
3423
b11a4f9c
HE		 3424 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3425 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3426
3427 mlx5_cur = to_mlx5_state(cur_state);
3428 mlx5_new = to_mlx5_state(new_state);
e126ba97 3429
427c1e7b 3430 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3431 !optab[mlx5_cur][mlx5_new]) {
3432 err = -EINVAL;
427c1e7b 3433 goto out;
5d414b17 3434 }
427c1e7b 3435
3436 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3437 optpar = ib_mask_to_mlx5_opt(attr_mask);
3438 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3439
c2e53b2c
YH		 3440 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3441 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3442 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3443
3444 raw_qp_param.operation = op;
eb49ab0c 3445 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3446 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3447 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3448 }
7d29f349
BW		 3449
3450 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3451 raw_qp_param.rl.rate = attr->rate_limit;
3452
3453 if (ucmd->burst_info.max_burst_sz) {
3454 if (attr->rate_limit &&
3455 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3456 raw_qp_param.rl.max_burst_sz =
3457 ucmd->burst_info.max_burst_sz;
3458 } else {
3459 err = -EINVAL;
3460 goto out;
3461 }
3462 }
3463
3464 if (ucmd->burst_info.typical_pkt_sz) {
3465 if (attr->rate_limit &&
3466 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3467 raw_qp_param.rl.typical_pkt_sz =
3468 ucmd->burst_info.typical_pkt_sz;
3469 } else {
3470 err = -EINVAL;
3471 goto out;
3472 }
3473 }
3474
7d29f349
BW		 3475 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3476 }
3477
13eab21f 3478 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3479 } else {
1a412fb1 3480 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3481 &base->mqp);
0680efa2
AV		 3482 }
3483
e126ba97
EC		 3484 if (err)
3485 goto out;
3486
3487 qp->state = new_state;
3488
3489 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3490 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3491 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3492 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3493 if (attr_mask & IB_QP_PORT)
3494 qp->port = attr->port_num;
3495 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3496 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3497
3498 /*
3499 * If we moved a kernel QP to RESET, clean up all old CQ
3500 * entries and reinitialize the QP.
3501 */
75a45982
LR		 3502 if (new_state == IB_QPS_RESET &&
3503 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 3504 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3505 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3506 if (send_cq != recv_cq)
19098df2 3507 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3508
3509 qp->rq.head = 0;
3510 qp->rq.tail = 0;
3511 qp->sq.head = 0;
3512 qp->sq.tail = 0;
3513 qp->sq.cur_post = 0;
34f4c955
GL		 3514 if (qp->sq.wqe_cnt)
3515 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
e126ba97
EC		 3516 qp->db.db[MLX5_RCV_DBR] = 0;
3517 qp->db.db[MLX5_SND_DBR] = 0;
3518 }
3519
3520out:
1a412fb1 3521 kfree(context);
e126ba97
EC		 3522 return err;
3523}
3524
c32a4f29
MS		 3525static inline bool is_valid_mask(int mask, int req, int opt)
3526{
3527 if ((mask & req) != req)
3528 return false;
3529
3530 if (mask & ~(req | opt))
3531 return false;
3532
3533 return true;
3534}
3535
3536/* check valid transition for driver QP types
3537 * for now the only QP type that this function supports is DCI
3538 */
3539static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3540 enum ib_qp_attr_mask attr_mask)
3541{
3542 int req = IB_QP_STATE;
3543 int opt = 0;
3544
99ed748e
MS		 3545 if (new_state == IB_QPS_RESET) {
3546 return is_valid_mask(attr_mask, req, opt);
3547 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 3548 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3549 return is_valid_mask(attr_mask, req, opt);
3550 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3551 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3552 return is_valid_mask(attr_mask, req, opt);
3553 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3554 req |= IB_QP_PATH_MTU;
5ec0304c 3555 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
c32a4f29
MS		 3556 return is_valid_mask(attr_mask, req, opt);
3557 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3558 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3559 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3560 opt = IB_QP_MIN_RNR_TIMER;
3561 return is_valid_mask(attr_mask, req, opt);
3562 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3563 opt = IB_QP_MIN_RNR_TIMER;
3564 return is_valid_mask(attr_mask, req, opt);
3565 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3566 return is_valid_mask(attr_mask, req, opt);
3567 }
3568 return false;
3569}
3570
776a3906
MS		 3571/* mlx5_ib_modify_dct: modify a DCT QP
3572 * valid transitions are:
3573 * RESET to INIT: must set access_flags, pkey_index and port
3574 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3575 * mtu, gid_index and hop_limit
3576 * Other transitions and attributes are illegal
3577 */
3578static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3579 int attr_mask, struct ib_udata *udata)
3580{
3581 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3582 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3583 enum ib_qp_state cur_state, new_state;
3584 int err = 0;
3585 int required = IB_QP_STATE;
3586 void *dctc;
3587
3588 if (!(attr_mask & IB_QP_STATE))
3589 return -EINVAL;
3590
3591 cur_state = qp->state;
3592 new_state = attr->qp_state;
3593
3594 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3595 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3596 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3597 if (!is_valid_mask(attr_mask, required, 0))
3598 return -EINVAL;
3599
3600 if (attr->port_num == 0 ||
3601 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3602 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3603 attr->port_num, dev->num_ports);
3604 return -EINVAL;
3605 }
3606 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3607 MLX5_SET(dctc, dctc, rre, 1);
3608 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3609 MLX5_SET(dctc, dctc, rwe, 1);
3610 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 3611 int atomic_mode;
3612
3613 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3614 if (atomic_mode < 0)
776a3906 3615 return -EOPNOTSUPP;
a60109dc
YC		 3616
3617 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
776a3906 3618 MLX5_SET(dctc, dctc, rae, 1);
776a3906
MS		 3619 }
3620 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3621 MLX5_SET(dctc, dctc, port, attr->port_num);
3622 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3623
3624 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3625 struct mlx5_ib_modify_qp_resp resp = {};
3626 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3627 sizeof(resp.dctn);
3628
3629 if (udata->outlen < min_resp_len)
3630 return -EINVAL;
3631 resp.response_length = min_resp_len;
3632
3633 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3634 if (!is_valid_mask(attr_mask, required, 0))
3635 return -EINVAL;
3636 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3637 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3638 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3639 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3640 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3641 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3642
3643 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3644 MLX5_ST_SZ_BYTES(create_dct_in));
3645 if (err)
3646 return err;
3647 resp.dctn = qp->dct.mdct.mqp.qpn;
3648 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3649 if (err) {
3650 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3651 return err;
3652 }
3653 } else {
3654 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3655 return -EINVAL;
3656 }
3657 if (err)
3658 qp->state = IB_QPS_ERR;
3659 else
3660 qp->state = new_state;
3661 return err;
3662}
3663
e126ba97
EC		 3664int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3665 int attr_mask, struct ib_udata *udata)
3666{
3667 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3668 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 3669 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 3670 enum ib_qp_type qp_type;
e126ba97 3671 enum ib_qp_state cur_state, new_state;
61147f39 3672 size_t required_cmd_sz;
e126ba97
EC		 3673 int err = -EINVAL;
3674 int port;
3675
28d61370
YH		 3676 if (ibqp->rwq_ind_tbl)
3677 return -ENOSYS;
3678
61147f39
BW		 3679 if (udata && udata->inlen) {
3680 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3681 sizeof(ucmd.reserved);
3682 if (udata->inlen < required_cmd_sz)
3683 return -EINVAL;
3684
3685 if (udata->inlen > sizeof(ucmd) &&
3686 !ib_is_udata_cleared(udata, sizeof(ucmd),
3687 udata->inlen - sizeof(ucmd)))
3688 return -EOPNOTSUPP;
3689
3690 if (ib_copy_from_udata(&ucmd, udata,
3691 min(udata->inlen, sizeof(ucmd))))
3692 return -EFAULT;
3693
3694 if (ucmd.comp_mask ||
3695 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3696 memchr_inv(&ucmd.burst_info.reserved, 0,
3697 sizeof(ucmd.burst_info.reserved)))
3698 return -EOPNOTSUPP;
3699 }
3700
d16e91da
HE		 3701 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3702 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3703
c32a4f29
MS		 3704 if (ibqp->qp_type == IB_QPT_DRIVER)
3705 qp_type = qp->qp_sub_type;
3706 else
3707 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3708 IB_QPT_GSI : ibqp->qp_type;
3709
776a3906
MS		 3710 if (qp_type == MLX5_IB_QPT_DCT)
3711 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3712
e126ba97
EC		 3713 mutex_lock(&qp->mutex);
3714
3715 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3716 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3717
2811ba51
AS		 3718 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3719 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2811ba51
AS		 3720 }
3721
c2e53b2c
YH		 3722 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3723 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3724 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3725 attr_mask);
3726 goto out;
3727 }
3728 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29 3729 qp_type != MLX5_IB_QPT_DCI &&
d31131bb
KH		 3730 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3731 attr_mask)) {
158abf86
HE		 3732 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3733 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3734 goto out;
c32a4f29
MS		 3735 } else if (qp_type == MLX5_IB_QPT_DCI &&
3736 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3737 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3738 cur_state, new_state, qp_type, attr_mask);
3739 goto out;
158abf86 3740 }
e126ba97
EC		 3741
3742 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3743 (attr->port_num == 0 ||
508562d6 3744 attr->port_num > dev->num_ports)) {
158abf86
HE		 3745 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3746 attr->port_num, dev->num_ports);
e126ba97 3747 goto out;
158abf86 3748 }
e126ba97
EC		 3749
3750 if (attr_mask & IB_QP_PKEY_INDEX) {
3751 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3752 if (attr->pkey_index >=
158abf86
HE		 3753 dev->mdev->port_caps[port - 1].pkey_table_len) {
3754 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3755 attr->pkey_index);
e126ba97 3756 goto out;
158abf86 3757 }
e126ba97
EC		 3758 }
3759
3760 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3761 attr->max_rd_atomic >
158abf86
HE		 3762 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3763 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3764 attr->max_rd_atomic);
e126ba97 3765 goto out;
158abf86 3766 }
e126ba97
EC		 3767
3768 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3769 attr->max_dest_rd_atomic >
158abf86
HE		 3770 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3771 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3772 attr->max_dest_rd_atomic);
e126ba97 3773 goto out;
158abf86 3774 }
e126ba97
EC		 3775
3776 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3777 err = 0;
3778 goto out;
3779 }
3780
61147f39
BW		 3781 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3782 new_state, &ucmd);
e126ba97
EC		 3783
3784out:
3785 mutex_unlock(&qp->mutex);
3786 return err;
3787}
3788
34f4c955
GL		 3789static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3790 u32 wqe_sz, void **cur_edge)
3791{
3792 u32 idx;
3793
3794 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3795 *cur_edge = get_sq_edge(sq, idx);
3796
3797 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3798}
3799
3800/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3801 * next nearby edge and get new address translation for current WQE position.
3802 * @sq - SQ buffer.
3803 * @seg: Current WQE position (16B aligned).
3804 * @wqe_sz: Total current WQE size [16B].
3805 * @cur_edge: Updated current edge.
3806 */
3807static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3808 u32 wqe_sz, void **cur_edge)
3809{
3810 if (likely(*seg != *cur_edge))
3811 return;
3812
3813 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3814}
3815
3816/* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3817 * pointers. At the end @seg is aligned to 16B regardless the copied size.
3818 * @sq - SQ buffer.
3819 * @cur_edge: Updated current edge.
3820 * @seg: Current WQE position (16B aligned).
3821 * @wqe_sz: Total current WQE size [16B].
3822 * @src: Pointer to copy from.
3823 * @n: Number of bytes to copy.
3824 */
3825static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3826 void **seg, u32 *wqe_sz, const void *src,
3827 size_t n)
3828{
3829 while (likely(n)) {
3830 size_t leftlen = *cur_edge - *seg;
3831 size_t copysz = min_t(size_t, leftlen, n);
3832 size_t stride;
3833
3834 memcpy(*seg, src, copysz);
3835
3836 n -= copysz;
3837 src += copysz;
3838 stride = !n ? ALIGN(copysz, 16) : copysz;
3839 *seg += stride;
3840 *wqe_sz += stride >> 4;
3841 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3842 }
3843}
3844
e126ba97
EC		 3845static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3846{
3847 struct mlx5_ib_cq *cq;
3848 unsigned cur;
3849
3850 cur = wq->head - wq->tail;
3851 if (likely(cur + nreq < wq->max_post))
3852 return 0;
3853
3854 cq = to_mcq(ib_cq);
3855 spin_lock(&cq->lock);
3856 cur = wq->head - wq->tail;
3857 spin_unlock(&cq->lock);
3858
3859 return cur + nreq >= wq->max_post;
3860}
3861
3862static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3863 u64 remote_addr, u32 rkey)
3864{
3865 rseg->raddr = cpu_to_be64(remote_addr);
3866 rseg->rkey = cpu_to_be32(rkey);
3867 rseg->reserved = 0;
3868}
3869
34f4c955
GL		 3870static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3871 void **seg, int *size, void **cur_edge)
f0313965 3872{
34f4c955 3873 struct mlx5_wqe_eth_seg *eseg = *seg;
f0313965
ES		 3874
3875 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3876
3877 if (wr->send_flags & IB_SEND_IP_CSUM)
3878 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3879 MLX5_ETH_WQE_L4_CSUM;
3880
f0313965
ES		 3881 if (wr->opcode == IB_WR_LSO) {
3882 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
34f4c955 3883 size_t left, copysz;
f0313965 3884 void *pdata = ud_wr->header;
34f4c955 3885 size_t stride;
f0313965
ES		 3886
3887 left = ud_wr->hlen;
3888 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3889 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965 3890
34f4c955
GL		 3891 /* memcpy_send_wqe should get a 16B align address. Hence, we
3892 * first copy up to the current edge and then, if needed,
3893 * fall-through to memcpy_send_wqe.
f0313965 3894 */
34f4c955
GL		 3895 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
3896 left);
3897 memcpy(eseg->inline_hdr.start, pdata, copysz);
3898 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
3899 sizeof(eseg->inline_hdr.start) + copysz, 16);
3900 *size += stride / 16;
3901 *seg += stride;
3902
3903 if (copysz < left) {
3904 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
f0313965
ES		 3905 left -= copysz;
3906 pdata += copysz;
34f4c955
GL		 3907 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
3908 left);
f0313965 3909 }
34f4c955
GL		 3910
3911 return;
f0313965
ES		 3912 }
3913
34f4c955
GL		 3914 *seg += sizeof(struct mlx5_wqe_eth_seg);
3915 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
f0313965
ES		 3916}
3917
e126ba97 3918static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
f696bf6d 3919 const struct ib_send_wr *wr)
e126ba97 3920{
e622f2f4
CH		 3921 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3922 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3923 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3924}
3925
3926static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3927{
3928 dseg->byte_count = cpu_to_be32(sg->length);
3929 dseg->lkey = cpu_to_be32(sg->lkey);
3930 dseg->addr = cpu_to_be64(sg->addr);
3931}
3932
31616255 3933static u64 get_xlt_octo(u64 bytes)
e126ba97 3934{
31616255
AK		 3935 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3936 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3937}
3938
3939static __be64 frwr_mkey_mask(void)
3940{
3941 u64 result;
3942
3943 result = MLX5_MKEY_MASK_LEN |
3944 MLX5_MKEY_MASK_PAGE_SIZE |
3945 MLX5_MKEY_MASK_START_ADDR |
3946 MLX5_MKEY_MASK_EN_RINVAL |
3947 MLX5_MKEY_MASK_KEY |
3948 MLX5_MKEY_MASK_LR |
3949 MLX5_MKEY_MASK_LW |
3950 MLX5_MKEY_MASK_RR |
3951 MLX5_MKEY_MASK_RW |
3952 MLX5_MKEY_MASK_A |
3953 MLX5_MKEY_MASK_SMALL_FENCE |
3954 MLX5_MKEY_MASK_FREE;
3955
3956 return cpu_to_be64(result);
3957}
3958
e6631814
SG		 3959static __be64 sig_mkey_mask(void)
3960{
3961 u64 result;
3962
3963 result = MLX5_MKEY_MASK_LEN |
3964 MLX5_MKEY_MASK_PAGE_SIZE |
3965 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3966 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3967 MLX5_MKEY_MASK_EN_RINVAL |
3968 MLX5_MKEY_MASK_KEY |
3969 MLX5_MKEY_MASK_LR |
3970 MLX5_MKEY_MASK_LW |
3971 MLX5_MKEY_MASK_RR |
3972 MLX5_MKEY_MASK_RW |
3973 MLX5_MKEY_MASK_SMALL_FENCE |
3974 MLX5_MKEY_MASK_FREE |
3975 MLX5_MKEY_MASK_BSF_EN;
3976
3977 return cpu_to_be64(result);
3978}
3979
8a187ee5 3980static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
064e5262 3981 struct mlx5_ib_mr *mr, bool umr_inline)
8a187ee5 3982{
31616255 3983 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3984
3985 memset(umr, 0, sizeof(*umr));
b005d316 3986
8a187ee5 3987 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
064e5262
IB		 3988 if (umr_inline)
3989 umr->flags |= MLX5_UMR_INLINE;
31616255 3990 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3991 umr->mkey_mask = frwr_mkey_mask();
3992}
3993
dd01e66a 3994static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3995{
3996 memset(umr, 0, sizeof(*umr));
dd01e66a 3997 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3998 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3999}
4000
31616255 4001static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 4002{
4003 u64 result;
4004
31616255 4005 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 4006 MLX5_MKEY_MASK_FREE;
4007
968e78dd
HE		 4008 return cpu_to_be64(result);
4009}
4010
31616255 4011static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 4012{
4013 u64 result;
4014
4015 result = MLX5_MKEY_MASK_FREE;
4016
4017 return cpu_to_be64(result);
4018}
4019
56e11d62
NO		 4020static __be64 get_umr_update_translation_mask(void)
4021{
4022 u64 result;
4023
4024 result = MLX5_MKEY_MASK_LEN |
4025 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 4026 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 4027
4028 return cpu_to_be64(result);
4029}
4030
31616255 4031static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 4032{
4033 u64 result;
4034
31616255
AK		 4035 result = MLX5_MKEY_MASK_LR |
4036 MLX5_MKEY_MASK_LW |
56e11d62 4037 MLX5_MKEY_MASK_RR |
31616255
AK		 4038 MLX5_MKEY_MASK_RW;
4039
4040 if (atomic)
4041 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 4042
4043 return cpu_to_be64(result);
4044}
4045
4046static __be64 get_umr_update_pd_mask(void)
4047{
4048 u64 result;
4049
31616255 4050 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 4051
4052 return cpu_to_be64(result);
4053}
4054
c8d75a98
MD		 4055static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4056{
4057 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4058 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4059 (mask & MLX5_MKEY_MASK_A &&
4060 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4061 return -EPERM;
4062 return 0;
4063}
4064
4065static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4066 struct mlx5_wqe_umr_ctrl_seg *umr,
f696bf6d 4067 const struct ib_send_wr *wr, int atomic)
e126ba97 4068{
f696bf6d 4069 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 4070
4071 memset(umr, 0, sizeof(*umr));
4072
968e78dd
HE		 4073 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4074 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4075 else
4076 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4077
31616255
AK		 4078 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4079 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4080 u64 offset = get_xlt_octo(umrwr->offset);
4081
4082 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4083 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4084 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 4085 }
31616255
AK		 4086 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4087 umr->mkey_mask |= get_umr_update_translation_mask();
4088 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4089 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4090 umr->mkey_mask |= get_umr_update_pd_mask();
4091 }
4092 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4093 umr->mkey_mask |= get_umr_enable_mr_mask();
4094 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4095 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 4096
4097 if (!wr->num_sge)
968e78dd 4098 umr->flags |= MLX5_UMR_INLINE;
c8d75a98
MD		 4099
4100 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
e126ba97
EC		 4101}
4102
4103static u8 get_umr_flags(int acc)
4104{
4105 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
4106 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
4107 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
4108 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 4109 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 4110}
4111
8a187ee5
SG		 4112static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4113 struct mlx5_ib_mr *mr,
4114 u32 key, int access)
4115{
4116 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4117
4118 memset(seg, 0, sizeof(*seg));
b005d316 4119
ec22eb53 4120 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 4121 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 4122 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 4123 /* KLMs take twice the size of MTTs */
4124 ndescs *= 2;
4125
4126 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 4127 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4128 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4129 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4130 seg->len = cpu_to_be64(mr->ibmr.length);
4131 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 4132}
4133
dd01e66a 4134static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 4135{
4136 memset(seg, 0, sizeof(*seg));
dd01e66a 4137 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 4138}
4139
f696bf6d
BVA		 4140static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4141 const struct ib_send_wr *wr)
e126ba97 4142{
f696bf6d 4143 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 4144
e126ba97 4145 memset(seg, 0, sizeof(*seg));
31616255 4146 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 4147 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 4148
968e78dd 4149 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 4150 if (umrwr->pd)
4151 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4152 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4153 !umrwr->length)
4154 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4155
4156 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 4157 seg->len = cpu_to_be64(umrwr->length);
4158 seg->log2_page_size = umrwr->page_shift;
746b5583 4159 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 4160 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 4161}
4162
8a187ee5
SG		 4163static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4164 struct mlx5_ib_mr *mr,
4165 struct mlx5_ib_pd *pd)
4166{
4167 int bcount = mr->desc_size * mr->ndescs;
4168
4169 dseg->addr = cpu_to_be64(mr->desc_map);
4170 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4171 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4172}
4173
f696bf6d 4174static __be32 send_ieth(const struct ib_send_wr *wr)
e126ba97
EC		 4175{
4176 switch (wr->opcode) {
4177 case IB_WR_SEND_WITH_IMM:
4178 case IB_WR_RDMA_WRITE_WITH_IMM:
4179 return wr->ex.imm_data;
4180
4181 case IB_WR_SEND_WITH_INV:
4182 return cpu_to_be32(wr->ex.invalidate_rkey);
4183
4184 default:
4185 return 0;
4186 }
4187}
4188
4189static u8 calc_sig(void *wqe, int size)
4190{
4191 u8 *p = wqe;
4192 u8 res = 0;
4193 int i;
4194
4195 for (i = 0; i < size; i++)
4196 res ^= p[i];
4197
4198 return ~res;
4199}
4200
4201static u8 wq_sig(void *wqe)
4202{
4203 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4204}
4205
f696bf6d 4206static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
34f4c955 4207 void **wqe, int *wqe_sz, void **cur_edge)
e126ba97
EC		 4208{
4209 struct mlx5_wqe_inline_seg *seg;
34f4c955 4210 size_t offset;
e126ba97 4211 int inl = 0;
e126ba97
EC		 4212 int i;
4213
34f4c955
GL		 4214 seg = *wqe;
4215 *wqe += sizeof(*seg);
4216 offset = sizeof(*seg);
4217
e126ba97 4218 for (i = 0; i < wr->num_sge; i++) {
34f4c955
GL		 4219 size_t len = wr->sg_list[i].length;
4220 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4221
e126ba97
EC		 4222 inl += len;
4223
4224 if (unlikely(inl > qp->max_inline_data))
4225 return -ENOMEM;
4226
34f4c955
GL		 4227 while (likely(len)) {
4228 size_t leftlen;
4229 size_t copysz;
4230
4231 handle_post_send_edge(&qp->sq, wqe,
4232 *wqe_sz + (offset >> 4),
4233 cur_edge);
4234
4235 leftlen = *cur_edge - *wqe;
4236 copysz = min_t(size_t, leftlen, len);
4237
4238 memcpy(*wqe, addr, copysz);
4239 len -= copysz;
4240 addr += copysz;
4241 *wqe += copysz;
4242 offset += copysz;
e126ba97 4243 }
e126ba97
EC		 4244 }
4245
4246 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4247
34f4c955 4248 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
e126ba97
EC		 4249
4250 return 0;
4251}
4252
e6631814
SG		 4253static u16 prot_field_size(enum ib_signature_type type)
4254{
4255 switch (type) {
4256 case IB_SIG_TYPE_T10_DIF:
4257 return MLX5_DIF_SIZE;
4258 default:
4259 return 0;
4260 }
4261}
4262
4263static u8 bs_selector(int block_size)
4264{
4265 switch (block_size) {
4266 case 512: return 0x1;
4267 case 520: return 0x2;
4268 case 4096: return 0x3;
4269 case 4160: return 0x4;
4270 case 1073741824: return 0x5;
4271 default: return 0;
4272 }
4273}
4274
78eda2bb
SG		 4275static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4276 struct mlx5_bsf_inl *inl)
e6631814 4277{
142537f4
SG		 4278 /* Valid inline section and allow BSF refresh */
4279 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4280 MLX5_BSF_REFRESH_DIF);
4281 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4282 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 4283 /* repeating block */
4284 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4285 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4286 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 4287
78eda2bb
SG		 4288 if (domain->sig.dif.ref_remap)
4289 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 4290
78eda2bb
SG		 4291 if (domain->sig.dif.app_escape) {
4292 if (domain->sig.dif.ref_escape)
4293 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4294 else
4295 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 4296 }
4297
78eda2bb
SG		 4298 inl->dif_app_bitmask_check =
4299 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 4300}
4301
4302static int mlx5_set_bsf(struct ib_mr *sig_mr,
4303 struct ib_sig_attrs *sig_attrs,
4304 struct mlx5_bsf *bsf, u32 data_size)
4305{
4306 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4307 struct mlx5_bsf_basic *basic = &bsf->basic;
4308 struct ib_sig_domain *mem = &sig_attrs->mem;
4309 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 4310
c7f44fbd 4311 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 4312
4313 /* Basic + Extended + Inline */
4314 basic->bsf_size_sbs = 1 << 7;
4315 /* Input domain check byte mask */
4316 basic->check_byte_mask = sig_attrs->check_mask;
4317 basic->raw_data_size = cpu_to_be32(data_size);
4318
4319 /* Memory domain */
e6631814 4320 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 4321 case IB_SIG_TYPE_NONE:
4322 break;
e6631814 4323 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 4324 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4325 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4326 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4327 break;
4328 default:
4329 return -EINVAL;
4330 }
e6631814 4331
78eda2bb
SG		 4332 /* Wire domain */
4333 switch (sig_attrs->wire.sig_type) {
4334 case IB_SIG_TYPE_NONE:
4335 break;
4336 case IB_SIG_TYPE_T10_DIF:
e6631814 4337 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 4338 mem->sig_type == wire->sig_type) {
e6631814 4339 /* Same block structure */
142537f4 4340 basic->bsf_size_sbs |= 1 << 4;
e6631814 4341 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 4342 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 4343 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 4344 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 4345 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 4346 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 4347 } else
4348 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4349
142537f4 4350 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 4351 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 4352 break;
e6631814
SG		 4353 default:
4354 return -EINVAL;
4355 }
4356
4357 return 0;
4358}
4359
f696bf6d 4360static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
34f4c955
GL		 4361 struct mlx5_ib_qp *qp, void **seg,
4362 int *size, void **cur_edge)
e6631814 4363{
e622f2f4
CH		 4364 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4365 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4366 struct mlx5_bsf *bsf;
e622f2f4
CH		 4367 u32 data_len = wr->wr.sg_list->length;
4368 u32 data_key = wr->wr.sg_list->lkey;
4369 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 4370 int ret;
4371 int wqe_size;
4372
e622f2f4
CH		 4373 if (!wr->prot ||
4374 (data_key == wr->prot->lkey &&
4375 data_va == wr->prot->addr &&
4376 data_len == wr->prot->length)) {
e6631814
SG		 4377 /**
4378 * Source domain doesn't contain signature information
5c273b16 4379 * or data and protection are interleaved in memory.
e6631814
SG		 4380 * So need construct:
4381 * ------------------
4382 * | data_klm |
4383 * ------------------
4384 * | BSF |
4385 * ------------------
4386 **/
4387 struct mlx5_klm *data_klm = *seg;
4388
4389 data_klm->bcount = cpu_to_be32(data_len);
4390 data_klm->key = cpu_to_be32(data_key);
4391 data_klm->va = cpu_to_be64(data_va);
4392 wqe_size = ALIGN(sizeof(*data_klm), 64);
4393 } else {
4394 /**
4395 * Source domain contains signature information
4396 * So need construct a strided block format:
4397 * ---------------------------
4398 * | stride_block_ctrl |
4399 * ---------------------------
4400 * | data_klm |
4401 * ---------------------------
4402 * | prot_klm |
4403 * ---------------------------
4404 * | BSF |
4405 * ---------------------------
4406 **/
4407 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4408 struct mlx5_stride_block_entry *data_sentry;
4409 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 4410 u32 prot_key = wr->prot->lkey;
4411 u64 prot_va = wr->prot->addr;
e6631814
SG		 4412 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4413 int prot_size;
4414
4415 sblock_ctrl = *seg;
4416 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4417 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4418
4419 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4420 if (!prot_size) {
4421 pr_err("Bad block size given: %u\n", block_size);
4422 return -EINVAL;
4423 }
4424 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4425 prot_size);
4426 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4427 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4428 sblock_ctrl->num_entries = cpu_to_be16(2);
4429
4430 data_sentry->bcount = cpu_to_be16(block_size);
4431 data_sentry->key = cpu_to_be32(data_key);
4432 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 4433 data_sentry->stride = cpu_to_be16(block_size);
4434
e6631814
SG		 4435 prot_sentry->bcount = cpu_to_be16(prot_size);
4436 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 4437 prot_sentry->va = cpu_to_be64(prot_va);
4438 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 4439
e6631814
SG		 4440 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4441 sizeof(*prot_sentry), 64);
4442 }
4443
4444 *seg += wqe_size;
4445 *size += wqe_size / 16;
34f4c955 4446 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814
SG		 4447
4448 bsf = *seg;
4449 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4450 if (ret)
4451 return -EINVAL;
4452
4453 *seg += sizeof(*bsf);
4454 *size += sizeof(*bsf) / 16;
34f4c955 4455 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814
SG		 4456
4457 return 0;
4458}
4459
4460static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
f696bf6d 4461 const struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4462 u32 length, u32 pdn)
4463{
e622f2f4 4464 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4465 u32 sig_key = sig_mr->rkey;
d5436ba0 4466 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4467
4468 memset(seg, 0, sizeof(*seg));
4469
e622f2f4 4470 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4471 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4472 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4473 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4474 MLX5_MKEY_BSF_EN | pdn);
4475 seg->len = cpu_to_be64(length);
31616255 4476 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4477 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4478}
4479
4480static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4481 u32 size)
e6631814
SG		 4482{
4483 memset(umr, 0, sizeof(*umr));
4484
4485 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4486 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4487 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4488 umr->mkey_mask = sig_mkey_mask();
4489}
4490
4491
f696bf6d 4492static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
34f4c955
GL		 4493 struct mlx5_ib_qp *qp, void **seg, int *size,
4494 void **cur_edge)
e6631814 4495{
f696bf6d 4496 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
e622f2f4 4497 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4498 u32 pdn = get_pd(qp)->pdn;
31616255 4499 u32 xlt_size;
e6631814
SG		 4500 int region_len, ret;
4501
e622f2f4
CH		 4502 if (unlikely(wr->wr.num_sge != 1) ||
4503 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4504 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4505 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4506 return -EINVAL;
4507
4508 /* length of the protected region, data + protection */
e622f2f4
CH		 4509 region_len = wr->wr.sg_list->length;
4510 if (wr->prot &&
4511 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4512 wr->prot->addr != wr->wr.sg_list->addr ||
4513 wr->prot->length != wr->wr.sg_list->length))
4514 region_len += wr->prot->length;
e6631814
SG		 4515
4516 /**
4517 * KLM octoword size - if protection was provided
4518 * then we use strided block format (3 octowords),
4519 * else we use single KLM (1 octoword)
4520 **/
31616255 4521 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4522
31616255 4523 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4524 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4525 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4526 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814 4527
31616255 4528 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4529 *seg += sizeof(struct mlx5_mkey_seg);
4530 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4531 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814 4532
34f4c955 4533 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
e6631814
SG		 4534 if (ret)
4535 return ret;
4536
d5436ba0 4537 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4538 return 0;
4539}
4540
4541static int set_psv_wr(struct ib_sig_domain *domain,
4542 u32 psv_idx, void **seg, int *size)
4543{
4544 struct mlx5_seg_set_psv *psv_seg = *seg;
4545
4546 memset(psv_seg, 0, sizeof(*psv_seg));
4547 psv_seg->psv_num = cpu_to_be32(psv_idx);
4548 switch (domain->sig_type) {
78eda2bb
SG		 4549 case IB_SIG_TYPE_NONE:
4550 break;
e6631814
SG		 4551 case IB_SIG_TYPE_T10_DIF:
4552 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4553 domain->sig.dif.app_tag);
4554 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4555 break;
e6631814 4556 default:
12bbf1ea
LR		 4557 pr_err("Bad signature type (%d) is given.\n",
4558 domain->sig_type);
4559 return -EINVAL;
e6631814
SG		 4560 }
4561
78eda2bb
SG		 4562 *seg += sizeof(*psv_seg);
4563 *size += sizeof(*psv_seg) / 16;
4564
e6631814
SG		 4565 return 0;
4566}
4567
8a187ee5 4568static int set_reg_wr(struct mlx5_ib_qp *qp,
f696bf6d 4569 const struct ib_reg_wr *wr,
34f4c955 4570 void **seg, int *size, void **cur_edge)
8a187ee5
SG		 4571{
4572 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4573 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
34f4c955 4574 size_t mr_list_size = mr->ndescs * mr->desc_size;
064e5262 4575 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
8a187ee5
SG		 4576
4577 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4578 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4579 "Invalid IB_SEND_INLINE send flag\n");
4580 return -EINVAL;
4581 }
4582
064e5262 4583 set_reg_umr_seg(*seg, mr, umr_inline);
8a187ee5
SG		 4584 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4585 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4586 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
8a187ee5
SG		 4587
4588 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4589 *seg += sizeof(struct mlx5_mkey_seg);
4590 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4591 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
8a187ee5 4592
064e5262 4593 if (umr_inline) {
34f4c955
GL		 4594 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4595 mr_list_size);
4596 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
064e5262
IB		 4597 } else {
4598 set_reg_data_seg(*seg, mr, pd);
4599 *seg += sizeof(struct mlx5_wqe_data_seg);
4600 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4601 }
8a187ee5
SG		 4602 return 0;
4603}
4604
34f4c955
GL		 4605static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4606 void **cur_edge)
e126ba97 4607{
dd01e66a 4608 set_linv_umr_seg(*seg);
e126ba97
EC		 4609 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4610 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4611 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
dd01e66a 4612 set_linv_mkey_seg(*seg);
e126ba97
EC		 4613 *seg += sizeof(struct mlx5_mkey_seg);
4614 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4615 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e126ba97
EC		 4616}
4617
34f4c955 4618static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
e126ba97
EC		 4619{
4620 __be32 *p = NULL;
34f4c955 4621 u32 tidx = idx;
e126ba97
EC		 4622 int i, j;
4623
34f4c955 4624 pr_debug("dump WQE index %u:\n", idx);
e126ba97
EC		 4625 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4626 if ((i & 0xf) == 0) {
e126ba97 4627 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
34f4c955
GL		 4628 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx);
4629 pr_debug("WQBB at %p:\n", (void *)p);
e126ba97
EC		 4630 j = 0;
4631 }
4632 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4633 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4634 be32_to_cpu(p[j + 3]));
4635 }
4636}
4637
7bb1fafc 4638static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
34f4c955
GL		 4639 struct mlx5_wqe_ctrl_seg **ctrl,
4640 const struct ib_send_wr *wr, unsigned int *idx,
4641 int *size, void **cur_edge, int nreq,
4642 bool send_signaled, bool solicited)
6e5eadac 4643{
b2a232d2
LR		 4644 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4645 return -ENOMEM;
6e5eadac
SG		 4646
4647 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
34f4c955 4648 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
6e5eadac
SG		 4649 *ctrl = *seg;
4650 *(uint32_t *)(*seg + 8) = 0;
4651 (*ctrl)->imm = send_ieth(wr);
4652 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
7bb1fafc
BVA		 4653 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4654 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
6e5eadac
SG		 4655
4656 *seg += sizeof(**ctrl);
4657 *size = sizeof(**ctrl) / 16;
34f4c955 4658 *cur_edge = qp->sq.cur_edge;
6e5eadac 4659
b2a232d2 4660 return 0;
6e5eadac
SG		 4661}
4662
7bb1fafc
BVA		 4663static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4664 struct mlx5_wqe_ctrl_seg **ctrl,
4665 const struct ib_send_wr *wr, unsigned *idx,
34f4c955 4666 int *size, void **cur_edge, int nreq)
7bb1fafc 4667{
34f4c955 4668 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
7bb1fafc
BVA		 4669 wr->send_flags & IB_SEND_SIGNALED,
4670 wr->send_flags & IB_SEND_SOLICITED);
4671}
4672
6e5eadac
SG		 4673static void finish_wqe(struct mlx5_ib_qp *qp,
4674 struct mlx5_wqe_ctrl_seg *ctrl,
34f4c955
GL		 4675 void *seg, u8 size, void *cur_edge,
4676 unsigned int idx, u64 wr_id, int nreq, u8 fence,
4677 u32 mlx5_opcode)
6e5eadac
SG		 4678{
4679 u8 opmod = 0;
4680
4681 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4682 mlx5_opcode | ((u32)opmod << 24));
19098df2 4683 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4684 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4685 if (unlikely(qp->wq_sig))
4686 ctrl->signature = wq_sig(ctrl);
4687
4688 qp->sq.wrid[idx] = wr_id;
4689 qp->sq.w_list[idx].opcode = mlx5_opcode;
4690 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4691 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4692 qp->sq.w_list[idx].next = qp->sq.cur_post;
34f4c955
GL		 4693
4694 /* We save the edge which was possibly updated during the WQE
4695 * construction, into SQ's cache.
4696 */
4697 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4698 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4699 get_sq_edge(&qp->sq, qp->sq.cur_post &
4700 (qp->sq.wqe_cnt - 1)) :
4701 cur_edge;
6e5eadac
SG		 4702}
4703
d34ac5cd
BVA		 4704static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4705 const struct ib_send_wr **bad_wr, bool drain)
e126ba97
EC		 4706{
4707 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4708 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4709 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4710 struct mlx5_ib_qp *qp;
e6631814 4711 struct mlx5_ib_mr *mr;
e126ba97 4712 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4713 struct mlx5_bf *bf;
34f4c955 4714 void *cur_edge;
e126ba97 4715 int uninitialized_var(size);
e126ba97 4716 unsigned long flags;
e126ba97
EC		 4717 unsigned idx;
4718 int err = 0;
e126ba97
EC		 4719 int num_sge;
4720 void *seg;
4721 int nreq;
4722 int i;
4723 u8 next_fence = 0;
e126ba97
EC		 4724 u8 fence;
4725
6c75520f
PP		 4726 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4727 !drain)) {
4728 *bad_wr = wr;
4729 return -EIO;
4730 }
4731
d16e91da
HE		 4732 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4733 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4734
4735 qp = to_mqp(ibqp);
5fe9dec0 4736 bf = &qp->bf;
d16e91da 4737
e126ba97
EC		 4738 spin_lock_irqsave(&qp->sq.lock, flags);
4739
4740 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4741 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4742 mlx5_ib_warn(dev, "\n");
4743 err = -EINVAL;
4744 *bad_wr = wr;
4745 goto out;
4746 }
4747
6e5eadac
SG		 4748 num_sge = wr->num_sge;
4749 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4750 mlx5_ib_warn(dev, "\n");
24be409b 4751 err = -EINVAL;
e126ba97
EC		 4752 *bad_wr = wr;
4753 goto out;
4754 }
4755
34f4c955
GL		 4756 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4757 nreq);
6e5eadac 4758 if (err) {
e126ba97
EC		 4759 mlx5_ib_warn(dev, "\n");
4760 err = -ENOMEM;
4761 *bad_wr = wr;
4762 goto out;
4763 }
4764
074fca3a 4765 if (wr->opcode == IB_WR_REG_MR) {
6e8484c5
MG		 4766 fence = dev->umr_fence;
4767 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
074fca3a
MD		 4768 } else {
4769 if (wr->send_flags & IB_SEND_FENCE) {
4770 if (qp->next_fence)
4771 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4772 else
4773 fence = MLX5_FENCE_MODE_FENCE;
4774 } else {
4775 fence = qp->next_fence;
4776 }
6e8484c5
MG		 4777 }
4778
e126ba97
EC		 4779 switch (ibqp->qp_type) {
4780 case IB_QPT_XRC_INI:
4781 xrc = seg;
e126ba97
EC		 4782 seg += sizeof(*xrc);
4783 size += sizeof(*xrc) / 16;
4784 /* fall through */
4785 case IB_QPT_RC:
4786 switch (wr->opcode) {
4787 case IB_WR_RDMA_READ:
4788 case IB_WR_RDMA_WRITE:
4789 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4790 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4791 rdma_wr(wr)->rkey);
f241e749 4792 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4793 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4794 break;
4795
4796 case IB_WR_ATOMIC_CMP_AND_SWP:
4797 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4798 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4799 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4800 err = -ENOSYS;
4801 *bad_wr = wr;
4802 goto out;
e126ba97
EC		 4803
4804 case IB_WR_LOCAL_INV:
e126ba97
EC		 4805 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4806 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
34f4c955 4807 set_linv_wr(qp, &seg, &size, &cur_edge);
e126ba97
EC		 4808 num_sge = 0;
4809 break;
4810
8a187ee5 4811 case IB_WR_REG_MR:
8a187ee5
SG		 4812 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4813 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
34f4c955
GL		 4814 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4815 &cur_edge);
8a187ee5
SG		 4816 if (err) {
4817 *bad_wr = wr;
4818 goto out;
4819 }
4820 num_sge = 0;
4821 break;
4822
e6631814
SG		 4823 case IB_WR_REG_SIG_MR:
4824 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4825 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4826
4827 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
34f4c955
GL		 4828 err = set_sig_umr_wr(wr, qp, &seg, &size,
4829 &cur_edge);
e6631814
SG		 4830 if (err) {
4831 mlx5_ib_warn(dev, "\n");
4832 *bad_wr = wr;
4833 goto out;
4834 }
4835
34f4c955
GL		 4836 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4837 wr->wr_id, nreq, fence,
4838 MLX5_OPCODE_UMR);
e6631814
SG		 4839 /*
4840 * SET_PSV WQEs are not signaled and solicited
4841 * on error
4842 */
7bb1fafc 4843 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
34f4c955
GL		 4844 &size, &cur_edge, nreq, false,
4845 true);
e6631814
SG		 4846 if (err) {
4847 mlx5_ib_warn(dev, "\n");
4848 err = -ENOMEM;
4849 *bad_wr = wr;
4850 goto out;
4851 }
4852
e622f2f4 4853 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4854 mr->sig->psv_memory.psv_idx, &seg,
4855 &size);
4856 if (err) {
4857 mlx5_ib_warn(dev, "\n");
4858 *bad_wr = wr;
4859 goto out;
4860 }
4861
34f4c955
GL		 4862 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4863 wr->wr_id, nreq, fence,
4864 MLX5_OPCODE_SET_PSV);
7bb1fafc 4865 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
34f4c955
GL		 4866 &size, &cur_edge, nreq, false,
4867 true);
e6631814
SG		 4868 if (err) {
4869 mlx5_ib_warn(dev, "\n");
4870 err = -ENOMEM;
4871 *bad_wr = wr;
4872 goto out;
4873 }
4874
e622f2f4 4875 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4876 mr->sig->psv_wire.psv_idx, &seg,
4877 &size);
4878 if (err) {
4879 mlx5_ib_warn(dev, "\n");
4880 *bad_wr = wr;
4881 goto out;
4882 }
4883
34f4c955
GL		 4884 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4885 wr->wr_id, nreq, fence,
4886 MLX5_OPCODE_SET_PSV);
6e8484c5 4887 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4888 num_sge = 0;
4889 goto skip_psv;
4890
e126ba97
EC		 4891 default:
4892 break;
4893 }
4894 break;
4895
4896 case IB_QPT_UC:
4897 switch (wr->opcode) {
4898 case IB_WR_RDMA_WRITE:
4899 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4900 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4901 rdma_wr(wr)->rkey);
e126ba97
EC		 4902 seg += sizeof(struct mlx5_wqe_raddr_seg);
4903 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4904 break;
4905
4906 default:
4907 break;
4908 }
4909 break;
4910
e126ba97 4911 case IB_QPT_SMI:
1e0e50b6
MG		 4912 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4913 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4914 err = -EPERM;
4915 *bad_wr = wr;
4916 goto out;
4917 }
f6b1ee34 4918 /* fall through */
d16e91da 4919 case MLX5_IB_QPT_HW_GSI:
e126ba97 4920 set_datagram_seg(seg, wr);
f241e749 4921 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97 4922 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
34f4c955
GL		 4923 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4924
e126ba97 4925 break;
f0313965
ES		 4926 case IB_QPT_UD:
4927 set_datagram_seg(seg, wr);
4928 seg += sizeof(struct mlx5_wqe_datagram_seg);
4929 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
34f4c955 4930 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
f0313965
ES		 4931
4932 /* handle qp that supports ud offload */
4933 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4934 struct mlx5_wqe_eth_pad *pad;
e126ba97 4935
f0313965
ES		 4936 pad = seg;
4937 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4938 seg += sizeof(struct mlx5_wqe_eth_pad);
4939 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
34f4c955
GL		 4940 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
4941 handle_post_send_edge(&qp->sq, &seg, size,
4942 &cur_edge);
f0313965
ES		 4943 }
4944 break;
e126ba97
EC		 4945 case MLX5_IB_QPT_REG_UMR:
4946 if (wr->opcode != MLX5_IB_WR_UMR) {
4947 err = -EINVAL;
4948 mlx5_ib_warn(dev, "bad opcode\n");
4949 goto out;
4950 }
4951 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4952 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
c8d75a98
MD		 4953 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4954 if (unlikely(err))
4955 goto out;
e126ba97
EC		 4956 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4957 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4958 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
e126ba97
EC		 4959 set_reg_mkey_segment(seg, wr);
4960 seg += sizeof(struct mlx5_mkey_seg);
4961 size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4962 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
e126ba97
EC		 4963 break;
4964
4965 default:
4966 break;
4967 }
4968
4969 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
34f4c955 4970 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
e126ba97
EC		 4971 if (unlikely(err)) {
4972 mlx5_ib_warn(dev, "\n");
4973 *bad_wr = wr;
4974 goto out;
4975 }
e126ba97 4976 } else {
e126ba97 4977 for (i = 0; i < num_sge; i++) {
34f4c955
GL		 4978 handle_post_send_edge(&qp->sq, &seg, size,
4979 &cur_edge);
e126ba97 4980 if (likely(wr->sg_list[i].length)) {
34f4c955
GL		 4981 set_data_ptr_seg
4982 ((struct mlx5_wqe_data_seg *)seg,
4983 wr->sg_list + i);
e126ba97 4984 size += sizeof(struct mlx5_wqe_data_seg) / 16;
34f4c955 4985 seg += sizeof(struct mlx5_wqe_data_seg);
e126ba97
EC		 4986 }
4987 }
4988 }
4989
6e8484c5 4990 qp->next_fence = next_fence;
34f4c955
GL		 4991 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
4992 fence, mlx5_ib_opcode[wr->opcode]);
e6631814 4993skip_psv:
e126ba97
EC		 4994 if (0)
4995 dump_wqe(qp, idx, size);
4996 }
4997
4998out:
4999 if (likely(nreq)) {
5000 qp->sq.head += nreq;
5001
5002 /* Make sure that descriptors are written before
5003 * updating doorbell record and ringing the doorbell
5004 */
5005 wmb();
5006
5007 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5008
ada388f7
EC		 5009 /* Make sure doorbell record is visible to the HCA before
5010 * we hit doorbell */
5011 wmb();
5012
5fe9dec0
EC		 5013 /* currently we support only regular doorbells */
5014 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
5015 /* Make sure doorbells don't leak out of SQ spinlock
5016 * and reach the HCA out of order.
5017 */
5018 mmiowb();
e126ba97 5019 bf->offset ^= bf->buf_size;
e126ba97
EC		 5020 }
5021
5022 spin_unlock_irqrestore(&qp->sq.lock, flags);
5023
5024 return err;
5025}
5026
d34ac5cd
BVA		 5027int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5028 const struct ib_send_wr **bad_wr)
d0e84c0a
YH		 5029{
5030 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5031}
5032
e126ba97
EC		 5033static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5034{
5035 sig->signature = calc_sig(sig, size);
5036}
5037
d34ac5cd
BVA		 5038static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5039 const struct ib_recv_wr **bad_wr, bool drain)
e126ba97
EC		 5040{
5041 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5042 struct mlx5_wqe_data_seg *scat;
5043 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 5044 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5045 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 5046 unsigned long flags;
5047 int err = 0;
5048 int nreq;
5049 int ind;
5050 int i;
5051
6c75520f
PP		 5052 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5053 !drain)) {
5054 *bad_wr = wr;
5055 return -EIO;
5056 }
5057
d16e91da
HE		 5058 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5059 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5060
e126ba97
EC		 5061 spin_lock_irqsave(&qp->rq.lock, flags);
5062
5063 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5064
5065 for (nreq = 0; wr; nreq++, wr = wr->next) {
5066 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5067 err = -ENOMEM;
5068 *bad_wr = wr;
5069 goto out;
5070 }
5071
5072 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5073 err = -EINVAL;
5074 *bad_wr = wr;
5075 goto out;
5076 }
5077
34f4c955 5078 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
e126ba97
EC		 5079 if (qp->wq_sig)
5080 scat++;
5081
5082 for (i = 0; i < wr->num_sge; i++)
5083 set_data_ptr_seg(scat + i, wr->sg_list + i);
5084
5085 if (i < qp->rq.max_gs) {
5086 scat[i].byte_count = 0;
5087 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
5088 scat[i].addr = 0;
5089 }
5090
5091 if (qp->wq_sig) {
5092 sig = (struct mlx5_rwqe_sig *)scat;
5093 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5094 }
5095
5096 qp->rq.wrid[ind] = wr->wr_id;
5097
5098 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5099 }
5100
5101out:
5102 if (likely(nreq)) {
5103 qp->rq.head += nreq;
5104
5105 /* Make sure that descriptors are written before
5106 * doorbell record.
5107 */
5108 wmb();
5109
5110 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5111 }
5112
5113 spin_unlock_irqrestore(&qp->rq.lock, flags);
5114
5115 return err;
5116}
5117
d34ac5cd
BVA		 5118int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5119 const struct ib_recv_wr **bad_wr)
d0e84c0a
YH		 5120{
5121 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5122}
5123
e126ba97
EC		 5124static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5125{
5126 switch (mlx5_state) {
5127 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
5128 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
5129 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
5130 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
5131 case MLX5_QP_STATE_SQ_DRAINING:
5132 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
5133 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
5134 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
5135 default: return -1;
5136 }
5137}
5138
5139static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5140{
5141 switch (mlx5_mig_state) {
5142 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
5143 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
5144 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
5145 default: return -1;
5146 }
5147}
5148
5149static int to_ib_qp_access_flags(int mlx5_flags)
5150{
5151 int ib_flags = 0;
5152
5153 if (mlx5_flags & MLX5_QP_BIT_RRE)
5154 ib_flags |= IB_ACCESS_REMOTE_READ;
5155 if (mlx5_flags & MLX5_QP_BIT_RWE)
5156 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5157 if (mlx5_flags & MLX5_QP_BIT_RAE)
5158 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5159
5160 return ib_flags;
5161}
5162
38349389 5163static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 5164 struct rdma_ah_attr *ah_attr,
38349389 5165 struct mlx5_qp_path *path)
e126ba97 5166{
e126ba97 5167
d8966fcd 5168 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 5169
e7996a9a 5170 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 5171 return;
5172
ae59c3f0
LR		 5173 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5174
d8966fcd
DC		 5175 rdma_ah_set_port_num(ah_attr, path->port);
5176 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5177
5178 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5179 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5180 rdma_ah_set_static_rate(ah_attr,
5181 path->static_rate ? path->static_rate - 5 : 0);
5182 if (path->grh_mlid & (1 << 7)) {
5183 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5184
5185 rdma_ah_set_grh(ah_attr, NULL,
5186 tc_fl & 0xfffff,
5187 path->mgid_index,
5188 path->hop_limit,
5189 (tc_fl >> 20) & 0xff);
5190 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 5191 }
5192}
5193
6d2f89df 5194static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5195 struct mlx5_ib_sq *sq,
5196 u8 *sq_state)
5197{
6d2f89df 5198 int err;
5199
28160771 5200 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 5201 if (err)
5202 goto out;
6d2f89df 5203 sq->state = *sq_state;
5204
5205out:
6d2f89df 5206 return err;
5207}
5208
5209static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5210 struct mlx5_ib_rq *rq,
5211 u8 *rq_state)
5212{
5213 void *out;
5214 void *rqc;
5215 int inlen;
5216 int err;
5217
5218 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 5219 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 5220 if (!out)
5221 return -ENOMEM;
5222
5223 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5224 if (err)
5225 goto out;
5226
5227 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5228 *rq_state = MLX5_GET(rqc, rqc, state);
5229 rq->state = *rq_state;
5230
5231out:
5232 kvfree(out);
5233 return err;
5234}
5235
5236static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5237 struct mlx5_ib_qp *qp, u8 *qp_state)
5238{
5239 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5240 [MLX5_RQC_STATE_RST] = {
5241 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5242 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5243 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5244 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5245 },
5246 [MLX5_RQC_STATE_RDY] = {
5247 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5248 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5249 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5250 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5251 },
5252 [MLX5_RQC_STATE_ERR] = {
5253 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5254 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5255 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5256 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5257 },
5258 [MLX5_RQ_STATE_NA] = {
5259 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5260 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5261 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5262 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5263 },
5264 };
5265
5266 *qp_state = sqrq_trans[rq_state][sq_state];
5267
5268 if (*qp_state == MLX5_QP_STATE_BAD) {
5269 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5270 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5271 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5272 return -EINVAL;
5273 }
5274
5275 if (*qp_state == MLX5_QP_STATE)
5276 *qp_state = qp->state;
5277
5278 return 0;
5279}
5280
5281static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5282 struct mlx5_ib_qp *qp,
5283 u8 *raw_packet_qp_state)
5284{
5285 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5286 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5287 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5288 int err;
5289 u8 sq_state = MLX5_SQ_STATE_NA;
5290 u8 rq_state = MLX5_RQ_STATE_NA;
5291
5292 if (qp->sq.wqe_cnt) {
5293 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5294 if (err)
5295 return err;
5296 }
5297
5298 if (qp->rq.wqe_cnt) {
5299 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5300 if (err)
5301 return err;
5302 }
5303
5304 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5305 raw_packet_qp_state);
5306}
5307
5308static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5309 struct ib_qp_attr *qp_attr)
e126ba97 5310{
09a7d9ec 5311 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 5312 struct mlx5_qp_context *context;
5313 int mlx5_state;
09a7d9ec 5314 u32 *outb;
e126ba97
EC		 5315 int err = 0;
5316
09a7d9ec 5317 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 5318 if (!outb)
5319 return -ENOMEM;
5320
19098df2 5321 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 5322 outlen);
e126ba97 5323 if (err)
6d2f89df 5324 goto out;
e126ba97 5325
09a7d9ec
SM		 5326 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5327 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5328
e126ba97
EC		 5329 mlx5_state = be32_to_cpu(context->flags) >> 28;
5330
5331 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 5332 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5333 qp_attr->path_mig_state =
5334 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5335 qp_attr->qkey = be32_to_cpu(context->qkey);
5336 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5337 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5338 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5339 qp_attr->qp_access_flags =
5340 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5341
5342 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 5343 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5344 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 5345 qp_attr->alt_pkey_index =
5346 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 5347 qp_attr->alt_port_num =
5348 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 5349 }
5350
d3ae2bde 5351 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 5352 qp_attr->port_num = context->pri_path.port;
5353
5354 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5355 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5356
5357 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5358
5359 qp_attr->max_dest_rd_atomic =
5360 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5361 qp_attr->min_rnr_timer =
5362 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5363 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5364 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5365 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5366 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 5367
5368out:
5369 kfree(outb);
5370 return err;
5371}
5372
776a3906
MS		 5373static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5374 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5375 struct ib_qp_init_attr *qp_init_attr)
5376{
5377 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5378 u32 *out;
5379 u32 access_flags = 0;
5380 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5381 void *dctc;
5382 int err;
5383 int supported_mask = IB_QP_STATE |
5384 IB_QP_ACCESS_FLAGS |
5385 IB_QP_PORT |
5386 IB_QP_MIN_RNR_TIMER |
5387 IB_QP_AV |
5388 IB_QP_PATH_MTU |
5389 IB_QP_PKEY_INDEX;
5390
5391 if (qp_attr_mask & ~supported_mask)
5392 return -EINVAL;
5393 if (mqp->state != IB_QPS_RTR)
5394 return -EINVAL;
5395
5396 out = kzalloc(outlen, GFP_KERNEL);
5397 if (!out)
5398 return -ENOMEM;
5399
5400 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5401 if (err)
5402 goto out;
5403
5404 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5405
5406 if (qp_attr_mask & IB_QP_STATE)
5407 qp_attr->qp_state = IB_QPS_RTR;
5408
5409 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5410 if (MLX5_GET(dctc, dctc, rre))
5411 access_flags |= IB_ACCESS_REMOTE_READ;
5412 if (MLX5_GET(dctc, dctc, rwe))
5413 access_flags |= IB_ACCESS_REMOTE_WRITE;
5414 if (MLX5_GET(dctc, dctc, rae))
5415 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5416 qp_attr->qp_access_flags = access_flags;
5417 }
5418
5419 if (qp_attr_mask & IB_QP_PORT)
5420 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5421 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5422 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5423 if (qp_attr_mask & IB_QP_AV) {
5424 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5425 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5426 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5427 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5428 }
5429 if (qp_attr_mask & IB_QP_PATH_MTU)
5430 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5431 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5432 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5433out:
5434 kfree(out);
5435 return err;
5436}
5437
6d2f89df 5438int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5439 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5440{
5441 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5442 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5443 int err = 0;
5444 u8 raw_packet_qp_state;
5445
28d61370
YH		 5446 if (ibqp->rwq_ind_tbl)
5447 return -ENOSYS;
5448
d16e91da
HE		 5449 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5450 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5451 qp_init_attr);
5452
c2e53b2c
YH		 5453 /* Not all of output fields are applicable, make sure to zero them */
5454 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5455 memset(qp_attr, 0, sizeof(*qp_attr));
5456
776a3906
MS		 5457 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5458 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5459 qp_attr_mask, qp_init_attr);
5460
6d2f89df 5461 mutex_lock(&qp->mutex);
5462
c2e53b2c
YH		 5463 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5464 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5465 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5466 if (err)
5467 goto out;
5468 qp->state = raw_packet_qp_state;
5469 qp_attr->port_num = 1;
5470 } else {
5471 err = query_qp_attr(dev, qp, qp_attr);
5472 if (err)
5473 goto out;
5474 }
5475
5476 qp_attr->qp_state = qp->state;
e126ba97
EC		 5477 qp_attr->cur_qp_state = qp_attr->qp_state;
5478 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5479 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5480
5481 if (!ibqp->uobject) {
0540d814 5482 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5483 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5484 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5485 } else {
5486 qp_attr->cap.max_send_wr = 0;
5487 qp_attr->cap.max_send_sge = 0;
5488 }
5489
0540d814
NO		 5490 qp_init_attr->qp_type = ibqp->qp_type;
5491 qp_init_attr->recv_cq = ibqp->recv_cq;
5492 qp_init_attr->send_cq = ibqp->send_cq;
5493 qp_init_attr->srq = ibqp->srq;
5494 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5495
5496 qp_init_attr->cap = qp_attr->cap;
5497
5498 qp_init_attr->create_flags = 0;
5499 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5500 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5501
051f2630
LR		 5502 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5503 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5504 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5505 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5506 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5507 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5508 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5509 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5510
e126ba97
EC		 5511 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5512 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5513
e126ba97
EC		 5514out:
5515 mutex_unlock(&qp->mutex);
5516 return err;
5517}
5518
5519struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5520 struct ib_ucontext *context,
5521 struct ib_udata *udata)
5522{
5523 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5524 struct mlx5_ib_xrcd *xrcd;
5525 int err;
5526
938fe83c 5527 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5528 return ERR_PTR(-ENOSYS);
5529
5530 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5531 if (!xrcd)
5532 return ERR_PTR(-ENOMEM);
5533
5aa3771d 5534 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
e126ba97
EC		 5535 if (err) {
5536 kfree(xrcd);
5537 return ERR_PTR(-ENOMEM);
5538 }
5539
5540 return &xrcd->ibxrcd;
5541}
5542
5543int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5544{
5545 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5546 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5547 int err;
5548
5aa3771d 5549 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
b081808a 5550 if (err)
e126ba97 5551 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5552
5553 kfree(xrcd);
e126ba97
EC		 5554 return 0;
5555}
79b20a6c 5556
350d0e4c
YH		 5557static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5558{
5559 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5560 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5561 struct ib_event event;
5562
5563 if (rwq->ibwq.event_handler) {
5564 event.device = rwq->ibwq.device;
5565 event.element.wq = &rwq->ibwq;
5566 switch (type) {
5567 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5568 event.event = IB_EVENT_WQ_FATAL;
5569 break;
5570 default:
5571 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5572 return;
5573 }
5574
5575 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5576 }
5577}
5578
03404e8a
MG		 5579static int set_delay_drop(struct mlx5_ib_dev *dev)
5580{
5581 int err = 0;
5582
5583 mutex_lock(&dev->delay_drop.lock);
5584 if (dev->delay_drop.activate)
5585 goto out;
5586
5587 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5588 if (err)
5589 goto out;
5590
5591 dev->delay_drop.activate = true;
5592out:
5593 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5594
5595 if (!err)
5596 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5597 return err;
5598}
5599
79b20a6c
YH		 5600static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5601 struct ib_wq_init_attr *init_attr)
5602{
5603 struct mlx5_ib_dev *dev;
4be6da1e 5604 int has_net_offloads;
79b20a6c
YH		 5605 __be64 *rq_pas0;
5606 void *in;
5607 void *rqc;
5608 void *wq;
5609 int inlen;
5610 int err;
5611
5612 dev = to_mdev(pd->device);
5613
5614 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5615 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5616 if (!in)
5617 return -ENOMEM;
5618
34d57585 5619 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 5620 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5621 MLX5_SET(rqc, rqc, mem_rq_type,
5622 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5623 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5624 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5625 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5626 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5627 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5628 MLX5_SET(wq, wq, wq_type,
5629 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5630 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5631 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5632 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5633 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5634 err = -EOPNOTSUPP;
5635 goto out;
5636 } else {
5637 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5638 }
5639 }
79b20a6c 5640 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5641 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5642 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5643 MLX5_SET(wq, wq, log_wqe_stride_size,
5644 rwq->single_stride_log_num_of_bytes -
5645 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5646 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5647 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5648 }
79b20a6c
YH		 5649 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5650 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5651 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5652 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5653 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5654 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5655 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5656 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5657 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5658 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5659 err = -EOPNOTSUPP;
5660 goto out;
5661 }
5662 } else {
5663 MLX5_SET(rqc, rqc, vsd, 1);
5664 }
4be6da1e
NO		 5665 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5666 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5667 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5668 err = -EOPNOTSUPP;
5669 goto out;
5670 }
5671 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5672 }
03404e8a
MG		 5673 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5674 if (!(dev->ib_dev.attrs.raw_packet_caps &
5675 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5676 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5677 err = -EOPNOTSUPP;
5678 goto out;
5679 }
5680 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5681 }
79b20a6c
YH		 5682 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5683 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5684 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5685 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5686 err = set_delay_drop(dev);
5687 if (err) {
5688 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5689 err);
5690 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5691 } else {
5692 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5693 }
5694 }
b1f74a84 5695out:
79b20a6c
YH		 5696 kvfree(in);
5697 return err;
5698}
5699
5700static int set_user_rq_size(struct mlx5_ib_dev *dev,
5701 struct ib_wq_init_attr *wq_init_attr,
5702 struct mlx5_ib_create_wq *ucmd,
5703 struct mlx5_ib_rwq *rwq)
5704{
5705 /* Sanity check RQ size before proceeding */
5706 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5707 return -EINVAL;
5708
5709 if (!ucmd->rq_wqe_count)
5710 return -EINVAL;
5711
5712 rwq->wqe_count = ucmd->rq_wqe_count;
5713 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 5714 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5715 return -EINVAL;
5716
79b20a6c
YH		 5717 rwq->log_rq_stride = rwq->wqe_shift;
5718 rwq->log_rq_size = ilog2(rwq->wqe_count);
5719 return 0;
5720}
5721
5722static int prepare_user_rq(struct ib_pd *pd,
5723 struct ib_wq_init_attr *init_attr,
5724 struct ib_udata *udata,
5725 struct mlx5_ib_rwq *rwq)
5726{
5727 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5728 struct mlx5_ib_create_wq ucmd = {};
5729 int err;
5730 size_t required_cmd_sz;
5731
ccc87087
NO		 5732 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5733 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5734 if (udata->inlen < required_cmd_sz) {
5735 mlx5_ib_dbg(dev, "invalid inlen\n");
5736 return -EINVAL;
5737 }
5738
5739 if (udata->inlen > sizeof(ucmd) &&
5740 !ib_is_udata_cleared(udata, sizeof(ucmd),
5741 udata->inlen - sizeof(ucmd))) {
5742 mlx5_ib_dbg(dev, "inlen is not supported\n");
5743 return -EOPNOTSUPP;
5744 }
5745
5746 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5747 mlx5_ib_dbg(dev, "copy failed\n");
5748 return -EFAULT;
5749 }
5750
ccc87087 5751 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5752 mlx5_ib_dbg(dev, "invalid comp mask\n");
5753 return -EOPNOTSUPP;
ccc87087
NO		 5754 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5755 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5756 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5757 return -EOPNOTSUPP;
5758 }
5759 if ((ucmd.single_stride_log_num_of_bytes <
5760 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5761 (ucmd.single_stride_log_num_of_bytes >
5762 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5763 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5764 ucmd.single_stride_log_num_of_bytes,
5765 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5766 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5767 return -EINVAL;
5768 }
5769 if ((ucmd.single_wqe_log_num_of_strides >
5770 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5771 (ucmd.single_wqe_log_num_of_strides <
5772 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5773 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5774 ucmd.single_wqe_log_num_of_strides,
5775 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5776 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5777 return -EINVAL;
5778 }
5779 rwq->single_stride_log_num_of_bytes =
5780 ucmd.single_stride_log_num_of_bytes;
5781 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5782 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5783 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5784 }
5785
5786 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5787 if (err) {
5788 mlx5_ib_dbg(dev, "err %d\n", err);
5789 return err;
5790 }
5791
b0ea0fa5 5792 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
79b20a6c
YH		 5793 if (err) {
5794 mlx5_ib_dbg(dev, "err %d\n", err);
645ba597 5795 return err;
79b20a6c
YH		 5796 }
5797
5798 rwq->user_index = ucmd.user_index;
5799 return 0;
5800}
5801
5802struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5803 struct ib_wq_init_attr *init_attr,
5804 struct ib_udata *udata)
5805{
5806 struct mlx5_ib_dev *dev;
5807 struct mlx5_ib_rwq *rwq;
5808 struct mlx5_ib_create_wq_resp resp = {};
5809 size_t min_resp_len;
5810 int err;
5811
5812 if (!udata)
5813 return ERR_PTR(-ENOSYS);
5814
5815 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5816 if (udata->outlen && udata->outlen < min_resp_len)
5817 return ERR_PTR(-EINVAL);
5818
5819 dev = to_mdev(pd->device);
5820 switch (init_attr->wq_type) {
5821 case IB_WQT_RQ:
5822 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5823 if (!rwq)
5824 return ERR_PTR(-ENOMEM);
5825 err = prepare_user_rq(pd, init_attr, udata, rwq);
5826 if (err)
5827 goto err;
5828 err = create_rq(rwq, pd, init_attr);
5829 if (err)
5830 goto err_user_rq;
5831 break;
5832 default:
5833 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5834 init_attr->wq_type);
5835 return ERR_PTR(-EINVAL);
5836 }
5837
350d0e4c 5838 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5839 rwq->ibwq.state = IB_WQS_RESET;
5840 if (udata->outlen) {
5841 resp.response_length = offsetof(typeof(resp), response_length) +
5842 sizeof(resp.response_length);
5843 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5844 if (err)
5845 goto err_copy;
5846 }
5847
350d0e4c
YH		 5848 rwq->core_qp.event = mlx5_ib_wq_event;
5849 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5850 return &rwq->ibwq;
5851
5852err_copy:
350d0e4c 5853 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5854err_user_rq:
fe248c3a 5855 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5856err:
5857 kfree(rwq);
5858 return ERR_PTR(err);
5859}
5860
5861int mlx5_ib_destroy_wq(struct ib_wq *wq)
5862{
5863 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5864 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5865
350d0e4c 5866 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5867 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5868 kfree(rwq);
5869
5870 return 0;
5871}
5872
c5f90929
YH		 5873struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5874 struct ib_rwq_ind_table_init_attr *init_attr,
5875 struct ib_udata *udata)
5876{
5877 struct mlx5_ib_dev *dev = to_mdev(device);
5878 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5879 int sz = 1 << init_attr->log_ind_tbl_size;
5880 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5881 size_t min_resp_len;
5882 int inlen;
5883 int err;
5884 int i;
5885 u32 *in;
5886 void *rqtc;
5887
5888 if (udata->inlen > 0 &&
5889 !ib_is_udata_cleared(udata, 0,
5890 udata->inlen))
5891 return ERR_PTR(-EOPNOTSUPP);
5892
efd7f400
MG		 5893 if (init_attr->log_ind_tbl_size >
5894 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5895 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5896 init_attr->log_ind_tbl_size,
5897 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5898 return ERR_PTR(-EINVAL);
5899 }
5900
c5f90929
YH		 5901 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5902 if (udata->outlen && udata->outlen < min_resp_len)
5903 return ERR_PTR(-EINVAL);
5904
5905 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5906 if (!rwq_ind_tbl)
5907 return ERR_PTR(-ENOMEM);
5908
5909 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5910 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5911 if (!in) {
5912 err = -ENOMEM;
5913 goto err;
5914 }
5915
5916 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5917
5918 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5919 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5920
5921 for (i = 0; i < sz; i++)
5922 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5923
5deba86e
YH		 5924 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5925 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5926
c5f90929
YH		 5927 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5928 kvfree(in);
5929
5930 if (err)
5931 goto err;
5932
5933 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5934 if (udata->outlen) {
5935 resp.response_length = offsetof(typeof(resp), response_length) +
5936 sizeof(resp.response_length);
5937 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5938 if (err)
5939 goto err_copy;
5940 }
5941
5942 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5943
5944err_copy:
5deba86e 5945 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5946err:
5947 kfree(rwq_ind_tbl);
5948 return ERR_PTR(err);
5949}
5950
5951int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5952{
5953 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5954 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5955
5deba86e 5956 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5957
5958 kfree(rwq_ind_tbl);
5959 return 0;
5960}
5961
79b20a6c
YH		 5962int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5963 u32 wq_attr_mask, struct ib_udata *udata)
5964{
5965 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5966 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5967 struct mlx5_ib_modify_wq ucmd = {};
5968 size_t required_cmd_sz;
5969 int curr_wq_state;
5970 int wq_state;
5971 int inlen;
5972 int err;
5973 void *rqc;
5974 void *in;
5975
5976 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5977 if (udata->inlen < required_cmd_sz)
5978 return -EINVAL;
5979
5980 if (udata->inlen > sizeof(ucmd) &&
5981 !ib_is_udata_cleared(udata, sizeof(ucmd),
5982 udata->inlen - sizeof(ucmd)))
5983 return -EOPNOTSUPP;
5984
5985 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5986 return -EFAULT;
5987
5988 if (ucmd.comp_mask || ucmd.reserved)
5989 return -EOPNOTSUPP;
5990
5991 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5992 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5993 if (!in)
5994 return -ENOMEM;
5995
5996 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5997
5998 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5999 wq_attr->curr_wq_state : wq->state;
6000 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6001 wq_attr->wq_state : curr_wq_state;
6002 if (curr_wq_state == IB_WQS_ERR)
6003 curr_wq_state = MLX5_RQC_STATE_ERR;
6004 if (wq_state == IB_WQS_ERR)
6005 wq_state = MLX5_RQC_STATE_ERR;
6006 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 6007 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 6008 MLX5_SET(rqc, rqc, state, wq_state);
6009
b1f74a84
NO		 6010 if (wq_attr_mask & IB_WQ_FLAGS) {
6011 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6012 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6013 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6014 mlx5_ib_dbg(dev, "VLAN offloads are not "
6015 "supported\n");
6016 err = -EOPNOTSUPP;
6017 goto out;
6018 }
6019 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6020 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6021 MLX5_SET(rqc, rqc, vsd,
6022 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6023 }
b1383aa6
NO		 6024
6025 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6026 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6027 err = -EOPNOTSUPP;
6028 goto out;
6029 }
b1f74a84
NO		 6030 }
6031
23a6964e
MD		 6032 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6033 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6034 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6035 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 6036 MLX5_SET(rqc, rqc, counter_set_id,
6037 dev->port->cnts.set_id);
23a6964e 6038 } else
5a738b5d
JG		 6039 dev_info_once(
6040 &dev->ib_dev.dev,
6041 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 6042 }
6043
350d0e4c 6044 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 6045 if (!err)
6046 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6047
b1f74a84
NO		 6048out:
6049 kvfree(in);
79b20a6c
YH		 6050 return err;
6051}
d0e84c0a
YH		 6052
6053struct mlx5_ib_drain_cqe {
6054 struct ib_cqe cqe;
6055 struct completion done;
6056};
6057
6058static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6059{
6060 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6061 struct mlx5_ib_drain_cqe,
6062 cqe);
6063
6064 complete(&cqe->done);
6065}
6066
6067/* This function returns only once the drained WR was completed */
6068static void handle_drain_completion(struct ib_cq *cq,
6069 struct mlx5_ib_drain_cqe *sdrain,
6070 struct mlx5_ib_dev *dev)
6071{
6072 struct mlx5_core_dev *mdev = dev->mdev;
6073
6074 if (cq->poll_ctx == IB_POLL_DIRECT) {
6075 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6076 ib_process_cq_direct(cq, -1);
6077 return;
6078 }
6079
6080 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6081 struct mlx5_ib_cq *mcq = to_mcq(cq);
6082 bool triggered = false;
6083 unsigned long flags;
6084
6085 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6086 /* Make sure that the CQ handler won't run if wasn't run yet */
6087 if (!mcq->mcq.reset_notify_added)
6088 mcq->mcq.reset_notify_added = 1;
6089 else
6090 triggered = true;
6091 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6092
6093 if (triggered) {
6094 /* Wait for any scheduled/running task to be ended */
6095 switch (cq->poll_ctx) {
6096 case IB_POLL_SOFTIRQ:
6097 irq_poll_disable(&cq->iop);
6098 irq_poll_enable(&cq->iop);
6099 break;
6100 case IB_POLL_WORKQUEUE:
6101 cancel_work_sync(&cq->work);
6102 break;
6103 default:
6104 WARN_ON_ONCE(1);
6105 }
6106 }
6107
6108 /* Run the CQ handler - this makes sure that the drain WR will
6109 * be processed if wasn't processed yet.
6110 */
6111 mcq->mcq.comp(&mcq->mcq);
6112 }
6113
6114 wait_for_completion(&sdrain->done);
6115}
6116
6117void mlx5_ib_drain_sq(struct ib_qp *qp)
6118{
6119 struct ib_cq *cq = qp->send_cq;
6120 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6121 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 6122 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 6123 struct ib_rdma_wr swr = {
6124 .wr = {
6125 .next = NULL,
6126 { .wr_cqe = &sdrain.cqe, },
6127 .opcode = IB_WR_RDMA_WRITE,
6128 },
6129 };
6130 int ret;
6131 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6132 struct mlx5_core_dev *mdev = dev->mdev;
6133
6134 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6135 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6136 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6137 return;
6138 }
6139
6140 sdrain.cqe.done = mlx5_ib_drain_qp_done;
6141 init_completion(&sdrain.done);
6142
6143 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6144 if (ret) {
6145 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6146 return;
6147 }
6148
6149 handle_drain_completion(cq, &sdrain, dev);
6150}
6151
6152void mlx5_ib_drain_rq(struct ib_qp *qp)
6153{
6154 struct ib_cq *cq = qp->recv_cq;
6155 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6156 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 6157 struct ib_recv_wr rwr = {};
6158 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 6159 int ret;
6160 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6161 struct mlx5_core_dev *mdev = dev->mdev;
6162
6163 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6164 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6165 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6166 return;
6167 }
6168
6169 rwr.wr_cqe = &rdrain.cqe;
6170 rdrain.cqe.done = mlx5_ib_drain_qp_done;
6171 init_completion(&rdrain.done);
6172
6173 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6174 if (ret) {
6175 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6176 return;
6177 }
6178
6179 handle_drain_completion(cq, &rdrain, dev);
6180}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git