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mlx5: Fix layout of struct mlx5_init_seg
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
35#include "mlx5_ib.h"
36#include "user.h"
37
38/* not supported currently */
39static int wq_signature;
40
41enum {
42 MLX5_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
48 MLX5_IB_LINK_TYPE_IB = 0,
49 MLX5_IB_LINK_TYPE_ETH = 1
50};
51
52enum {
53 MLX5_IB_SQ_STRIDE = 6,
54 MLX5_IB_CACHE_LINE_SIZE = 64,
55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR,
68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
71};
72
73struct umr_wr {
74 u64 virt_addr;
75 struct ib_pd *pd;
76 unsigned int page_shift;
77 unsigned int npages;
78 u32 length;
79 int access_flags;
80 u32 mkey;
81};
82
83static int is_qp0(enum ib_qp_type qp_type)
84{
85 return qp_type == IB_QPT_SMI;
86}
87
88static int is_qp1(enum ib_qp_type qp_type)
89{
90 return qp_type == IB_QPT_GSI;
91}
92
93static int is_sqp(enum ib_qp_type qp_type)
94{
95 return is_qp0(qp_type) || is_qp1(qp_type);
96}
97
98static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99{
100 return mlx5_buf_offset(&qp->buf, offset);
101}
102
103static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104{
105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106}
107
108void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109{
110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111}
112
113static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
114{
115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116 struct ib_event event;
117
118 if (type == MLX5_EVENT_TYPE_PATH_MIG)
119 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
120
121 if (ibqp->event_handler) {
122 event.device = ibqp->device;
123 event.element.qp = ibqp;
124 switch (type) {
125 case MLX5_EVENT_TYPE_PATH_MIG:
126 event.event = IB_EVENT_PATH_MIG;
127 break;
128 case MLX5_EVENT_TYPE_COMM_EST:
129 event.event = IB_EVENT_COMM_EST;
130 break;
131 case MLX5_EVENT_TYPE_SQ_DRAINED:
132 event.event = IB_EVENT_SQ_DRAINED;
133 break;
134 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
135 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
136 break;
137 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
138 event.event = IB_EVENT_QP_FATAL;
139 break;
140 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
141 event.event = IB_EVENT_PATH_MIG_ERR;
142 break;
143 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
144 event.event = IB_EVENT_QP_REQ_ERR;
145 break;
146 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
147 event.event = IB_EVENT_QP_ACCESS_ERR;
148 break;
149 default:
150 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
151 return;
152 }
153
154 ibqp->event_handler(&event, ibqp->qp_context);
155 }
156}
157
158static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
159 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
160{
161 int wqe_size;
162 int wq_size;
163
164 /* Sanity check RQ size before proceeding */
165 if (cap->max_recv_wr > dev->mdev.caps.max_wqes)
166 return -EINVAL;
167
168 if (!has_rq) {
169 qp->rq.max_gs = 0;
170 qp->rq.wqe_cnt = 0;
171 qp->rq.wqe_shift = 0;
172 } else {
173 if (ucmd) {
174 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
175 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
176 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
177 qp->rq.max_post = qp->rq.wqe_cnt;
178 } else {
179 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
180 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
181 wqe_size = roundup_pow_of_two(wqe_size);
182 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
183 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
184 qp->rq.wqe_cnt = wq_size / wqe_size;
185 if (wqe_size > dev->mdev.caps.max_rq_desc_sz) {
186 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
187 wqe_size,
188 dev->mdev.caps.max_rq_desc_sz);
189 return -EINVAL;
190 }
191 qp->rq.wqe_shift = ilog2(wqe_size);
192 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
193 qp->rq.max_post = qp->rq.wqe_cnt;
194 }
195 }
196
197 return 0;
198}
199
200static int sq_overhead(enum ib_qp_type qp_type)
201{
618af384 202 int size = 0;
e126ba97
EC		 203
204 switch (qp_type) {
205 case IB_QPT_XRC_INI:
b125a54b 206 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 207 /* fall through */
208 case IB_QPT_RC:
209 size += sizeof(struct mlx5_wqe_ctrl_seg) +
210 sizeof(struct mlx5_wqe_atomic_seg) +
211 sizeof(struct mlx5_wqe_raddr_seg);
212 break;
213
b125a54b
EC		 214 case IB_QPT_XRC_TGT:
215 return 0;
216
e126ba97 217 case IB_QPT_UC:
b125a54b 218 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 219 sizeof(struct mlx5_wqe_raddr_seg);
220 break;
221
222 case IB_QPT_UD:
223 case IB_QPT_SMI:
224 case IB_QPT_GSI:
b125a54b 225 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 226 sizeof(struct mlx5_wqe_datagram_seg);
227 break;
228
229 case MLX5_IB_QPT_REG_UMR:
b125a54b 230 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 231 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
232 sizeof(struct mlx5_mkey_seg);
233 break;
234
235 default:
236 return -EINVAL;
237 }
238
239 return size;
240}
241
242static int calc_send_wqe(struct ib_qp_init_attr *attr)
243{
244 int inl_size = 0;
245 int size;
246
247 size = sq_overhead(attr->qp_type);
248 if (size < 0)
249 return size;
250
251 if (attr->cap.max_inline_data) {
252 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
253 attr->cap.max_inline_data;
254 }
255
256 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
257
258 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
259}
260
261static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
262 struct mlx5_ib_qp *qp)
263{
264 int wqe_size;
265 int wq_size;
266
267 if (!attr->cap.max_send_wr)
268 return 0;
269
270 wqe_size = calc_send_wqe(attr);
271 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
272 if (wqe_size < 0)
273 return wqe_size;
274
275 if (wqe_size > dev->mdev.caps.max_sq_desc_sz) {
b125a54b
EC		 276 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
277 wqe_size, dev->mdev.caps.max_sq_desc_sz);
e126ba97
EC		 278 return -EINVAL;
279 }
280
281 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
282 sizeof(struct mlx5_wqe_inline_seg);
283 attr->cap.max_inline_data = qp->max_inline_data;
284
285 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
286 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
b125a54b
EC		 287 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
288 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
289 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
290 return -ENOMEM;
291 }
e126ba97
EC		 292 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
293 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 294 qp->sq.max_post = wq_size / wqe_size;
295 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 296
297 return wq_size;
298}
299
300static int set_user_buf_size(struct mlx5_ib_dev *dev,
301 struct mlx5_ib_qp *qp,
302 struct mlx5_ib_create_qp *ucmd)
303{
304 int desc_sz = 1 << qp->sq.wqe_shift;
305
306 if (desc_sz > dev->mdev.caps.max_sq_desc_sz) {
307 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
308 desc_sz, dev->mdev.caps.max_sq_desc_sz);
309 return -EINVAL;
310 }
311
312 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
313 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
314 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
315 return -EINVAL;
316 }
317
318 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
319
320 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
321 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
322 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
323 return -EINVAL;
324 }
325
326 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
327 (qp->sq.wqe_cnt << 6);
328
329 return 0;
330}
331
332static int qp_has_rq(struct ib_qp_init_attr *attr)
333{
334 if (attr->qp_type == IB_QPT_XRC_INI ||
335 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
336 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
337 !attr->cap.max_recv_wr)
338 return 0;
339
340 return 1;
341}
342
343static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
344{
345 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
346 int start_uuar;
347 int i;
348
349 start_uuar = nuuars - uuari->num_low_latency_uuars;
350 for (i = start_uuar; i < nuuars; i++) {
351 if (!test_bit(i, uuari->bitmap)) {
352 set_bit(i, uuari->bitmap);
353 uuari->count[i]++;
354 return i;
355 }
356 }
357
358 return -ENOMEM;
359}
360
361static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
362{
363 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
364 int minidx = 1;
365 int uuarn;
366 int end;
367 int i;
368
369 end = nuuars - uuari->num_low_latency_uuars;
370
371 for (i = 1; i < end; i++) {
372 uuarn = i & 3;
373 if (uuarn == 2 || uuarn == 3)
374 continue;
375
376 if (uuari->count[i] < uuari->count[minidx])
377 minidx = i;
378 }
379
380 uuari->count[minidx]++;
381 return minidx;
382}
383
384static int alloc_uuar(struct mlx5_uuar_info *uuari,
385 enum mlx5_ib_latency_class lat)
386{
387 int uuarn = -EINVAL;
388
389 mutex_lock(&uuari->lock);
390 switch (lat) {
391 case MLX5_IB_LATENCY_CLASS_LOW:
392 uuarn = 0;
393 uuari->count[uuarn]++;
394 break;
395
396 case MLX5_IB_LATENCY_CLASS_MEDIUM:
397 uuarn = alloc_med_class_uuar(uuari);
398 break;
399
400 case MLX5_IB_LATENCY_CLASS_HIGH:
401 uuarn = alloc_high_class_uuar(uuari);
402 break;
403
404 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
405 uuarn = 2;
406 break;
407 }
408 mutex_unlock(&uuari->lock);
409
410 return uuarn;
411}
412
413static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
414{
415 clear_bit(uuarn, uuari->bitmap);
416 --uuari->count[uuarn];
417}
418
419static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
420{
421 clear_bit(uuarn, uuari->bitmap);
422 --uuari->count[uuarn];
423}
424
425static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
426{
427 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
428 int high_uuar = nuuars - uuari->num_low_latency_uuars;
429
430 mutex_lock(&uuari->lock);
431 if (uuarn == 0) {
432 --uuari->count[uuarn];
433 goto out;
434 }
435
436 if (uuarn < high_uuar) {
437 free_med_class_uuar(uuari, uuarn);
438 goto out;
439 }
440
441 free_high_class_uuar(uuari, uuarn);
442
443out:
444 mutex_unlock(&uuari->lock);
445}
446
447static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
448{
449 switch (state) {
450 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
451 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
452 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
453 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
454 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
455 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
456 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
457 default: return -1;
458 }
459}
460
461static int to_mlx5_st(enum ib_qp_type type)
462{
463 switch (type) {
464 case IB_QPT_RC: return MLX5_QP_ST_RC;
465 case IB_QPT_UC: return MLX5_QP_ST_UC;
466 case IB_QPT_UD: return MLX5_QP_ST_UD;
467 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
468 case IB_QPT_XRC_INI:
469 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
470 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
471 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
472 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
473 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
474 case IB_QPT_RAW_PACKET:
475 case IB_QPT_MAX:
476 default: return -EINVAL;
477 }
478}
479
480static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
481{
482 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
483}
484
485static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
486 struct mlx5_ib_qp *qp, struct ib_udata *udata,
487 struct mlx5_create_qp_mbox_in **in,
488 struct mlx5_ib_create_qp_resp *resp, int *inlen)
489{
490 struct mlx5_ib_ucontext *context;
491 struct mlx5_ib_create_qp ucmd;
492 int page_shift;
493 int uar_index;
494 int npages;
495 u32 offset;
496 int uuarn;
497 int ncont;
498 int err;
499
500 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
501 if (err) {
502 mlx5_ib_dbg(dev, "copy failed\n");
503 return err;
504 }
505
506 context = to_mucontext(pd->uobject->context);
507 /*
508 * TBD: should come from the verbs when we have the API
509 */
510 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
511 if (uuarn < 0) {
512 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
513 mlx5_ib_dbg(dev, "reverting to high latency\n");
514 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
515 if (uuarn < 0) {
516 mlx5_ib_dbg(dev, "uuar allocation failed\n");
517 return uuarn;
518 }
519 }
520
521 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
522 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
523
524 err = set_user_buf_size(dev, qp, &ucmd);
525 if (err)
526 goto err_uuar;
527
528 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
529 qp->buf_size, 0, 0);
530 if (IS_ERR(qp->umem)) {
531 mlx5_ib_dbg(dev, "umem_get failed\n");
532 err = PTR_ERR(qp->umem);
533 goto err_uuar;
534 }
535
536 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
537 &ncont, NULL);
538 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
539 if (err) {
540 mlx5_ib_warn(dev, "bad offset\n");
541 goto err_umem;
542 }
543 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
544 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
545
546 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
547 *in = mlx5_vzalloc(*inlen);
548 if (!*in) {
549 err = -ENOMEM;
550 goto err_umem;
551 }
552 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
553 (*in)->ctx.log_pg_sz_remote_qpn =
554 cpu_to_be32((page_shift - PAGE_SHIFT) << 24);
555 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
556
557 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
558 resp->uuar_index = uuarn;
559 qp->uuarn = uuarn;
560
561 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
562 if (err) {
563 mlx5_ib_dbg(dev, "map failed\n");
564 goto err_free;
565 }
566
567 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
568 if (err) {
569 mlx5_ib_dbg(dev, "copy failed\n");
570 goto err_unmap;
571 }
572 qp->create_type = MLX5_QP_USER;
573
574 return 0;
575
576err_unmap:
577 mlx5_ib_db_unmap_user(context, &qp->db);
578
579err_free:
580 mlx5_vfree(*in);
581
582err_umem:
583 ib_umem_release(qp->umem);
584
585err_uuar:
586 free_uuar(&context->uuari, uuarn);
587 return err;
588}
589
590static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
591{
592 struct mlx5_ib_ucontext *context;
593
594 context = to_mucontext(pd->uobject->context);
595 mlx5_ib_db_unmap_user(context, &qp->db);
596 ib_umem_release(qp->umem);
597 free_uuar(&context->uuari, qp->uuarn);
598}
599
600static int create_kernel_qp(struct mlx5_ib_dev *dev,
601 struct ib_qp_init_attr *init_attr,
602 struct mlx5_ib_qp *qp,
603 struct mlx5_create_qp_mbox_in **in, int *inlen)
604{
605 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
606 struct mlx5_uuar_info *uuari;
607 int uar_index;
608 int uuarn;
609 int err;
610
611 uuari = &dev->mdev.priv.uuari;
612 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
613 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
614
615 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
616 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
617
618 uuarn = alloc_uuar(uuari, lc);
619 if (uuarn < 0) {
620 mlx5_ib_dbg(dev, "\n");
621 return -ENOMEM;
622 }
623
624 qp->bf = &uuari->bfs[uuarn];
625 uar_index = qp->bf->uar->index;
626
627 err = calc_sq_size(dev, init_attr, qp);
628 if (err < 0) {
629 mlx5_ib_dbg(dev, "err %d\n", err);
630 goto err_uuar;
631 }
632
633 qp->rq.offset = 0;
634 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
635 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
636
637 err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
638 if (err) {
639 mlx5_ib_dbg(dev, "err %d\n", err);
640 goto err_uuar;
641 }
642
643 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
644 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
645 *in = mlx5_vzalloc(*inlen);
646 if (!*in) {
647 err = -ENOMEM;
648 goto err_buf;
649 }
650 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
651 (*in)->ctx.log_pg_sz_remote_qpn = cpu_to_be32((qp->buf.page_shift - PAGE_SHIFT) << 24);
652 /* Set "fast registration enabled" for all kernel QPs */
653 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
654 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
655
656 mlx5_fill_page_array(&qp->buf, (*in)->pas);
657
658 err = mlx5_db_alloc(&dev->mdev, &qp->db);
659 if (err) {
660 mlx5_ib_dbg(dev, "err %d\n", err);
661 goto err_free;
662 }
663
664 qp->db.db[0] = 0;
665 qp->db.db[1] = 0;
666
667 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
668 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
669 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
670 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
671 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
672
673 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
674 !qp->sq.w_list || !qp->sq.wqe_head) {
675 err = -ENOMEM;
676 goto err_wrid;
677 }
678 qp->create_type = MLX5_QP_KERNEL;
679
680 return 0;
681
682err_wrid:
683 mlx5_db_free(&dev->mdev, &qp->db);
684 kfree(qp->sq.wqe_head);
685 kfree(qp->sq.w_list);
686 kfree(qp->sq.wrid);
687 kfree(qp->sq.wr_data);
688 kfree(qp->rq.wrid);
689
690err_free:
691 mlx5_vfree(*in);
692
693err_buf:
694 mlx5_buf_free(&dev->mdev, &qp->buf);
695
696err_uuar:
697 free_uuar(&dev->mdev.priv.uuari, uuarn);
698 return err;
699}
700
701static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
702{
703 mlx5_db_free(&dev->mdev, &qp->db);
704 kfree(qp->sq.wqe_head);
705 kfree(qp->sq.w_list);
706 kfree(qp->sq.wrid);
707 kfree(qp->sq.wr_data);
708 kfree(qp->rq.wrid);
709 mlx5_buf_free(&dev->mdev, &qp->buf);
710 free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn);
711}
712
713static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
714{
715 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
716 (attr->qp_type == IB_QPT_XRC_INI))
717 return cpu_to_be32(MLX5_SRQ_RQ);
718 else if (!qp->has_rq)
719 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
720 else
721 return cpu_to_be32(MLX5_NON_ZERO_RQ);
722}
723
724static int is_connected(enum ib_qp_type qp_type)
725{
726 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
727 return 1;
728
729 return 0;
730}
731
732static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
733 struct ib_qp_init_attr *init_attr,
734 struct ib_udata *udata, struct mlx5_ib_qp *qp)
735{
736 struct mlx5_ib_resources *devr = &dev->devr;
737 struct mlx5_ib_create_qp_resp resp;
738 struct mlx5_create_qp_mbox_in *in;
739 struct mlx5_ib_create_qp ucmd;
740 int inlen = sizeof(*in);
741 int err;
742
743 mutex_init(&qp->mutex);
744 spin_lock_init(&qp->sq.lock);
745 spin_lock_init(&qp->rq.lock);
746
747 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
748 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
749
750 if (pd && pd->uobject) {
751 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
752 mlx5_ib_dbg(dev, "copy failed\n");
753 return -EFAULT;
754 }
755
756 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
757 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
758 } else {
759 qp->wq_sig = !!wq_signature;
760 }
761
762 qp->has_rq = qp_has_rq(init_attr);
763 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
764 qp, (pd && pd->uobject) ? &ucmd : NULL);
765 if (err) {
766 mlx5_ib_dbg(dev, "err %d\n", err);
767 return err;
768 }
769
770 if (pd) {
771 if (pd->uobject) {
772 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
773 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
774 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
775 mlx5_ib_dbg(dev, "invalid rq params\n");
776 return -EINVAL;
777 }
778 if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) {
779 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
780 ucmd.sq_wqe_count, dev->mdev.caps.max_wqes);
781 return -EINVAL;
782 }
783 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
784 if (err)
785 mlx5_ib_dbg(dev, "err %d\n", err);
786 } else {
787 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
788 if (err)
789 mlx5_ib_dbg(dev, "err %d\n", err);
790 else
791 qp->pa_lkey = to_mpd(pd)->pa_lkey;
792 }
793
794 if (err)
795 return err;
796 } else {
797 in = mlx5_vzalloc(sizeof(*in));
798 if (!in)
799 return -ENOMEM;
800
801 qp->create_type = MLX5_QP_EMPTY;
802 }
803
804 if (is_sqp(init_attr->qp_type))
805 qp->port = init_attr->port_num;
806
807 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
808 MLX5_QP_PM_MIGRATED << 11);
809
810 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
811 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
812 else
813 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
814
815 if (qp->wq_sig)
816 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
817
818 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
819 int rcqe_sz;
820 int scqe_sz;
821
822 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
823 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
824
825 if (rcqe_sz == 128)
826 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
827 else
828 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
829
830 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
831 if (scqe_sz == 128)
832 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
833 else
834 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
835 }
836 }
837
838 if (qp->rq.wqe_cnt) {
839 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
840 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
841 }
842
843 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
844
845 if (qp->sq.wqe_cnt)
846 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
847 else
848 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
849
850 /* Set default resources */
851 switch (init_attr->qp_type) {
852 case IB_QPT_XRC_TGT:
853 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
854 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
855 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
856 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
857 break;
858 case IB_QPT_XRC_INI:
859 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
860 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
861 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
862 break;
863 default:
864 if (init_attr->srq) {
865 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
866 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
867 } else {
868 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
869 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
870 }
871 }
872
873 if (init_attr->send_cq)
874 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
875
876 if (init_attr->recv_cq)
877 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
878
879 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
880
881 err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen);
882 if (err) {
883 mlx5_ib_dbg(dev, "create qp failed\n");
884 goto err_create;
885 }
886
887 mlx5_vfree(in);
888 /* Hardware wants QPN written in big-endian order (after
889 * shifting) for send doorbell. Precompute this value to save
890 * a little bit when posting sends.
891 */
892 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
893
894 qp->mqp.event = mlx5_ib_qp_event;
895
896 return 0;
897
898err_create:
899 if (qp->create_type == MLX5_QP_USER)
900 destroy_qp_user(pd, qp);
901 else if (qp->create_type == MLX5_QP_KERNEL)
902 destroy_qp_kernel(dev, qp);
903
904 mlx5_vfree(in);
905 return err;
906}
907
908static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
909 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
910{
911 if (send_cq) {
912 if (recv_cq) {
913 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
914 spin_lock_irq(&send_cq->lock);
915 spin_lock_nested(&recv_cq->lock,
916 SINGLE_DEPTH_NESTING);
917 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
918 spin_lock_irq(&send_cq->lock);
919 __acquire(&recv_cq->lock);
920 } else {
921 spin_lock_irq(&recv_cq->lock);
922 spin_lock_nested(&send_cq->lock,
923 SINGLE_DEPTH_NESTING);
924 }
925 } else {
926 spin_lock_irq(&send_cq->lock);
927 }
928 } else if (recv_cq) {
929 spin_lock_irq(&recv_cq->lock);
930 }
931}
932
933static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
934 __releases(&send_cq->lock) __releases(&recv_cq->lock)
935{
936 if (send_cq) {
937 if (recv_cq) {
938 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
939 spin_unlock(&recv_cq->lock);
940 spin_unlock_irq(&send_cq->lock);
941 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
942 __release(&recv_cq->lock);
943 spin_unlock_irq(&send_cq->lock);
944 } else {
945 spin_unlock(&send_cq->lock);
946 spin_unlock_irq(&recv_cq->lock);
947 }
948 } else {
949 spin_unlock_irq(&send_cq->lock);
950 }
951 } else if (recv_cq) {
952 spin_unlock_irq(&recv_cq->lock);
953 }
954}
955
956static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
957{
958 return to_mpd(qp->ibqp.pd);
959}
960
961static void get_cqs(struct mlx5_ib_qp *qp,
962 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
963{
964 switch (qp->ibqp.qp_type) {
965 case IB_QPT_XRC_TGT:
966 *send_cq = NULL;
967 *recv_cq = NULL;
968 break;
969 case MLX5_IB_QPT_REG_UMR:
970 case IB_QPT_XRC_INI:
971 *send_cq = to_mcq(qp->ibqp.send_cq);
972 *recv_cq = NULL;
973 break;
974
975 case IB_QPT_SMI:
976 case IB_QPT_GSI:
977 case IB_QPT_RC:
978 case IB_QPT_UC:
979 case IB_QPT_UD:
980 case IB_QPT_RAW_IPV6:
981 case IB_QPT_RAW_ETHERTYPE:
982 *send_cq = to_mcq(qp->ibqp.send_cq);
983 *recv_cq = to_mcq(qp->ibqp.recv_cq);
984 break;
985
986 case IB_QPT_RAW_PACKET:
987 case IB_QPT_MAX:
988 default:
989 *send_cq = NULL;
990 *recv_cq = NULL;
991 break;
992 }
993}
994
995static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
996{
997 struct mlx5_ib_cq *send_cq, *recv_cq;
998 struct mlx5_modify_qp_mbox_in *in;
999 int err;
1000
1001 in = kzalloc(sizeof(*in), GFP_KERNEL);
1002 if (!in)
1003 return;
1004 if (qp->state != IB_QPS_RESET)
1005 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state),
1006 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1007 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1008 qp->mqp.qpn);
1009
1010 get_cqs(qp, &send_cq, &recv_cq);
1011
1012 if (qp->create_type == MLX5_QP_KERNEL) {
1013 mlx5_ib_lock_cqs(send_cq, recv_cq);
1014 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1015 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1016 if (send_cq != recv_cq)
1017 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1018 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1019 }
1020
1021 err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp);
1022 if (err)
1023 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1024 kfree(in);
1025
1026
1027 if (qp->create_type == MLX5_QP_KERNEL)
1028 destroy_qp_kernel(dev, qp);
1029 else if (qp->create_type == MLX5_QP_USER)
1030 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1031}
1032
1033static const char *ib_qp_type_str(enum ib_qp_type type)
1034{
1035 switch (type) {
1036 case IB_QPT_SMI:
1037 return "IB_QPT_SMI";
1038 case IB_QPT_GSI:
1039 return "IB_QPT_GSI";
1040 case IB_QPT_RC:
1041 return "IB_QPT_RC";
1042 case IB_QPT_UC:
1043 return "IB_QPT_UC";
1044 case IB_QPT_UD:
1045 return "IB_QPT_UD";
1046 case IB_QPT_RAW_IPV6:
1047 return "IB_QPT_RAW_IPV6";
1048 case IB_QPT_RAW_ETHERTYPE:
1049 return "IB_QPT_RAW_ETHERTYPE";
1050 case IB_QPT_XRC_INI:
1051 return "IB_QPT_XRC_INI";
1052 case IB_QPT_XRC_TGT:
1053 return "IB_QPT_XRC_TGT";
1054 case IB_QPT_RAW_PACKET:
1055 return "IB_QPT_RAW_PACKET";
1056 case MLX5_IB_QPT_REG_UMR:
1057 return "MLX5_IB_QPT_REG_UMR";
1058 case IB_QPT_MAX:
1059 default:
1060 return "Invalid QP type";
1061 }
1062}
1063
1064struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1065 struct ib_qp_init_attr *init_attr,
1066 struct ib_udata *udata)
1067{
1068 struct mlx5_ib_dev *dev;
1069 struct mlx5_ib_qp *qp;
1070 u16 xrcdn = 0;
1071 int err;
1072
1073 if (pd) {
1074 dev = to_mdev(pd->device);
1075 } else {
1076 /* being cautious here */
1077 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1078 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1079 pr_warn("%s: no PD for transport %s\n", __func__,
1080 ib_qp_type_str(init_attr->qp_type));
1081 return ERR_PTR(-EINVAL);
1082 }
1083 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1084 }
1085
1086 switch (init_attr->qp_type) {
1087 case IB_QPT_XRC_TGT:
1088 case IB_QPT_XRC_INI:
1089 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) {
1090 mlx5_ib_dbg(dev, "XRC not supported\n");
1091 return ERR_PTR(-ENOSYS);
1092 }
1093 init_attr->recv_cq = NULL;
1094 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1095 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1096 init_attr->send_cq = NULL;
1097 }
1098
1099 /* fall through */
1100 case IB_QPT_RC:
1101 case IB_QPT_UC:
1102 case IB_QPT_UD:
1103 case IB_QPT_SMI:
1104 case IB_QPT_GSI:
1105 case MLX5_IB_QPT_REG_UMR:
1106 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1107 if (!qp)
1108 return ERR_PTR(-ENOMEM);
1109
1110 err = create_qp_common(dev, pd, init_attr, udata, qp);
1111 if (err) {
1112 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1113 kfree(qp);
1114 return ERR_PTR(err);
1115 }
1116
1117 if (is_qp0(init_attr->qp_type))
1118 qp->ibqp.qp_num = 0;
1119 else if (is_qp1(init_attr->qp_type))
1120 qp->ibqp.qp_num = 1;
1121 else
1122 qp->ibqp.qp_num = qp->mqp.qpn;
1123
1124 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1125 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1126 to_mcq(init_attr->send_cq)->mcq.cqn);
1127
1128 qp->xrcdn = xrcdn;
1129
1130 break;
1131
1132 case IB_QPT_RAW_IPV6:
1133 case IB_QPT_RAW_ETHERTYPE:
1134 case IB_QPT_RAW_PACKET:
1135 case IB_QPT_MAX:
1136 default:
1137 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1138 init_attr->qp_type);
1139 /* Don't support raw QPs */
1140 return ERR_PTR(-EINVAL);
1141 }
1142
1143 return &qp->ibqp;
1144}
1145
1146int mlx5_ib_destroy_qp(struct ib_qp *qp)
1147{
1148 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1149 struct mlx5_ib_qp *mqp = to_mqp(qp);
1150
1151 destroy_qp_common(dev, mqp);
1152
1153 kfree(mqp);
1154
1155 return 0;
1156}
1157
1158static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1159 int attr_mask)
1160{
1161 u32 hw_access_flags = 0;
1162 u8 dest_rd_atomic;
1163 u32 access_flags;
1164
1165 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1166 dest_rd_atomic = attr->max_dest_rd_atomic;
1167 else
1168 dest_rd_atomic = qp->resp_depth;
1169
1170 if (attr_mask & IB_QP_ACCESS_FLAGS)
1171 access_flags = attr->qp_access_flags;
1172 else
1173 access_flags = qp->atomic_rd_en;
1174
1175 if (!dest_rd_atomic)
1176 access_flags &= IB_ACCESS_REMOTE_WRITE;
1177
1178 if (access_flags & IB_ACCESS_REMOTE_READ)
1179 hw_access_flags |= MLX5_QP_BIT_RRE;
1180 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1181 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1182 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1183 hw_access_flags |= MLX5_QP_BIT_RWE;
1184
1185 return cpu_to_be32(hw_access_flags);
1186}
1187
1188enum {
1189 MLX5_PATH_FLAG_FL = 1 << 0,
1190 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1191 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1192};
1193
1194static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1195{
1196 if (rate == IB_RATE_PORT_CURRENT) {
1197 return 0;
1198 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1199 return -EINVAL;
1200 } else {
1201 while (rate != IB_RATE_2_5_GBPS &&
1202 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1203 dev->mdev.caps.stat_rate_support))
1204 --rate;
1205 }
1206
1207 return rate + MLX5_STAT_RATE_OFFSET;
1208}
1209
1210static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1211 struct mlx5_qp_path *path, u8 port, int attr_mask,
1212 u32 path_flags, const struct ib_qp_attr *attr)
1213{
1214 int err;
1215
1216 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1217 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1218
1219 if (attr_mask & IB_QP_PKEY_INDEX)
1220 path->pkey_index = attr->pkey_index;
1221
1222 path->grh_mlid = ah->src_path_bits & 0x7f;
1223 path->rlid = cpu_to_be16(ah->dlid);
1224
1225 if (ah->ah_flags & IB_AH_GRH) {
1226 path->grh_mlid |= 1 << 7;
1227 path->mgid_index = ah->grh.sgid_index;
1228 path->hop_limit = ah->grh.hop_limit;
1229 path->tclass_flowlabel =
1230 cpu_to_be32((ah->grh.traffic_class << 20) |
1231 (ah->grh.flow_label));
1232 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1233 }
1234
1235 err = ib_rate_to_mlx5(dev, ah->static_rate);
1236 if (err < 0)
1237 return err;
1238 path->static_rate = err;
1239 path->port = port;
1240
1241 if (ah->ah_flags & IB_AH_GRH) {
1242 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) {
1243 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1244 ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len);
1245 return -EINVAL;
1246 }
1247
1248 path->grh_mlid |= 1 << 7;
1249 path->mgid_index = ah->grh.sgid_index;
1250 path->hop_limit = ah->grh.hop_limit;
1251 path->tclass_flowlabel =
1252 cpu_to_be32((ah->grh.traffic_class << 20) |
1253 (ah->grh.flow_label));
1254 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1255 }
1256
1257 if (attr_mask & IB_QP_TIMEOUT)
1258 path->ackto_lt = attr->timeout << 3;
1259
1260 path->sl = ah->sl & 0xf;
1261
1262 return 0;
1263}
1264
1265static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1266 [MLX5_QP_STATE_INIT] = {
1267 [MLX5_QP_STATE_INIT] = {
1268 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1269 MLX5_QP_OPTPAR_RAE |
1270 MLX5_QP_OPTPAR_RWE |
1271 MLX5_QP_OPTPAR_PKEY_INDEX |
1272 MLX5_QP_OPTPAR_PRI_PORT,
1273 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1274 MLX5_QP_OPTPAR_PKEY_INDEX |
1275 MLX5_QP_OPTPAR_PRI_PORT,
1276 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1277 MLX5_QP_OPTPAR_Q_KEY |
1278 MLX5_QP_OPTPAR_PRI_PORT,
1279 },
1280 [MLX5_QP_STATE_RTR] = {
1281 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1282 MLX5_QP_OPTPAR_RRE |
1283 MLX5_QP_OPTPAR_RAE |
1284 MLX5_QP_OPTPAR_RWE |
1285 MLX5_QP_OPTPAR_PKEY_INDEX,
1286 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1287 MLX5_QP_OPTPAR_RWE |
1288 MLX5_QP_OPTPAR_PKEY_INDEX,
1289 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1290 MLX5_QP_OPTPAR_Q_KEY,
1291 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1292 MLX5_QP_OPTPAR_Q_KEY,
1293 },
1294 },
1295 [MLX5_QP_STATE_RTR] = {
1296 [MLX5_QP_STATE_RTS] = {
1297 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1298 MLX5_QP_OPTPAR_RRE |
1299 MLX5_QP_OPTPAR_RAE |
1300 MLX5_QP_OPTPAR_RWE |
1301 MLX5_QP_OPTPAR_PM_STATE |
1302 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1303 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1304 MLX5_QP_OPTPAR_RWE |
1305 MLX5_QP_OPTPAR_PM_STATE,
1306 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1307 },
1308 },
1309 [MLX5_QP_STATE_RTS] = {
1310 [MLX5_QP_STATE_RTS] = {
1311 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1312 MLX5_QP_OPTPAR_RAE |
1313 MLX5_QP_OPTPAR_RWE |
1314 MLX5_QP_OPTPAR_RNR_TIMEOUT |
1315 MLX5_QP_OPTPAR_PM_STATE,
1316 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1317 MLX5_QP_OPTPAR_PM_STATE,
1318 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1319 MLX5_QP_OPTPAR_SRQN |
1320 MLX5_QP_OPTPAR_CQN_RCV,
1321 },
1322 },
1323 [MLX5_QP_STATE_SQER] = {
1324 [MLX5_QP_STATE_RTS] = {
1325 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1326 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1327 },
1328 },
1329};
1330
1331static int ib_nr_to_mlx5_nr(int ib_mask)
1332{
1333 switch (ib_mask) {
1334 case IB_QP_STATE:
1335 return 0;
1336 case IB_QP_CUR_STATE:
1337 return 0;
1338 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1339 return 0;
1340 case IB_QP_ACCESS_FLAGS:
1341 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1342 MLX5_QP_OPTPAR_RAE;
1343 case IB_QP_PKEY_INDEX:
1344 return MLX5_QP_OPTPAR_PKEY_INDEX;
1345 case IB_QP_PORT:
1346 return MLX5_QP_OPTPAR_PRI_PORT;
1347 case IB_QP_QKEY:
1348 return MLX5_QP_OPTPAR_Q_KEY;
1349 case IB_QP_AV:
1350 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1351 MLX5_QP_OPTPAR_PRI_PORT;
1352 case IB_QP_PATH_MTU:
1353 return 0;
1354 case IB_QP_TIMEOUT:
1355 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1356 case IB_QP_RETRY_CNT:
1357 return MLX5_QP_OPTPAR_RETRY_COUNT;
1358 case IB_QP_RNR_RETRY:
1359 return MLX5_QP_OPTPAR_RNR_RETRY;
1360 case IB_QP_RQ_PSN:
1361 return 0;
1362 case IB_QP_MAX_QP_RD_ATOMIC:
1363 return MLX5_QP_OPTPAR_SRA_MAX;
1364 case IB_QP_ALT_PATH:
1365 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1366 case IB_QP_MIN_RNR_TIMER:
1367 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1368 case IB_QP_SQ_PSN:
1369 return 0;
1370 case IB_QP_MAX_DEST_RD_ATOMIC:
1371 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1372 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1373 case IB_QP_PATH_MIG_STATE:
1374 return MLX5_QP_OPTPAR_PM_STATE;
1375 case IB_QP_CAP:
1376 return 0;
1377 case IB_QP_DEST_QPN:
1378 return 0;
1379 }
1380 return 0;
1381}
1382
1383static int ib_mask_to_mlx5_opt(int ib_mask)
1384{
1385 int result = 0;
1386 int i;
1387
1388 for (i = 0; i < 8 * sizeof(int); i++) {
1389 if ((1 << i) & ib_mask)
1390 result |= ib_nr_to_mlx5_nr(1 << i);
1391 }
1392
1393 return result;
1394}
1395
1396static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1397 const struct ib_qp_attr *attr, int attr_mask,
1398 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1399{
1400 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1401 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1402 struct mlx5_ib_cq *send_cq, *recv_cq;
1403 struct mlx5_qp_context *context;
1404 struct mlx5_modify_qp_mbox_in *in;
1405 struct mlx5_ib_pd *pd;
1406 enum mlx5_qp_state mlx5_cur, mlx5_new;
1407 enum mlx5_qp_optpar optpar;
1408 int sqd_event;
1409 int mlx5_st;
1410 int err;
1411
1412 in = kzalloc(sizeof(*in), GFP_KERNEL);
1413 if (!in)
1414 return -ENOMEM;
1415
1416 context = &in->ctx;
1417 err = to_mlx5_st(ibqp->qp_type);
1418 if (err < 0)
1419 goto out;
1420
1421 context->flags = cpu_to_be32(err << 16);
1422
1423 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1424 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1425 } else {
1426 switch (attr->path_mig_state) {
1427 case IB_MIG_MIGRATED:
1428 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1429 break;
1430 case IB_MIG_REARM:
1431 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1432 break;
1433 case IB_MIG_ARMED:
1434 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1435 break;
1436 }
1437 }
1438
1439 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1440 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1441 } else if (ibqp->qp_type == IB_QPT_UD ||
1442 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1443 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1444 } else if (attr_mask & IB_QP_PATH_MTU) {
1445 if (attr->path_mtu < IB_MTU_256 ||
1446 attr->path_mtu > IB_MTU_4096) {
1447 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1448 err = -EINVAL;
1449 goto out;
1450 }
1451 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg;
1452 }
1453
1454 if (attr_mask & IB_QP_DEST_QPN)
1455 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1456
1457 if (attr_mask & IB_QP_PKEY_INDEX)
1458 context->pri_path.pkey_index = attr->pkey_index;
1459
1460 /* todo implement counter_index functionality */
1461
1462 if (is_sqp(ibqp->qp_type))
1463 context->pri_path.port = qp->port;
1464
1465 if (attr_mask & IB_QP_PORT)
1466 context->pri_path.port = attr->port_num;
1467
1468 if (attr_mask & IB_QP_AV) {
1469 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1470 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1471 attr_mask, 0, attr);
1472 if (err)
1473 goto out;
1474 }
1475
1476 if (attr_mask & IB_QP_TIMEOUT)
1477 context->pri_path.ackto_lt |= attr->timeout << 3;
1478
1479 if (attr_mask & IB_QP_ALT_PATH) {
1480 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1481 attr->alt_port_num, attr_mask, 0, attr);
1482 if (err)
1483 goto out;
1484 }
1485
1486 pd = get_pd(qp);
1487 get_cqs(qp, &send_cq, &recv_cq);
1488
1489 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1490 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1491 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1492 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1493
1494 if (attr_mask & IB_QP_RNR_RETRY)
1495 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1496
1497 if (attr_mask & IB_QP_RETRY_CNT)
1498 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1499
1500 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1501 if (attr->max_rd_atomic)
1502 context->params1 |=
1503 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1504 }
1505
1506 if (attr_mask & IB_QP_SQ_PSN)
1507 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1508
1509 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1510 if (attr->max_dest_rd_atomic)
1511 context->params2 |=
1512 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1513 }
1514
1515 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1516 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1517
1518 if (attr_mask & IB_QP_MIN_RNR_TIMER)
1519 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1520
1521 if (attr_mask & IB_QP_RQ_PSN)
1522 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1523
1524 if (attr_mask & IB_QP_QKEY)
1525 context->qkey = cpu_to_be32(attr->qkey);
1526
1527 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1528 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1529
1530 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1531 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1532 sqd_event = 1;
1533 else
1534 sqd_event = 0;
1535
1536 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1537 context->sq_crq_size |= cpu_to_be16(1 << 4);
1538
1539
1540 mlx5_cur = to_mlx5_state(cur_state);
1541 mlx5_new = to_mlx5_state(new_state);
1542 mlx5_st = to_mlx5_st(ibqp->qp_type);
1543 if (mlx5_cur < 0 || mlx5_new < 0 || mlx5_st < 0)
1544 goto out;
1545
1546 optpar = ib_mask_to_mlx5_opt(attr_mask);
1547 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1548 in->optparam = cpu_to_be32(optpar);
1549 err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state),
1550 to_mlx5_state(new_state), in, sqd_event,
1551 &qp->mqp);
1552 if (err)
1553 goto out;
1554
1555 qp->state = new_state;
1556
1557 if (attr_mask & IB_QP_ACCESS_FLAGS)
1558 qp->atomic_rd_en = attr->qp_access_flags;
1559 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1560 qp->resp_depth = attr->max_dest_rd_atomic;
1561 if (attr_mask & IB_QP_PORT)
1562 qp->port = attr->port_num;
1563 if (attr_mask & IB_QP_ALT_PATH)
1564 qp->alt_port = attr->alt_port_num;
1565
1566 /*
1567 * If we moved a kernel QP to RESET, clean up all old CQ
1568 * entries and reinitialize the QP.
1569 */
1570 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1571 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1572 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1573 if (send_cq != recv_cq)
1574 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1575
1576 qp->rq.head = 0;
1577 qp->rq.tail = 0;
1578 qp->sq.head = 0;
1579 qp->sq.tail = 0;
1580 qp->sq.cur_post = 0;
1581 qp->sq.last_poll = 0;
1582 qp->db.db[MLX5_RCV_DBR] = 0;
1583 qp->db.db[MLX5_SND_DBR] = 0;
1584 }
1585
1586out:
1587 kfree(in);
1588 return err;
1589}
1590
1591int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1592 int attr_mask, struct ib_udata *udata)
1593{
1594 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1595 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1596 enum ib_qp_state cur_state, new_state;
1597 int err = -EINVAL;
1598 int port;
1599
1600 mutex_lock(&qp->mutex);
1601
1602 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1603 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1604
1605 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1606 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1607 goto out;
1608
1609 if ((attr_mask & IB_QP_PORT) &&
1610 (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports))
1611 goto out;
1612
1613 if (attr_mask & IB_QP_PKEY_INDEX) {
1614 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1615 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len)
1616 goto out;
1617 }
1618
1619 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1620 attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp)
1621 goto out;
1622
1623 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1624 attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp)
1625 goto out;
1626
1627 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1628 err = 0;
1629 goto out;
1630 }
1631
1632 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1633
1634out:
1635 mutex_unlock(&qp->mutex);
1636 return err;
1637}
1638
1639static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1640{
1641 struct mlx5_ib_cq *cq;
1642 unsigned cur;
1643
1644 cur = wq->head - wq->tail;
1645 if (likely(cur + nreq < wq->max_post))
1646 return 0;
1647
1648 cq = to_mcq(ib_cq);
1649 spin_lock(&cq->lock);
1650 cur = wq->head - wq->tail;
1651 spin_unlock(&cq->lock);
1652
1653 return cur + nreq >= wq->max_post;
1654}
1655
1656static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1657 u64 remote_addr, u32 rkey)
1658{
1659 rseg->raddr = cpu_to_be64(remote_addr);
1660 rseg->rkey = cpu_to_be32(rkey);
1661 rseg->reserved = 0;
1662}
1663
1664static void set_atomic_seg(struct mlx5_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1665{
1666 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1667 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1668 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1669 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
1670 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1671 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1672 } else {
1673 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1674 aseg->compare = 0;
1675 }
1676}
1677
1678static void set_masked_atomic_seg(struct mlx5_wqe_masked_atomic_seg *aseg,
1679 struct ib_send_wr *wr)
1680{
1681 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1682 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
1683 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1684 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1685}
1686
1687static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1688 struct ib_send_wr *wr)
1689{
1690 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1691 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1692 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1693}
1694
1695static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1696{
1697 dseg->byte_count = cpu_to_be32(sg->length);
1698 dseg->lkey = cpu_to_be32(sg->lkey);
1699 dseg->addr = cpu_to_be64(sg->addr);
1700}
1701
1702static __be16 get_klm_octo(int npages)
1703{
1704 return cpu_to_be16(ALIGN(npages, 8) / 2);
1705}
1706
1707static __be64 frwr_mkey_mask(void)
1708{
1709 u64 result;
1710
1711 result = MLX5_MKEY_MASK_LEN |
1712 MLX5_MKEY_MASK_PAGE_SIZE |
1713 MLX5_MKEY_MASK_START_ADDR |
1714 MLX5_MKEY_MASK_EN_RINVAL |
1715 MLX5_MKEY_MASK_KEY |
1716 MLX5_MKEY_MASK_LR |
1717 MLX5_MKEY_MASK_LW |
1718 MLX5_MKEY_MASK_RR |
1719 MLX5_MKEY_MASK_RW |
1720 MLX5_MKEY_MASK_A |
1721 MLX5_MKEY_MASK_SMALL_FENCE |
1722 MLX5_MKEY_MASK_FREE;
1723
1724 return cpu_to_be64(result);
1725}
1726
1727static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1728 struct ib_send_wr *wr, int li)
1729{
1730 memset(umr, 0, sizeof(*umr));
1731
1732 if (li) {
1733 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1734 umr->flags = 1 << 7;
1735 return;
1736 }
1737
1738 umr->flags = (1 << 5); /* fail if not free */
1739 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1740 umr->mkey_mask = frwr_mkey_mask();
1741}
1742
1743static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1744 struct ib_send_wr *wr)
1745{
1746 struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1747 u64 mask;
1748
1749 memset(umr, 0, sizeof(*umr));
1750
1751 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1752 umr->flags = 1 << 5; /* fail if not free */
1753 umr->klm_octowords = get_klm_octo(umrwr->npages);
1754 mask = MLX5_MKEY_MASK_LEN |
1755 MLX5_MKEY_MASK_PAGE_SIZE |
1756 MLX5_MKEY_MASK_START_ADDR |
1757 MLX5_MKEY_MASK_PD |
1758 MLX5_MKEY_MASK_LR |
1759 MLX5_MKEY_MASK_LW |
1760 MLX5_MKEY_MASK_RR |
1761 MLX5_MKEY_MASK_RW |
1762 MLX5_MKEY_MASK_A |
1763 MLX5_MKEY_MASK_FREE;
1764 umr->mkey_mask = cpu_to_be64(mask);
1765 } else {
1766 umr->flags = 2 << 5; /* fail if free */
1767 mask = MLX5_MKEY_MASK_FREE;
1768 umr->mkey_mask = cpu_to_be64(mask);
1769 }
1770
1771 if (!wr->num_sge)
1772 umr->flags |= (1 << 7); /* inline */
1773}
1774
1775static u8 get_umr_flags(int acc)
1776{
1777 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1778 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1779 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1780 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1781 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1782}
1783
1784static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1785 int li, int *writ)
1786{
1787 memset(seg, 0, sizeof(*seg));
1788 if (li) {
1789 seg->status = 1 << 6;
1790 return;
1791 }
1792
1793 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags);
1794 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1795 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1796 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1797 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1798 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1799 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1800 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1801}
1802
1803static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1804{
1805 memset(seg, 0, sizeof(*seg));
1806 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1807 seg->status = 1 << 6;
1808 return;
1809 }
1810
1811 seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1812 seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1813 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1814 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1815 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1816 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1817}
1818
1819static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1820 struct ib_send_wr *wr,
1821 struct mlx5_core_dev *mdev,
1822 struct mlx5_ib_pd *pd,
1823 int writ)
1824{
1825 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1826 u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1827 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1828 int i;
1829
1830 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1831 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1832 dseg->addr = cpu_to_be64(mfrpl->map);
1833 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1834 dseg->lkey = cpu_to_be32(pd->pa_lkey);
1835}
1836
1837static __be32 send_ieth(struct ib_send_wr *wr)
1838{
1839 switch (wr->opcode) {
1840 case IB_WR_SEND_WITH_IMM:
1841 case IB_WR_RDMA_WRITE_WITH_IMM:
1842 return wr->ex.imm_data;
1843
1844 case IB_WR_SEND_WITH_INV:
1845 return cpu_to_be32(wr->ex.invalidate_rkey);
1846
1847 default:
1848 return 0;
1849 }
1850}
1851
1852static u8 calc_sig(void *wqe, int size)
1853{
1854 u8 *p = wqe;
1855 u8 res = 0;
1856 int i;
1857
1858 for (i = 0; i < size; i++)
1859 res ^= p[i];
1860
1861 return ~res;
1862}
1863
1864static u8 wq_sig(void *wqe)
1865{
1866 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1867}
1868
1869static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1870 void *wqe, int *sz)
1871{
1872 struct mlx5_wqe_inline_seg *seg;
1873 void *qend = qp->sq.qend;
1874 void *addr;
1875 int inl = 0;
1876 int copy;
1877 int len;
1878 int i;
1879
1880 seg = wqe;
1881 wqe += sizeof(*seg);
1882 for (i = 0; i < wr->num_sge; i++) {
1883 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1884 len = wr->sg_list[i].length;
1885 inl += len;
1886
1887 if (unlikely(inl > qp->max_inline_data))
1888 return -ENOMEM;
1889
1890 if (unlikely(wqe + len > qend)) {
1891 copy = qend - wqe;
1892 memcpy(wqe, addr, copy);
1893 addr += copy;
1894 len -= copy;
1895 wqe = mlx5_get_send_wqe(qp, 0);
1896 }
1897 memcpy(wqe, addr, len);
1898 wqe += len;
1899 }
1900
1901 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
1902
1903 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
1904
1905 return 0;
1906}
1907
1908static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
1909 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
1910{
1911 int writ = 0;
1912 int li;
1913
1914 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
1915 if (unlikely(wr->send_flags & IB_SEND_INLINE))
1916 return -EINVAL;
1917
1918 set_frwr_umr_segment(*seg, wr, li);
1919 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
1920 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
1921 if (unlikely((*seg == qp->sq.qend)))
1922 *seg = mlx5_get_send_wqe(qp, 0);
1923 set_mkey_segment(*seg, wr, li, &writ);
1924 *seg += sizeof(struct mlx5_mkey_seg);
1925 *size += sizeof(struct mlx5_mkey_seg) / 16;
1926 if (unlikely((*seg == qp->sq.qend)))
1927 *seg = mlx5_get_send_wqe(qp, 0);
1928 if (!li) {
1929 set_frwr_pages(*seg, wr, mdev, pd, writ);
1930 *seg += sizeof(struct mlx5_wqe_data_seg);
1931 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
1932 }
1933 return 0;
1934}
1935
1936static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
1937{
1938 __be32 *p = NULL;
1939 int tidx = idx;
1940 int i, j;
1941
1942 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
1943 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
1944 if ((i & 0xf) == 0) {
1945 void *buf = mlx5_get_send_wqe(qp, tidx);
1946 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
1947 p = buf;
1948 j = 0;
1949 }
1950 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
1951 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
1952 be32_to_cpu(p[j + 3]));
1953 }
1954}
1955
1956static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
1957 unsigned bytecnt, struct mlx5_ib_qp *qp)
1958{
1959 while (bytecnt > 0) {
1960 __iowrite64_copy(dst++, src++, 8);
1961 __iowrite64_copy(dst++, src++, 8);
1962 __iowrite64_copy(dst++, src++, 8);
1963 __iowrite64_copy(dst++, src++, 8);
1964 __iowrite64_copy(dst++, src++, 8);
1965 __iowrite64_copy(dst++, src++, 8);
1966 __iowrite64_copy(dst++, src++, 8);
1967 __iowrite64_copy(dst++, src++, 8);
1968 bytecnt -= 64;
1969 if (unlikely(src == qp->sq.qend))
1970 src = mlx5_get_send_wqe(qp, 0);
1971 }
1972}
1973
1974static u8 get_fence(u8 fence, struct ib_send_wr *wr)
1975{
1976 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
1977 wr->send_flags & IB_SEND_FENCE))
1978 return MLX5_FENCE_MODE_STRONG_ORDERING;
1979
1980 if (unlikely(fence)) {
1981 if (wr->send_flags & IB_SEND_FENCE)
1982 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
1983 else
1984 return fence;
1985
1986 } else {
1987 return 0;
1988 }
1989}
1990
1991int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1992 struct ib_send_wr **bad_wr)
1993{
1994 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
1995 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1996 struct mlx5_core_dev *mdev = &dev->mdev;
1997 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1998 struct mlx5_wqe_data_seg *dpseg;
1999 struct mlx5_wqe_xrc_seg *xrc;
2000 struct mlx5_bf *bf = qp->bf;
2001 int uninitialized_var(size);
2002 void *qend = qp->sq.qend;
2003 unsigned long flags;
2004 u32 mlx5_opcode;
2005 unsigned idx;
2006 int err = 0;
2007 int inl = 0;
2008 int num_sge;
2009 void *seg;
2010 int nreq;
2011 int i;
2012 u8 next_fence = 0;
2013 u8 opmod = 0;
2014 u8 fence;
2015
2016 spin_lock_irqsave(&qp->sq.lock, flags);
2017
2018 for (nreq = 0; wr; nreq++, wr = wr->next) {
2019 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) {
2020 mlx5_ib_warn(dev, "\n");
2021 err = -EINVAL;
2022 *bad_wr = wr;
2023 goto out;
2024 }
2025
2026 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2027 mlx5_ib_warn(dev, "\n");
2028 err = -ENOMEM;
2029 *bad_wr = wr;
2030 goto out;
2031 }
2032
2033 fence = qp->fm_cache;
2034 num_sge = wr->num_sge;
2035 if (unlikely(num_sge > qp->sq.max_gs)) {
2036 mlx5_ib_warn(dev, "\n");
2037 err = -ENOMEM;
2038 *bad_wr = wr;
2039 goto out;
2040 }
2041
2042 idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2043 seg = mlx5_get_send_wqe(qp, idx);
2044 ctrl = seg;
2045 *(uint32_t *)(seg + 8) = 0;
2046 ctrl->imm = send_ieth(wr);
2047 ctrl->fm_ce_se = qp->sq_signal_bits |
2048 (wr->send_flags & IB_SEND_SIGNALED ?
2049 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2050 (wr->send_flags & IB_SEND_SOLICITED ?
2051 MLX5_WQE_CTRL_SOLICITED : 0);
2052
2053 seg += sizeof(*ctrl);
2054 size = sizeof(*ctrl) / 16;
2055
2056 switch (ibqp->qp_type) {
2057 case IB_QPT_XRC_INI:
2058 xrc = seg;
2059 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2060 seg += sizeof(*xrc);
2061 size += sizeof(*xrc) / 16;
2062 /* fall through */
2063 case IB_QPT_RC:
2064 switch (wr->opcode) {
2065 case IB_WR_RDMA_READ:
2066 case IB_WR_RDMA_WRITE:
2067 case IB_WR_RDMA_WRITE_WITH_IMM:
2068 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2069 wr->wr.rdma.rkey);
2070 seg += sizeof(struct mlx5_wqe_raddr_seg);
2071 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2072 break;
2073
2074 case IB_WR_ATOMIC_CMP_AND_SWP:
2075 case IB_WR_ATOMIC_FETCH_AND_ADD:
2076 set_raddr_seg(seg, wr->wr.atomic.remote_addr,
2077 wr->wr.atomic.rkey);
2078 seg += sizeof(struct mlx5_wqe_raddr_seg);
2079
2080 set_atomic_seg(seg, wr);
2081 seg += sizeof(struct mlx5_wqe_atomic_seg);
2082
2083 size += (sizeof(struct mlx5_wqe_raddr_seg) +
2084 sizeof(struct mlx5_wqe_atomic_seg)) / 16;
2085 break;
2086
2087 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2088 set_raddr_seg(seg, wr->wr.atomic.remote_addr,
2089 wr->wr.atomic.rkey);
2090 seg += sizeof(struct mlx5_wqe_raddr_seg);
2091
2092 set_masked_atomic_seg(seg, wr);
2093 seg += sizeof(struct mlx5_wqe_masked_atomic_seg);
2094
2095 size += (sizeof(struct mlx5_wqe_raddr_seg) +
2096 sizeof(struct mlx5_wqe_masked_atomic_seg)) / 16;
2097 break;
2098
2099 case IB_WR_LOCAL_INV:
2100 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2101 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2102 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2103 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2104 if (err) {
2105 mlx5_ib_warn(dev, "\n");
2106 *bad_wr = wr;
2107 goto out;
2108 }
2109 num_sge = 0;
2110 break;
2111
2112 case IB_WR_FAST_REG_MR:
2113 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2114 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2115 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2116 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2117 if (err) {
2118 mlx5_ib_warn(dev, "\n");
2119 *bad_wr = wr;
2120 goto out;
2121 }
2122 num_sge = 0;
2123 break;
2124
2125 default:
2126 break;
2127 }
2128 break;
2129
2130 case IB_QPT_UC:
2131 switch (wr->opcode) {
2132 case IB_WR_RDMA_WRITE:
2133 case IB_WR_RDMA_WRITE_WITH_IMM:
2134 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2135 wr->wr.rdma.rkey);
2136 seg += sizeof(struct mlx5_wqe_raddr_seg);
2137 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2138 break;
2139
2140 default:
2141 break;
2142 }
2143 break;
2144
2145 case IB_QPT_UD:
2146 case IB_QPT_SMI:
2147 case IB_QPT_GSI:
2148 set_datagram_seg(seg, wr);
2149 seg += sizeof(struct mlx5_wqe_datagram_seg);
2150 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2151 if (unlikely((seg == qend)))
2152 seg = mlx5_get_send_wqe(qp, 0);
2153 break;
2154
2155 case MLX5_IB_QPT_REG_UMR:
2156 if (wr->opcode != MLX5_IB_WR_UMR) {
2157 err = -EINVAL;
2158 mlx5_ib_warn(dev, "bad opcode\n");
2159 goto out;
2160 }
2161 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2162 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2163 set_reg_umr_segment(seg, wr);
2164 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2165 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2166 if (unlikely((seg == qend)))
2167 seg = mlx5_get_send_wqe(qp, 0);
2168 set_reg_mkey_segment(seg, wr);
2169 seg += sizeof(struct mlx5_mkey_seg);
2170 size += sizeof(struct mlx5_mkey_seg) / 16;
2171 if (unlikely((seg == qend)))
2172 seg = mlx5_get_send_wqe(qp, 0);
2173 break;
2174
2175 default:
2176 break;
2177 }
2178
2179 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2180 int uninitialized_var(sz);
2181
2182 err = set_data_inl_seg(qp, wr, seg, &sz);
2183 if (unlikely(err)) {
2184 mlx5_ib_warn(dev, "\n");
2185 *bad_wr = wr;
2186 goto out;
2187 }
2188 inl = 1;
2189 size += sz;
2190 } else {
2191 dpseg = seg;
2192 for (i = 0; i < num_sge; i++) {
2193 if (unlikely(dpseg == qend)) {
2194 seg = mlx5_get_send_wqe(qp, 0);
2195 dpseg = seg;
2196 }
2197 if (likely(wr->sg_list[i].length)) {
2198 set_data_ptr_seg(dpseg, wr->sg_list + i);
2199 size += sizeof(struct mlx5_wqe_data_seg) / 16;
2200 dpseg++;
2201 }
2202 }
2203 }
2204
2205 mlx5_opcode = mlx5_ib_opcode[wr->opcode];
2206 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2207 mlx5_opcode |
2208 ((u32)opmod << 24));
2209 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2210 ctrl->fm_ce_se |= get_fence(fence, wr);
2211 qp->fm_cache = next_fence;
2212 if (unlikely(qp->wq_sig))
2213 ctrl->signature = wq_sig(ctrl);
2214
2215 qp->sq.wrid[idx] = wr->wr_id;
2216 qp->sq.w_list[idx].opcode = mlx5_opcode;
2217 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2218 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2219 qp->sq.w_list[idx].next = qp->sq.cur_post;
2220
2221 if (0)
2222 dump_wqe(qp, idx, size);
2223 }
2224
2225out:
2226 if (likely(nreq)) {
2227 qp->sq.head += nreq;
2228
2229 /* Make sure that descriptors are written before
2230 * updating doorbell record and ringing the doorbell
2231 */
2232 wmb();
2233
2234 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2235
2236 if (bf->need_lock)
2237 spin_lock(&bf->lock);
2238
2239 /* TBD enable WC */
2240 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2241 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2242 /* wc_wmb(); */
2243 } else {
2244 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2245 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2246 /* Make sure doorbells don't leak out of SQ spinlock
2247 * and reach the HCA out of order.
2248 */
2249 mmiowb();
2250 }
2251 bf->offset ^= bf->buf_size;
2252 if (bf->need_lock)
2253 spin_unlock(&bf->lock);
2254 }
2255
2256 spin_unlock_irqrestore(&qp->sq.lock, flags);
2257
2258 return err;
2259}
2260
2261static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2262{
2263 sig->signature = calc_sig(sig, size);
2264}
2265
2266int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2267 struct ib_recv_wr **bad_wr)
2268{
2269 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2270 struct mlx5_wqe_data_seg *scat;
2271 struct mlx5_rwqe_sig *sig;
2272 unsigned long flags;
2273 int err = 0;
2274 int nreq;
2275 int ind;
2276 int i;
2277
2278 spin_lock_irqsave(&qp->rq.lock, flags);
2279
2280 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2281
2282 for (nreq = 0; wr; nreq++, wr = wr->next) {
2283 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2284 err = -ENOMEM;
2285 *bad_wr = wr;
2286 goto out;
2287 }
2288
2289 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2290 err = -EINVAL;
2291 *bad_wr = wr;
2292 goto out;
2293 }
2294
2295 scat = get_recv_wqe(qp, ind);
2296 if (qp->wq_sig)
2297 scat++;
2298
2299 for (i = 0; i < wr->num_sge; i++)
2300 set_data_ptr_seg(scat + i, wr->sg_list + i);
2301
2302 if (i < qp->rq.max_gs) {
2303 scat[i].byte_count = 0;
2304 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
2305 scat[i].addr = 0;
2306 }
2307
2308 if (qp->wq_sig) {
2309 sig = (struct mlx5_rwqe_sig *)scat;
2310 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2311 }
2312
2313 qp->rq.wrid[ind] = wr->wr_id;
2314
2315 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2316 }
2317
2318out:
2319 if (likely(nreq)) {
2320 qp->rq.head += nreq;
2321
2322 /* Make sure that descriptors are written before
2323 * doorbell record.
2324 */
2325 wmb();
2326
2327 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2328 }
2329
2330 spin_unlock_irqrestore(&qp->rq.lock, flags);
2331
2332 return err;
2333}
2334
2335static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2336{
2337 switch (mlx5_state) {
2338 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
2339 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
2340 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
2341 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
2342 case MLX5_QP_STATE_SQ_DRAINING:
2343 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
2344 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
2345 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
2346 default: return -1;
2347 }
2348}
2349
2350static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2351{
2352 switch (mlx5_mig_state) {
2353 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
2354 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
2355 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2356 default: return -1;
2357 }
2358}
2359
2360static int to_ib_qp_access_flags(int mlx5_flags)
2361{
2362 int ib_flags = 0;
2363
2364 if (mlx5_flags & MLX5_QP_BIT_RRE)
2365 ib_flags |= IB_ACCESS_REMOTE_READ;
2366 if (mlx5_flags & MLX5_QP_BIT_RWE)
2367 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2368 if (mlx5_flags & MLX5_QP_BIT_RAE)
2369 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2370
2371 return ib_flags;
2372}
2373
2374static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2375 struct mlx5_qp_path *path)
2376{
2377 struct mlx5_core_dev *dev = &ibdev->mdev;
2378
2379 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2380 ib_ah_attr->port_num = path->port;
2381
2382 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2383 return;
2384
2385 ib_ah_attr->sl = path->sl & 0xf;
2386
2387 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
2388 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2389 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2390 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2391 if (ib_ah_attr->ah_flags) {
2392 ib_ah_attr->grh.sgid_index = path->mgid_index;
2393 ib_ah_attr->grh.hop_limit = path->hop_limit;
2394 ib_ah_attr->grh.traffic_class =
2395 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2396 ib_ah_attr->grh.flow_label =
2397 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2398 memcpy(ib_ah_attr->grh.dgid.raw,
2399 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2400 }
2401}
2402
2403int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2404 struct ib_qp_init_attr *qp_init_attr)
2405{
2406 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2407 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2408 struct mlx5_query_qp_mbox_out *outb;
2409 struct mlx5_qp_context *context;
2410 int mlx5_state;
2411 int err = 0;
2412
2413 mutex_lock(&qp->mutex);
2414 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2415 if (!outb) {
2416 err = -ENOMEM;
2417 goto out;
2418 }
2419 context = &outb->ctx;
2420 err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb));
2421 if (err)
2422 goto out_free;
2423
2424 mlx5_state = be32_to_cpu(context->flags) >> 28;
2425
2426 qp->state = to_ib_qp_state(mlx5_state);
2427 qp_attr->qp_state = qp->state;
2428 qp_attr->path_mtu = context->mtu_msgmax >> 5;
2429 qp_attr->path_mig_state =
2430 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2431 qp_attr->qkey = be32_to_cpu(context->qkey);
2432 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2433 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
2434 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2435 qp_attr->qp_access_flags =
2436 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2437
2438 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2439 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2440 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2441 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2442 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2443 }
2444
2445 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2446 qp_attr->port_num = context->pri_path.port;
2447
2448 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2449 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2450
2451 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2452
2453 qp_attr->max_dest_rd_atomic =
2454 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2455 qp_attr->min_rnr_timer =
2456 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2457 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
2458 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
2459 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
2460 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
2461 qp_attr->cur_qp_state = qp_attr->qp_state;
2462 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2463 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2464
2465 if (!ibqp->uobject) {
2466 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
2467 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2468 } else {
2469 qp_attr->cap.max_send_wr = 0;
2470 qp_attr->cap.max_send_sge = 0;
2471 }
2472
2473 /* We don't support inline sends for kernel QPs (yet), and we
2474 * don't know what userspace's value should be.
2475 */
2476 qp_attr->cap.max_inline_data = 0;
2477
2478 qp_init_attr->cap = qp_attr->cap;
2479
2480 qp_init_attr->create_flags = 0;
2481 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2482 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2483
2484 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2485 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2486
2487out_free:
2488 kfree(outb);
2489
2490out:
2491 mutex_unlock(&qp->mutex);
2492 return err;
2493}
2494
2495struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2496 struct ib_ucontext *context,
2497 struct ib_udata *udata)
2498{
2499 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2500 struct mlx5_ib_xrcd *xrcd;
2501 int err;
2502
2503 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC))
2504 return ERR_PTR(-ENOSYS);
2505
2506 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
2507 if (!xrcd)
2508 return ERR_PTR(-ENOMEM);
2509
2510 err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn);
2511 if (err) {
2512 kfree(xrcd);
2513 return ERR_PTR(-ENOMEM);
2514 }
2515
2516 return &xrcd->ibxrcd;
2517}
2518
2519int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
2520{
2521 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
2522 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
2523 int err;
2524
2525 err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn);
2526 if (err) {
2527 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
2528 return err;
2529 }
2530
2531 kfree(xrcd);
2532
2533 return 0;
2534}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git