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IB/mlx5: Allow XRC usage via verbs in DEVX context
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
443c1cf9 40#include "cmd.h"
e126ba97
EC		 41
42/* not supported currently */
43static int wq_signature;
44
45enum {
46 MLX5_IB_ACK_REQ_FREQ = 8,
47};
48
49enum {
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
54};
55
56enum {
57 MLX5_IB_SQ_STRIDE = 6,
064e5262 58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
e126ba97
EC		 59};
60
61static const u32 mlx5_ib_opcode[] = {
62 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 63 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
76};
77
f0313965
ES		 78struct mlx5_wqe_eth_pad {
79 u8 rsvd0[16];
80};
e126ba97 81
eb49ab0c
AV		 82enum raw_qp_set_mask_map {
83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 85};
86
0680efa2
AV		 87struct mlx5_modify_raw_qp_param {
88 u16 operation;
eb49ab0c
AV		 89
90 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 91
92 struct mlx5_rate_limit rl;
93
eb49ab0c 94 u8 rq_q_ctr_id;
0680efa2
AV		 95};
96
89ea94a7
MG		 97static void get_cqs(enum ib_qp_type qp_type,
98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100
e126ba97
EC		 101static int is_qp0(enum ib_qp_type qp_type)
102{
103 return qp_type == IB_QPT_SMI;
104}
105
e126ba97
EC		 106static int is_sqp(enum ib_qp_type qp_type)
107{
108 return is_qp0(qp_type) || is_qp1(qp_type);
109}
110
c1395a2a
HE		 111/**
112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
113 *
114 * @qp: QP to copy from.
115 * @send: copy from the send queue when non-zero, use the receive queue
116 * otherwise.
117 * @wqe_index: index to start copying from. For send work queues, the
118 * wqe_index is in units of MLX5_SEND_WQE_BB.
119 * For receive work queue, it is the number of work queue
120 * element in the queue.
121 * @buffer: destination buffer.
122 * @length: maximum number of bytes to copy.
123 *
124 * Copies at least a single WQE, but may copy more data.
125 *
126 * Return: the number of bytes copied, or an error code.
127 */
128int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 129 void *buffer, u32 length,
130 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 131{
132 struct ib_device *ibdev = qp->ibqp.device;
133 struct mlx5_ib_dev *dev = to_mdev(ibdev);
134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
135 size_t offset;
136 size_t wq_end;
19098df2 137 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 138 u32 first_copy_length;
139 int wqe_length;
140 int ret;
141
142 if (wq->wqe_cnt == 0) {
143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
144 qp->ibqp.qp_type);
145 return -EINVAL;
146 }
147
148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
150
151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
152 return -EINVAL;
153
154 if (offset > umem->length ||
155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
156 return -EINVAL;
157
158 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
160 if (ret)
161 return ret;
162
163 if (send) {
164 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
166
167 wqe_length = ds * MLX5_WQE_DS_UNITS;
168 } else {
169 wqe_length = 1 << wq->wqe_shift;
170 }
171
172 if (wqe_length <= first_copy_length)
173 return first_copy_length;
174
175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
176 wqe_length - first_copy_length);
177 if (ret)
178 return ret;
179
180 return wqe_length;
181}
182
e126ba97
EC		 183static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
184{
185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
186 struct ib_event event;
187
19098df2 188 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
189 /* This event is only valid for trans_qps */
190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
191 }
e126ba97
EC		 192
193 if (ibqp->event_handler) {
194 event.device = ibqp->device;
195 event.element.qp = ibqp;
196 switch (type) {
197 case MLX5_EVENT_TYPE_PATH_MIG:
198 event.event = IB_EVENT_PATH_MIG;
199 break;
200 case MLX5_EVENT_TYPE_COMM_EST:
201 event.event = IB_EVENT_COMM_EST;
202 break;
203 case MLX5_EVENT_TYPE_SQ_DRAINED:
204 event.event = IB_EVENT_SQ_DRAINED;
205 break;
206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
207 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
208 break;
209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
210 event.event = IB_EVENT_QP_FATAL;
211 break;
212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
213 event.event = IB_EVENT_PATH_MIG_ERR;
214 break;
215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
216 event.event = IB_EVENT_QP_REQ_ERR;
217 break;
218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
219 event.event = IB_EVENT_QP_ACCESS_ERR;
220 break;
221 default:
222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
223 return;
224 }
225
226 ibqp->event_handler(&event, ibqp->qp_context);
227 }
228}
229
230static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
232{
233 int wqe_size;
234 int wq_size;
235
236 /* Sanity check RQ size before proceeding */
938fe83c 237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 238 return -EINVAL;
239
240 if (!has_rq) {
241 qp->rq.max_gs = 0;
242 qp->rq.wqe_cnt = 0;
243 qp->rq.wqe_shift = 0;
0540d814
NO		 244 cap->max_recv_wr = 0;
245 cap->max_recv_sge = 0;
e126ba97
EC		 246 } else {
247 if (ucmd) {
248 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
250 return -EINVAL;
e126ba97 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
002bf228
LR		 252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
253 return -EINVAL;
e126ba97
EC		 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
255 qp->rq.max_post = qp->rq.wqe_cnt;
256 } else {
257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
259 wqe_size = roundup_pow_of_two(wqe_size);
260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
262 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
265 wqe_size,
938fe83c
SM		 266 MLX5_CAP_GEN(dev->mdev,
267 max_wqe_sz_rq));
e126ba97
EC		 268 return -EINVAL;
269 }
270 qp->rq.wqe_shift = ilog2(wqe_size);
271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
272 qp->rq.max_post = qp->rq.wqe_cnt;
273 }
274 }
275
276 return 0;
277}
278
f0313965 279static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 280{
618af384 281 int size = 0;
e126ba97 282
f0313965 283 switch (attr->qp_type) {
e126ba97 284 case IB_QPT_XRC_INI:
b125a54b 285 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 286 /* fall through */
287 case IB_QPT_RC:
288 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 289 max(sizeof(struct mlx5_wqe_atomic_seg) +
290 sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 292 sizeof(struct mlx5_mkey_seg) +
293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
294 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 295 break;
296
b125a54b
EC		 297 case IB_QPT_XRC_TGT:
298 return 0;
299
e126ba97 300 case IB_QPT_UC:
b125a54b 301 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 302 max(sizeof(struct mlx5_wqe_raddr_seg),
303 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
304 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 305 break;
306
307 case IB_QPT_UD:
f0313965
ES		 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
309 size += sizeof(struct mlx5_wqe_eth_pad) +
310 sizeof(struct mlx5_wqe_eth_seg);
311 /* fall through */
e126ba97 312 case IB_QPT_SMI:
d16e91da 313 case MLX5_IB_QPT_HW_GSI:
b125a54b 314 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 315 sizeof(struct mlx5_wqe_datagram_seg);
316 break;
317
318 case MLX5_IB_QPT_REG_UMR:
b125a54b 319 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
321 sizeof(struct mlx5_mkey_seg);
322 break;
323
324 default:
325 return -EINVAL;
326 }
327
328 return size;
329}
330
331static int calc_send_wqe(struct ib_qp_init_attr *attr)
332{
333 int inl_size = 0;
334 int size;
335
f0313965 336 size = sq_overhead(attr);
e126ba97
EC		 337 if (size < 0)
338 return size;
339
340 if (attr->cap.max_inline_data) {
341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
342 attr->cap.max_inline_data;
343 }
344
345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
348 return MLX5_SIG_WQE_SIZE;
349 else
350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 351}
352
288c01b7
EC		 353static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
354{
355 int max_sge;
356
357 if (attr->qp_type == IB_QPT_RC)
358 max_sge = (min_t(int, wqe_size, 512) -
359 sizeof(struct mlx5_wqe_ctrl_seg) -
360 sizeof(struct mlx5_wqe_raddr_seg)) /
361 sizeof(struct mlx5_wqe_data_seg);
362 else if (attr->qp_type == IB_QPT_XRC_INI)
363 max_sge = (min_t(int, wqe_size, 512) -
364 sizeof(struct mlx5_wqe_ctrl_seg) -
365 sizeof(struct mlx5_wqe_xrc_seg) -
366 sizeof(struct mlx5_wqe_raddr_seg)) /
367 sizeof(struct mlx5_wqe_data_seg);
368 else
369 max_sge = (wqe_size - sq_overhead(attr)) /
370 sizeof(struct mlx5_wqe_data_seg);
371
372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
373 sizeof(struct mlx5_wqe_data_seg));
374}
375
e126ba97
EC		 376static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
377 struct mlx5_ib_qp *qp)
378{
379 int wqe_size;
380 int wq_size;
381
382 if (!attr->cap.max_send_wr)
383 return 0;
384
385 wqe_size = calc_send_wqe(attr);
386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
387 if (wqe_size < 0)
388 return wqe_size;
389
938fe83c 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 393 return -EINVAL;
394 }
395
f0313965
ES		 396 qp->max_inline_data = wqe_size - sq_overhead(attr) -
397 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 398 attr->cap.max_inline_data = qp->max_inline_data;
399
e1e66cc2
SG		 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
401 qp->signature_en = true;
402
e126ba97
EC		 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 408 qp->sq.wqe_cnt,
409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 410 return -ENOMEM;
411 }
e126ba97 412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 413 qp->sq.max_gs = get_send_sge(attr, wqe_size);
414 if (qp->sq.max_gs < attr->cap.max_send_sge)
415 return -ENOMEM;
416
417 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 418 qp->sq.max_post = wq_size / wqe_size;
419 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 420
421 return wq_size;
422}
423
424static int set_user_buf_size(struct mlx5_ib_dev *dev,
425 struct mlx5_ib_qp *qp,
19098df2 426 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 427 struct mlx5_ib_qp_base *base,
428 struct ib_qp_init_attr *attr)
e126ba97
EC		 429{
430 int desc_sz = 1 << qp->sq.wqe_shift;
431
938fe83c 432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 435 return -EINVAL;
436 }
437
438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
440 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
441 return -EINVAL;
442 }
443
444 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
445
938fe83c 446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 448 qp->sq.wqe_cnt,
449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 450 return -EINVAL;
451 }
452
c2e53b2c
YH		 453 if (attr->qp_type == IB_QPT_RAW_PACKET ||
454 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
457 } else {
458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
459 (qp->sq.wqe_cnt << 6);
460 }
e126ba97
EC		 461
462 return 0;
463}
464
465static int qp_has_rq(struct ib_qp_init_attr *attr)
466{
467 if (attr->qp_type == IB_QPT_XRC_INI ||
468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
469 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
470 !attr->cap.max_recv_wr)
471 return 0;
472
473 return 1;
474}
475
0b80c14f
EC		 476enum {
477 /* this is the first blue flame register in the array of bfregs assigned
478 * to a processes. Since we do not use it for blue flame but rather
479 * regular 64 bit doorbells, we do not need a lock for maintaiing
480 * "odd/even" order
481 */
482 NUM_NON_BLUE_FLAME_BFREGS = 1,
483};
484
b037c29a
EC		 485static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
486{
31a78a5a 487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 488}
489
490static int num_med_bfreg(struct mlx5_ib_dev *dev,
491 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 492{
493 int n;
494
b037c29a
EC		 495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
496 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 497
498 return n >= 0 ? n : 0;
499}
500
18b0362e
YH		 501static int first_med_bfreg(struct mlx5_ib_dev *dev,
502 struct mlx5_bfreg_info *bfregi)
503{
504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
505}
506
b037c29a
EC		 507static int first_hi_bfreg(struct mlx5_ib_dev *dev,
508 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 509{
510 int med;
c1be5232 511
b037c29a
EC		 512 med = num_med_bfreg(dev, bfregi);
513 return ++med;
c1be5232
EC		 514}
515
b037c29a
EC		 516static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
517 struct mlx5_bfreg_info *bfregi)
e126ba97 518{
e126ba97
EC		 519 int i;
520
b037c29a
EC		 521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
522 if (!bfregi->count[i]) {
2f5ff264 523 bfregi->count[i]++;
e126ba97
EC		 524 return i;
525 }
526 }
527
528 return -ENOMEM;
529}
530
b037c29a
EC		 531static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
532 struct mlx5_bfreg_info *bfregi)
e126ba97 533{
18b0362e 534 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 535 int i;
536
18b0362e
YH		 537 if (minidx < 0)
538 return minidx;
539
540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 541 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 542 minidx = i;
0b80c14f
EC		 543 if (!bfregi->count[minidx])
544 break;
e126ba97
EC		 545 }
546
2f5ff264 547 bfregi->count[minidx]++;
e126ba97
EC		 548 return minidx;
549}
550
b037c29a 551static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 552 struct mlx5_bfreg_info *bfregi)
e126ba97 553{
ffaf58de 554 int bfregn = -ENOMEM;
e126ba97 555
2f5ff264 556 mutex_lock(&bfregi->lock);
ffaf58de
LR		 557 if (bfregi->ver >= 2) {
558 bfregn = alloc_high_class_bfreg(dev, bfregi);
559 if (bfregn < 0)
560 bfregn = alloc_med_class_bfreg(dev, bfregi);
561 }
562
563 if (bfregn < 0) {
0b80c14f 564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 565 bfregn = 0;
566 bfregi->count[bfregn]++;
e126ba97 567 }
2f5ff264 568 mutex_unlock(&bfregi->lock);
e126ba97 569
2f5ff264 570 return bfregn;
e126ba97
EC		 571}
572
4ed131d0 573void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 574{
2f5ff264 575 mutex_lock(&bfregi->lock);
b037c29a 576 bfregi->count[bfregn]--;
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97
EC		 578}
579
580static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
581{
582 switch (state) {
583 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
590 default: return -1;
591 }
592}
593
594static int to_mlx5_st(enum ib_qp_type type)
595{
596 switch (type) {
597 case IB_QPT_RC: return MLX5_QP_ST_RC;
598 case IB_QPT_UC: return MLX5_QP_ST_UC;
599 case IB_QPT_UD: return MLX5_QP_ST_UD;
600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
601 case IB_QPT_XRC_INI:
602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
603 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 607 case IB_QPT_RAW_PACKET:
0fb2ed66 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 609 case IB_QPT_MAX:
610 default: return -EINVAL;
611 }
612}
613
89ea94a7
MG		 614static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
615 struct mlx5_ib_cq *recv_cq);
616static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
618
7c043e90 619int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 620 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 621 bool dyn_bfreg)
e126ba97 622{
05f58ceb
LR		 623 unsigned int bfregs_per_sys_page;
624 u32 index_of_sys_page;
625 u32 offset;
b037c29a
EC		 626
627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
628 MLX5_NON_FP_BFREGS_PER_UAR;
629 index_of_sys_page = bfregn / bfregs_per_sys_page;
630
1ee47ab3
YH		 631 if (dyn_bfreg) {
632 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 633
634 if (index_of_sys_page >= bfregi->num_sys_pages)
635 return -EINVAL;
636
1ee47ab3
YH		 637 if (bfregn > bfregi->num_dyn_bfregs ||
638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
640 return -EINVAL;
641 }
642 }
b037c29a 643
1ee47ab3 644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 645 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 646}
647
19098df2 648static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
649 struct ib_pd *pd,
650 unsigned long addr, size_t size,
651 struct ib_umem **umem,
652 int *npages, int *page_shift, int *ncont,
653 u32 *offset)
654{
655 int err;
656
657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
658 if (IS_ERR(*umem)) {
659 mlx5_ib_dbg(dev, "umem_get failed\n");
660 return PTR_ERR(*umem);
661 }
662
762f899a 663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 664
665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
666 if (err) {
667 mlx5_ib_warn(dev, "bad offset\n");
668 goto err_umem;
669 }
670
671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
672 addr, size, *npages, *page_shift, *ncont, *offset);
673
674 return 0;
675
676err_umem:
677 ib_umem_release(*umem);
678 *umem = NULL;
679
680 return err;
681}
682
fe248c3a
MG		 683static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
684 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 685{
686 struct mlx5_ib_ucontext *context;
687
fe248c3a
MG		 688 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
689 atomic_dec(&dev->delay_drop.rqs_cnt);
690
79b20a6c
YH		 691 context = to_mucontext(pd->uobject->context);
692 mlx5_ib_db_unmap_user(context, &rwq->db);
693 if (rwq->umem)
694 ib_umem_release(rwq->umem);
695}
696
697static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
698 struct mlx5_ib_rwq *rwq,
699 struct mlx5_ib_create_wq *ucmd)
700{
701 struct mlx5_ib_ucontext *context;
702 int page_shift = 0;
703 int npages;
704 u32 offset = 0;
705 int ncont = 0;
706 int err;
707
708 if (!ucmd->buf_addr)
709 return -EINVAL;
710
711 context = to_mucontext(pd->uobject->context);
712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
713 rwq->buf_size, 0, 0);
714 if (IS_ERR(rwq->umem)) {
715 mlx5_ib_dbg(dev, "umem_get failed\n");
716 err = PTR_ERR(rwq->umem);
717 return err;
718 }
719
762f899a 720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 721 &ncont, NULL);
722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
723 &rwq->rq_page_offset);
724 if (err) {
725 mlx5_ib_warn(dev, "bad offset\n");
726 goto err_umem;
727 }
728
729 rwq->rq_num_pas = ncont;
730 rwq->page_shift = page_shift;
731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
733
734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
735 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
736 npages, page_shift, ncont, offset);
737
738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
739 if (err) {
740 mlx5_ib_dbg(dev, "map failed\n");
741 goto err_umem;
742 }
743
744 rwq->create_type = MLX5_WQ_USER;
745 return 0;
746
747err_umem:
748 ib_umem_release(rwq->umem);
749 return err;
750}
751
b037c29a
EC		 752static int adjust_bfregn(struct mlx5_ib_dev *dev,
753 struct mlx5_bfreg_info *bfregi, int bfregn)
754{
755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
757}
758
e126ba97
EC		 759static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
760 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 761 struct ib_qp_init_attr *attr,
09a7d9ec 762 u32 **in,
19098df2 763 struct mlx5_ib_create_qp_resp *resp, int *inlen,
764 struct mlx5_ib_qp_base *base)
e126ba97
EC		 765{
766 struct mlx5_ib_ucontext *context;
767 struct mlx5_ib_create_qp ucmd;
19098df2 768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 769 int page_shift = 0;
1ee47ab3 770 int uar_index = 0;
e126ba97 771 int npages;
9e9c47d0 772 u32 offset = 0;
2f5ff264 773 int bfregn;
9e9c47d0 774 int ncont = 0;
09a7d9ec
SM		 775 __be64 *pas;
776 void *qpc;
e126ba97 777 int err;
5aa3771d 778 u16 uid;
e126ba97
EC		 779
780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
781 if (err) {
782 mlx5_ib_dbg(dev, "copy failed\n");
783 return err;
784 }
785
786 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 787 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
788 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
789 ucmd.bfreg_index, true);
790 if (uar_index < 0)
791 return uar_index;
792
793 bfregn = MLX5_IB_INVALID_BFREG;
794 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
795 /*
796 * TBD: should come from the verbs when we have the API
797 */
051f2630 798 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 799 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 800 }
051f2630 801 else {
ffaf58de
LR		 802 bfregn = alloc_bfreg(dev, &context->bfregi);
803 if (bfregn < 0)
804 return bfregn;
e126ba97
EC		 805 }
806
2f5ff264 807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 808 if (bfregn != MLX5_IB_INVALID_BFREG)
809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
810 false);
e126ba97 811
48fea837
HE		 812 qp->rq.offset = 0;
813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
815
0fb2ed66 816 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 817 if (err)
2f5ff264 818 goto err_bfreg;
e126ba97 819
19098df2 820 if (ucmd.buf_addr && ubuffer->buf_size) {
821 ubuffer->buf_addr = ucmd.buf_addr;
822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
823 ubuffer->buf_size,
824 &ubuffer->umem, &npages, &page_shift,
825 &ncont, &offset);
826 if (err)
2f5ff264 827 goto err_bfreg;
9e9c47d0 828 } else {
19098df2 829 ubuffer->umem = NULL;
e126ba97 830 }
e126ba97 831
09a7d9ec
SM		 832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 834 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 835 if (!*in) {
836 err = -ENOMEM;
837 goto err_umem;
838 }
09a7d9ec 839
5aa3771d
YH		 840 uid = (attr->qp_type != IB_QPT_XRC_TGT) ? to_mpd(pd)->uid : 0;
841 MLX5_SET(create_qp_in, *in, uid, uid);
09a7d9ec 842 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 843 if (ubuffer->umem)
09a7d9ec
SM		 844 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
845
846 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
847
848 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
849 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 850
09a7d9ec 851 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 852 if (bfregn != MLX5_IB_INVALID_BFREG)
853 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
854 else
855 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 856 qp->bfregn = bfregn;
e126ba97
EC		 857
858 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
859 if (err) {
860 mlx5_ib_dbg(dev, "map failed\n");
861 goto err_free;
862 }
863
41d902cb 864 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
e126ba97
EC		 865 if (err) {
866 mlx5_ib_dbg(dev, "copy failed\n");
867 goto err_unmap;
868 }
869 qp->create_type = MLX5_QP_USER;
870
871 return 0;
872
873err_unmap:
874 mlx5_ib_db_unmap_user(context, &qp->db);
875
876err_free:
479163f4 877 kvfree(*in);
e126ba97
EC		 878
879err_umem:
19098df2 880 if (ubuffer->umem)
881 ib_umem_release(ubuffer->umem);
e126ba97 882
2f5ff264 883err_bfreg:
1ee47ab3
YH		 884 if (bfregn != MLX5_IB_INVALID_BFREG)
885 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 886 return err;
887}
888
b037c29a
EC		 889static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
890 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 891{
892 struct mlx5_ib_ucontext *context;
893
894 context = to_mucontext(pd->uobject->context);
895 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 896 if (base->ubuffer.umem)
897 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 898
899 /*
900 * Free only the BFREGs which are handled by the kernel.
901 * BFREGs of UARs allocated dynamically are handled by user.
902 */
903 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
904 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 905}
906
34f4c955
GL		 907/* get_sq_edge - Get the next nearby edge.
908 *
909 * An 'edge' is defined as the first following address after the end
910 * of the fragment or the SQ. Accordingly, during the WQE construction
911 * which repetitively increases the pointer to write the next data, it
912 * simply should check if it gets to an edge.
913 *
914 * @sq - SQ buffer.
915 * @idx - Stride index in the SQ buffer.
916 *
917 * Return:
918 * The new edge.
919 */
920static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
921{
922 void *fragment_end;
923
924 fragment_end = mlx5_frag_buf_get_wqe
925 (&sq->fbc,
926 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
927
928 return fragment_end + MLX5_SEND_WQE_BB;
929}
930
e126ba97
EC		 931static int create_kernel_qp(struct mlx5_ib_dev *dev,
932 struct ib_qp_init_attr *init_attr,
933 struct mlx5_ib_qp *qp,
09a7d9ec 934 u32 **in, int *inlen,
19098df2 935 struct mlx5_ib_qp_base *base)
e126ba97 936{
e126ba97 937 int uar_index;
09a7d9ec 938 void *qpc;
e126ba97
EC		 939 int err;
940
f0313965
ES		 941 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
942 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 943 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 944 IB_QP_CREATE_NETIF_QP |
b11a4f9c 945 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 946 return -EINVAL;
e126ba97
EC		 947
948 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 949 qp->bf.bfreg = &dev->fp_bfreg;
950 else
951 qp->bf.bfreg = &dev->bfreg;
e126ba97 952
d8030b0d
EC		 953 /* We need to divide by two since each register is comprised of
954 * two buffers of identical size, namely odd and even
955 */
956 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 957 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 958
959 err = calc_sq_size(dev, init_attr, qp);
960 if (err < 0) {
961 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 962 return err;
e126ba97
EC		 963 }
964
965 qp->rq.offset = 0;
966 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 967 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 968
34f4c955
GL		 969 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
970 &qp->buf, dev->mdev->priv.numa_node);
e126ba97
EC		 971 if (err) {
972 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 973 return err;
e126ba97
EC		 974 }
975
34f4c955
GL		 976 if (qp->rq.wqe_cnt)
977 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
978 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
979
980 if (qp->sq.wqe_cnt) {
981 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
982 MLX5_SEND_WQE_BB;
983 mlx5_init_fbc_offset(qp->buf.frags +
984 (qp->sq.offset / PAGE_SIZE),
985 ilog2(MLX5_SEND_WQE_BB),
986 ilog2(qp->sq.wqe_cnt),
987 sq_strides_offset, &qp->sq.fbc);
988
989 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
990 }
991
09a7d9ec
SM		 992 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
993 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 994 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 995 if (!*in) {
996 err = -ENOMEM;
997 goto err_buf;
998 }
09a7d9ec
SM		 999
1000 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1001 MLX5_SET(qpc, qpc, uar_page, uar_index);
1002 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1003
e126ba97 1004 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 1005 MLX5_SET(qpc, qpc, fre, 1);
1006 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 1007
b11a4f9c 1008 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 1009 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 1010 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1011 }
1012
34f4c955
GL		 1013 mlx5_fill_page_frag_array(&qp->buf,
1014 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1015 *in, pas));
e126ba97 1016
9603b61d 1017 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 1018 if (err) {
1019 mlx5_ib_dbg(dev, "err %d\n", err);
1020 goto err_free;
1021 }
1022
b5883008
LD		 1023 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1024 sizeof(*qp->sq.wrid), GFP_KERNEL);
1025 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1026 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1027 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1028 sizeof(*qp->rq.wrid), GFP_KERNEL);
1029 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1030 sizeof(*qp->sq.w_list), GFP_KERNEL);
1031 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1032 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1033
1034 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1035 !qp->sq.w_list || !qp->sq.wqe_head) {
1036 err = -ENOMEM;
1037 goto err_wrid;
1038 }
1039 qp->create_type = MLX5_QP_KERNEL;
1040
1041 return 0;
1042
1043err_wrid:
b5883008
LD		 1044 kvfree(qp->sq.wqe_head);
1045 kvfree(qp->sq.w_list);
1046 kvfree(qp->sq.wrid);
1047 kvfree(qp->sq.wr_data);
1048 kvfree(qp->rq.wrid);
f4044dac 1049 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1050
1051err_free:
479163f4 1052 kvfree(*in);
e126ba97
EC		 1053
1054err_buf:
34f4c955 1055 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1056 return err;
1057}
1058
1059static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1060{
b5883008
LD		 1061 kvfree(qp->sq.wqe_head);
1062 kvfree(qp->sq.w_list);
1063 kvfree(qp->sq.wrid);
1064 kvfree(qp->sq.wr_data);
1065 kvfree(qp->rq.wrid);
f4044dac 1066 mlx5_db_free(dev->mdev, &qp->db);
34f4c955 1067 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1068}
1069
09a7d9ec 1070static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1071{
1072 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1073 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1074 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1075 return MLX5_SRQ_RQ;
e126ba97 1076 else if (!qp->has_rq)
09a7d9ec 1077 return MLX5_ZERO_LEN_RQ;
e126ba97 1078 else
09a7d9ec 1079 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1080}
1081
1082static int is_connected(enum ib_qp_type qp_type)
1083{
5d6ff1ba
YC		 1084 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1085 qp_type == MLX5_IB_QPT_DCI)
e126ba97
EC		 1086 return 1;
1087
1088 return 0;
1089}
1090
0fb2ed66 1091static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1092 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1093 struct mlx5_ib_sq *sq, u32 tdn,
1094 struct ib_pd *pd)
0fb2ed66 1095{
c4f287c4 1096 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1097 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1098
1cd6dbd3 1099 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1100 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1101 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1102 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1103
0fb2ed66 1104 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1105}
1106
1107static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1108 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1109{
1cd6dbd3 1110 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1111}
1112
b96c9dde
MB		 1113static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1114 struct mlx5_ib_sq *sq)
1115{
1116 if (sq->flow_rule)
1117 mlx5_del_flow_rules(sq->flow_rule);
1118}
1119
0fb2ed66 1120static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1121 struct mlx5_ib_sq *sq, void *qpin,
1122 struct ib_pd *pd)
1123{
1124 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1125 __be64 *pas;
1126 void *in;
1127 void *sqc;
1128 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1129 void *wq;
1130 int inlen;
1131 int err;
1132 int page_shift = 0;
1133 int npages;
1134 int ncont = 0;
1135 u32 offset = 0;
1136
1137 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1138 &sq->ubuffer.umem, &npages, &page_shift,
1139 &ncont, &offset);
1140 if (err)
1141 return err;
1142
1143 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1144 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1145 if (!in) {
1146 err = -ENOMEM;
1147 goto err_umem;
1148 }
1149
c14003f0 1150 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1151 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1152 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1153 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1154 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1155 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1156 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1157 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1158 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1159 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1160 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1161 MLX5_CAP_ETH(dev->mdev, swp))
1162 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1163
1164 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1165 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1166 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1167 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1168 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1169 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1171 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1172 MLX5_SET(wq, wq, page_offset, offset);
1173
1174 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1175 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1176
1177 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1178
1179 kvfree(in);
1180
1181 if (err)
1182 goto err_umem;
1183
b96c9dde
MB		 1184 err = create_flow_rule_vport_sq(dev, sq);
1185 if (err)
1186 goto err_flow;
1187
0fb2ed66 1188 return 0;
1189
b96c9dde
MB		 1190err_flow:
1191 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1192
0fb2ed66 1193err_umem:
1194 ib_umem_release(sq->ubuffer.umem);
1195 sq->ubuffer.umem = NULL;
1196
1197 return err;
1198}
1199
1200static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1201 struct mlx5_ib_sq *sq)
1202{
b96c9dde 1203 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1204 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1205 ib_umem_release(sq->ubuffer.umem);
1206}
1207
2c292dbb 1208static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1209{
1210 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1211 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1212 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1213 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1214 u32 po_quanta = 1 << (log_page_size - 6);
1215 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1216 u32 page_size = 1 << log_page_size;
1217 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1218 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1219
1220 return rq_num_pas * sizeof(u64);
1221}
1222
1223static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1224 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1225 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1226{
358e42ea 1227 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1228 __be64 *pas;
1229 __be64 *qp_pas;
1230 void *in;
1231 void *rqc;
1232 void *wq;
1233 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1234 size_t rq_pas_size = get_rq_pas_size(qpc);
1235 size_t inlen;
0fb2ed66 1236 int err;
2c292dbb
BP		 1237
1238 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1239 return -EINVAL;
0fb2ed66 1240
1241 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1242 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1243 if (!in)
1244 return -ENOMEM;
1245
34d57585 1246 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1247 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1248 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1249 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1250 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1251 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1252 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1253 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1254 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1255
358e42ea
MD		 1256 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1257 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1258
0fb2ed66 1259 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1260 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1261 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1262 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1263 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1264 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1265 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1266 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1267 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1268 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1269
1270 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1271 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1272 memcpy(pas, qp_pas, rq_pas_size);
1273
1274 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1275
1276 kvfree(in);
1277
1278 return err;
1279}
1280
1281static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1282 struct mlx5_ib_rq *rq)
1283{
1284 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1285}
1286
f95ef6cb
MG		 1287static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1288{
1289 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1290 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1291 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1292}
1293
0042f9e4
MB		 1294static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1295 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1296 u32 qp_flags_en,
1297 struct ib_pd *pd)
0042f9e4
MB		 1298{
1299 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1300 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1301 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1302 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1303}
1304
0fb2ed66 1305static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1306 struct mlx5_ib_rq *rq, u32 tdn,
443c1cf9
YH		 1307 u32 *qp_flags_en,
1308 struct ib_pd *pd)
0fb2ed66 1309{
175edba8 1310 u8 lb_flag = 0;
0fb2ed66 1311 u32 *in;
1312 void *tirc;
1313 int inlen;
1314 int err;
1315
1316 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1317 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1318 if (!in)
1319 return -ENOMEM;
1320
443c1cf9 1321 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1322 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1323 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1324 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1325 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1326 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1327 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1328
175edba8
MB		 1329 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1330 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1331
1332 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1333 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1334
1335 if (dev->rep) {
1336 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1337 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1338 }
1339
1340 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
ec9c2fb8 1341
0fb2ed66 1342 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1343
0042f9e4
MB		 1344 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1345 err = mlx5_ib_enable_lb(dev, false, true);
1346
1347 if (err)
443c1cf9 1348 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1349 }
0fb2ed66 1350 kvfree(in);
1351
1352 return err;
1353}
1354
0fb2ed66 1355static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1356 u32 *in, size_t inlen,
7f72052c
YH		 1357 struct ib_pd *pd,
1358 struct ib_udata *udata,
1359 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1360{
1361 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1364 struct ib_uobject *uobj = pd->uobject;
1365 struct ib_ucontext *ucontext = uobj->context;
1366 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1367 int err;
1368 u32 tdn = mucontext->tdn;
7f72052c 1369 u16 uid = to_mpd(pd)->uid;
0fb2ed66 1370
1371 if (qp->sq.wqe_cnt) {
1cd6dbd3 1372 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1373 if (err)
1374 return err;
1375
1376 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1377 if (err)
1378 goto err_destroy_tis;
1379
7f72052c
YH		 1380 if (uid) {
1381 resp->tisn = sq->tisn;
1382 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1383 resp->sqn = sq->base.mqp.qpn;
1384 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1385 }
1386
0fb2ed66 1387 sq->base.container_mibqp = qp;
1d31e9c0 1388 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1389 }
1390
1391 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1392 rq->base.container_mibqp = qp;
1393
e4cc4fa7
NO		 1394 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1395 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1396 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1397 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1398 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1399 if (err)
1400 goto err_destroy_sq;
1401
443c1cf9 1402 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
0fb2ed66 1403 if (err)
1404 goto err_destroy_rq;
7f72052c
YH		 1405
1406 if (uid) {
1407 resp->rqn = rq->base.mqp.qpn;
1408 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1409 resp->tirn = rq->tirn;
1410 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1411 }
0fb2ed66 1412 }
1413
1414 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1415 rq->base.mqp.qpn;
7f72052c
YH		 1416 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1417 if (err)
1418 goto err_destroy_tir;
0fb2ed66 1419
1420 return 0;
1421
7f72052c
YH		 1422err_destroy_tir:
1423 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
0fb2ed66 1424err_destroy_rq:
1425 destroy_raw_packet_qp_rq(dev, rq);
1426err_destroy_sq:
1427 if (!qp->sq.wqe_cnt)
1428 return err;
1429 destroy_raw_packet_qp_sq(dev, sq);
1430err_destroy_tis:
1cd6dbd3 1431 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1432
1433 return err;
1434}
1435
1436static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1437 struct mlx5_ib_qp *qp)
1438{
1439 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1440 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1441 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1442
1443 if (qp->rq.wqe_cnt) {
443c1cf9 1444 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1445 destroy_raw_packet_qp_rq(dev, rq);
1446 }
1447
1448 if (qp->sq.wqe_cnt) {
1449 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1450 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1451 }
1452}
1453
1454static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1455 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1456{
1457 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1459
1460 sq->sq = &qp->sq;
1461 rq->rq = &qp->rq;
1462 sq->doorbell = &qp->db;
1463 rq->doorbell = &qp->db;
1464}
1465
28d61370
YH		 1466static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1467{
0042f9e4
MB		 1468 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1469 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1470 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1471 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1472 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1473}
1474
1475static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1476 struct ib_pd *pd,
1477 struct ib_qp_init_attr *init_attr,
1478 struct ib_udata *udata)
1479{
1480 struct ib_uobject *uobj = pd->uobject;
1481 struct ib_ucontext *ucontext = uobj->context;
1482 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1483 struct mlx5_ib_create_qp_resp resp = {};
1484 int inlen;
1485 int err;
1486 u32 *in;
1487 void *tirc;
1488 void *hfso;
1489 u32 selected_fields = 0;
2d93fc85 1490 u32 outer_l4;
28d61370
YH		 1491 size_t min_resp_len;
1492 u32 tdn = mucontext->tdn;
1493 struct mlx5_ib_create_qp_rss ucmd = {};
1494 size_t required_cmd_sz;
175edba8 1495 u8 lb_flag = 0;
28d61370
YH		 1496
1497 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1498 return -EOPNOTSUPP;
1499
1500 if (init_attr->create_flags || init_attr->send_cq)
1501 return -EINVAL;
1502
2f5ff264 1503 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1504 if (udata->outlen < min_resp_len)
1505 return -EINVAL;
1506
f95ef6cb 1507 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1508 if (udata->inlen < required_cmd_sz) {
1509 mlx5_ib_dbg(dev, "invalid inlen\n");
1510 return -EINVAL;
1511 }
1512
1513 if (udata->inlen > sizeof(ucmd) &&
1514 !ib_is_udata_cleared(udata, sizeof(ucmd),
1515 udata->inlen - sizeof(ucmd))) {
1516 mlx5_ib_dbg(dev, "inlen is not supported\n");
1517 return -EOPNOTSUPP;
1518 }
1519
1520 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1521 mlx5_ib_dbg(dev, "copy failed\n");
1522 return -EFAULT;
1523 }
1524
1525 if (ucmd.comp_mask) {
1526 mlx5_ib_dbg(dev, "invalid comp mask\n");
1527 return -EOPNOTSUPP;
1528 }
1529
175edba8
MB		 1530 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1531 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1532 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
f95ef6cb
MG		 1533 mlx5_ib_dbg(dev, "invalid flags\n");
1534 return -EOPNOTSUPP;
1535 }
1536
1537 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1538 !tunnel_offload_supported(dev->mdev)) {
1539 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1540 return -EOPNOTSUPP;
1541 }
1542
309fa347
MG		 1543 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1544 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1545 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1546 return -EOPNOTSUPP;
1547 }
1548
175edba8
MB		 1549 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1550 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1551 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1552 }
1553
1554 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1555 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1556 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1557 }
1558
41d902cb 1559 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
28d61370
YH		 1560 if (err) {
1561 mlx5_ib_dbg(dev, "copy failed\n");
1562 return -EINVAL;
1563 }
1564
1565 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1566 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1567 if (!in)
1568 return -ENOMEM;
1569
443c1cf9 1570 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1571 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1572 MLX5_SET(tirc, tirc, disp_type,
1573 MLX5_TIRC_DISP_TYPE_INDIRECT);
1574 MLX5_SET(tirc, tirc, indirect_table,
1575 init_attr->rwq_ind_tbl->ind_tbl_num);
1576 MLX5_SET(tirc, tirc, transport_domain, tdn);
1577
1578 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1579
1580 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1581 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1582
175edba8
MB		 1583 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1584
309fa347
MG		 1585 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1586 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1587 else
1588 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1589
28d61370
YH		 1590 switch (ucmd.rx_hash_function) {
1591 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1592 {
1593 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1594 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1595
1596 if (len != ucmd.rx_key_len) {
1597 err = -EINVAL;
1598 goto err;
1599 }
1600
1601 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1602 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1603 memcpy(rss_key, ucmd.rx_hash_key, len);
1604 break;
1605 }
1606 default:
1607 err = -EOPNOTSUPP;
1608 goto err;
1609 }
1610
1611 if (!ucmd.rx_hash_fields_mask) {
1612 /* special case when this TIR serves as steering entry without hashing */
1613 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1614 goto create_tir;
1615 err = -EINVAL;
1616 goto err;
1617 }
1618
1619 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1620 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1621 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1622 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1623 err = -EINVAL;
1624 goto err;
1625 }
1626
1627 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1628 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1629 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1630 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1631 MLX5_L3_PROT_TYPE_IPV4);
1632 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1633 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1634 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1635 MLX5_L3_PROT_TYPE_IPV6);
1636
2d93fc85
MB		 1637 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1638 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1639 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1640 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1641 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1642
1643 /* Check that only one l4 protocol is set */
1644 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1645 err = -EINVAL;
1646 goto err;
1647 }
1648
1649 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1650 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1651 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1652 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1653 MLX5_L4_PROT_TYPE_TCP);
1654 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1655 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1656 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1657 MLX5_L4_PROT_TYPE_UDP);
1658
1659 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1661 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1662
1663 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1664 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1665 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1666
1667 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1668 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1669 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1670
1671 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1672 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1673 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1674
2d93fc85
MB		 1675 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1676 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1677
28d61370
YH		 1678 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1679
1680create_tir:
1681 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1682
0042f9e4
MB		 1683 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1684 err = mlx5_ib_enable_lb(dev, false, true);
1685
1686 if (err)
443c1cf9
YH		 1687 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1688 to_mpd(pd)->uid);
0042f9e4
MB		 1689 }
1690
28d61370
YH		 1691 if (err)
1692 goto err;
1693
7f72052c
YH		 1694 if (mucontext->devx_uid) {
1695 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1696 resp.tirn = qp->rss_qp.tirn;
1697 }
1698
1699 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1700 if (err)
1701 goto err_copy;
1702
28d61370
YH		 1703 kvfree(in);
1704 /* qpn is reserved for that QP */
1705 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1706 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1707 return 0;
1708
7f72052c
YH		 1709err_copy:
1710 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
28d61370
YH		 1711err:
1712 kvfree(in);
1713 return err;
1714}
1715
5d6ff1ba
YC		 1716static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1717 void *qpc)
1718{
1719 int rcqe_sz;
1720
1721 if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1722 return;
1723
1724 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1725
1726 if (rcqe_sz == 128) {
1727 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1728 return;
1729 }
1730
1731 if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1732 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1733}
1734
1735static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1736 struct ib_qp_init_attr *init_attr,
6f4bc0ea 1737 struct mlx5_ib_create_qp *ucmd,
5d6ff1ba
YC		 1738 void *qpc)
1739{
1740 enum ib_qp_type qpt = init_attr->qp_type;
1741 int scqe_sz;
6f4bc0ea 1742 bool allow_scat_cqe = 0;
5d6ff1ba
YC		 1743
1744 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1745 return;
1746
6f4bc0ea
YC		 1747 if (ucmd)
1748 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1749
1750 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
5d6ff1ba
YC		 1751 return;
1752
1753 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1754 if (scqe_sz == 128) {
1755 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1756 return;
1757 }
1758
1759 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1760 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1761 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1762}
1763
a60109dc
YC		 1764static int atomic_size_to_mode(int size_mask)
1765{
1766 /* driver does not support atomic_size > 256B
1767 * and does not know how to translate bigger sizes
1768 */
1769 int supported_size_mask = size_mask & 0x1ff;
1770 int log_max_size;
1771
1772 if (!supported_size_mask)
1773 return -EOPNOTSUPP;
1774
1775 log_max_size = __fls(supported_size_mask);
1776
1777 if (log_max_size > 3)
1778 return log_max_size;
1779
1780 return MLX5_ATOMIC_MODE_8B;
1781}
1782
1783static int get_atomic_mode(struct mlx5_ib_dev *dev,
1784 enum ib_qp_type qp_type)
1785{
1786 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1787 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1788 int atomic_mode = -EOPNOTSUPP;
1789 int atomic_size_mask;
1790
1791 if (!atomic)
1792 return -EOPNOTSUPP;
1793
1794 if (qp_type == MLX5_IB_QPT_DCT)
1795 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1796 else
1797 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1798
1799 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1800 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1801 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1802
1803 if (atomic_mode <= 0 &&
1804 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1805 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1806 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1807
1808 return atomic_mode;
1809}
1810
2e43bb31
YC		 1811static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1812{
1813 return (input & ~supported) == 0;
1814}
1815
e126ba97
EC		 1816static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1817 struct ib_qp_init_attr *init_attr,
1818 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1819{
1820 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1821 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1822 struct mlx5_core_dev *mdev = dev->mdev;
0625b4ba 1823 struct mlx5_ib_create_qp_resp resp = {};
89ea94a7
MG		 1824 struct mlx5_ib_cq *send_cq;
1825 struct mlx5_ib_cq *recv_cq;
1826 unsigned long flags;
cfb5e088 1827 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1828 struct mlx5_ib_create_qp ucmd;
1829 struct mlx5_ib_qp_base *base;
e7b169f3 1830 int mlx5_st;
cfb5e088 1831 void *qpc;
09a7d9ec
SM		 1832 u32 *in;
1833 int err;
e126ba97
EC		 1834
1835 mutex_init(&qp->mutex);
1836 spin_lock_init(&qp->sq.lock);
1837 spin_lock_init(&qp->rq.lock);
1838
e7b169f3
NO		 1839 mlx5_st = to_mlx5_st(init_attr->qp_type);
1840 if (mlx5_st < 0)
1841 return -EINVAL;
1842
28d61370
YH		 1843 if (init_attr->rwq_ind_tbl) {
1844 if (!udata)
1845 return -ENOSYS;
1846
1847 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1848 return err;
1849 }
1850
f360d88a 1851 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1852 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1853 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1854 return -EINVAL;
1855 } else {
1856 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1857 }
1858 }
1859
051f2630
LR		 1860 if (init_attr->create_flags &
1861 (IB_QP_CREATE_CROSS_CHANNEL |
1862 IB_QP_CREATE_MANAGED_SEND |
1863 IB_QP_CREATE_MANAGED_RECV)) {
1864 if (!MLX5_CAP_GEN(mdev, cd)) {
1865 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1866 return -EINVAL;
1867 }
1868 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1869 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1870 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1871 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1872 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1873 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1874 }
f0313965
ES		 1875
1876 if (init_attr->qp_type == IB_QPT_UD &&
1877 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1878 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1879 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1880 return -EOPNOTSUPP;
1881 }
1882
358e42ea
MD		 1883 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1884 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1885 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1886 return -EOPNOTSUPP;
1887 }
1888 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1889 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1890 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1891 return -EOPNOTSUPP;
1892 }
1893 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1894 }
1895
e126ba97
EC		 1896 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1897 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1898
e4cc4fa7
NO		 1899 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1900 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1901 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1902 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1903 return -EOPNOTSUPP;
1904 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1905 }
1906
e126ba97
EC		 1907 if (pd && pd->uobject) {
1908 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1909 mlx5_ib_dbg(dev, "copy failed\n");
1910 return -EFAULT;
1911 }
1912
2e43bb31
YC		 1913 if (!check_flags_mask(ucmd.flags,
1914 MLX5_QP_FLAG_SIGNATURE |
1915 MLX5_QP_FLAG_SCATTER_CQE |
1916 MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1917 MLX5_QP_FLAG_BFREG_INDEX |
1918 MLX5_QP_FLAG_TYPE_DCT |
6f4bc0ea
YC		 1919 MLX5_QP_FLAG_TYPE_DCI |
1920 MLX5_QP_FLAG_ALLOW_SCATTER_CQE))
2e43bb31
YC		 1921 return -EINVAL;
1922
cfb5e088
HA		 1923 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1924 &ucmd, udata->inlen, &uidx);
1925 if (err)
1926 return err;
1927
e126ba97 1928 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
5d6ff1ba
YC		 1929 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1930 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1931 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1932 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1933 !tunnel_offload_supported(mdev)) {
1934 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1935 return -EOPNOTSUPP;
1936 }
175edba8
MB		 1937 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1938 }
1939
1940 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1941 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1942 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1943 return -EOPNOTSUPP;
1944 }
1945 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1946 }
1947
1948 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1949 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1950 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1951 return -EOPNOTSUPP;
1952 }
1953 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
f95ef6cb 1954 }
c2e53b2c
YH		 1955
1956 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1957 if (init_attr->qp_type != IB_QPT_UD ||
1958 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1959 MLX5_CAP_PORT_TYPE_IB) ||
1960 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1961 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1962 return -EOPNOTSUPP;
1963 }
1964
1965 qp->flags |= MLX5_IB_QP_UNDERLAY;
1966 qp->underlay_qpn = init_attr->source_qpn;
1967 }
e126ba97
EC		 1968 } else {
1969 qp->wq_sig = !!wq_signature;
1970 }
1971
c2e53b2c
YH		 1972 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1973 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1974 &qp->raw_packet_qp.rq.base :
1975 &qp->trans_qp.base;
1976
e126ba97
EC		 1977 qp->has_rq = qp_has_rq(init_attr);
1978 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1979 qp, (pd && pd->uobject) ? &ucmd : NULL);
1980 if (err) {
1981 mlx5_ib_dbg(dev, "err %d\n", err);
1982 return err;
1983 }
1984
1985 if (pd) {
1986 if (pd->uobject) {
938fe83c
SM		 1987 __u32 max_wqes =
1988 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1989 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1990 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1991 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1992 mlx5_ib_dbg(dev, "invalid rq params\n");
1993 return -EINVAL;
1994 }
938fe83c 1995 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1996 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1997 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1998 return -EINVAL;
1999 }
b11a4f9c
HE		 2000 if (init_attr->create_flags &
2001 mlx5_ib_create_qp_sqpn_qp1()) {
2002 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2003 return -EINVAL;
2004 }
0fb2ed66 2005 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2006 &resp, &inlen, base);
e126ba97
EC		 2007 if (err)
2008 mlx5_ib_dbg(dev, "err %d\n", err);
2009 } else {
19098df2 2010 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2011 base);
e126ba97
EC		 2012 if (err)
2013 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 2014 }
2015
2016 if (err)
2017 return err;
2018 } else {
1b9a07ee 2019 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 2020 if (!in)
2021 return -ENOMEM;
2022
2023 qp->create_type = MLX5_QP_EMPTY;
2024 }
2025
2026 if (is_sqp(init_attr->qp_type))
2027 qp->port = init_attr->port_num;
2028
09a7d9ec
SM		 2029 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2030
e7b169f3 2031 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 2032 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 2033
2034 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 2035 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 2036 else
09a7d9ec
SM		 2037 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2038
e126ba97
EC		 2039
2040 if (qp->wq_sig)
09a7d9ec 2041 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 2042
f360d88a 2043 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 2044 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 2045
051f2630 2046 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 2047 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 2048 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 2049 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 2050 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 2051 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 2052
e126ba97 2053 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
5d6ff1ba 2054 configure_responder_scat_cqe(init_attr, qpc);
6f4bc0ea
YC		 2055 configure_requester_scat_cqe(dev, init_attr,
2056 (pd && pd->uobject) ? &ucmd : NULL,
2057 qpc);
e126ba97
EC		 2058 }
2059
2060 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 2061 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2062 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 2063 }
2064
09a7d9ec 2065 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 2066
3fd3307e 2067 if (qp->sq.wqe_cnt) {
09a7d9ec 2068 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 2069 } else {
09a7d9ec 2070 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 2071 if (init_attr->srq &&
2072 init_attr->srq->srq_type == IB_SRQT_TM)
2073 MLX5_SET(qpc, qpc, offload_type,
2074 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2075 }
e126ba97
EC		 2076
2077 /* Set default resources */
2078 switch (init_attr->qp_type) {
2079 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 2080 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2081 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2082 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2083 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 2084 break;
2085 case IB_QPT_XRC_INI:
09a7d9ec
SM		 2086 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2087 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2088 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 2089 break;
2090 default:
2091 if (init_attr->srq) {
09a7d9ec
SM		 2092 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2093 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 2094 } else {
09a7d9ec
SM		 2095 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2096 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 2097 }
2098 }
2099
2100 if (init_attr->send_cq)
09a7d9ec 2101 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 2102
2103 if (init_attr->recv_cq)
09a7d9ec 2104 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 2105
09a7d9ec 2106 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 2107
09a7d9ec
SM		 2108 /* 0xffffff means we ask to work with cqe version 0 */
2109 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 2110 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 2111
f0313965
ES		 2112 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2113 if (init_attr->qp_type == IB_QPT_UD &&
2114 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 2115 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2116 qp->flags |= MLX5_IB_QP_LSO;
2117 }
cfb5e088 2118
b1383aa6
NO		 2119 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2120 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2121 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2122 err = -EOPNOTSUPP;
2123 goto err;
2124 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2125 MLX5_SET(qpc, qpc, end_padding_mode,
2126 MLX5_WQ_END_PAD_MODE_ALIGN);
2127 } else {
2128 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2129 }
2130 }
2131
2c292dbb
BP		 2132 if (inlen < 0) {
2133 err = -EINVAL;
2134 goto err;
2135 }
2136
c2e53b2c
YH		 2137 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2138 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2139 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2140 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c
YH		 2141 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2142 &resp);
0fb2ed66 2143 } else {
2144 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2145 }
2146
e126ba97
EC		 2147 if (err) {
2148 mlx5_ib_dbg(dev, "create qp failed\n");
2149 goto err_create;
2150 }
2151
479163f4 2152 kvfree(in);
e126ba97 2153
19098df2 2154 base->container_mibqp = qp;
2155 base->mqp.event = mlx5_ib_qp_event;
e126ba97 2156
89ea94a7
MG		 2157 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2158 &send_cq, &recv_cq);
2159 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2160 mlx5_ib_lock_cqs(send_cq, recv_cq);
2161 /* Maintain device to QPs access, needed for further handling via reset
2162 * flow
2163 */
2164 list_add_tail(&qp->qps_list, &dev->qp_list);
2165 /* Maintain CQ to QPs access, needed for further handling via reset flow
2166 */
2167 if (send_cq)
2168 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2169 if (recv_cq)
2170 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2171 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2172 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2173
e126ba97
EC		 2174 return 0;
2175
2176err_create:
2177 if (qp->create_type == MLX5_QP_USER)
b037c29a 2178 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 2179 else if (qp->create_type == MLX5_QP_KERNEL)
2180 destroy_qp_kernel(dev, qp);
2181
b1383aa6 2182err:
479163f4 2183 kvfree(in);
e126ba97
EC		 2184 return err;
2185}
2186
2187static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2188 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2189{
2190 if (send_cq) {
2191 if (recv_cq) {
2192 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2193 spin_lock(&send_cq->lock);
e126ba97
EC		 2194 spin_lock_nested(&recv_cq->lock,
2195 SINGLE_DEPTH_NESTING);
2196 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2197 spin_lock(&send_cq->lock);
e126ba97
EC		 2198 __acquire(&recv_cq->lock);
2199 } else {
89ea94a7 2200 spin_lock(&recv_cq->lock);
e126ba97
EC		 2201 spin_lock_nested(&send_cq->lock,
2202 SINGLE_DEPTH_NESTING);
2203 }
2204 } else {
89ea94a7 2205 spin_lock(&send_cq->lock);
6a4f139a 2206 __acquire(&recv_cq->lock);
e126ba97
EC		 2207 }
2208 } else if (recv_cq) {
89ea94a7 2209 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2210 __acquire(&send_cq->lock);
2211 } else {
2212 __acquire(&send_cq->lock);
2213 __acquire(&recv_cq->lock);
e126ba97
EC		 2214 }
2215}
2216
2217static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2218 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2219{
2220 if (send_cq) {
2221 if (recv_cq) {
2222 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2223 spin_unlock(&recv_cq->lock);
89ea94a7 2224 spin_unlock(&send_cq->lock);
e126ba97
EC		 2225 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2226 __release(&recv_cq->lock);
89ea94a7 2227 spin_unlock(&send_cq->lock);
e126ba97
EC		 2228 } else {
2229 spin_unlock(&send_cq->lock);
89ea94a7 2230 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2231 }
2232 } else {
6a4f139a 2233 __release(&recv_cq->lock);
89ea94a7 2234 spin_unlock(&send_cq->lock);
e126ba97
EC		 2235 }
2236 } else if (recv_cq) {
6a4f139a 2237 __release(&send_cq->lock);
89ea94a7 2238 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2239 } else {
2240 __release(&recv_cq->lock);
2241 __release(&send_cq->lock);
e126ba97
EC		 2242 }
2243}
2244
2245static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2246{
2247 return to_mpd(qp->ibqp.pd);
2248}
2249
89ea94a7
MG		 2250static void get_cqs(enum ib_qp_type qp_type,
2251 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2252 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2253{
89ea94a7 2254 switch (qp_type) {
e126ba97
EC		 2255 case IB_QPT_XRC_TGT:
2256 *send_cq = NULL;
2257 *recv_cq = NULL;
2258 break;
2259 case MLX5_IB_QPT_REG_UMR:
2260 case IB_QPT_XRC_INI:
89ea94a7 2261 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2262 *recv_cq = NULL;
2263 break;
2264
2265 case IB_QPT_SMI:
d16e91da 2266 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2267 case IB_QPT_RC:
2268 case IB_QPT_UC:
2269 case IB_QPT_UD:
2270 case IB_QPT_RAW_IPV6:
2271 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2272 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2273 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2274 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2275 break;
2276
e126ba97
EC		 2277 case IB_QPT_MAX:
2278 default:
2279 *send_cq = NULL;
2280 *recv_cq = NULL;
2281 break;
2282 }
2283}
2284
ad5f8e96 2285static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2286 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2287 u8 lag_tx_affinity);
ad5f8e96 2288
e126ba97
EC		 2289static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2290{
2291 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2292 struct mlx5_ib_qp_base *base;
89ea94a7 2293 unsigned long flags;
e126ba97
EC		 2294 int err;
2295
28d61370
YH		 2296 if (qp->ibqp.rwq_ind_tbl) {
2297 destroy_rss_raw_qp_tir(dev, qp);
2298 return;
2299 }
2300
c2e53b2c
YH		 2301 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2302 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2303 &qp->raw_packet_qp.rq.base :
2304 &qp->trans_qp.base;
2305
6aec21f6 2306 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2307 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2308 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2309 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2310 MLX5_CMD_OP_2RST_QP, 0,
2311 NULL, &base->mqp);
ad5f8e96 2312 } else {
0680efa2
AV		 2313 struct mlx5_modify_raw_qp_param raw_qp_param = {
2314 .operation = MLX5_CMD_OP_2RST_QP
2315 };
2316
13eab21f 2317 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2318 }
2319 if (err)
427c1e7b 2320 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2321 base->mqp.qpn);
6aec21f6 2322 }
e126ba97 2323
89ea94a7
MG		 2324 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2325 &send_cq, &recv_cq);
2326
2327 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2328 mlx5_ib_lock_cqs(send_cq, recv_cq);
2329 /* del from lists under both locks above to protect reset flow paths */
2330 list_del(&qp->qps_list);
2331 if (send_cq)
2332 list_del(&qp->cq_send_list);
2333
2334 if (recv_cq)
2335 list_del(&qp->cq_recv_list);
e126ba97
EC		 2336
2337 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2338 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2339 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2340 if (send_cq != recv_cq)
19098df2 2341 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2342 NULL);
e126ba97 2343 }
89ea94a7
MG		 2344 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2345 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2346
c2e53b2c
YH		 2347 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2348 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2349 destroy_raw_packet_qp(dev, qp);
2350 } else {
2351 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2352 if (err)
2353 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2354 base->mqp.qpn);
2355 }
e126ba97 2356
e126ba97
EC		 2357 if (qp->create_type == MLX5_QP_KERNEL)
2358 destroy_qp_kernel(dev, qp);
2359 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2360 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2361}
2362
2363static const char *ib_qp_type_str(enum ib_qp_type type)
2364{
2365 switch (type) {
2366 case IB_QPT_SMI:
2367 return "IB_QPT_SMI";
2368 case IB_QPT_GSI:
2369 return "IB_QPT_GSI";
2370 case IB_QPT_RC:
2371 return "IB_QPT_RC";
2372 case IB_QPT_UC:
2373 return "IB_QPT_UC";
2374 case IB_QPT_UD:
2375 return "IB_QPT_UD";
2376 case IB_QPT_RAW_IPV6:
2377 return "IB_QPT_RAW_IPV6";
2378 case IB_QPT_RAW_ETHERTYPE:
2379 return "IB_QPT_RAW_ETHERTYPE";
2380 case IB_QPT_XRC_INI:
2381 return "IB_QPT_XRC_INI";
2382 case IB_QPT_XRC_TGT:
2383 return "IB_QPT_XRC_TGT";
2384 case IB_QPT_RAW_PACKET:
2385 return "IB_QPT_RAW_PACKET";
2386 case MLX5_IB_QPT_REG_UMR:
2387 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2388 case IB_QPT_DRIVER:
2389 return "IB_QPT_DRIVER";
e126ba97
EC		 2390 case IB_QPT_MAX:
2391 default:
2392 return "Invalid QP type";
2393 }
2394}
2395
b4aaa1f0
MS		 2396static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2397 struct ib_qp_init_attr *attr,
2398 struct mlx5_ib_create_qp *ucmd)
2399{
b4aaa1f0
MS		 2400 struct mlx5_ib_qp *qp;
2401 int err = 0;
2402 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2403 void *dctc;
2404
2405 if (!attr->srq || !attr->recv_cq)
2406 return ERR_PTR(-EINVAL);
2407
b4aaa1f0
MS		 2408 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2409 ucmd, sizeof(*ucmd), &uidx);
2410 if (err)
2411 return ERR_PTR(err);
2412
2413 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2414 if (!qp)
2415 return ERR_PTR(-ENOMEM);
2416
2417 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2418 if (!qp->dct.in) {
2419 err = -ENOMEM;
2420 goto err_free;
2421 }
2422
a01a5860 2423 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2424 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2425 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2426 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2427 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2428 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2429 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2430 MLX5_SET(dctc, dctc, user_index, uidx);
2431
5d6ff1ba
YC		 2432 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2433 configure_responder_scat_cqe(attr, dctc);
2434
b4aaa1f0
MS		 2435 qp->state = IB_QPS_RESET;
2436
2437 return &qp->ibqp;
2438err_free:
2439 kfree(qp);
2440 return ERR_PTR(err);
2441}
2442
2443static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2444 struct ib_qp_init_attr *init_attr,
2445 struct mlx5_ib_create_qp *ucmd,
2446 struct ib_udata *udata)
2447{
2448 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2449 int err;
2450
2451 if (!udata)
2452 return -EINVAL;
2453
2454 if (udata->inlen < sizeof(*ucmd)) {
2455 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2456 return -EINVAL;
2457 }
2458 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2459 if (err)
2460 return err;
2461
2462 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2463 init_attr->qp_type = MLX5_IB_QPT_DCI;
2464 } else {
2465 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2466 init_attr->qp_type = MLX5_IB_QPT_DCT;
2467 } else {
2468 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2469 return -EINVAL;
2470 }
2471 }
2472
2473 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2474 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2475 return -EOPNOTSUPP;
2476 }
2477
2478 return 0;
2479}
2480
e126ba97 2481struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2482 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2483 struct ib_udata *udata)
2484{
2485 struct mlx5_ib_dev *dev;
2486 struct mlx5_ib_qp *qp;
2487 u16 xrcdn = 0;
2488 int err;
b4aaa1f0
MS		 2489 struct ib_qp_init_attr mlx_init_attr;
2490 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2491
2492 if (pd) {
2493 dev = to_mdev(pd->device);
0fb2ed66 2494
2495 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2496 if (!pd->uobject) {
2497 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2498 return ERR_PTR(-EINVAL);
2499 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2500 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2501 return ERR_PTR(-EINVAL);
2502 }
2503 }
09f16cf5
MD		 2504 } else {
2505 /* being cautious here */
2506 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2507 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2508 pr_warn("%s: no PD for transport %s\n", __func__,
2509 ib_qp_type_str(init_attr->qp_type));
2510 return ERR_PTR(-EINVAL);
2511 }
2512 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2513 }
2514
b4aaa1f0
MS		 2515 if (init_attr->qp_type == IB_QPT_DRIVER) {
2516 struct mlx5_ib_create_qp ucmd;
2517
2518 init_attr = &mlx_init_attr;
2519 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2520 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2521 if (err)
2522 return ERR_PTR(err);
c32a4f29
MS		 2523
2524 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2525 if (init_attr->cap.max_recv_wr ||
2526 init_attr->cap.max_recv_sge) {
2527 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2528 return ERR_PTR(-EINVAL);
2529 }
776a3906
MS		 2530 } else {
2531 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2532 }
b4aaa1f0
MS		 2533 }
2534
e126ba97
EC		 2535 switch (init_attr->qp_type) {
2536 case IB_QPT_XRC_TGT:
2537 case IB_QPT_XRC_INI:
938fe83c 2538 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2539 mlx5_ib_dbg(dev, "XRC not supported\n");
2540 return ERR_PTR(-ENOSYS);
2541 }
2542 init_attr->recv_cq = NULL;
2543 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2544 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2545 init_attr->send_cq = NULL;
2546 }
2547
2548 /* fall through */
0fb2ed66 2549 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2550 case IB_QPT_RC:
2551 case IB_QPT_UC:
2552 case IB_QPT_UD:
2553 case IB_QPT_SMI:
d16e91da 2554 case MLX5_IB_QPT_HW_GSI:
e126ba97 2555 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2556 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2557 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2558 if (!qp)
2559 return ERR_PTR(-ENOMEM);
2560
2561 err = create_qp_common(dev, pd, init_attr, udata, qp);
2562 if (err) {
2563 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2564 kfree(qp);
2565 return ERR_PTR(err);
2566 }
2567
2568 if (is_qp0(init_attr->qp_type))
2569 qp->ibqp.qp_num = 0;
2570 else if (is_qp1(init_attr->qp_type))
2571 qp->ibqp.qp_num = 1;
2572 else
19098df2 2573 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2574
2575 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2576 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2577 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2578 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2579
19098df2 2580 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2581
2582 break;
2583
d16e91da
HE		 2584 case IB_QPT_GSI:
2585 return mlx5_ib_gsi_create_qp(pd, init_attr);
2586
e126ba97
EC		 2587 case IB_QPT_RAW_IPV6:
2588 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2589 case IB_QPT_MAX:
2590 default:
2591 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2592 init_attr->qp_type);
2593 /* Don't support raw QPs */
2594 return ERR_PTR(-EINVAL);
2595 }
2596
b4aaa1f0
MS		 2597 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2598 qp->qp_sub_type = init_attr->qp_type;
2599
e126ba97
EC		 2600 return &qp->ibqp;
2601}
2602
776a3906
MS		 2603static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2604{
2605 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2606
2607 if (mqp->state == IB_QPS_RTR) {
2608 int err;
2609
2610 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2611 if (err) {
2612 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2613 return err;
2614 }
2615 }
2616
2617 kfree(mqp->dct.in);
2618 kfree(mqp);
2619 return 0;
2620}
2621
e126ba97
EC		 2622int mlx5_ib_destroy_qp(struct ib_qp *qp)
2623{
2624 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2625 struct mlx5_ib_qp *mqp = to_mqp(qp);
2626
d16e91da
HE		 2627 if (unlikely(qp->qp_type == IB_QPT_GSI))
2628 return mlx5_ib_gsi_destroy_qp(qp);
2629
776a3906
MS		 2630 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2631 return mlx5_ib_destroy_dct(mqp);
2632
e126ba97
EC		 2633 destroy_qp_common(dev, mqp);
2634
2635 kfree(mqp);
2636
2637 return 0;
2638}
2639
a60109dc
YC		 2640static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2641 const struct ib_qp_attr *attr,
2642 int attr_mask, __be32 *hw_access_flags)
e126ba97 2643{
e126ba97
EC		 2644 u8 dest_rd_atomic;
2645 u32 access_flags;
2646
a60109dc
YC		 2647 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2648
e126ba97
EC		 2649 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2650 dest_rd_atomic = attr->max_dest_rd_atomic;
2651 else
19098df2 2652 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2653
2654 if (attr_mask & IB_QP_ACCESS_FLAGS)
2655 access_flags = attr->qp_access_flags;
2656 else
19098df2 2657 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2658
2659 if (!dest_rd_atomic)
2660 access_flags &= IB_ACCESS_REMOTE_WRITE;
2661
2662 if (access_flags & IB_ACCESS_REMOTE_READ)
a60109dc
YC		 2663 *hw_access_flags |= MLX5_QP_BIT_RRE;
2664 if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
2665 qp->ibqp.qp_type == IB_QPT_RC) {
2666 int atomic_mode;
2667
2668 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2669 if (atomic_mode < 0)
2670 return -EOPNOTSUPP;
2671
2672 *hw_access_flags |= MLX5_QP_BIT_RAE;
2673 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2674 }
2675
e126ba97 2676 if (access_flags & IB_ACCESS_REMOTE_WRITE)
a60109dc
YC		 2677 *hw_access_flags |= MLX5_QP_BIT_RWE;
2678
2679 *hw_access_flags = cpu_to_be32(*hw_access_flags);
e126ba97 2680
a60109dc 2681 return 0;
e126ba97
EC		 2682}
2683
2684enum {
2685 MLX5_PATH_FLAG_FL = 1 << 0,
2686 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2687 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2688};
2689
2690static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2691{
4f32ac2e 2692 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 2693 return 0;
4f32ac2e
DG		 2694
2695 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
e126ba97 2696 return -EINVAL;
e126ba97 2697
4f32ac2e
DG		 2698 while (rate != IB_RATE_PORT_CURRENT &&
2699 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2700 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2701 --rate;
2702
2703 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 2704}
2705
75850d0b 2706static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2707 struct mlx5_ib_sq *sq, u8 sl,
2708 struct ib_pd *pd)
75850d0b 2709{
2710 void *in;
2711 void *tisc;
2712 int inlen;
2713 int err;
2714
2715 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2716 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2717 if (!in)
2718 return -ENOMEM;
2719
2720 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 2721 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 2722
2723 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2724 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2725
2726 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2727
2728 kvfree(in);
2729
2730 return err;
2731}
2732
13eab21f 2733static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 2734 struct mlx5_ib_sq *sq, u8 tx_affinity,
2735 struct ib_pd *pd)
13eab21f
AH		 2736{
2737 void *in;
2738 void *tisc;
2739 int inlen;
2740 int err;
2741
2742 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2743 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2744 if (!in)
2745 return -ENOMEM;
2746
2747 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 2748 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 2749
2750 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2751 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2752
2753 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2754
2755 kvfree(in);
2756
2757 return err;
2758}
2759
75850d0b 2760static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2761 const struct rdma_ah_attr *ah,
e126ba97 2762 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2763 u32 path_flags, const struct ib_qp_attr *attr,
2764 bool alt)
e126ba97 2765{
d8966fcd 2766 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2767 int err;
ed88451e 2768 enum ib_gid_type gid_type;
d8966fcd
DC		 2769 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2770 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2771
e126ba97 2772 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2773 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2774 attr->pkey_index);
e126ba97 2775
d8966fcd
DC		 2776 if (ah_flags & IB_AH_GRH) {
2777 if (grh->sgid_index >=
938fe83c 2778 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2779 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2780 grh->sgid_index,
938fe83c 2781 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2782 return -EINVAL;
2783 }
2811ba51 2784 }
44c58487
DC		 2785
2786 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2787 if (!(ah_flags & IB_AH_GRH))
2811ba51 2788 return -EINVAL;
47ec3866 2789
44c58487 2790 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2791 if (qp->ibqp.qp_type == IB_QPT_RC ||
2792 qp->ibqp.qp_type == IB_QPT_UC ||
2793 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2794 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
47ec3866
PP		 2795 path->udp_sport =
2796 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
d8966fcd 2797 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
47ec3866 2798 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 2799 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2800 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2801 } else {
d3ae2bde
NO		 2802 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2803 path->fl_free_ar |=
2804 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2805 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2806 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2807 if (ah_flags & IB_AH_GRH)
2811ba51 2808 path->grh_mlid |= 1 << 7;
d8966fcd 2809 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2810 }
2811
d8966fcd
DC		 2812 if (ah_flags & IB_AH_GRH) {
2813 path->mgid_index = grh->sgid_index;
2814 path->hop_limit = grh->hop_limit;
e126ba97 2815 path->tclass_flowlabel =
d8966fcd
DC		 2816 cpu_to_be32((grh->traffic_class << 20) |
2817 (grh->flow_label));
2818 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2819 }
2820
d8966fcd 2821 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2822 if (err < 0)
2823 return err;
2824 path->static_rate = err;
2825 path->port = port;
2826
e126ba97 2827 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2828 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2829
75850d0b 2830 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2831 return modify_raw_packet_eth_prio(dev->mdev,
2832 &qp->raw_packet_qp.sq,
1cd6dbd3 2833 sl & 0xf, qp->ibqp.pd);
75850d0b 2834
e126ba97
EC		 2835 return 0;
2836}
2837
2838static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2839 [MLX5_QP_STATE_INIT] = {
2840 [MLX5_QP_STATE_INIT] = {
2841 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2842 MLX5_QP_OPTPAR_RAE |
2843 MLX5_QP_OPTPAR_RWE |
2844 MLX5_QP_OPTPAR_PKEY_INDEX |
2845 MLX5_QP_OPTPAR_PRI_PORT,
2846 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2847 MLX5_QP_OPTPAR_PKEY_INDEX |
2848 MLX5_QP_OPTPAR_PRI_PORT,
2849 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2850 MLX5_QP_OPTPAR_Q_KEY |
2851 MLX5_QP_OPTPAR_PRI_PORT,
2852 },
2853 [MLX5_QP_STATE_RTR] = {
2854 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2855 MLX5_QP_OPTPAR_RRE |
2856 MLX5_QP_OPTPAR_RAE |
2857 MLX5_QP_OPTPAR_RWE |
2858 MLX5_QP_OPTPAR_PKEY_INDEX,
2859 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2860 MLX5_QP_OPTPAR_RWE |
2861 MLX5_QP_OPTPAR_PKEY_INDEX,
2862 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2863 MLX5_QP_OPTPAR_Q_KEY,
2864 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2865 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2866 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2867 MLX5_QP_OPTPAR_RRE |
2868 MLX5_QP_OPTPAR_RAE |
2869 MLX5_QP_OPTPAR_RWE |
2870 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2871 },
2872 },
2873 [MLX5_QP_STATE_RTR] = {
2874 [MLX5_QP_STATE_RTS] = {
2875 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2876 MLX5_QP_OPTPAR_RRE |
2877 MLX5_QP_OPTPAR_RAE |
2878 MLX5_QP_OPTPAR_RWE |
2879 MLX5_QP_OPTPAR_PM_STATE |
2880 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2881 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2882 MLX5_QP_OPTPAR_RWE |
2883 MLX5_QP_OPTPAR_PM_STATE,
2884 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2885 },
2886 },
2887 [MLX5_QP_STATE_RTS] = {
2888 [MLX5_QP_STATE_RTS] = {
2889 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2890 MLX5_QP_OPTPAR_RAE |
2891 MLX5_QP_OPTPAR_RWE |
2892 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2893 MLX5_QP_OPTPAR_PM_STATE |
2894 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2895 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2896 MLX5_QP_OPTPAR_PM_STATE |
2897 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2898 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2899 MLX5_QP_OPTPAR_SRQN |
2900 MLX5_QP_OPTPAR_CQN_RCV,
2901 },
2902 },
2903 [MLX5_QP_STATE_SQER] = {
2904 [MLX5_QP_STATE_RTS] = {
2905 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2906 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2907 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2908 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2909 MLX5_QP_OPTPAR_RWE |
2910 MLX5_QP_OPTPAR_RAE |
2911 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2912 },
2913 },
2914};
2915
2916static int ib_nr_to_mlx5_nr(int ib_mask)
2917{
2918 switch (ib_mask) {
2919 case IB_QP_STATE:
2920 return 0;
2921 case IB_QP_CUR_STATE:
2922 return 0;
2923 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2924 return 0;
2925 case IB_QP_ACCESS_FLAGS:
2926 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2927 MLX5_QP_OPTPAR_RAE;
2928 case IB_QP_PKEY_INDEX:
2929 return MLX5_QP_OPTPAR_PKEY_INDEX;
2930 case IB_QP_PORT:
2931 return MLX5_QP_OPTPAR_PRI_PORT;
2932 case IB_QP_QKEY:
2933 return MLX5_QP_OPTPAR_Q_KEY;
2934 case IB_QP_AV:
2935 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2936 MLX5_QP_OPTPAR_PRI_PORT;
2937 case IB_QP_PATH_MTU:
2938 return 0;
2939 case IB_QP_TIMEOUT:
2940 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2941 case IB_QP_RETRY_CNT:
2942 return MLX5_QP_OPTPAR_RETRY_COUNT;
2943 case IB_QP_RNR_RETRY:
2944 return MLX5_QP_OPTPAR_RNR_RETRY;
2945 case IB_QP_RQ_PSN:
2946 return 0;
2947 case IB_QP_MAX_QP_RD_ATOMIC:
2948 return MLX5_QP_OPTPAR_SRA_MAX;
2949 case IB_QP_ALT_PATH:
2950 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2951 case IB_QP_MIN_RNR_TIMER:
2952 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2953 case IB_QP_SQ_PSN:
2954 return 0;
2955 case IB_QP_MAX_DEST_RD_ATOMIC:
2956 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2957 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2958 case IB_QP_PATH_MIG_STATE:
2959 return MLX5_QP_OPTPAR_PM_STATE;
2960 case IB_QP_CAP:
2961 return 0;
2962 case IB_QP_DEST_QPN:
2963 return 0;
2964 }
2965 return 0;
2966}
2967
2968static int ib_mask_to_mlx5_opt(int ib_mask)
2969{
2970 int result = 0;
2971 int i;
2972
2973 for (i = 0; i < 8 * sizeof(int); i++) {
2974 if ((1 << i) & ib_mask)
2975 result |= ib_nr_to_mlx5_nr(1 << i);
2976 }
2977
2978 return result;
2979}
2980
34d57585
YH		 2981static int modify_raw_packet_qp_rq(
2982 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2983 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 2984{
2985 void *in;
2986 void *rqc;
2987 int inlen;
2988 int err;
2989
2990 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2991 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2992 if (!in)
2993 return -ENOMEM;
2994
2995 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 2996 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 2997
2998 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2999 MLX5_SET(rqc, rqc, state, new_state);
3000
eb49ab0c
AV		 3001 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3002 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3003 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 3004 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 3005 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3006 } else
5a738b5d
JG		 3007 dev_info_once(
3008 &dev->ib_dev.dev,
3009 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 3010 }
3011
3012 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 3013 if (err)
3014 goto out;
3015
3016 rq->state = new_state;
3017
3018out:
3019 kvfree(in);
3020 return err;
3021}
3022
c14003f0
YH		 3023static int modify_raw_packet_qp_sq(
3024 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3025 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3026{
7d29f349 3027 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 3028 struct mlx5_rate_limit old_rl = ibqp->rl;
3029 struct mlx5_rate_limit new_rl = old_rl;
3030 bool new_rate_added = false;
7d29f349 3031 u16 rl_index = 0;
ad5f8e96 3032 void *in;
3033 void *sqc;
3034 int inlen;
3035 int err;
3036
3037 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 3038 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3039 if (!in)
3040 return -ENOMEM;
3041
c14003f0 3042 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3043 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3044
3045 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3046 MLX5_SET(sqc, sqc, state, new_state);
3047
7d29f349
BW		 3048 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3049 if (new_state != MLX5_SQC_STATE_RDY)
3050 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3051 __func__);
3052 else
61147f39 3053 new_rl = raw_qp_param->rl;
7d29f349
BW		 3054 }
3055
61147f39
BW		 3056 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3057 if (new_rl.rate) {
3058 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 3059 if (err) {
61147f39
BW		 3060 pr_err("Failed configuring rate limit(err %d): \
3061 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3062 err, new_rl.rate, new_rl.max_burst_sz,
3063 new_rl.typical_pkt_sz);
3064
7d29f349
BW		 3065 goto out;
3066 }
61147f39 3067 new_rate_added = true;
7d29f349
BW		 3068 }
3069
3070 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 3071 /* index 0 means no limit */
7d29f349
BW		 3072 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3073 }
3074
ad5f8e96 3075 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 3076 if (err) {
3077 /* Remove new rate from table if failed */
61147f39
BW		 3078 if (new_rate_added)
3079 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 3080 goto out;
7d29f349
BW		 3081 }
3082
3083 /* Only remove the old rate after new rate was set */
61147f39
BW		 3084 if ((old_rl.rate &&
3085 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
7d29f349 3086 (new_state != MLX5_SQC_STATE_RDY))
61147f39 3087 mlx5_rl_remove_rate(dev, &old_rl);
ad5f8e96 3088
61147f39 3089 ibqp->rl = new_rl;
ad5f8e96 3090 sq->state = new_state;
3091
3092out:
3093 kvfree(in);
3094 return err;
3095}
3096
3097static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 3098 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3099 u8 tx_affinity)
ad5f8e96 3100{
3101 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3102 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3103 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 3104 int modify_rq = !!qp->rq.wqe_cnt;
3105 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 3106 int rq_state;
3107 int sq_state;
3108 int err;
3109
0680efa2 3110 switch (raw_qp_param->operation) {
ad5f8e96 3111 case MLX5_CMD_OP_RST2INIT_QP:
3112 rq_state = MLX5_RQC_STATE_RDY;
3113 sq_state = MLX5_SQC_STATE_RDY;
3114 break;
3115 case MLX5_CMD_OP_2ERR_QP:
3116 rq_state = MLX5_RQC_STATE_ERR;
3117 sq_state = MLX5_SQC_STATE_ERR;
3118 break;
3119 case MLX5_CMD_OP_2RST_QP:
3120 rq_state = MLX5_RQC_STATE_RST;
3121 sq_state = MLX5_SQC_STATE_RST;
3122 break;
ad5f8e96 3123 case MLX5_CMD_OP_RTR2RTS_QP:
3124 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 3125 if (raw_qp_param->set_mask ==
3126 MLX5_RAW_QP_RATE_LIMIT) {
3127 modify_rq = 0;
3128 sq_state = sq->state;
3129 } else {
3130 return raw_qp_param->set_mask ? -EINVAL : 0;
3131 }
3132 break;
3133 case MLX5_CMD_OP_INIT2INIT_QP:
3134 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 3135 if (raw_qp_param->set_mask)
3136 return -EINVAL;
3137 else
3138 return 0;
ad5f8e96 3139 default:
3140 WARN_ON(1);
3141 return -EINVAL;
3142 }
3143
7d29f349 3144 if (modify_rq) {
34d57585
YH		 3145 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3146 qp->ibqp.pd);
ad5f8e96 3147 if (err)
3148 return err;
3149 }
3150
7d29f349 3151 if (modify_sq) {
13eab21f
AH		 3152 if (tx_affinity) {
3153 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3154 tx_affinity,
3155 qp->ibqp.pd);
13eab21f
AH		 3156 if (err)
3157 return err;
3158 }
3159
c14003f0
YH		 3160 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3161 raw_qp_param, qp->ibqp.pd);
13eab21f 3162 }
ad5f8e96 3163
3164 return 0;
3165}
3166
c6a21c38
MD		 3167static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3168 struct mlx5_ib_pd *pd,
3169 struct mlx5_ib_qp_base *qp_base,
3170 u8 port_num)
3171{
3172 struct mlx5_ib_ucontext *ucontext = NULL;
3173 unsigned int tx_port_affinity;
3174
3175 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3176 ucontext = to_mucontext(pd->ibpd.uobject->context);
3177
3178 if (ucontext) {
3179 tx_port_affinity = (unsigned int)atomic_add_return(
3180 1, &ucontext->tx_port_affinity) %
3181 MLX5_MAX_PORTS +
3182 1;
3183 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3184 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3185 } else {
3186 tx_port_affinity =
3187 (unsigned int)atomic_add_return(
3188 1, &dev->roce[port_num].tx_port_affinity) %
3189 MLX5_MAX_PORTS +
3190 1;
3191 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3192 tx_port_affinity, qp_base->mqp.qpn);
3193 }
3194
3195 return tx_port_affinity;
3196}
3197
e126ba97
EC		 3198static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3199 const struct ib_qp_attr *attr, int attr_mask,
61147f39
BW		 3200 enum ib_qp_state cur_state, enum ib_qp_state new_state,
3201 const struct mlx5_ib_modify_qp *ucmd)
e126ba97 3202{
427c1e7b 3203 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3204 [MLX5_QP_STATE_RST] = {
3205 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3206 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3207 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3208 },
3209 [MLX5_QP_STATE_INIT] = {
3210 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3211 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3212 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3213 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3214 },
3215 [MLX5_QP_STATE_RTR] = {
3216 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3217 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3218 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3219 },
3220 [MLX5_QP_STATE_RTS] = {
3221 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3222 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3223 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3224 },
3225 [MLX5_QP_STATE_SQD] = {
3226 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3227 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3228 },
3229 [MLX5_QP_STATE_SQER] = {
3230 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3231 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3232 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3233 },
3234 [MLX5_QP_STATE_ERR] = {
3235 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3236 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3237 }
3238 };
3239
e126ba97
EC		 3240 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3241 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3242 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 3243 struct mlx5_ib_cq *send_cq, *recv_cq;
3244 struct mlx5_qp_context *context;
e126ba97 3245 struct mlx5_ib_pd *pd;
eb49ab0c 3246 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 3247 enum mlx5_qp_state mlx5_cur, mlx5_new;
3248 enum mlx5_qp_optpar optpar;
e126ba97
EC		 3249 int mlx5_st;
3250 int err;
427c1e7b 3251 u16 op;
13eab21f 3252 u8 tx_affinity = 0;
e126ba97 3253
55de9a77
LR		 3254 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3255 qp->qp_sub_type : ibqp->qp_type);
3256 if (mlx5_st < 0)
3257 return -EINVAL;
3258
1a412fb1
SM		 3259 context = kzalloc(sizeof(*context), GFP_KERNEL);
3260 if (!context)
e126ba97
EC		 3261 return -ENOMEM;
3262
c6a21c38 3263 pd = get_pd(qp);
55de9a77 3264 context->flags = cpu_to_be32(mlx5_st << 16);
e126ba97
EC		 3265
3266 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3267 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3268 } else {
3269 switch (attr->path_mig_state) {
3270 case IB_MIG_MIGRATED:
3271 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3272 break;
3273 case IB_MIG_REARM:
3274 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3275 break;
3276 case IB_MIG_ARMED:
3277 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3278 break;
3279 }
3280 }
3281
13eab21f
AH		 3282 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3283 if ((ibqp->qp_type == IB_QPT_RC) ||
3284 (ibqp->qp_type == IB_QPT_UD &&
3285 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3286 (ibqp->qp_type == IB_QPT_UC) ||
3287 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3288 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3289 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3290 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 3291 u8 p = mlx5_core_native_port_num(dev->mdev);
c6a21c38 3292 tx_affinity = get_tx_affinity(dev, pd, base, p);
13eab21f
AH		 3293 context->flags |= cpu_to_be32(tx_affinity << 24);
3294 }
3295 }
3296 }
3297
d16e91da 3298 if (is_sqp(ibqp->qp_type)) {
e126ba97 3299 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 3300 } else if ((ibqp->qp_type == IB_QPT_UD &&
3301 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 3302 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3303 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3304 } else if (attr_mask & IB_QP_PATH_MTU) {
3305 if (attr->path_mtu < IB_MTU_256 ||
3306 attr->path_mtu > IB_MTU_4096) {
3307 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3308 err = -EINVAL;
3309 goto out;
3310 }
938fe83c
SM		 3311 context->mtu_msgmax = (attr->path_mtu << 5) |
3312 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3313 }
3314
3315 if (attr_mask & IB_QP_DEST_QPN)
3316 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3317
3318 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3319 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3320
3321 /* todo implement counter_index functionality */
3322
3323 if (is_sqp(ibqp->qp_type))
3324 context->pri_path.port = qp->port;
3325
3326 if (attr_mask & IB_QP_PORT)
3327 context->pri_path.port = attr->port_num;
3328
3329 if (attr_mask & IB_QP_AV) {
75850d0b 3330 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3331 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3332 attr_mask, 0, attr, false);
e126ba97
EC		 3333 if (err)
3334 goto out;
3335 }
3336
3337 if (attr_mask & IB_QP_TIMEOUT)
3338 context->pri_path.ackto_lt |= attr->timeout << 3;
3339
3340 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3341 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3342 &context->alt_path,
f879ee8d
AS		 3343 attr->alt_port_num,
3344 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3345 0, attr, true);
e126ba97
EC		 3346 if (err)
3347 goto out;
3348 }
3349
89ea94a7
MG		 3350 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3351 &send_cq, &recv_cq);
e126ba97
EC		 3352
3353 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3354 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3355 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3356 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3357
3358 if (attr_mask & IB_QP_RNR_RETRY)
3359 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3360
3361 if (attr_mask & IB_QP_RETRY_CNT)
3362 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3363
3364 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3365 if (attr->max_rd_atomic)
3366 context->params1 |=
3367 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3368 }
3369
3370 if (attr_mask & IB_QP_SQ_PSN)
3371 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3372
3373 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3374 if (attr->max_dest_rd_atomic)
3375 context->params2 |=
3376 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3377 }
3378
a60109dc
YC		 3379 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3380 __be32 access_flags = 0;
3381
3382 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3383 if (err)
3384 goto out;
3385
3386 context->params2 |= access_flags;
3387 }
e126ba97
EC		 3388
3389 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3390 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3391
3392 if (attr_mask & IB_QP_RQ_PSN)
3393 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3394
3395 if (attr_mask & IB_QP_QKEY)
3396 context->qkey = cpu_to_be32(attr->qkey);
3397
3398 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3399 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3400
0837e86a
MB		 3401 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3402 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3403 qp->port) - 1;
c2e53b2c
YH		 3404
3405 /* Underlay port should be used - index 0 function per port */
3406 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3407 port_num = 0;
3408
eb49ab0c 3409 mibport = &dev->port[port_num];
0837e86a 3410 context->qp_counter_set_usr_page |=
e1f24a79 3411 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3412 }
3413
e126ba97
EC		 3414 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3415 context->sq_crq_size |= cpu_to_be16(1 << 4);
3416
b11a4f9c
HE		 3417 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3418 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3419
3420 mlx5_cur = to_mlx5_state(cur_state);
3421 mlx5_new = to_mlx5_state(new_state);
e126ba97 3422
427c1e7b 3423 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3424 !optab[mlx5_cur][mlx5_new]) {
3425 err = -EINVAL;
427c1e7b 3426 goto out;
5d414b17 3427 }
427c1e7b 3428
3429 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3430 optpar = ib_mask_to_mlx5_opt(attr_mask);
3431 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3432
c2e53b2c
YH		 3433 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3434 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3435 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3436
3437 raw_qp_param.operation = op;
eb49ab0c 3438 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3439 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3440 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3441 }
7d29f349
BW		 3442
3443 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3444 raw_qp_param.rl.rate = attr->rate_limit;
3445
3446 if (ucmd->burst_info.max_burst_sz) {
3447 if (attr->rate_limit &&
3448 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3449 raw_qp_param.rl.max_burst_sz =
3450 ucmd->burst_info.max_burst_sz;
3451 } else {
3452 err = -EINVAL;
3453 goto out;
3454 }
3455 }
3456
3457 if (ucmd->burst_info.typical_pkt_sz) {
3458 if (attr->rate_limit &&
3459 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3460 raw_qp_param.rl.typical_pkt_sz =
3461 ucmd->burst_info.typical_pkt_sz;
3462 } else {
3463 err = -EINVAL;
3464 goto out;
3465 }
3466 }
3467
7d29f349
BW		 3468 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3469 }
3470
13eab21f 3471 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3472 } else {
1a412fb1 3473 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3474 &base->mqp);
0680efa2
AV		 3475 }
3476
e126ba97
EC		 3477 if (err)
3478 goto out;
3479
3480 qp->state = new_state;
3481
3482 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3483 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3484 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3485 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3486 if (attr_mask & IB_QP_PORT)
3487 qp->port = attr->port_num;
3488 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3489 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3490
3491 /*
3492 * If we moved a kernel QP to RESET, clean up all old CQ
3493 * entries and reinitialize the QP.
3494 */
75a45982
LR		 3495 if (new_state == IB_QPS_RESET &&
3496 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 3497 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3498 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3499 if (send_cq != recv_cq)
19098df2 3500 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3501
3502 qp->rq.head = 0;
3503 qp->rq.tail = 0;
3504 qp->sq.head = 0;
3505 qp->sq.tail = 0;
3506 qp->sq.cur_post = 0;
34f4c955
GL		 3507 if (qp->sq.wqe_cnt)
3508 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
e126ba97
EC		 3509 qp->sq.last_poll = 0;
3510 qp->db.db[MLX5_RCV_DBR] = 0;
3511 qp->db.db[MLX5_SND_DBR] = 0;
3512 }
3513
3514out:
1a412fb1 3515 kfree(context);
e126ba97
EC		 3516 return err;
3517}
3518
c32a4f29
MS		 3519static inline bool is_valid_mask(int mask, int req, int opt)
3520{
3521 if ((mask & req) != req)
3522 return false;
3523
3524 if (mask & ~(req | opt))
3525 return false;
3526
3527 return true;
3528}
3529
3530/* check valid transition for driver QP types
3531 * for now the only QP type that this function supports is DCI
3532 */
3533static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3534 enum ib_qp_attr_mask attr_mask)
3535{
3536 int req = IB_QP_STATE;
3537 int opt = 0;
3538
99ed748e
MS		 3539 if (new_state == IB_QPS_RESET) {
3540 return is_valid_mask(attr_mask, req, opt);
3541 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 3542 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3543 return is_valid_mask(attr_mask, req, opt);
3544 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3545 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3546 return is_valid_mask(attr_mask, req, opt);
3547 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3548 req |= IB_QP_PATH_MTU;
5ec0304c 3549 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
c32a4f29
MS		 3550 return is_valid_mask(attr_mask, req, opt);
3551 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3552 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3553 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3554 opt = IB_QP_MIN_RNR_TIMER;
3555 return is_valid_mask(attr_mask, req, opt);
3556 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3557 opt = IB_QP_MIN_RNR_TIMER;
3558 return is_valid_mask(attr_mask, req, opt);
3559 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3560 return is_valid_mask(attr_mask, req, opt);
3561 }
3562 return false;
3563}
3564
776a3906
MS		 3565/* mlx5_ib_modify_dct: modify a DCT QP
3566 * valid transitions are:
3567 * RESET to INIT: must set access_flags, pkey_index and port
3568 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3569 * mtu, gid_index and hop_limit
3570 * Other transitions and attributes are illegal
3571 */
3572static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3573 int attr_mask, struct ib_udata *udata)
3574{
3575 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3576 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3577 enum ib_qp_state cur_state, new_state;
3578 int err = 0;
3579 int required = IB_QP_STATE;
3580 void *dctc;
3581
3582 if (!(attr_mask & IB_QP_STATE))
3583 return -EINVAL;
3584
3585 cur_state = qp->state;
3586 new_state = attr->qp_state;
3587
3588 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3589 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3590 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3591 if (!is_valid_mask(attr_mask, required, 0))
3592 return -EINVAL;
3593
3594 if (attr->port_num == 0 ||
3595 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3596 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3597 attr->port_num, dev->num_ports);
3598 return -EINVAL;
3599 }
3600 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3601 MLX5_SET(dctc, dctc, rre, 1);
3602 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3603 MLX5_SET(dctc, dctc, rwe, 1);
3604 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 3605 int atomic_mode;
3606
3607 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3608 if (atomic_mode < 0)
776a3906 3609 return -EOPNOTSUPP;
a60109dc
YC		 3610
3611 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
776a3906 3612 MLX5_SET(dctc, dctc, rae, 1);
776a3906
MS		 3613 }
3614 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3615 MLX5_SET(dctc, dctc, port, attr->port_num);
3616 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3617
3618 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3619 struct mlx5_ib_modify_qp_resp resp = {};
3620 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3621 sizeof(resp.dctn);
3622
3623 if (udata->outlen < min_resp_len)
3624 return -EINVAL;
3625 resp.response_length = min_resp_len;
3626
3627 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3628 if (!is_valid_mask(attr_mask, required, 0))
3629 return -EINVAL;
3630 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3631 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3632 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3633 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3634 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3635 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3636
3637 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3638 MLX5_ST_SZ_BYTES(create_dct_in));
3639 if (err)
3640 return err;
3641 resp.dctn = qp->dct.mdct.mqp.qpn;
3642 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3643 if (err) {
3644 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3645 return err;
3646 }
3647 } else {
3648 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3649 return -EINVAL;
3650 }
3651 if (err)
3652 qp->state = IB_QPS_ERR;
3653 else
3654 qp->state = new_state;
3655 return err;
3656}
3657
e126ba97
EC		 3658int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3659 int attr_mask, struct ib_udata *udata)
3660{
3661 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3662 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 3663 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 3664 enum ib_qp_type qp_type;
e126ba97 3665 enum ib_qp_state cur_state, new_state;
61147f39 3666 size_t required_cmd_sz;
e126ba97
EC		 3667 int err = -EINVAL;
3668 int port;
3669
28d61370
YH		 3670 if (ibqp->rwq_ind_tbl)
3671 return -ENOSYS;
3672
61147f39
BW		 3673 if (udata && udata->inlen) {
3674 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3675 sizeof(ucmd.reserved);
3676 if (udata->inlen < required_cmd_sz)
3677 return -EINVAL;
3678
3679 if (udata->inlen > sizeof(ucmd) &&
3680 !ib_is_udata_cleared(udata, sizeof(ucmd),
3681 udata->inlen - sizeof(ucmd)))
3682 return -EOPNOTSUPP;
3683
3684 if (ib_copy_from_udata(&ucmd, udata,
3685 min(udata->inlen, sizeof(ucmd))))
3686 return -EFAULT;
3687
3688 if (ucmd.comp_mask ||
3689 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3690 memchr_inv(&ucmd.burst_info.reserved, 0,
3691 sizeof(ucmd.burst_info.reserved)))
3692 return -EOPNOTSUPP;
3693 }
3694
d16e91da
HE		 3695 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3696 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3697
c32a4f29
MS		 3698 if (ibqp->qp_type == IB_QPT_DRIVER)
3699 qp_type = qp->qp_sub_type;
3700 else
3701 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3702 IB_QPT_GSI : ibqp->qp_type;
3703
776a3906
MS		 3704 if (qp_type == MLX5_IB_QPT_DCT)
3705 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3706
e126ba97
EC		 3707 mutex_lock(&qp->mutex);
3708
3709 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3710 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3711
2811ba51
AS		 3712 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3713 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2811ba51
AS		 3714 }
3715
c2e53b2c
YH		 3716 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3717 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3718 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3719 attr_mask);
3720 goto out;
3721 }
3722 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29 3723 qp_type != MLX5_IB_QPT_DCI &&
d31131bb
KH		 3724 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3725 attr_mask)) {
158abf86
HE		 3726 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3727 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3728 goto out;
c32a4f29
MS		 3729 } else if (qp_type == MLX5_IB_QPT_DCI &&
3730 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3731 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3732 cur_state, new_state, qp_type, attr_mask);
3733 goto out;
158abf86 3734 }
e126ba97
EC		 3735
3736 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3737 (attr->port_num == 0 ||
508562d6 3738 attr->port_num > dev->num_ports)) {
158abf86
HE		 3739 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3740 attr->port_num, dev->num_ports);
e126ba97 3741 goto out;
158abf86 3742 }
e126ba97
EC		 3743
3744 if (attr_mask & IB_QP_PKEY_INDEX) {
3745 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3746 if (attr->pkey_index >=
158abf86
HE		 3747 dev->mdev->port_caps[port - 1].pkey_table_len) {
3748 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3749 attr->pkey_index);
e126ba97 3750 goto out;
158abf86 3751 }
e126ba97
EC		 3752 }
3753
3754 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3755 attr->max_rd_atomic >
158abf86
HE		 3756 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3757 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3758 attr->max_rd_atomic);
e126ba97 3759 goto out;
158abf86 3760 }
e126ba97
EC		 3761
3762 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3763 attr->max_dest_rd_atomic >
158abf86
HE		 3764 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3765 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3766 attr->max_dest_rd_atomic);
e126ba97 3767 goto out;
158abf86 3768 }
e126ba97
EC		 3769
3770 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3771 err = 0;
3772 goto out;
3773 }
3774
61147f39
BW		 3775 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3776 new_state, &ucmd);
e126ba97
EC		 3777
3778out:
3779 mutex_unlock(&qp->mutex);
3780 return err;
3781}
3782
34f4c955
GL		 3783static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3784 u32 wqe_sz, void **cur_edge)
3785{
3786 u32 idx;
3787
3788 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3789 *cur_edge = get_sq_edge(sq, idx);
3790
3791 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3792}
3793
3794/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3795 * next nearby edge and get new address translation for current WQE position.
3796 * @sq - SQ buffer.
3797 * @seg: Current WQE position (16B aligned).
3798 * @wqe_sz: Total current WQE size [16B].
3799 * @cur_edge: Updated current edge.
3800 */
3801static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3802 u32 wqe_sz, void **cur_edge)
3803{
3804 if (likely(*seg != *cur_edge))
3805 return;
3806
3807 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3808}
3809
3810/* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3811 * pointers. At the end @seg is aligned to 16B regardless the copied size.
3812 * @sq - SQ buffer.
3813 * @cur_edge: Updated current edge.
3814 * @seg: Current WQE position (16B aligned).
3815 * @wqe_sz: Total current WQE size [16B].
3816 * @src: Pointer to copy from.
3817 * @n: Number of bytes to copy.
3818 */
3819static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3820 void **seg, u32 *wqe_sz, const void *src,
3821 size_t n)
3822{
3823 while (likely(n)) {
3824 size_t leftlen = *cur_edge - *seg;
3825 size_t copysz = min_t(size_t, leftlen, n);
3826 size_t stride;
3827
3828 memcpy(*seg, src, copysz);
3829
3830 n -= copysz;
3831 src += copysz;
3832 stride = !n ? ALIGN(copysz, 16) : copysz;
3833 *seg += stride;
3834 *wqe_sz += stride >> 4;
3835 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3836 }
3837}
3838
e126ba97
EC		 3839static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3840{
3841 struct mlx5_ib_cq *cq;
3842 unsigned cur;
3843
3844 cur = wq->head - wq->tail;
3845 if (likely(cur + nreq < wq->max_post))
3846 return 0;
3847
3848 cq = to_mcq(ib_cq);
3849 spin_lock(&cq->lock);
3850 cur = wq->head - wq->tail;
3851 spin_unlock(&cq->lock);
3852
3853 return cur + nreq >= wq->max_post;
3854}
3855
3856static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3857 u64 remote_addr, u32 rkey)
3858{
3859 rseg->raddr = cpu_to_be64(remote_addr);
3860 rseg->rkey = cpu_to_be32(rkey);
3861 rseg->reserved = 0;
3862}
3863
34f4c955
GL		 3864static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3865 void **seg, int *size, void **cur_edge)
f0313965 3866{
34f4c955 3867 struct mlx5_wqe_eth_seg *eseg = *seg;
f0313965
ES		 3868
3869 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3870
3871 if (wr->send_flags & IB_SEND_IP_CSUM)
3872 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3873 MLX5_ETH_WQE_L4_CSUM;
3874
f0313965
ES		 3875 if (wr->opcode == IB_WR_LSO) {
3876 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
34f4c955 3877 size_t left, copysz;
f0313965 3878 void *pdata = ud_wr->header;
34f4c955 3879 size_t stride;
f0313965
ES		 3880
3881 left = ud_wr->hlen;
3882 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3883 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965 3884
34f4c955
GL		 3885 /* memcpy_send_wqe should get a 16B align address. Hence, we
3886 * first copy up to the current edge and then, if needed,
3887 * fall-through to memcpy_send_wqe.
f0313965 3888 */
34f4c955
GL		 3889 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
3890 left);
3891 memcpy(eseg->inline_hdr.start, pdata, copysz);
3892 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
3893 sizeof(eseg->inline_hdr.start) + copysz, 16);
3894 *size += stride / 16;
3895 *seg += stride;
3896
3897 if (copysz < left) {
3898 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
f0313965
ES		 3899 left -= copysz;
3900 pdata += copysz;
34f4c955
GL		 3901 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
3902 left);
f0313965 3903 }
34f4c955
GL		 3904
3905 return;
f0313965
ES		 3906 }
3907
34f4c955
GL		 3908 *seg += sizeof(struct mlx5_wqe_eth_seg);
3909 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
f0313965
ES		 3910}
3911
e126ba97 3912static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
f696bf6d 3913 const struct ib_send_wr *wr)
e126ba97 3914{
e622f2f4
CH		 3915 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3916 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3917 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3918}
3919
3920static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3921{
3922 dseg->byte_count = cpu_to_be32(sg->length);
3923 dseg->lkey = cpu_to_be32(sg->lkey);
3924 dseg->addr = cpu_to_be64(sg->addr);
3925}
3926
31616255 3927static u64 get_xlt_octo(u64 bytes)
e126ba97 3928{
31616255
AK		 3929 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3930 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3931}
3932
3933static __be64 frwr_mkey_mask(void)
3934{
3935 u64 result;
3936
3937 result = MLX5_MKEY_MASK_LEN |
3938 MLX5_MKEY_MASK_PAGE_SIZE |
3939 MLX5_MKEY_MASK_START_ADDR |
3940 MLX5_MKEY_MASK_EN_RINVAL |
3941 MLX5_MKEY_MASK_KEY |
3942 MLX5_MKEY_MASK_LR |
3943 MLX5_MKEY_MASK_LW |
3944 MLX5_MKEY_MASK_RR |
3945 MLX5_MKEY_MASK_RW |
3946 MLX5_MKEY_MASK_A |
3947 MLX5_MKEY_MASK_SMALL_FENCE |
3948 MLX5_MKEY_MASK_FREE;
3949
3950 return cpu_to_be64(result);
3951}
3952
e6631814
SG		 3953static __be64 sig_mkey_mask(void)
3954{
3955 u64 result;
3956
3957 result = MLX5_MKEY_MASK_LEN |
3958 MLX5_MKEY_MASK_PAGE_SIZE |
3959 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3960 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3961 MLX5_MKEY_MASK_EN_RINVAL |
3962 MLX5_MKEY_MASK_KEY |
3963 MLX5_MKEY_MASK_LR |
3964 MLX5_MKEY_MASK_LW |
3965 MLX5_MKEY_MASK_RR |
3966 MLX5_MKEY_MASK_RW |
3967 MLX5_MKEY_MASK_SMALL_FENCE |
3968 MLX5_MKEY_MASK_FREE |
3969 MLX5_MKEY_MASK_BSF_EN;
3970
3971 return cpu_to_be64(result);
3972}
3973
8a187ee5 3974static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
064e5262 3975 struct mlx5_ib_mr *mr, bool umr_inline)
8a187ee5 3976{
31616255 3977 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3978
3979 memset(umr, 0, sizeof(*umr));
b005d316 3980
8a187ee5 3981 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
064e5262
IB		 3982 if (umr_inline)
3983 umr->flags |= MLX5_UMR_INLINE;
31616255 3984 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3985 umr->mkey_mask = frwr_mkey_mask();
3986}
3987
dd01e66a 3988static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3989{
3990 memset(umr, 0, sizeof(*umr));
dd01e66a 3991 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3992 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3993}
3994
31616255 3995static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3996{
3997 u64 result;
3998
31616255 3999 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 4000 MLX5_MKEY_MASK_FREE;
4001
968e78dd
HE		 4002 return cpu_to_be64(result);
4003}
4004
31616255 4005static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 4006{
4007 u64 result;
4008
4009 result = MLX5_MKEY_MASK_FREE;
4010
4011 return cpu_to_be64(result);
4012}
4013
56e11d62
NO		 4014static __be64 get_umr_update_translation_mask(void)
4015{
4016 u64 result;
4017
4018 result = MLX5_MKEY_MASK_LEN |
4019 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 4020 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 4021
4022 return cpu_to_be64(result);
4023}
4024
31616255 4025static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 4026{
4027 u64 result;
4028
31616255
AK		 4029 result = MLX5_MKEY_MASK_LR |
4030 MLX5_MKEY_MASK_LW |
56e11d62 4031 MLX5_MKEY_MASK_RR |
31616255
AK		 4032 MLX5_MKEY_MASK_RW;
4033
4034 if (atomic)
4035 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 4036
4037 return cpu_to_be64(result);
4038}
4039
4040static __be64 get_umr_update_pd_mask(void)
4041{
4042 u64 result;
4043
31616255 4044 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 4045
4046 return cpu_to_be64(result);
4047}
4048
c8d75a98
MD		 4049static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4050{
4051 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4052 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4053 (mask & MLX5_MKEY_MASK_A &&
4054 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4055 return -EPERM;
4056 return 0;
4057}
4058
4059static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4060 struct mlx5_wqe_umr_ctrl_seg *umr,
f696bf6d 4061 const struct ib_send_wr *wr, int atomic)
e126ba97 4062{
f696bf6d 4063 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 4064
4065 memset(umr, 0, sizeof(*umr));
4066
968e78dd
HE		 4067 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4068 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4069 else
4070 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4071
31616255
AK		 4072 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4073 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4074 u64 offset = get_xlt_octo(umrwr->offset);
4075
4076 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4077 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4078 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 4079 }
31616255
AK		 4080 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4081 umr->mkey_mask |= get_umr_update_translation_mask();
4082 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4083 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4084 umr->mkey_mask |= get_umr_update_pd_mask();
4085 }
4086 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4087 umr->mkey_mask |= get_umr_enable_mr_mask();
4088 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4089 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 4090
4091 if (!wr->num_sge)
968e78dd 4092 umr->flags |= MLX5_UMR_INLINE;
c8d75a98
MD		 4093
4094 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
e126ba97
EC		 4095}
4096
4097static u8 get_umr_flags(int acc)
4098{
4099 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
4100 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
4101 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
4102 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 4103 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 4104}
4105
8a187ee5
SG		 4106static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4107 struct mlx5_ib_mr *mr,
4108 u32 key, int access)
4109{
4110 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4111
4112 memset(seg, 0, sizeof(*seg));
b005d316 4113
ec22eb53 4114 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 4115 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 4116 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 4117 /* KLMs take twice the size of MTTs */
4118 ndescs *= 2;
4119
4120 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 4121 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4122 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4123 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4124 seg->len = cpu_to_be64(mr->ibmr.length);
4125 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 4126}
4127
dd01e66a 4128static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 4129{
4130 memset(seg, 0, sizeof(*seg));
dd01e66a 4131 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 4132}
4133
f696bf6d
BVA		 4134static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4135 const struct ib_send_wr *wr)
e126ba97 4136{
f696bf6d 4137 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 4138
e126ba97 4139 memset(seg, 0, sizeof(*seg));
31616255 4140 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 4141 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 4142
968e78dd 4143 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 4144 if (umrwr->pd)
4145 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4146 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4147 !umrwr->length)
4148 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4149
4150 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 4151 seg->len = cpu_to_be64(umrwr->length);
4152 seg->log2_page_size = umrwr->page_shift;
746b5583 4153 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 4154 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 4155}
4156
8a187ee5
SG		 4157static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4158 struct mlx5_ib_mr *mr,
4159 struct mlx5_ib_pd *pd)
4160{
4161 int bcount = mr->desc_size * mr->ndescs;
4162
4163 dseg->addr = cpu_to_be64(mr->desc_map);
4164 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4165 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4166}
4167
f696bf6d 4168static __be32 send_ieth(const struct ib_send_wr *wr)
e126ba97
EC		 4169{
4170 switch (wr->opcode) {
4171 case IB_WR_SEND_WITH_IMM:
4172 case IB_WR_RDMA_WRITE_WITH_IMM:
4173 return wr->ex.imm_data;
4174
4175 case IB_WR_SEND_WITH_INV:
4176 return cpu_to_be32(wr->ex.invalidate_rkey);
4177
4178 default:
4179 return 0;
4180 }
4181}
4182
4183static u8 calc_sig(void *wqe, int size)
4184{
4185 u8 *p = wqe;
4186 u8 res = 0;
4187 int i;
4188
4189 for (i = 0; i < size; i++)
4190 res ^= p[i];
4191
4192 return ~res;
4193}
4194
4195static u8 wq_sig(void *wqe)
4196{
4197 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4198}
4199
f696bf6d 4200static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
34f4c955 4201 void **wqe, int *wqe_sz, void **cur_edge)
e126ba97
EC		 4202{
4203 struct mlx5_wqe_inline_seg *seg;
34f4c955 4204 size_t offset;
e126ba97 4205 int inl = 0;
e126ba97
EC		 4206 int i;
4207
34f4c955
GL		 4208 seg = *wqe;
4209 *wqe += sizeof(*seg);
4210 offset = sizeof(*seg);
4211
e126ba97 4212 for (i = 0; i < wr->num_sge; i++) {
34f4c955
GL		 4213 size_t len = wr->sg_list[i].length;
4214 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4215
e126ba97
EC		 4216 inl += len;
4217
4218 if (unlikely(inl > qp->max_inline_data))
4219 return -ENOMEM;
4220
34f4c955
GL		 4221 while (likely(len)) {
4222 size_t leftlen;
4223 size_t copysz;
4224
4225 handle_post_send_edge(&qp->sq, wqe,
4226 *wqe_sz + (offset >> 4),
4227 cur_edge);
4228
4229 leftlen = *cur_edge - *wqe;
4230 copysz = min_t(size_t, leftlen, len);
4231
4232 memcpy(*wqe, addr, copysz);
4233 len -= copysz;
4234 addr += copysz;
4235 *wqe += copysz;
4236 offset += copysz;
e126ba97 4237 }
e126ba97
EC		 4238 }
4239
4240 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4241
34f4c955 4242 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
e126ba97
EC		 4243
4244 return 0;
4245}
4246
e6631814
SG		 4247static u16 prot_field_size(enum ib_signature_type type)
4248{
4249 switch (type) {
4250 case IB_SIG_TYPE_T10_DIF:
4251 return MLX5_DIF_SIZE;
4252 default:
4253 return 0;
4254 }
4255}
4256
4257static u8 bs_selector(int block_size)
4258{
4259 switch (block_size) {
4260 case 512: return 0x1;
4261 case 520: return 0x2;
4262 case 4096: return 0x3;
4263 case 4160: return 0x4;
4264 case 1073741824: return 0x5;
4265 default: return 0;
4266 }
4267}
4268
78eda2bb
SG		 4269static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4270 struct mlx5_bsf_inl *inl)
e6631814 4271{
142537f4
SG		 4272 /* Valid inline section and allow BSF refresh */
4273 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4274 MLX5_BSF_REFRESH_DIF);
4275 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4276 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 4277 /* repeating block */
4278 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4279 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4280 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 4281
78eda2bb
SG		 4282 if (domain->sig.dif.ref_remap)
4283 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 4284
78eda2bb
SG		 4285 if (domain->sig.dif.app_escape) {
4286 if (domain->sig.dif.ref_escape)
4287 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4288 else
4289 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 4290 }
4291
78eda2bb
SG		 4292 inl->dif_app_bitmask_check =
4293 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 4294}
4295
4296static int mlx5_set_bsf(struct ib_mr *sig_mr,
4297 struct ib_sig_attrs *sig_attrs,
4298 struct mlx5_bsf *bsf, u32 data_size)
4299{
4300 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4301 struct mlx5_bsf_basic *basic = &bsf->basic;
4302 struct ib_sig_domain *mem = &sig_attrs->mem;
4303 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 4304
c7f44fbd 4305 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 4306
4307 /* Basic + Extended + Inline */
4308 basic->bsf_size_sbs = 1 << 7;
4309 /* Input domain check byte mask */
4310 basic->check_byte_mask = sig_attrs->check_mask;
4311 basic->raw_data_size = cpu_to_be32(data_size);
4312
4313 /* Memory domain */
e6631814 4314 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 4315 case IB_SIG_TYPE_NONE:
4316 break;
e6631814 4317 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 4318 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4319 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4320 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4321 break;
4322 default:
4323 return -EINVAL;
4324 }
e6631814 4325
78eda2bb
SG		 4326 /* Wire domain */
4327 switch (sig_attrs->wire.sig_type) {
4328 case IB_SIG_TYPE_NONE:
4329 break;
4330 case IB_SIG_TYPE_T10_DIF:
e6631814 4331 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 4332 mem->sig_type == wire->sig_type) {
e6631814 4333 /* Same block structure */
142537f4 4334 basic->bsf_size_sbs |= 1 << 4;
e6631814 4335 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 4336 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 4337 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 4338 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 4339 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 4340 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 4341 } else
4342 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4343
142537f4 4344 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 4345 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 4346 break;
e6631814
SG		 4347 default:
4348 return -EINVAL;
4349 }
4350
4351 return 0;
4352}
4353
f696bf6d 4354static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
34f4c955
GL		 4355 struct mlx5_ib_qp *qp, void **seg,
4356 int *size, void **cur_edge)
e6631814 4357{
e622f2f4
CH		 4358 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4359 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4360 struct mlx5_bsf *bsf;
e622f2f4
CH		 4361 u32 data_len = wr->wr.sg_list->length;
4362 u32 data_key = wr->wr.sg_list->lkey;
4363 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 4364 int ret;
4365 int wqe_size;
4366
e622f2f4
CH		 4367 if (!wr->prot ||
4368 (data_key == wr->prot->lkey &&
4369 data_va == wr->prot->addr &&
4370 data_len == wr->prot->length)) {
e6631814
SG		 4371 /**
4372 * Source domain doesn't contain signature information
5c273b16 4373 * or data and protection are interleaved in memory.
e6631814
SG		 4374 * So need construct:
4375 * ------------------
4376 * | data_klm |
4377 * ------------------
4378 * | BSF |
4379 * ------------------
4380 **/
4381 struct mlx5_klm *data_klm = *seg;
4382
4383 data_klm->bcount = cpu_to_be32(data_len);
4384 data_klm->key = cpu_to_be32(data_key);
4385 data_klm->va = cpu_to_be64(data_va);
4386 wqe_size = ALIGN(sizeof(*data_klm), 64);
4387 } else {
4388 /**
4389 * Source domain contains signature information
4390 * So need construct a strided block format:
4391 * ---------------------------
4392 * | stride_block_ctrl |
4393 * ---------------------------
4394 * | data_klm |
4395 * ---------------------------
4396 * | prot_klm |
4397 * ---------------------------
4398 * | BSF |
4399 * ---------------------------
4400 **/
4401 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4402 struct mlx5_stride_block_entry *data_sentry;
4403 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 4404 u32 prot_key = wr->prot->lkey;
4405 u64 prot_va = wr->prot->addr;
e6631814
SG		 4406 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4407 int prot_size;
4408
4409 sblock_ctrl = *seg;
4410 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4411 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4412
4413 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4414 if (!prot_size) {
4415 pr_err("Bad block size given: %u\n", block_size);
4416 return -EINVAL;
4417 }
4418 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4419 prot_size);
4420 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4421 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4422 sblock_ctrl->num_entries = cpu_to_be16(2);
4423
4424 data_sentry->bcount = cpu_to_be16(block_size);
4425 data_sentry->key = cpu_to_be32(data_key);
4426 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 4427 data_sentry->stride = cpu_to_be16(block_size);
4428
e6631814
SG		 4429 prot_sentry->bcount = cpu_to_be16(prot_size);
4430 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 4431 prot_sentry->va = cpu_to_be64(prot_va);
4432 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 4433
e6631814
SG		 4434 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4435 sizeof(*prot_sentry), 64);
4436 }
4437
4438 *seg += wqe_size;
4439 *size += wqe_size / 16;
34f4c955 4440 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814
SG		 4441
4442 bsf = *seg;
4443 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4444 if (ret)
4445 return -EINVAL;
4446
4447 *seg += sizeof(*bsf);
4448 *size += sizeof(*bsf) / 16;
34f4c955 4449 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814
SG		 4450
4451 return 0;
4452}
4453
4454static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
f696bf6d 4455 const struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4456 u32 length, u32 pdn)
4457{
e622f2f4 4458 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4459 u32 sig_key = sig_mr->rkey;
d5436ba0 4460 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4461
4462 memset(seg, 0, sizeof(*seg));
4463
e622f2f4 4464 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4465 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4466 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4467 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4468 MLX5_MKEY_BSF_EN | pdn);
4469 seg->len = cpu_to_be64(length);
31616255 4470 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4471 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4472}
4473
4474static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4475 u32 size)
e6631814
SG		 4476{
4477 memset(umr, 0, sizeof(*umr));
4478
4479 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4480 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4481 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4482 umr->mkey_mask = sig_mkey_mask();
4483}
4484
4485
f696bf6d 4486static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
34f4c955
GL		 4487 struct mlx5_ib_qp *qp, void **seg, int *size,
4488 void **cur_edge)
e6631814 4489{
f696bf6d 4490 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
e622f2f4 4491 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4492 u32 pdn = get_pd(qp)->pdn;
31616255 4493 u32 xlt_size;
e6631814
SG		 4494 int region_len, ret;
4495
e622f2f4
CH		 4496 if (unlikely(wr->wr.num_sge != 1) ||
4497 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4498 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4499 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4500 return -EINVAL;
4501
4502 /* length of the protected region, data + protection */
e622f2f4
CH		 4503 region_len = wr->wr.sg_list->length;
4504 if (wr->prot &&
4505 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4506 wr->prot->addr != wr->wr.sg_list->addr ||
4507 wr->prot->length != wr->wr.sg_list->length))
4508 region_len += wr->prot->length;
e6631814
SG		 4509
4510 /**
4511 * KLM octoword size - if protection was provided
4512 * then we use strided block format (3 octowords),
4513 * else we use single KLM (1 octoword)
4514 **/
31616255 4515 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4516
31616255 4517 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4518 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4519 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4520 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814 4521
31616255 4522 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4523 *seg += sizeof(struct mlx5_mkey_seg);
4524 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4525 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e6631814 4526
34f4c955 4527 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
e6631814
SG		 4528 if (ret)
4529 return ret;
4530
d5436ba0 4531 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4532 return 0;
4533}
4534
4535static int set_psv_wr(struct ib_sig_domain *domain,
4536 u32 psv_idx, void **seg, int *size)
4537{
4538 struct mlx5_seg_set_psv *psv_seg = *seg;
4539
4540 memset(psv_seg, 0, sizeof(*psv_seg));
4541 psv_seg->psv_num = cpu_to_be32(psv_idx);
4542 switch (domain->sig_type) {
78eda2bb
SG		 4543 case IB_SIG_TYPE_NONE:
4544 break;
e6631814
SG		 4545 case IB_SIG_TYPE_T10_DIF:
4546 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4547 domain->sig.dif.app_tag);
4548 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4549 break;
e6631814 4550 default:
12bbf1ea
LR		 4551 pr_err("Bad signature type (%d) is given.\n",
4552 domain->sig_type);
4553 return -EINVAL;
e6631814
SG		 4554 }
4555
78eda2bb
SG		 4556 *seg += sizeof(*psv_seg);
4557 *size += sizeof(*psv_seg) / 16;
4558
e6631814
SG		 4559 return 0;
4560}
4561
8a187ee5 4562static int set_reg_wr(struct mlx5_ib_qp *qp,
f696bf6d 4563 const struct ib_reg_wr *wr,
34f4c955 4564 void **seg, int *size, void **cur_edge)
8a187ee5
SG		 4565{
4566 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4567 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
34f4c955 4568 size_t mr_list_size = mr->ndescs * mr->desc_size;
064e5262 4569 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
8a187ee5
SG		 4570
4571 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4572 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4573 "Invalid IB_SEND_INLINE send flag\n");
4574 return -EINVAL;
4575 }
4576
064e5262 4577 set_reg_umr_seg(*seg, mr, umr_inline);
8a187ee5
SG		 4578 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4579 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4580 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
8a187ee5
SG		 4581
4582 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4583 *seg += sizeof(struct mlx5_mkey_seg);
4584 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4585 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
8a187ee5 4586
064e5262 4587 if (umr_inline) {
34f4c955
GL		 4588 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4589 mr_list_size);
4590 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
064e5262
IB		 4591 } else {
4592 set_reg_data_seg(*seg, mr, pd);
4593 *seg += sizeof(struct mlx5_wqe_data_seg);
4594 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4595 }
8a187ee5
SG		 4596 return 0;
4597}
4598
34f4c955
GL		 4599static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4600 void **cur_edge)
e126ba97 4601{
dd01e66a 4602 set_linv_umr_seg(*seg);
e126ba97
EC		 4603 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4604 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4605 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
dd01e66a 4606 set_linv_mkey_seg(*seg);
e126ba97
EC		 4607 *seg += sizeof(struct mlx5_mkey_seg);
4608 *size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4609 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
e126ba97
EC		 4610}
4611
34f4c955 4612static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
e126ba97
EC		 4613{
4614 __be32 *p = NULL;
34f4c955 4615 u32 tidx = idx;
e126ba97
EC		 4616 int i, j;
4617
34f4c955 4618 pr_debug("dump WQE index %u:\n", idx);
e126ba97
EC		 4619 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4620 if ((i & 0xf) == 0) {
e126ba97 4621 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
34f4c955
GL		 4622 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx);
4623 pr_debug("WQBB at %p:\n", (void *)p);
e126ba97
EC		 4624 j = 0;
4625 }
4626 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4627 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4628 be32_to_cpu(p[j + 3]));
4629 }
4630}
4631
7bb1fafc 4632static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
34f4c955
GL		 4633 struct mlx5_wqe_ctrl_seg **ctrl,
4634 const struct ib_send_wr *wr, unsigned int *idx,
4635 int *size, void **cur_edge, int nreq,
4636 bool send_signaled, bool solicited)
6e5eadac 4637{
b2a232d2
LR		 4638 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4639 return -ENOMEM;
6e5eadac
SG		 4640
4641 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
34f4c955 4642 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
6e5eadac
SG		 4643 *ctrl = *seg;
4644 *(uint32_t *)(*seg + 8) = 0;
4645 (*ctrl)->imm = send_ieth(wr);
4646 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
7bb1fafc
BVA		 4647 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4648 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
6e5eadac
SG		 4649
4650 *seg += sizeof(**ctrl);
4651 *size = sizeof(**ctrl) / 16;
34f4c955 4652 *cur_edge = qp->sq.cur_edge;
6e5eadac 4653
b2a232d2 4654 return 0;
6e5eadac
SG		 4655}
4656
7bb1fafc
BVA		 4657static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4658 struct mlx5_wqe_ctrl_seg **ctrl,
4659 const struct ib_send_wr *wr, unsigned *idx,
34f4c955 4660 int *size, void **cur_edge, int nreq)
7bb1fafc 4661{
34f4c955 4662 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
7bb1fafc
BVA		 4663 wr->send_flags & IB_SEND_SIGNALED,
4664 wr->send_flags & IB_SEND_SOLICITED);
4665}
4666
6e5eadac
SG		 4667static void finish_wqe(struct mlx5_ib_qp *qp,
4668 struct mlx5_wqe_ctrl_seg *ctrl,
34f4c955
GL		 4669 void *seg, u8 size, void *cur_edge,
4670 unsigned int idx, u64 wr_id, int nreq, u8 fence,
4671 u32 mlx5_opcode)
6e5eadac
SG		 4672{
4673 u8 opmod = 0;
4674
4675 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4676 mlx5_opcode | ((u32)opmod << 24));
19098df2 4677 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4678 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4679 if (unlikely(qp->wq_sig))
4680 ctrl->signature = wq_sig(ctrl);
4681
4682 qp->sq.wrid[idx] = wr_id;
4683 qp->sq.w_list[idx].opcode = mlx5_opcode;
4684 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4685 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4686 qp->sq.w_list[idx].next = qp->sq.cur_post;
34f4c955
GL		 4687
4688 /* We save the edge which was possibly updated during the WQE
4689 * construction, into SQ's cache.
4690 */
4691 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4692 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4693 get_sq_edge(&qp->sq, qp->sq.cur_post &
4694 (qp->sq.wqe_cnt - 1)) :
4695 cur_edge;
6e5eadac
SG		 4696}
4697
d34ac5cd
BVA		 4698static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4699 const struct ib_send_wr **bad_wr, bool drain)
e126ba97
EC		 4700{
4701 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4702 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4703 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4704 struct mlx5_ib_qp *qp;
e6631814 4705 struct mlx5_ib_mr *mr;
e126ba97 4706 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4707 struct mlx5_bf *bf;
34f4c955 4708 void *cur_edge;
e126ba97 4709 int uninitialized_var(size);
e126ba97 4710 unsigned long flags;
e126ba97
EC		 4711 unsigned idx;
4712 int err = 0;
e126ba97
EC		 4713 int num_sge;
4714 void *seg;
4715 int nreq;
4716 int i;
4717 u8 next_fence = 0;
e126ba97
EC		 4718 u8 fence;
4719
6c75520f
PP		 4720 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4721 !drain)) {
4722 *bad_wr = wr;
4723 return -EIO;
4724 }
4725
d16e91da
HE		 4726 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4727 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4728
4729 qp = to_mqp(ibqp);
5fe9dec0 4730 bf = &qp->bf;
d16e91da 4731
e126ba97
EC		 4732 spin_lock_irqsave(&qp->sq.lock, flags);
4733
4734 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4735 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4736 mlx5_ib_warn(dev, "\n");
4737 err = -EINVAL;
4738 *bad_wr = wr;
4739 goto out;
4740 }
4741
6e5eadac
SG		 4742 num_sge = wr->num_sge;
4743 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4744 mlx5_ib_warn(dev, "\n");
24be409b 4745 err = -EINVAL;
e126ba97
EC		 4746 *bad_wr = wr;
4747 goto out;
4748 }
4749
34f4c955
GL		 4750 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4751 nreq);
6e5eadac 4752 if (err) {
e126ba97
EC		 4753 mlx5_ib_warn(dev, "\n");
4754 err = -ENOMEM;
4755 *bad_wr = wr;
4756 goto out;
4757 }
4758
6e8484c5
MG		 4759 if (wr->opcode == IB_WR_LOCAL_INV ||
4760 wr->opcode == IB_WR_REG_MR) {
4761 fence = dev->umr_fence;
4762 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4763 } else if (wr->send_flags & IB_SEND_FENCE) {
4764 if (qp->next_fence)
4765 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4766 else
4767 fence = MLX5_FENCE_MODE_FENCE;
4768 } else {
4769 fence = qp->next_fence;
4770 }
4771
e126ba97
EC		 4772 switch (ibqp->qp_type) {
4773 case IB_QPT_XRC_INI:
4774 xrc = seg;
e126ba97
EC		 4775 seg += sizeof(*xrc);
4776 size += sizeof(*xrc) / 16;
4777 /* fall through */
4778 case IB_QPT_RC:
4779 switch (wr->opcode) {
4780 case IB_WR_RDMA_READ:
4781 case IB_WR_RDMA_WRITE:
4782 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4783 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4784 rdma_wr(wr)->rkey);
f241e749 4785 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4786 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4787 break;
4788
4789 case IB_WR_ATOMIC_CMP_AND_SWP:
4790 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4791 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4792 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4793 err = -ENOSYS;
4794 *bad_wr = wr;
4795 goto out;
e126ba97
EC		 4796
4797 case IB_WR_LOCAL_INV:
e126ba97
EC		 4798 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4799 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
34f4c955 4800 set_linv_wr(qp, &seg, &size, &cur_edge);
e126ba97
EC		 4801 num_sge = 0;
4802 break;
4803
8a187ee5 4804 case IB_WR_REG_MR:
8a187ee5
SG		 4805 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4806 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
34f4c955
GL		 4807 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4808 &cur_edge);
8a187ee5
SG		 4809 if (err) {
4810 *bad_wr = wr;
4811 goto out;
4812 }
4813 num_sge = 0;
4814 break;
4815
e6631814
SG		 4816 case IB_WR_REG_SIG_MR:
4817 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4818 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4819
4820 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
34f4c955
GL		 4821 err = set_sig_umr_wr(wr, qp, &seg, &size,
4822 &cur_edge);
e6631814
SG		 4823 if (err) {
4824 mlx5_ib_warn(dev, "\n");
4825 *bad_wr = wr;
4826 goto out;
4827 }
4828
34f4c955
GL		 4829 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4830 wr->wr_id, nreq, fence,
4831 MLX5_OPCODE_UMR);
e6631814
SG		 4832 /*
4833 * SET_PSV WQEs are not signaled and solicited
4834 * on error
4835 */
7bb1fafc 4836 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
34f4c955
GL		 4837 &size, &cur_edge, nreq, false,
4838 true);
e6631814
SG		 4839 if (err) {
4840 mlx5_ib_warn(dev, "\n");
4841 err = -ENOMEM;
4842 *bad_wr = wr;
4843 goto out;
4844 }
4845
e622f2f4 4846 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4847 mr->sig->psv_memory.psv_idx, &seg,
4848 &size);
4849 if (err) {
4850 mlx5_ib_warn(dev, "\n");
4851 *bad_wr = wr;
4852 goto out;
4853 }
4854
34f4c955
GL		 4855 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4856 wr->wr_id, nreq, fence,
4857 MLX5_OPCODE_SET_PSV);
7bb1fafc 4858 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
34f4c955
GL		 4859 &size, &cur_edge, nreq, false,
4860 true);
e6631814
SG		 4861 if (err) {
4862 mlx5_ib_warn(dev, "\n");
4863 err = -ENOMEM;
4864 *bad_wr = wr;
4865 goto out;
4866 }
4867
e622f2f4 4868 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4869 mr->sig->psv_wire.psv_idx, &seg,
4870 &size);
4871 if (err) {
4872 mlx5_ib_warn(dev, "\n");
4873 *bad_wr = wr;
4874 goto out;
4875 }
4876
34f4c955
GL		 4877 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4878 wr->wr_id, nreq, fence,
4879 MLX5_OPCODE_SET_PSV);
6e8484c5 4880 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4881 num_sge = 0;
4882 goto skip_psv;
4883
e126ba97
EC		 4884 default:
4885 break;
4886 }
4887 break;
4888
4889 case IB_QPT_UC:
4890 switch (wr->opcode) {
4891 case IB_WR_RDMA_WRITE:
4892 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4893 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4894 rdma_wr(wr)->rkey);
e126ba97
EC		 4895 seg += sizeof(struct mlx5_wqe_raddr_seg);
4896 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4897 break;
4898
4899 default:
4900 break;
4901 }
4902 break;
4903
e126ba97 4904 case IB_QPT_SMI:
1e0e50b6
MG		 4905 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4906 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4907 err = -EPERM;
4908 *bad_wr = wr;
4909 goto out;
4910 }
f6b1ee34 4911 /* fall through */
d16e91da 4912 case MLX5_IB_QPT_HW_GSI:
e126ba97 4913 set_datagram_seg(seg, wr);
f241e749 4914 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97 4915 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
34f4c955
GL		 4916 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4917
e126ba97 4918 break;
f0313965
ES		 4919 case IB_QPT_UD:
4920 set_datagram_seg(seg, wr);
4921 seg += sizeof(struct mlx5_wqe_datagram_seg);
4922 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
34f4c955 4923 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
f0313965
ES		 4924
4925 /* handle qp that supports ud offload */
4926 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4927 struct mlx5_wqe_eth_pad *pad;
e126ba97 4928
f0313965
ES		 4929 pad = seg;
4930 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4931 seg += sizeof(struct mlx5_wqe_eth_pad);
4932 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
34f4c955
GL		 4933 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
4934 handle_post_send_edge(&qp->sq, &seg, size,
4935 &cur_edge);
f0313965
ES		 4936 }
4937 break;
e126ba97
EC		 4938 case MLX5_IB_QPT_REG_UMR:
4939 if (wr->opcode != MLX5_IB_WR_UMR) {
4940 err = -EINVAL;
4941 mlx5_ib_warn(dev, "bad opcode\n");
4942 goto out;
4943 }
4944 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4945 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
c8d75a98
MD		 4946 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4947 if (unlikely(err))
4948 goto out;
e126ba97
EC		 4949 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4950 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
34f4c955 4951 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
e126ba97
EC		 4952 set_reg_mkey_segment(seg, wr);
4953 seg += sizeof(struct mlx5_mkey_seg);
4954 size += sizeof(struct mlx5_mkey_seg) / 16;
34f4c955 4955 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
e126ba97
EC		 4956 break;
4957
4958 default:
4959 break;
4960 }
4961
4962 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
34f4c955 4963 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
e126ba97
EC		 4964 if (unlikely(err)) {
4965 mlx5_ib_warn(dev, "\n");
4966 *bad_wr = wr;
4967 goto out;
4968 }
e126ba97 4969 } else {
e126ba97 4970 for (i = 0; i < num_sge; i++) {
34f4c955
GL		 4971 handle_post_send_edge(&qp->sq, &seg, size,
4972 &cur_edge);
e126ba97 4973 if (likely(wr->sg_list[i].length)) {
34f4c955
GL		 4974 set_data_ptr_seg
4975 ((struct mlx5_wqe_data_seg *)seg,
4976 wr->sg_list + i);
e126ba97 4977 size += sizeof(struct mlx5_wqe_data_seg) / 16;
34f4c955 4978 seg += sizeof(struct mlx5_wqe_data_seg);
e126ba97
EC		 4979 }
4980 }
4981 }
4982
6e8484c5 4983 qp->next_fence = next_fence;
34f4c955
GL		 4984 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
4985 fence, mlx5_ib_opcode[wr->opcode]);
e6631814 4986skip_psv:
e126ba97
EC		 4987 if (0)
4988 dump_wqe(qp, idx, size);
4989 }
4990
4991out:
4992 if (likely(nreq)) {
4993 qp->sq.head += nreq;
4994
4995 /* Make sure that descriptors are written before
4996 * updating doorbell record and ringing the doorbell
4997 */
4998 wmb();
4999
5000 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5001
ada388f7
EC		 5002 /* Make sure doorbell record is visible to the HCA before
5003 * we hit doorbell */
5004 wmb();
5005
5fe9dec0
EC		 5006 /* currently we support only regular doorbells */
5007 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
5008 /* Make sure doorbells don't leak out of SQ spinlock
5009 * and reach the HCA out of order.
5010 */
5011 mmiowb();
e126ba97 5012 bf->offset ^= bf->buf_size;
e126ba97
EC		 5013 }
5014
5015 spin_unlock_irqrestore(&qp->sq.lock, flags);
5016
5017 return err;
5018}
5019
d34ac5cd
BVA		 5020int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5021 const struct ib_send_wr **bad_wr)
d0e84c0a
YH		 5022{
5023 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5024}
5025
e126ba97
EC		 5026static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5027{
5028 sig->signature = calc_sig(sig, size);
5029}
5030
d34ac5cd
BVA		 5031static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5032 const struct ib_recv_wr **bad_wr, bool drain)
e126ba97
EC		 5033{
5034 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5035 struct mlx5_wqe_data_seg *scat;
5036 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 5037 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5038 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 5039 unsigned long flags;
5040 int err = 0;
5041 int nreq;
5042 int ind;
5043 int i;
5044
6c75520f
PP		 5045 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5046 !drain)) {
5047 *bad_wr = wr;
5048 return -EIO;
5049 }
5050
d16e91da
HE		 5051 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5052 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5053
e126ba97
EC		 5054 spin_lock_irqsave(&qp->rq.lock, flags);
5055
5056 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5057
5058 for (nreq = 0; wr; nreq++, wr = wr->next) {
5059 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5060 err = -ENOMEM;
5061 *bad_wr = wr;
5062 goto out;
5063 }
5064
5065 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5066 err = -EINVAL;
5067 *bad_wr = wr;
5068 goto out;
5069 }
5070
34f4c955 5071 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
e126ba97
EC		 5072 if (qp->wq_sig)
5073 scat++;
5074
5075 for (i = 0; i < wr->num_sge; i++)
5076 set_data_ptr_seg(scat + i, wr->sg_list + i);
5077
5078 if (i < qp->rq.max_gs) {
5079 scat[i].byte_count = 0;
5080 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
5081 scat[i].addr = 0;
5082 }
5083
5084 if (qp->wq_sig) {
5085 sig = (struct mlx5_rwqe_sig *)scat;
5086 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5087 }
5088
5089 qp->rq.wrid[ind] = wr->wr_id;
5090
5091 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5092 }
5093
5094out:
5095 if (likely(nreq)) {
5096 qp->rq.head += nreq;
5097
5098 /* Make sure that descriptors are written before
5099 * doorbell record.
5100 */
5101 wmb();
5102
5103 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5104 }
5105
5106 spin_unlock_irqrestore(&qp->rq.lock, flags);
5107
5108 return err;
5109}
5110
d34ac5cd
BVA		 5111int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5112 const struct ib_recv_wr **bad_wr)
d0e84c0a
YH		 5113{
5114 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5115}
5116
e126ba97
EC		 5117static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5118{
5119 switch (mlx5_state) {
5120 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
5121 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
5122 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
5123 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
5124 case MLX5_QP_STATE_SQ_DRAINING:
5125 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
5126 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
5127 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
5128 default: return -1;
5129 }
5130}
5131
5132static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5133{
5134 switch (mlx5_mig_state) {
5135 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
5136 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
5137 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
5138 default: return -1;
5139 }
5140}
5141
5142static int to_ib_qp_access_flags(int mlx5_flags)
5143{
5144 int ib_flags = 0;
5145
5146 if (mlx5_flags & MLX5_QP_BIT_RRE)
5147 ib_flags |= IB_ACCESS_REMOTE_READ;
5148 if (mlx5_flags & MLX5_QP_BIT_RWE)
5149 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5150 if (mlx5_flags & MLX5_QP_BIT_RAE)
5151 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5152
5153 return ib_flags;
5154}
5155
38349389 5156static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 5157 struct rdma_ah_attr *ah_attr,
38349389 5158 struct mlx5_qp_path *path)
e126ba97 5159{
e126ba97 5160
d8966fcd 5161 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 5162
e7996a9a 5163 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 5164 return;
5165
ae59c3f0
LR		 5166 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5167
d8966fcd
DC		 5168 rdma_ah_set_port_num(ah_attr, path->port);
5169 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5170
5171 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5172 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5173 rdma_ah_set_static_rate(ah_attr,
5174 path->static_rate ? path->static_rate - 5 : 0);
5175 if (path->grh_mlid & (1 << 7)) {
5176 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5177
5178 rdma_ah_set_grh(ah_attr, NULL,
5179 tc_fl & 0xfffff,
5180 path->mgid_index,
5181 path->hop_limit,
5182 (tc_fl >> 20) & 0xff);
5183 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 5184 }
5185}
5186
6d2f89df 5187static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5188 struct mlx5_ib_sq *sq,
5189 u8 *sq_state)
5190{
6d2f89df 5191 int err;
5192
28160771 5193 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 5194 if (err)
5195 goto out;
6d2f89df 5196 sq->state = *sq_state;
5197
5198out:
6d2f89df 5199 return err;
5200}
5201
5202static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5203 struct mlx5_ib_rq *rq,
5204 u8 *rq_state)
5205{
5206 void *out;
5207 void *rqc;
5208 int inlen;
5209 int err;
5210
5211 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 5212 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 5213 if (!out)
5214 return -ENOMEM;
5215
5216 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5217 if (err)
5218 goto out;
5219
5220 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5221 *rq_state = MLX5_GET(rqc, rqc, state);
5222 rq->state = *rq_state;
5223
5224out:
5225 kvfree(out);
5226 return err;
5227}
5228
5229static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5230 struct mlx5_ib_qp *qp, u8 *qp_state)
5231{
5232 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5233 [MLX5_RQC_STATE_RST] = {
5234 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5235 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5236 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5237 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5238 },
5239 [MLX5_RQC_STATE_RDY] = {
5240 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5241 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5242 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5243 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5244 },
5245 [MLX5_RQC_STATE_ERR] = {
5246 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5247 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5248 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5249 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5250 },
5251 [MLX5_RQ_STATE_NA] = {
5252 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5253 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5254 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5255 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5256 },
5257 };
5258
5259 *qp_state = sqrq_trans[rq_state][sq_state];
5260
5261 if (*qp_state == MLX5_QP_STATE_BAD) {
5262 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5263 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5264 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5265 return -EINVAL;
5266 }
5267
5268 if (*qp_state == MLX5_QP_STATE)
5269 *qp_state = qp->state;
5270
5271 return 0;
5272}
5273
5274static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5275 struct mlx5_ib_qp *qp,
5276 u8 *raw_packet_qp_state)
5277{
5278 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5279 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5280 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5281 int err;
5282 u8 sq_state = MLX5_SQ_STATE_NA;
5283 u8 rq_state = MLX5_RQ_STATE_NA;
5284
5285 if (qp->sq.wqe_cnt) {
5286 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5287 if (err)
5288 return err;
5289 }
5290
5291 if (qp->rq.wqe_cnt) {
5292 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5293 if (err)
5294 return err;
5295 }
5296
5297 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5298 raw_packet_qp_state);
5299}
5300
5301static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5302 struct ib_qp_attr *qp_attr)
e126ba97 5303{
09a7d9ec 5304 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 5305 struct mlx5_qp_context *context;
5306 int mlx5_state;
09a7d9ec 5307 u32 *outb;
e126ba97
EC		 5308 int err = 0;
5309
09a7d9ec 5310 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 5311 if (!outb)
5312 return -ENOMEM;
5313
19098df2 5314 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 5315 outlen);
e126ba97 5316 if (err)
6d2f89df 5317 goto out;
e126ba97 5318
09a7d9ec
SM		 5319 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5320 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5321
e126ba97
EC		 5322 mlx5_state = be32_to_cpu(context->flags) >> 28;
5323
5324 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 5325 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5326 qp_attr->path_mig_state =
5327 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5328 qp_attr->qkey = be32_to_cpu(context->qkey);
5329 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5330 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5331 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5332 qp_attr->qp_access_flags =
5333 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5334
5335 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 5336 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5337 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 5338 qp_attr->alt_pkey_index =
5339 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 5340 qp_attr->alt_port_num =
5341 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 5342 }
5343
d3ae2bde 5344 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 5345 qp_attr->port_num = context->pri_path.port;
5346
5347 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5348 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5349
5350 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5351
5352 qp_attr->max_dest_rd_atomic =
5353 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5354 qp_attr->min_rnr_timer =
5355 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5356 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5357 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5358 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5359 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 5360
5361out:
5362 kfree(outb);
5363 return err;
5364}
5365
776a3906
MS		 5366static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5367 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5368 struct ib_qp_init_attr *qp_init_attr)
5369{
5370 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5371 u32 *out;
5372 u32 access_flags = 0;
5373 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5374 void *dctc;
5375 int err;
5376 int supported_mask = IB_QP_STATE |
5377 IB_QP_ACCESS_FLAGS |
5378 IB_QP_PORT |
5379 IB_QP_MIN_RNR_TIMER |
5380 IB_QP_AV |
5381 IB_QP_PATH_MTU |
5382 IB_QP_PKEY_INDEX;
5383
5384 if (qp_attr_mask & ~supported_mask)
5385 return -EINVAL;
5386 if (mqp->state != IB_QPS_RTR)
5387 return -EINVAL;
5388
5389 out = kzalloc(outlen, GFP_KERNEL);
5390 if (!out)
5391 return -ENOMEM;
5392
5393 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5394 if (err)
5395 goto out;
5396
5397 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5398
5399 if (qp_attr_mask & IB_QP_STATE)
5400 qp_attr->qp_state = IB_QPS_RTR;
5401
5402 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5403 if (MLX5_GET(dctc, dctc, rre))
5404 access_flags |= IB_ACCESS_REMOTE_READ;
5405 if (MLX5_GET(dctc, dctc, rwe))
5406 access_flags |= IB_ACCESS_REMOTE_WRITE;
5407 if (MLX5_GET(dctc, dctc, rae))
5408 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5409 qp_attr->qp_access_flags = access_flags;
5410 }
5411
5412 if (qp_attr_mask & IB_QP_PORT)
5413 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5414 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5415 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5416 if (qp_attr_mask & IB_QP_AV) {
5417 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5418 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5419 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5420 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5421 }
5422 if (qp_attr_mask & IB_QP_PATH_MTU)
5423 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5424 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5425 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5426out:
5427 kfree(out);
5428 return err;
5429}
5430
6d2f89df 5431int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5432 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5433{
5434 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5435 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5436 int err = 0;
5437 u8 raw_packet_qp_state;
5438
28d61370
YH		 5439 if (ibqp->rwq_ind_tbl)
5440 return -ENOSYS;
5441
d16e91da
HE		 5442 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5443 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5444 qp_init_attr);
5445
c2e53b2c
YH		 5446 /* Not all of output fields are applicable, make sure to zero them */
5447 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5448 memset(qp_attr, 0, sizeof(*qp_attr));
5449
776a3906
MS		 5450 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5451 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5452 qp_attr_mask, qp_init_attr);
5453
6d2f89df 5454 mutex_lock(&qp->mutex);
5455
c2e53b2c
YH		 5456 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5457 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5458 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5459 if (err)
5460 goto out;
5461 qp->state = raw_packet_qp_state;
5462 qp_attr->port_num = 1;
5463 } else {
5464 err = query_qp_attr(dev, qp, qp_attr);
5465 if (err)
5466 goto out;
5467 }
5468
5469 qp_attr->qp_state = qp->state;
e126ba97
EC		 5470 qp_attr->cur_qp_state = qp_attr->qp_state;
5471 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5472 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5473
5474 if (!ibqp->uobject) {
0540d814 5475 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5476 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5477 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5478 } else {
5479 qp_attr->cap.max_send_wr = 0;
5480 qp_attr->cap.max_send_sge = 0;
5481 }
5482
0540d814
NO		 5483 qp_init_attr->qp_type = ibqp->qp_type;
5484 qp_init_attr->recv_cq = ibqp->recv_cq;
5485 qp_init_attr->send_cq = ibqp->send_cq;
5486 qp_init_attr->srq = ibqp->srq;
5487 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5488
5489 qp_init_attr->cap = qp_attr->cap;
5490
5491 qp_init_attr->create_flags = 0;
5492 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5493 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5494
051f2630
LR		 5495 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5496 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5497 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5498 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5499 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5500 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5501 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5502 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5503
e126ba97
EC		 5504 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5505 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5506
e126ba97
EC		 5507out:
5508 mutex_unlock(&qp->mutex);
5509 return err;
5510}
5511
5512struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5513 struct ib_ucontext *context,
5514 struct ib_udata *udata)
5515{
5516 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5517 struct mlx5_ib_xrcd *xrcd;
5518 int err;
5519
938fe83c 5520 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5521 return ERR_PTR(-ENOSYS);
5522
5523 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5524 if (!xrcd)
5525 return ERR_PTR(-ENOMEM);
5526
5aa3771d 5527 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
e126ba97
EC		 5528 if (err) {
5529 kfree(xrcd);
5530 return ERR_PTR(-ENOMEM);
5531 }
5532
5533 return &xrcd->ibxrcd;
5534}
5535
5536int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5537{
5538 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5539 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5540 int err;
5541
5aa3771d 5542 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
b081808a 5543 if (err)
e126ba97 5544 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5545
5546 kfree(xrcd);
e126ba97
EC		 5547 return 0;
5548}
79b20a6c 5549
350d0e4c
YH		 5550static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5551{
5552 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5553 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5554 struct ib_event event;
5555
5556 if (rwq->ibwq.event_handler) {
5557 event.device = rwq->ibwq.device;
5558 event.element.wq = &rwq->ibwq;
5559 switch (type) {
5560 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5561 event.event = IB_EVENT_WQ_FATAL;
5562 break;
5563 default:
5564 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5565 return;
5566 }
5567
5568 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5569 }
5570}
5571
03404e8a
MG		 5572static int set_delay_drop(struct mlx5_ib_dev *dev)
5573{
5574 int err = 0;
5575
5576 mutex_lock(&dev->delay_drop.lock);
5577 if (dev->delay_drop.activate)
5578 goto out;
5579
5580 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5581 if (err)
5582 goto out;
5583
5584 dev->delay_drop.activate = true;
5585out:
5586 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5587
5588 if (!err)
5589 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5590 return err;
5591}
5592
79b20a6c
YH		 5593static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5594 struct ib_wq_init_attr *init_attr)
5595{
5596 struct mlx5_ib_dev *dev;
4be6da1e 5597 int has_net_offloads;
79b20a6c
YH		 5598 __be64 *rq_pas0;
5599 void *in;
5600 void *rqc;
5601 void *wq;
5602 int inlen;
5603 int err;
5604
5605 dev = to_mdev(pd->device);
5606
5607 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5608 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5609 if (!in)
5610 return -ENOMEM;
5611
34d57585 5612 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 5613 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5614 MLX5_SET(rqc, rqc, mem_rq_type,
5615 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5616 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5617 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5618 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5619 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5620 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5621 MLX5_SET(wq, wq, wq_type,
5622 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5623 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5624 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5625 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5626 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5627 err = -EOPNOTSUPP;
5628 goto out;
5629 } else {
5630 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5631 }
5632 }
79b20a6c 5633 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5634 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5635 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5636 MLX5_SET(wq, wq, log_wqe_stride_size,
5637 rwq->single_stride_log_num_of_bytes -
5638 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5639 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5640 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5641 }
79b20a6c
YH		 5642 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5643 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5644 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5645 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5646 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5647 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5648 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5649 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5650 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5651 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5652 err = -EOPNOTSUPP;
5653 goto out;
5654 }
5655 } else {
5656 MLX5_SET(rqc, rqc, vsd, 1);
5657 }
4be6da1e
NO		 5658 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5659 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5660 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5661 err = -EOPNOTSUPP;
5662 goto out;
5663 }
5664 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5665 }
03404e8a
MG		 5666 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5667 if (!(dev->ib_dev.attrs.raw_packet_caps &
5668 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5669 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5670 err = -EOPNOTSUPP;
5671 goto out;
5672 }
5673 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5674 }
79b20a6c
YH		 5675 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5676 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5677 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5678 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5679 err = set_delay_drop(dev);
5680 if (err) {
5681 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5682 err);
5683 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5684 } else {
5685 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5686 }
5687 }
b1f74a84 5688out:
79b20a6c
YH		 5689 kvfree(in);
5690 return err;
5691}
5692
5693static int set_user_rq_size(struct mlx5_ib_dev *dev,
5694 struct ib_wq_init_attr *wq_init_attr,
5695 struct mlx5_ib_create_wq *ucmd,
5696 struct mlx5_ib_rwq *rwq)
5697{
5698 /* Sanity check RQ size before proceeding */
5699 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5700 return -EINVAL;
5701
5702 if (!ucmd->rq_wqe_count)
5703 return -EINVAL;
5704
5705 rwq->wqe_count = ucmd->rq_wqe_count;
5706 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 5707 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5708 return -EINVAL;
5709
79b20a6c
YH		 5710 rwq->log_rq_stride = rwq->wqe_shift;
5711 rwq->log_rq_size = ilog2(rwq->wqe_count);
5712 return 0;
5713}
5714
5715static int prepare_user_rq(struct ib_pd *pd,
5716 struct ib_wq_init_attr *init_attr,
5717 struct ib_udata *udata,
5718 struct mlx5_ib_rwq *rwq)
5719{
5720 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5721 struct mlx5_ib_create_wq ucmd = {};
5722 int err;
5723 size_t required_cmd_sz;
5724
ccc87087
NO		 5725 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5726 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5727 if (udata->inlen < required_cmd_sz) {
5728 mlx5_ib_dbg(dev, "invalid inlen\n");
5729 return -EINVAL;
5730 }
5731
5732 if (udata->inlen > sizeof(ucmd) &&
5733 !ib_is_udata_cleared(udata, sizeof(ucmd),
5734 udata->inlen - sizeof(ucmd))) {
5735 mlx5_ib_dbg(dev, "inlen is not supported\n");
5736 return -EOPNOTSUPP;
5737 }
5738
5739 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5740 mlx5_ib_dbg(dev, "copy failed\n");
5741 return -EFAULT;
5742 }
5743
ccc87087 5744 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5745 mlx5_ib_dbg(dev, "invalid comp mask\n");
5746 return -EOPNOTSUPP;
ccc87087
NO		 5747 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5748 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5749 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5750 return -EOPNOTSUPP;
5751 }
5752 if ((ucmd.single_stride_log_num_of_bytes <
5753 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5754 (ucmd.single_stride_log_num_of_bytes >
5755 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5756 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5757 ucmd.single_stride_log_num_of_bytes,
5758 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5759 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5760 return -EINVAL;
5761 }
5762 if ((ucmd.single_wqe_log_num_of_strides >
5763 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5764 (ucmd.single_wqe_log_num_of_strides <
5765 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5766 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5767 ucmd.single_wqe_log_num_of_strides,
5768 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5769 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5770 return -EINVAL;
5771 }
5772 rwq->single_stride_log_num_of_bytes =
5773 ucmd.single_stride_log_num_of_bytes;
5774 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5775 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5776 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5777 }
5778
5779 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5780 if (err) {
5781 mlx5_ib_dbg(dev, "err %d\n", err);
5782 return err;
5783 }
5784
5785 err = create_user_rq(dev, pd, rwq, &ucmd);
5786 if (err) {
5787 mlx5_ib_dbg(dev, "err %d\n", err);
645ba597 5788 return err;
79b20a6c
YH		 5789 }
5790
5791 rwq->user_index = ucmd.user_index;
5792 return 0;
5793}
5794
5795struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5796 struct ib_wq_init_attr *init_attr,
5797 struct ib_udata *udata)
5798{
5799 struct mlx5_ib_dev *dev;
5800 struct mlx5_ib_rwq *rwq;
5801 struct mlx5_ib_create_wq_resp resp = {};
5802 size_t min_resp_len;
5803 int err;
5804
5805 if (!udata)
5806 return ERR_PTR(-ENOSYS);
5807
5808 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5809 if (udata->outlen && udata->outlen < min_resp_len)
5810 return ERR_PTR(-EINVAL);
5811
5812 dev = to_mdev(pd->device);
5813 switch (init_attr->wq_type) {
5814 case IB_WQT_RQ:
5815 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5816 if (!rwq)
5817 return ERR_PTR(-ENOMEM);
5818 err = prepare_user_rq(pd, init_attr, udata, rwq);
5819 if (err)
5820 goto err;
5821 err = create_rq(rwq, pd, init_attr);
5822 if (err)
5823 goto err_user_rq;
5824 break;
5825 default:
5826 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5827 init_attr->wq_type);
5828 return ERR_PTR(-EINVAL);
5829 }
5830
350d0e4c 5831 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5832 rwq->ibwq.state = IB_WQS_RESET;
5833 if (udata->outlen) {
5834 resp.response_length = offsetof(typeof(resp), response_length) +
5835 sizeof(resp.response_length);
5836 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5837 if (err)
5838 goto err_copy;
5839 }
5840
350d0e4c
YH		 5841 rwq->core_qp.event = mlx5_ib_wq_event;
5842 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5843 return &rwq->ibwq;
5844
5845err_copy:
350d0e4c 5846 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5847err_user_rq:
fe248c3a 5848 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5849err:
5850 kfree(rwq);
5851 return ERR_PTR(err);
5852}
5853
5854int mlx5_ib_destroy_wq(struct ib_wq *wq)
5855{
5856 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5857 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5858
350d0e4c 5859 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5860 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5861 kfree(rwq);
5862
5863 return 0;
5864}
5865
c5f90929
YH		 5866struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5867 struct ib_rwq_ind_table_init_attr *init_attr,
5868 struct ib_udata *udata)
5869{
5870 struct mlx5_ib_dev *dev = to_mdev(device);
5871 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5872 int sz = 1 << init_attr->log_ind_tbl_size;
5873 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5874 size_t min_resp_len;
5875 int inlen;
5876 int err;
5877 int i;
5878 u32 *in;
5879 void *rqtc;
5880
5881 if (udata->inlen > 0 &&
5882 !ib_is_udata_cleared(udata, 0,
5883 udata->inlen))
5884 return ERR_PTR(-EOPNOTSUPP);
5885
efd7f400
MG		 5886 if (init_attr->log_ind_tbl_size >
5887 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5888 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5889 init_attr->log_ind_tbl_size,
5890 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5891 return ERR_PTR(-EINVAL);
5892 }
5893
c5f90929
YH		 5894 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5895 if (udata->outlen && udata->outlen < min_resp_len)
5896 return ERR_PTR(-EINVAL);
5897
5898 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5899 if (!rwq_ind_tbl)
5900 return ERR_PTR(-ENOMEM);
5901
5902 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5903 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5904 if (!in) {
5905 err = -ENOMEM;
5906 goto err;
5907 }
5908
5909 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5910
5911 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5912 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5913
5914 for (i = 0; i < sz; i++)
5915 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5916
5deba86e
YH		 5917 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5918 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5919
c5f90929
YH		 5920 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5921 kvfree(in);
5922
5923 if (err)
5924 goto err;
5925
5926 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5927 if (udata->outlen) {
5928 resp.response_length = offsetof(typeof(resp), response_length) +
5929 sizeof(resp.response_length);
5930 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5931 if (err)
5932 goto err_copy;
5933 }
5934
5935 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5936
5937err_copy:
5deba86e 5938 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5939err:
5940 kfree(rwq_ind_tbl);
5941 return ERR_PTR(err);
5942}
5943
5944int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5945{
5946 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5947 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5948
5deba86e 5949 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5950
5951 kfree(rwq_ind_tbl);
5952 return 0;
5953}
5954
79b20a6c
YH		 5955int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5956 u32 wq_attr_mask, struct ib_udata *udata)
5957{
5958 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5959 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5960 struct mlx5_ib_modify_wq ucmd = {};
5961 size_t required_cmd_sz;
5962 int curr_wq_state;
5963 int wq_state;
5964 int inlen;
5965 int err;
5966 void *rqc;
5967 void *in;
5968
5969 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5970 if (udata->inlen < required_cmd_sz)
5971 return -EINVAL;
5972
5973 if (udata->inlen > sizeof(ucmd) &&
5974 !ib_is_udata_cleared(udata, sizeof(ucmd),
5975 udata->inlen - sizeof(ucmd)))
5976 return -EOPNOTSUPP;
5977
5978 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5979 return -EFAULT;
5980
5981 if (ucmd.comp_mask || ucmd.reserved)
5982 return -EOPNOTSUPP;
5983
5984 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5985 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5986 if (!in)
5987 return -ENOMEM;
5988
5989 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5990
5991 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5992 wq_attr->curr_wq_state : wq->state;
5993 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5994 wq_attr->wq_state : curr_wq_state;
5995 if (curr_wq_state == IB_WQS_ERR)
5996 curr_wq_state = MLX5_RQC_STATE_ERR;
5997 if (wq_state == IB_WQS_ERR)
5998 wq_state = MLX5_RQC_STATE_ERR;
5999 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 6000 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 6001 MLX5_SET(rqc, rqc, state, wq_state);
6002
b1f74a84
NO		 6003 if (wq_attr_mask & IB_WQ_FLAGS) {
6004 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6005 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6006 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6007 mlx5_ib_dbg(dev, "VLAN offloads are not "
6008 "supported\n");
6009 err = -EOPNOTSUPP;
6010 goto out;
6011 }
6012 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6013 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6014 MLX5_SET(rqc, rqc, vsd,
6015 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6016 }
b1383aa6
NO		 6017
6018 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6019 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6020 err = -EOPNOTSUPP;
6021 goto out;
6022 }
b1f74a84
NO		 6023 }
6024
23a6964e
MD		 6025 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6026 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6027 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6028 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 6029 MLX5_SET(rqc, rqc, counter_set_id,
6030 dev->port->cnts.set_id);
23a6964e 6031 } else
5a738b5d
JG		 6032 dev_info_once(
6033 &dev->ib_dev.dev,
6034 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 6035 }
6036
350d0e4c 6037 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 6038 if (!err)
6039 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6040
b1f74a84
NO		 6041out:
6042 kvfree(in);
79b20a6c
YH		 6043 return err;
6044}
d0e84c0a
YH		 6045
6046struct mlx5_ib_drain_cqe {
6047 struct ib_cqe cqe;
6048 struct completion done;
6049};
6050
6051static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6052{
6053 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6054 struct mlx5_ib_drain_cqe,
6055 cqe);
6056
6057 complete(&cqe->done);
6058}
6059
6060/* This function returns only once the drained WR was completed */
6061static void handle_drain_completion(struct ib_cq *cq,
6062 struct mlx5_ib_drain_cqe *sdrain,
6063 struct mlx5_ib_dev *dev)
6064{
6065 struct mlx5_core_dev *mdev = dev->mdev;
6066
6067 if (cq->poll_ctx == IB_POLL_DIRECT) {
6068 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6069 ib_process_cq_direct(cq, -1);
6070 return;
6071 }
6072
6073 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6074 struct mlx5_ib_cq *mcq = to_mcq(cq);
6075 bool triggered = false;
6076 unsigned long flags;
6077
6078 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6079 /* Make sure that the CQ handler won't run if wasn't run yet */
6080 if (!mcq->mcq.reset_notify_added)
6081 mcq->mcq.reset_notify_added = 1;
6082 else
6083 triggered = true;
6084 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6085
6086 if (triggered) {
6087 /* Wait for any scheduled/running task to be ended */
6088 switch (cq->poll_ctx) {
6089 case IB_POLL_SOFTIRQ:
6090 irq_poll_disable(&cq->iop);
6091 irq_poll_enable(&cq->iop);
6092 break;
6093 case IB_POLL_WORKQUEUE:
6094 cancel_work_sync(&cq->work);
6095 break;
6096 default:
6097 WARN_ON_ONCE(1);
6098 }
6099 }
6100
6101 /* Run the CQ handler - this makes sure that the drain WR will
6102 * be processed if wasn't processed yet.
6103 */
6104 mcq->mcq.comp(&mcq->mcq);
6105 }
6106
6107 wait_for_completion(&sdrain->done);
6108}
6109
6110void mlx5_ib_drain_sq(struct ib_qp *qp)
6111{
6112 struct ib_cq *cq = qp->send_cq;
6113 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6114 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 6115 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 6116 struct ib_rdma_wr swr = {
6117 .wr = {
6118 .next = NULL,
6119 { .wr_cqe = &sdrain.cqe, },
6120 .opcode = IB_WR_RDMA_WRITE,
6121 },
6122 };
6123 int ret;
6124 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6125 struct mlx5_core_dev *mdev = dev->mdev;
6126
6127 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6128 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6129 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6130 return;
6131 }
6132
6133 sdrain.cqe.done = mlx5_ib_drain_qp_done;
6134 init_completion(&sdrain.done);
6135
6136 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6137 if (ret) {
6138 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6139 return;
6140 }
6141
6142 handle_drain_completion(cq, &sdrain, dev);
6143}
6144
6145void mlx5_ib_drain_rq(struct ib_qp *qp)
6146{
6147 struct ib_cq *cq = qp->recv_cq;
6148 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6149 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 6150 struct ib_recv_wr rwr = {};
6151 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 6152 int ret;
6153 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6154 struct mlx5_core_dev *mdev = dev->mdev;
6155
6156 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6157 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6158 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6159 return;
6160 }
6161
6162 rwr.wr_cqe = &rdrain.cqe;
6163 rdrain.cqe.done = mlx5_ib_drain_qp_done;
6164 init_completion(&rdrain.done);
6165
6166 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6167 if (ret) {
6168 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6169 return;
6170 }
6171
6172 handle_drain_completion(cq, &rdrain, dev);
6173}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git