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{net, IB}/mlx5: Refactor internal SRQ API
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97 79
89ea94a7
MG		 80static void get_cqs(enum ib_qp_type qp_type,
81 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
82 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
83
e126ba97
EC		 84static int is_qp0(enum ib_qp_type qp_type)
85{
86 return qp_type == IB_QPT_SMI;
87}
88
e126ba97
EC		 89static int is_sqp(enum ib_qp_type qp_type)
90{
91 return is_qp0(qp_type) || is_qp1(qp_type);
92}
93
94static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
95{
96 return mlx5_buf_offset(&qp->buf, offset);
97}
98
99static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
100{
101 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
102}
103
104void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
105{
106 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
107}
108
c1395a2a
HE		 109/**
110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
111 *
112 * @qp: QP to copy from.
113 * @send: copy from the send queue when non-zero, use the receive queue
114 * otherwise.
115 * @wqe_index: index to start copying from. For send work queues, the
116 * wqe_index is in units of MLX5_SEND_WQE_BB.
117 * For receive work queue, it is the number of work queue
118 * element in the queue.
119 * @buffer: destination buffer.
120 * @length: maximum number of bytes to copy.
121 *
122 * Copies at least a single WQE, but may copy more data.
123 *
124 * Return: the number of bytes copied, or an error code.
125 */
126int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 127 void *buffer, u32 length,
128 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 129{
130 struct ib_device *ibdev = qp->ibqp.device;
131 struct mlx5_ib_dev *dev = to_mdev(ibdev);
132 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
133 size_t offset;
134 size_t wq_end;
19098df2 135 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 136 u32 first_copy_length;
137 int wqe_length;
138 int ret;
139
140 if (wq->wqe_cnt == 0) {
141 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
142 qp->ibqp.qp_type);
143 return -EINVAL;
144 }
145
146 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
147 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
148
149 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
150 return -EINVAL;
151
152 if (offset > umem->length ||
153 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
154 return -EINVAL;
155
156 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
157 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
158 if (ret)
159 return ret;
160
161 if (send) {
162 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
163 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
164
165 wqe_length = ds * MLX5_WQE_DS_UNITS;
166 } else {
167 wqe_length = 1 << wq->wqe_shift;
168 }
169
170 if (wqe_length <= first_copy_length)
171 return first_copy_length;
172
173 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
174 wqe_length - first_copy_length);
175 if (ret)
176 return ret;
177
178 return wqe_length;
179}
180
e126ba97
EC		 181static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
182{
183 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
184 struct ib_event event;
185
19098df2 186 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
187 /* This event is only valid for trans_qps */
188 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
189 }
e126ba97
EC		 190
191 if (ibqp->event_handler) {
192 event.device = ibqp->device;
193 event.element.qp = ibqp;
194 switch (type) {
195 case MLX5_EVENT_TYPE_PATH_MIG:
196 event.event = IB_EVENT_PATH_MIG;
197 break;
198 case MLX5_EVENT_TYPE_COMM_EST:
199 event.event = IB_EVENT_COMM_EST;
200 break;
201 case MLX5_EVENT_TYPE_SQ_DRAINED:
202 event.event = IB_EVENT_SQ_DRAINED;
203 break;
204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
205 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
206 break;
207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
208 event.event = IB_EVENT_QP_FATAL;
209 break;
210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
211 event.event = IB_EVENT_PATH_MIG_ERR;
212 break;
213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
214 event.event = IB_EVENT_QP_REQ_ERR;
215 break;
216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
217 event.event = IB_EVENT_QP_ACCESS_ERR;
218 break;
219 default:
220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
221 return;
222 }
223
224 ibqp->event_handler(&event, ibqp->qp_context);
225 }
226}
227
228static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
229 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
230{
231 int wqe_size;
232 int wq_size;
233
234 /* Sanity check RQ size before proceeding */
938fe83c 235 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 236 return -EINVAL;
237
238 if (!has_rq) {
239 qp->rq.max_gs = 0;
240 qp->rq.wqe_cnt = 0;
241 qp->rq.wqe_shift = 0;
0540d814
NO		 242 cap->max_recv_wr = 0;
243 cap->max_recv_sge = 0;
e126ba97
EC		 244 } else {
245 if (ucmd) {
246 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
247 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
248 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
249 qp->rq.max_post = qp->rq.wqe_cnt;
250 } else {
251 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
252 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
253 wqe_size = roundup_pow_of_two(wqe_size);
254 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
255 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
256 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 257 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 258 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
259 wqe_size,
938fe83c
SM		 260 MLX5_CAP_GEN(dev->mdev,
261 max_wqe_sz_rq));
e126ba97
EC		 262 return -EINVAL;
263 }
264 qp->rq.wqe_shift = ilog2(wqe_size);
265 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
266 qp->rq.max_post = qp->rq.wqe_cnt;
267 }
268 }
269
270 return 0;
271}
272
f0313965 273static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 274{
618af384 275 int size = 0;
e126ba97 276
f0313965 277 switch (attr->qp_type) {
e126ba97 278 case IB_QPT_XRC_INI:
b125a54b 279 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 280 /* fall through */
281 case IB_QPT_RC:
282 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 283 max(sizeof(struct mlx5_wqe_atomic_seg) +
284 sizeof(struct mlx5_wqe_raddr_seg),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
286 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 287 break;
288
b125a54b
EC		 289 case IB_QPT_XRC_TGT:
290 return 0;
291
e126ba97 292 case IB_QPT_UC:
b125a54b 293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_raddr_seg),
295 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
296 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 297 break;
298
299 case IB_QPT_UD:
f0313965
ES		 300 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
301 size += sizeof(struct mlx5_wqe_eth_pad) +
302 sizeof(struct mlx5_wqe_eth_seg);
303 /* fall through */
e126ba97 304 case IB_QPT_SMI:
d16e91da 305 case MLX5_IB_QPT_HW_GSI:
b125a54b 306 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 307 sizeof(struct mlx5_wqe_datagram_seg);
308 break;
309
310 case MLX5_IB_QPT_REG_UMR:
b125a54b 311 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 312 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
313 sizeof(struct mlx5_mkey_seg);
314 break;
315
316 default:
317 return -EINVAL;
318 }
319
320 return size;
321}
322
323static int calc_send_wqe(struct ib_qp_init_attr *attr)
324{
325 int inl_size = 0;
326 int size;
327
f0313965 328 size = sq_overhead(attr);
e126ba97
EC		 329 if (size < 0)
330 return size;
331
332 if (attr->cap.max_inline_data) {
333 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
334 attr->cap.max_inline_data;
335 }
336
337 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 338 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
339 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
340 return MLX5_SIG_WQE_SIZE;
341 else
342 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 343}
344
345static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
346 struct mlx5_ib_qp *qp)
347{
348 int wqe_size;
349 int wq_size;
350
351 if (!attr->cap.max_send_wr)
352 return 0;
353
354 wqe_size = calc_send_wqe(attr);
355 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
356 if (wqe_size < 0)
357 return wqe_size;
358
938fe83c 359 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 360 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 361 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 362 return -EINVAL;
363 }
364
f0313965
ES		 365 qp->max_inline_data = wqe_size - sq_overhead(attr) -
366 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 367 attr->cap.max_inline_data = qp->max_inline_data;
368
e1e66cc2
SG		 369 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
370 qp->signature_en = true;
371
e126ba97
EC		 372 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
373 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 374 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 375 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 376 qp->sq.wqe_cnt,
377 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 378 return -ENOMEM;
379 }
e126ba97
EC		 380 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
381 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 382 qp->sq.max_post = wq_size / wqe_size;
383 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 384
385 return wq_size;
386}
387
388static int set_user_buf_size(struct mlx5_ib_dev *dev,
389 struct mlx5_ib_qp *qp,
19098df2 390 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 391 struct mlx5_ib_qp_base *base,
392 struct ib_qp_init_attr *attr)
e126ba97
EC		 393{
394 int desc_sz = 1 << qp->sq.wqe_shift;
395
938fe83c 396 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 397 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 398 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 399 return -EINVAL;
400 }
401
402 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
403 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
404 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
405 return -EINVAL;
406 }
407
408 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
409
938fe83c 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 411 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 414 return -EINVAL;
415 }
416
0fb2ed66 417 if (attr->qp_type == IB_QPT_RAW_PACKET) {
418 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
419 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
420 } else {
421 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
422 (qp->sq.wqe_cnt << 6);
423 }
e126ba97
EC		 424
425 return 0;
426}
427
428static int qp_has_rq(struct ib_qp_init_attr *attr)
429{
430 if (attr->qp_type == IB_QPT_XRC_INI ||
431 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
432 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
433 !attr->cap.max_recv_wr)
434 return 0;
435
436 return 1;
437}
438
c1be5232
EC		 439static int first_med_uuar(void)
440{
441 return 1;
442}
443
444static int next_uuar(int n)
445{
446 n++;
447
448 while (((n % 4) & 2))
449 n++;
450
451 return n;
452}
453
454static int num_med_uuar(struct mlx5_uuar_info *uuari)
455{
456 int n;
457
458 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
459 uuari->num_low_latency_uuars - 1;
460
461 return n >= 0 ? n : 0;
462}
463
464static int max_uuari(struct mlx5_uuar_info *uuari)
465{
466 return uuari->num_uars * 4;
467}
468
469static int first_hi_uuar(struct mlx5_uuar_info *uuari)
470{
471 int med;
472 int i;
473 int t;
474
475 med = num_med_uuar(uuari);
476 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
477 t++;
478 if (t == med)
479 return next_uuar(i);
480 }
481
482 return 0;
483}
484
e126ba97
EC		 485static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
486{
e126ba97
EC		 487 int i;
488
c1be5232 489 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 490 if (!test_bit(i, uuari->bitmap)) {
491 set_bit(i, uuari->bitmap);
492 uuari->count[i]++;
493 return i;
494 }
495 }
496
497 return -ENOMEM;
498}
499
500static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
501{
c1be5232 502 int minidx = first_med_uuar();
e126ba97
EC		 503 int i;
504
c1be5232 505 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 506 if (uuari->count[i] < uuari->count[minidx])
507 minidx = i;
508 }
509
510 uuari->count[minidx]++;
511 return minidx;
512}
513
514static int alloc_uuar(struct mlx5_uuar_info *uuari,
515 enum mlx5_ib_latency_class lat)
516{
517 int uuarn = -EINVAL;
518
519 mutex_lock(&uuari->lock);
520 switch (lat) {
521 case MLX5_IB_LATENCY_CLASS_LOW:
522 uuarn = 0;
523 uuari->count[uuarn]++;
524 break;
525
526 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 527 if (uuari->ver < 2)
528 uuarn = -ENOMEM;
529 else
530 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 531 break;
532
533 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 534 if (uuari->ver < 2)
535 uuarn = -ENOMEM;
536 else
537 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 538 break;
539
540 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
541 uuarn = 2;
542 break;
543 }
544 mutex_unlock(&uuari->lock);
545
546 return uuarn;
547}
548
549static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
550{
551 clear_bit(uuarn, uuari->bitmap);
552 --uuari->count[uuarn];
553}
554
555static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
556{
557 clear_bit(uuarn, uuari->bitmap);
558 --uuari->count[uuarn];
559}
560
561static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
562{
563 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
564 int high_uuar = nuuars - uuari->num_low_latency_uuars;
565
566 mutex_lock(&uuari->lock);
567 if (uuarn == 0) {
568 --uuari->count[uuarn];
569 goto out;
570 }
571
572 if (uuarn < high_uuar) {
573 free_med_class_uuar(uuari, uuarn);
574 goto out;
575 }
576
577 free_high_class_uuar(uuari, uuarn);
578
579out:
580 mutex_unlock(&uuari->lock);
581}
582
583static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
584{
585 switch (state) {
586 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
587 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
588 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
589 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
590 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
591 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
592 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
593 default: return -1;
594 }
595}
596
597static int to_mlx5_st(enum ib_qp_type type)
598{
599 switch (type) {
600 case IB_QPT_RC: return MLX5_QP_ST_RC;
601 case IB_QPT_UC: return MLX5_QP_ST_UC;
602 case IB_QPT_UD: return MLX5_QP_ST_UD;
603 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
604 case IB_QPT_XRC_INI:
605 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
606 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 607 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 608 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 609 case IB_QPT_RAW_PACKET:
0fb2ed66 610 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 611 case IB_QPT_MAX:
612 default: return -EINVAL;
613 }
614}
615
89ea94a7
MG		 616static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
618static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
619 struct mlx5_ib_cq *recv_cq);
620
e126ba97
EC		 621static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
622{
623 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
624}
625
19098df2 626static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
627 struct ib_pd *pd,
628 unsigned long addr, size_t size,
629 struct ib_umem **umem,
630 int *npages, int *page_shift, int *ncont,
631 u32 *offset)
632{
633 int err;
634
635 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
636 if (IS_ERR(*umem)) {
637 mlx5_ib_dbg(dev, "umem_get failed\n");
638 return PTR_ERR(*umem);
639 }
640
641 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
642
643 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
644 if (err) {
645 mlx5_ib_warn(dev, "bad offset\n");
646 goto err_umem;
647 }
648
649 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
650 addr, size, *npages, *page_shift, *ncont, *offset);
651
652 return 0;
653
654err_umem:
655 ib_umem_release(*umem);
656 *umem = NULL;
657
658 return err;
659}
660
79b20a6c
YH		 661static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
662{
663 struct mlx5_ib_ucontext *context;
664
665 context = to_mucontext(pd->uobject->context);
666 mlx5_ib_db_unmap_user(context, &rwq->db);
667 if (rwq->umem)
668 ib_umem_release(rwq->umem);
669}
670
671static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
672 struct mlx5_ib_rwq *rwq,
673 struct mlx5_ib_create_wq *ucmd)
674{
675 struct mlx5_ib_ucontext *context;
676 int page_shift = 0;
677 int npages;
678 u32 offset = 0;
679 int ncont = 0;
680 int err;
681
682 if (!ucmd->buf_addr)
683 return -EINVAL;
684
685 context = to_mucontext(pd->uobject->context);
686 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
687 rwq->buf_size, 0, 0);
688 if (IS_ERR(rwq->umem)) {
689 mlx5_ib_dbg(dev, "umem_get failed\n");
690 err = PTR_ERR(rwq->umem);
691 return err;
692 }
693
694 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
695 &ncont, NULL);
696 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
697 &rwq->rq_page_offset);
698 if (err) {
699 mlx5_ib_warn(dev, "bad offset\n");
700 goto err_umem;
701 }
702
703 rwq->rq_num_pas = ncont;
704 rwq->page_shift = page_shift;
705 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
706 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
707
708 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
709 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
710 npages, page_shift, ncont, offset);
711
712 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
713 if (err) {
714 mlx5_ib_dbg(dev, "map failed\n");
715 goto err_umem;
716 }
717
718 rwq->create_type = MLX5_WQ_USER;
719 return 0;
720
721err_umem:
722 ib_umem_release(rwq->umem);
723 return err;
724}
725
e126ba97
EC		 726static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
727 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 728 struct ib_qp_init_attr *attr,
e126ba97 729 struct mlx5_create_qp_mbox_in **in,
19098df2 730 struct mlx5_ib_create_qp_resp *resp, int *inlen,
731 struct mlx5_ib_qp_base *base)
e126ba97
EC		 732{
733 struct mlx5_ib_ucontext *context;
734 struct mlx5_ib_create_qp ucmd;
19098df2 735 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 736 int page_shift = 0;
e126ba97
EC		 737 int uar_index;
738 int npages;
9e9c47d0 739 u32 offset = 0;
e126ba97 740 int uuarn;
9e9c47d0 741 int ncont = 0;
e126ba97
EC		 742 int err;
743
744 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
745 if (err) {
746 mlx5_ib_dbg(dev, "copy failed\n");
747 return err;
748 }
749
750 context = to_mucontext(pd->uobject->context);
751 /*
752 * TBD: should come from the verbs when we have the API
753 */
051f2630
LR		 754 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
755 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
756 uuarn = MLX5_CROSS_CHANNEL_UUAR;
757 else {
758 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 759 if (uuarn < 0) {
051f2630
LR		 760 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
761 mlx5_ib_dbg(dev, "reverting to medium latency\n");
762 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 763 if (uuarn < 0) {
051f2630
LR		 764 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
765 mlx5_ib_dbg(dev, "reverting to high latency\n");
766 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
767 if (uuarn < 0) {
768 mlx5_ib_warn(dev, "uuar allocation failed\n");
769 return uuarn;
770 }
c1be5232 771 }
e126ba97
EC		 772 }
773 }
774
775 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
776 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
777
48fea837
HE		 778 qp->rq.offset = 0;
779 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
780 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
781
0fb2ed66 782 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 783 if (err)
784 goto err_uuar;
785
19098df2 786 if (ucmd.buf_addr && ubuffer->buf_size) {
787 ubuffer->buf_addr = ucmd.buf_addr;
788 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
789 ubuffer->buf_size,
790 &ubuffer->umem, &npages, &page_shift,
791 &ncont, &offset);
792 if (err)
9e9c47d0 793 goto err_uuar;
9e9c47d0 794 } else {
19098df2 795 ubuffer->umem = NULL;
e126ba97 796 }
e126ba97
EC		 797
798 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
799 *in = mlx5_vzalloc(*inlen);
800 if (!*in) {
801 err = -ENOMEM;
802 goto err_umem;
803 }
19098df2 804 if (ubuffer->umem)
805 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
806 (*in)->pas, 0);
e126ba97 807 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 808 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 809 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
810
811 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
812 resp->uuar_index = uuarn;
813 qp->uuarn = uuarn;
814
815 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
816 if (err) {
817 mlx5_ib_dbg(dev, "map failed\n");
818 goto err_free;
819 }
820
821 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
822 if (err) {
823 mlx5_ib_dbg(dev, "copy failed\n");
824 goto err_unmap;
825 }
826 qp->create_type = MLX5_QP_USER;
827
828 return 0;
829
830err_unmap:
831 mlx5_ib_db_unmap_user(context, &qp->db);
832
833err_free:
479163f4 834 kvfree(*in);
e126ba97
EC		 835
836err_umem:
19098df2 837 if (ubuffer->umem)
838 ib_umem_release(ubuffer->umem);
e126ba97
EC		 839
840err_uuar:
841 free_uuar(&context->uuari, uuarn);
842 return err;
843}
844
19098df2 845static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
846 struct mlx5_ib_qp_base *base)
e126ba97
EC		 847{
848 struct mlx5_ib_ucontext *context;
849
850 context = to_mucontext(pd->uobject->context);
851 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 852 if (base->ubuffer.umem)
853 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 854 free_uuar(&context->uuari, qp->uuarn);
855}
856
857static int create_kernel_qp(struct mlx5_ib_dev *dev,
858 struct ib_qp_init_attr *init_attr,
859 struct mlx5_ib_qp *qp,
19098df2 860 struct mlx5_create_qp_mbox_in **in, int *inlen,
861 struct mlx5_ib_qp_base *base)
e126ba97
EC		 862{
863 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
864 struct mlx5_uuar_info *uuari;
865 int uar_index;
866 int uuarn;
867 int err;
868
9603b61d 869 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 870 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
871 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 872 IB_QP_CREATE_IPOIB_UD_LSO |
873 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 874 return -EINVAL;
e126ba97
EC		 875
876 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
877 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
878
879 uuarn = alloc_uuar(uuari, lc);
880 if (uuarn < 0) {
881 mlx5_ib_dbg(dev, "\n");
882 return -ENOMEM;
883 }
884
885 qp->bf = &uuari->bfs[uuarn];
886 uar_index = qp->bf->uar->index;
887
888 err = calc_sq_size(dev, init_attr, qp);
889 if (err < 0) {
890 mlx5_ib_dbg(dev, "err %d\n", err);
891 goto err_uuar;
892 }
893
894 qp->rq.offset = 0;
895 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 896 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 897
19098df2 898 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 899 if (err) {
900 mlx5_ib_dbg(dev, "err %d\n", err);
901 goto err_uuar;
902 }
903
904 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
905 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
906 *in = mlx5_vzalloc(*inlen);
907 if (!*in) {
908 err = -ENOMEM;
909 goto err_buf;
910 }
911 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 912 (*in)->ctx.log_pg_sz_remote_qpn =
913 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 914 /* Set "fast registration enabled" for all kernel QPs */
915 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
916 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
917
b11a4f9c
HE		 918 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
919 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
920 qp->flags |= MLX5_IB_QP_SQPN_QP1;
921 }
922
e126ba97
EC		 923 mlx5_fill_page_array(&qp->buf, (*in)->pas);
924
9603b61d 925 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 926 if (err) {
927 mlx5_ib_dbg(dev, "err %d\n", err);
928 goto err_free;
929 }
930
e126ba97
EC		 931 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
932 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
933 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
934 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
935 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
936
937 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
938 !qp->sq.w_list || !qp->sq.wqe_head) {
939 err = -ENOMEM;
940 goto err_wrid;
941 }
942 qp->create_type = MLX5_QP_KERNEL;
943
944 return 0;
945
946err_wrid:
9603b61d 947 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 948 kfree(qp->sq.wqe_head);
949 kfree(qp->sq.w_list);
950 kfree(qp->sq.wrid);
951 kfree(qp->sq.wr_data);
952 kfree(qp->rq.wrid);
953
954err_free:
479163f4 955 kvfree(*in);
e126ba97
EC		 956
957err_buf:
9603b61d 958 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 959
960err_uuar:
9603b61d 961 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 962 return err;
963}
964
965static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
966{
9603b61d 967 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 968 kfree(qp->sq.wqe_head);
969 kfree(qp->sq.w_list);
970 kfree(qp->sq.wrid);
971 kfree(qp->sq.wr_data);
972 kfree(qp->rq.wrid);
9603b61d
JM		 973 mlx5_buf_free(dev->mdev, &qp->buf);
974 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 975}
976
977static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
978{
979 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
980 (attr->qp_type == IB_QPT_XRC_INI))
981 return cpu_to_be32(MLX5_SRQ_RQ);
982 else if (!qp->has_rq)
983 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
984 else
985 return cpu_to_be32(MLX5_NON_ZERO_RQ);
986}
987
988static int is_connected(enum ib_qp_type qp_type)
989{
990 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
991 return 1;
992
993 return 0;
994}
995
0fb2ed66 996static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
997 struct mlx5_ib_sq *sq, u32 tdn)
998{
999 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1000 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1001
1002 memset(in, 0, sizeof(in));
1003
1004 MLX5_SET(tisc, tisc, transport_domain, tdn);
1005
1006 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1007}
1008
1009static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1010 struct mlx5_ib_sq *sq)
1011{
1012 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1013}
1014
1015static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1016 struct mlx5_ib_sq *sq, void *qpin,
1017 struct ib_pd *pd)
1018{
1019 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1020 __be64 *pas;
1021 void *in;
1022 void *sqc;
1023 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1024 void *wq;
1025 int inlen;
1026 int err;
1027 int page_shift = 0;
1028 int npages;
1029 int ncont = 0;
1030 u32 offset = 0;
1031
1032 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1033 &sq->ubuffer.umem, &npages, &page_shift,
1034 &ncont, &offset);
1035 if (err)
1036 return err;
1037
1038 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1039 in = mlx5_vzalloc(inlen);
1040 if (!in) {
1041 err = -ENOMEM;
1042 goto err_umem;
1043 }
1044
1045 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1046 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1047 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1048 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1049 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1050 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1051 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1052
1053 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1054 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1055 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1056 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1057 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1058 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1059 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1060 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1061 MLX5_SET(wq, wq, page_offset, offset);
1062
1063 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1064 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1065
1066 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1067
1068 kvfree(in);
1069
1070 if (err)
1071 goto err_umem;
1072
1073 return 0;
1074
1075err_umem:
1076 ib_umem_release(sq->ubuffer.umem);
1077 sq->ubuffer.umem = NULL;
1078
1079 return err;
1080}
1081
1082static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1083 struct mlx5_ib_sq *sq)
1084{
1085 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1086 ib_umem_release(sq->ubuffer.umem);
1087}
1088
1089static int get_rq_pas_size(void *qpc)
1090{
1091 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1092 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1093 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1094 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1095 u32 po_quanta = 1 << (log_page_size - 6);
1096 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1097 u32 page_size = 1 << log_page_size;
1098 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1099 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1100
1101 return rq_num_pas * sizeof(u64);
1102}
1103
1104static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1105 struct mlx5_ib_rq *rq, void *qpin)
1106{
358e42ea 1107 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1108 __be64 *pas;
1109 __be64 *qp_pas;
1110 void *in;
1111 void *rqc;
1112 void *wq;
1113 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1114 int inlen;
1115 int err;
1116 u32 rq_pas_size = get_rq_pas_size(qpc);
1117
1118 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1119 in = mlx5_vzalloc(inlen);
1120 if (!in)
1121 return -ENOMEM;
1122
1123 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1124 MLX5_SET(rqc, rqc, vsd, 1);
1125 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1126 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1127 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1128 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1129 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1130
358e42ea
MD		 1131 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1132 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1133
0fb2ed66 1134 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1135 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1136 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1137 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1138 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1139 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1140 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1141 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1142 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1143 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1144
1145 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1146 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1147 memcpy(pas, qp_pas, rq_pas_size);
1148
1149 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1150
1151 kvfree(in);
1152
1153 return err;
1154}
1155
1156static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1157 struct mlx5_ib_rq *rq)
1158{
1159 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1160}
1161
1162static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1163 struct mlx5_ib_rq *rq, u32 tdn)
1164{
1165 u32 *in;
1166 void *tirc;
1167 int inlen;
1168 int err;
1169
1170 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1171 in = mlx5_vzalloc(inlen);
1172 if (!in)
1173 return -ENOMEM;
1174
1175 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1176 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1177 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1178 MLX5_SET(tirc, tirc, transport_domain, tdn);
1179
1180 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1181
1182 kvfree(in);
1183
1184 return err;
1185}
1186
1187static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1188 struct mlx5_ib_rq *rq)
1189{
1190 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1191}
1192
1193static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1194 struct mlx5_create_qp_mbox_in *in,
1195 struct ib_pd *pd)
1196{
1197 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1198 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1199 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1200 struct ib_uobject *uobj = pd->uobject;
1201 struct ib_ucontext *ucontext = uobj->context;
1202 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1203 int err;
1204 u32 tdn = mucontext->tdn;
1205
1206 if (qp->sq.wqe_cnt) {
1207 err = create_raw_packet_qp_tis(dev, sq, tdn);
1208 if (err)
1209 return err;
1210
1211 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1212 if (err)
1213 goto err_destroy_tis;
1214
1215 sq->base.container_mibqp = qp;
1216 }
1217
1218 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1219 rq->base.container_mibqp = qp;
1220
0fb2ed66 1221 err = create_raw_packet_qp_rq(dev, rq, in);
1222 if (err)
1223 goto err_destroy_sq;
1224
0fb2ed66 1225
1226 err = create_raw_packet_qp_tir(dev, rq, tdn);
1227 if (err)
1228 goto err_destroy_rq;
1229 }
1230
1231 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1232 rq->base.mqp.qpn;
1233
1234 return 0;
1235
1236err_destroy_rq:
1237 destroy_raw_packet_qp_rq(dev, rq);
1238err_destroy_sq:
1239 if (!qp->sq.wqe_cnt)
1240 return err;
1241 destroy_raw_packet_qp_sq(dev, sq);
1242err_destroy_tis:
1243 destroy_raw_packet_qp_tis(dev, sq);
1244
1245 return err;
1246}
1247
1248static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1249 struct mlx5_ib_qp *qp)
1250{
1251 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1252 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1253 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1254
1255 if (qp->rq.wqe_cnt) {
1256 destroy_raw_packet_qp_tir(dev, rq);
1257 destroy_raw_packet_qp_rq(dev, rq);
1258 }
1259
1260 if (qp->sq.wqe_cnt) {
1261 destroy_raw_packet_qp_sq(dev, sq);
1262 destroy_raw_packet_qp_tis(dev, sq);
1263 }
1264}
1265
1266static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1267 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1268{
1269 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1270 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1271
1272 sq->sq = &qp->sq;
1273 rq->rq = &qp->rq;
1274 sq->doorbell = &qp->db;
1275 rq->doorbell = &qp->db;
1276}
1277
28d61370
YH		 1278static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1279{
1280 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1281}
1282
1283static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1284 struct ib_pd *pd,
1285 struct ib_qp_init_attr *init_attr,
1286 struct ib_udata *udata)
1287{
1288 struct ib_uobject *uobj = pd->uobject;
1289 struct ib_ucontext *ucontext = uobj->context;
1290 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1291 struct mlx5_ib_create_qp_resp resp = {};
1292 int inlen;
1293 int err;
1294 u32 *in;
1295 void *tirc;
1296 void *hfso;
1297 u32 selected_fields = 0;
1298 size_t min_resp_len;
1299 u32 tdn = mucontext->tdn;
1300 struct mlx5_ib_create_qp_rss ucmd = {};
1301 size_t required_cmd_sz;
1302
1303 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1304 return -EOPNOTSUPP;
1305
1306 if (init_attr->create_flags || init_attr->send_cq)
1307 return -EINVAL;
1308
1309 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1310 if (udata->outlen < min_resp_len)
1311 return -EINVAL;
1312
1313 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1314 if (udata->inlen < required_cmd_sz) {
1315 mlx5_ib_dbg(dev, "invalid inlen\n");
1316 return -EINVAL;
1317 }
1318
1319 if (udata->inlen > sizeof(ucmd) &&
1320 !ib_is_udata_cleared(udata, sizeof(ucmd),
1321 udata->inlen - sizeof(ucmd))) {
1322 mlx5_ib_dbg(dev, "inlen is not supported\n");
1323 return -EOPNOTSUPP;
1324 }
1325
1326 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1327 mlx5_ib_dbg(dev, "copy failed\n");
1328 return -EFAULT;
1329 }
1330
1331 if (ucmd.comp_mask) {
1332 mlx5_ib_dbg(dev, "invalid comp mask\n");
1333 return -EOPNOTSUPP;
1334 }
1335
1336 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1337 mlx5_ib_dbg(dev, "invalid reserved\n");
1338 return -EOPNOTSUPP;
1339 }
1340
1341 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1342 if (err) {
1343 mlx5_ib_dbg(dev, "copy failed\n");
1344 return -EINVAL;
1345 }
1346
1347 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1348 in = mlx5_vzalloc(inlen);
1349 if (!in)
1350 return -ENOMEM;
1351
1352 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1353 MLX5_SET(tirc, tirc, disp_type,
1354 MLX5_TIRC_DISP_TYPE_INDIRECT);
1355 MLX5_SET(tirc, tirc, indirect_table,
1356 init_attr->rwq_ind_tbl->ind_tbl_num);
1357 MLX5_SET(tirc, tirc, transport_domain, tdn);
1358
1359 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1360 switch (ucmd.rx_hash_function) {
1361 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1362 {
1363 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1364 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1365
1366 if (len != ucmd.rx_key_len) {
1367 err = -EINVAL;
1368 goto err;
1369 }
1370
1371 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1372 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1373 memcpy(rss_key, ucmd.rx_hash_key, len);
1374 break;
1375 }
1376 default:
1377 err = -EOPNOTSUPP;
1378 goto err;
1379 }
1380
1381 if (!ucmd.rx_hash_fields_mask) {
1382 /* special case when this TIR serves as steering entry without hashing */
1383 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1384 goto create_tir;
1385 err = -EINVAL;
1386 goto err;
1387 }
1388
1389 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1390 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1391 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1392 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1393 err = -EINVAL;
1394 goto err;
1395 }
1396
1397 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1398 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1399 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1400 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1401 MLX5_L3_PROT_TYPE_IPV4);
1402 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1403 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1404 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1405 MLX5_L3_PROT_TYPE_IPV6);
1406
1407 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1408 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1409 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1410 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1411 err = -EINVAL;
1412 goto err;
1413 }
1414
1415 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1416 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1417 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1418 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1419 MLX5_L4_PROT_TYPE_TCP);
1420 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1421 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1422 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1423 MLX5_L4_PROT_TYPE_UDP);
1424
1425 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1426 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1427 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1428
1429 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1430 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1431 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1432
1433 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1435 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1436
1437 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1439 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1440
1441 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1442
1443create_tir:
1444 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1445
1446 if (err)
1447 goto err;
1448
1449 kvfree(in);
1450 /* qpn is reserved for that QP */
1451 qp->trans_qp.base.mqp.qpn = 0;
1452 return 0;
1453
1454err:
1455 kvfree(in);
1456 return err;
1457}
1458
e126ba97
EC		 1459static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1460 struct ib_qp_init_attr *init_attr,
1461 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1462{
1463 struct mlx5_ib_resources *devr = &dev->devr;
938fe83c 1464 struct mlx5_core_dev *mdev = dev->mdev;
0fb2ed66 1465 struct mlx5_ib_qp_base *base;
e126ba97
EC		 1466 struct mlx5_ib_create_qp_resp resp;
1467 struct mlx5_create_qp_mbox_in *in;
1468 struct mlx5_ib_create_qp ucmd;
89ea94a7
MG		 1469 struct mlx5_ib_cq *send_cq;
1470 struct mlx5_ib_cq *recv_cq;
1471 unsigned long flags;
e126ba97
EC		 1472 int inlen = sizeof(*in);
1473 int err;
cfb5e088
HA		 1474 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1475 void *qpc;
e126ba97 1476
0fb2ed66 1477 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1478 &qp->raw_packet_qp.rq.base :
1479 &qp->trans_qp.base;
1480
1481 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1482 mlx5_ib_odp_create_qp(qp);
6aec21f6 1483
e126ba97
EC		 1484 mutex_init(&qp->mutex);
1485 spin_lock_init(&qp->sq.lock);
1486 spin_lock_init(&qp->rq.lock);
1487
28d61370
YH		 1488 if (init_attr->rwq_ind_tbl) {
1489 if (!udata)
1490 return -ENOSYS;
1491
1492 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1493 return err;
1494 }
1495
f360d88a 1496 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1497 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1498 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1499 return -EINVAL;
1500 } else {
1501 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1502 }
1503 }
1504
051f2630
LR		 1505 if (init_attr->create_flags &
1506 (IB_QP_CREATE_CROSS_CHANNEL |
1507 IB_QP_CREATE_MANAGED_SEND |
1508 IB_QP_CREATE_MANAGED_RECV)) {
1509 if (!MLX5_CAP_GEN(mdev, cd)) {
1510 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1511 return -EINVAL;
1512 }
1513 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1514 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1515 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1516 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1517 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1518 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1519 }
f0313965
ES		 1520
1521 if (init_attr->qp_type == IB_QPT_UD &&
1522 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1523 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1524 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1525 return -EOPNOTSUPP;
1526 }
1527
358e42ea
MD		 1528 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1529 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1530 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1531 return -EOPNOTSUPP;
1532 }
1533 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1534 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1535 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1536 return -EOPNOTSUPP;
1537 }
1538 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1539 }
1540
e126ba97
EC		 1541 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1542 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1543
1544 if (pd && pd->uobject) {
1545 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1546 mlx5_ib_dbg(dev, "copy failed\n");
1547 return -EFAULT;
1548 }
1549
cfb5e088
HA		 1550 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1551 &ucmd, udata->inlen, &uidx);
1552 if (err)
1553 return err;
1554
e126ba97
EC		 1555 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1556 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1557 } else {
1558 qp->wq_sig = !!wq_signature;
1559 }
1560
1561 qp->has_rq = qp_has_rq(init_attr);
1562 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1563 qp, (pd && pd->uobject) ? &ucmd : NULL);
1564 if (err) {
1565 mlx5_ib_dbg(dev, "err %d\n", err);
1566 return err;
1567 }
1568
1569 if (pd) {
1570 if (pd->uobject) {
938fe83c
SM		 1571 __u32 max_wqes =
1572 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1573 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1574 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1575 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1576 mlx5_ib_dbg(dev, "invalid rq params\n");
1577 return -EINVAL;
1578 }
938fe83c 1579 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1580 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1581 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1582 return -EINVAL;
1583 }
b11a4f9c
HE		 1584 if (init_attr->create_flags &
1585 mlx5_ib_create_qp_sqpn_qp1()) {
1586 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1587 return -EINVAL;
1588 }
0fb2ed66 1589 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1590 &resp, &inlen, base);
e126ba97
EC		 1591 if (err)
1592 mlx5_ib_dbg(dev, "err %d\n", err);
1593 } else {
19098df2 1594 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1595 base);
e126ba97
EC		 1596 if (err)
1597 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1598 }
1599
1600 if (err)
1601 return err;
1602 } else {
1603 in = mlx5_vzalloc(sizeof(*in));
1604 if (!in)
1605 return -ENOMEM;
1606
1607 qp->create_type = MLX5_QP_EMPTY;
1608 }
1609
1610 if (is_sqp(init_attr->qp_type))
1611 qp->port = init_attr->port_num;
1612
1613 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1614 MLX5_QP_PM_MIGRATED << 11);
1615
1616 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1617 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1618 else
1619 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1620
1621 if (qp->wq_sig)
1622 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1623
f360d88a
EC		 1624 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1625 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1626
051f2630
LR		 1627 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1628 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1629 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1630 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1631 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1632 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1633
e126ba97
EC		 1634 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1635 int rcqe_sz;
1636 int scqe_sz;
1637
1638 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1639 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1640
1641 if (rcqe_sz == 128)
1642 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1643 else
1644 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1645
1646 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1647 if (scqe_sz == 128)
1648 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1649 else
1650 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1651 }
1652 }
1653
1654 if (qp->rq.wqe_cnt) {
1655 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1656 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1657 }
1658
1659 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1660
1661 if (qp->sq.wqe_cnt)
1662 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1663 else
1664 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1665
1666 /* Set default resources */
1667 switch (init_attr->qp_type) {
1668 case IB_QPT_XRC_TGT:
1669 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1670 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1671 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1672 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1673 break;
1674 case IB_QPT_XRC_INI:
1675 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1676 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1677 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1678 break;
1679 default:
1680 if (init_attr->srq) {
1681 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1682 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1683 } else {
1684 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
4aa17b28
HA		 1685 in->ctx.rq_type_srqn |=
1686 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1687 }
1688 }
1689
1690 if (init_attr->send_cq)
1691 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1692
1693 if (init_attr->recv_cq)
1694 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1695
1696 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1697
cfb5e088
HA		 1698 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1699 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1700 /* 0xffffff means we ask to work with cqe version 0 */
1701 MLX5_SET(qpc, qpc, user_index, uidx);
1702 }
f0313965
ES		 1703 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1704 if (init_attr->qp_type == IB_QPT_UD &&
1705 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1706 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1707 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1708 qp->flags |= MLX5_IB_QP_LSO;
1709 }
cfb5e088 1710
0fb2ed66 1711 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1712 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1713 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1714 err = create_raw_packet_qp(dev, qp, in, pd);
1715 } else {
1716 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1717 }
1718
e126ba97
EC		 1719 if (err) {
1720 mlx5_ib_dbg(dev, "create qp failed\n");
1721 goto err_create;
1722 }
1723
479163f4 1724 kvfree(in);
e126ba97 1725
19098df2 1726 base->container_mibqp = qp;
1727 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1728
89ea94a7
MG		 1729 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1730 &send_cq, &recv_cq);
1731 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1732 mlx5_ib_lock_cqs(send_cq, recv_cq);
1733 /* Maintain device to QPs access, needed for further handling via reset
1734 * flow
1735 */
1736 list_add_tail(&qp->qps_list, &dev->qp_list);
1737 /* Maintain CQ to QPs access, needed for further handling via reset flow
1738 */
1739 if (send_cq)
1740 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1741 if (recv_cq)
1742 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1743 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1744 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1745
e126ba97
EC		 1746 return 0;
1747
1748err_create:
1749 if (qp->create_type == MLX5_QP_USER)
19098df2 1750 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1751 else if (qp->create_type == MLX5_QP_KERNEL)
1752 destroy_qp_kernel(dev, qp);
1753
479163f4 1754 kvfree(in);
e126ba97
EC		 1755 return err;
1756}
1757
1758static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1759 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1760{
1761 if (send_cq) {
1762 if (recv_cq) {
1763 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1764 spin_lock(&send_cq->lock);
e126ba97
EC		 1765 spin_lock_nested(&recv_cq->lock,
1766 SINGLE_DEPTH_NESTING);
1767 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1768 spin_lock(&send_cq->lock);
e126ba97
EC		 1769 __acquire(&recv_cq->lock);
1770 } else {
89ea94a7 1771 spin_lock(&recv_cq->lock);
e126ba97
EC		 1772 spin_lock_nested(&send_cq->lock,
1773 SINGLE_DEPTH_NESTING);
1774 }
1775 } else {
89ea94a7 1776 spin_lock(&send_cq->lock);
6a4f139a 1777 __acquire(&recv_cq->lock);
e126ba97
EC		 1778 }
1779 } else if (recv_cq) {
89ea94a7 1780 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1781 __acquire(&send_cq->lock);
1782 } else {
1783 __acquire(&send_cq->lock);
1784 __acquire(&recv_cq->lock);
e126ba97
EC		 1785 }
1786}
1787
1788static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1789 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1790{
1791 if (send_cq) {
1792 if (recv_cq) {
1793 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1794 spin_unlock(&recv_cq->lock);
89ea94a7 1795 spin_unlock(&send_cq->lock);
e126ba97
EC		 1796 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1797 __release(&recv_cq->lock);
89ea94a7 1798 spin_unlock(&send_cq->lock);
e126ba97
EC		 1799 } else {
1800 spin_unlock(&send_cq->lock);
89ea94a7 1801 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1802 }
1803 } else {
6a4f139a 1804 __release(&recv_cq->lock);
89ea94a7 1805 spin_unlock(&send_cq->lock);
e126ba97
EC		 1806 }
1807 } else if (recv_cq) {
6a4f139a 1808 __release(&send_cq->lock);
89ea94a7 1809 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1810 } else {
1811 __release(&recv_cq->lock);
1812 __release(&send_cq->lock);
e126ba97
EC		 1813 }
1814}
1815
1816static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1817{
1818 return to_mpd(qp->ibqp.pd);
1819}
1820
89ea94a7
MG		 1821static void get_cqs(enum ib_qp_type qp_type,
1822 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1823 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1824{
89ea94a7 1825 switch (qp_type) {
e126ba97
EC		 1826 case IB_QPT_XRC_TGT:
1827 *send_cq = NULL;
1828 *recv_cq = NULL;
1829 break;
1830 case MLX5_IB_QPT_REG_UMR:
1831 case IB_QPT_XRC_INI:
89ea94a7 1832 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1833 *recv_cq = NULL;
1834 break;
1835
1836 case IB_QPT_SMI:
d16e91da 1837 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1838 case IB_QPT_RC:
1839 case IB_QPT_UC:
1840 case IB_QPT_UD:
1841 case IB_QPT_RAW_IPV6:
1842 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1843 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1844 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1845 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1846 break;
1847
e126ba97
EC		 1848 case IB_QPT_MAX:
1849 default:
1850 *send_cq = NULL;
1851 *recv_cq = NULL;
1852 break;
1853 }
1854}
1855
ad5f8e96 1856static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1857 u16 operation);
1858
e126ba97
EC		 1859static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1860{
1861 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1862 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
0fb2ed66 1863 struct mlx5_modify_qp_mbox_in *in;
89ea94a7 1864 unsigned long flags;
e126ba97
EC		 1865 int err;
1866
28d61370
YH		 1867 if (qp->ibqp.rwq_ind_tbl) {
1868 destroy_rss_raw_qp_tir(dev, qp);
1869 return;
1870 }
1871
0fb2ed66 1872 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1873 &qp->raw_packet_qp.rq.base :
1874 &qp->trans_qp.base;
1875
e126ba97
EC		 1876 in = kzalloc(sizeof(*in), GFP_KERNEL);
1877 if (!in)
1878 return;
7bef7ad2 1879
6aec21f6 1880 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1881 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1882 mlx5_ib_qp_disable_pagefaults(qp);
1883 err = mlx5_core_qp_modify(dev->mdev,
1884 MLX5_CMD_OP_2RST_QP, in, 0,
1885 &base->mqp);
1886 } else {
1887 err = modify_raw_packet_qp(dev, qp,
1888 MLX5_CMD_OP_2RST_QP);
1889 }
1890 if (err)
427c1e7b 1891 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1892 base->mqp.qpn);
6aec21f6 1893 }
e126ba97 1894
89ea94a7
MG		 1895 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1896 &send_cq, &recv_cq);
1897
1898 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1899 mlx5_ib_lock_cqs(send_cq, recv_cq);
1900 /* del from lists under both locks above to protect reset flow paths */
1901 list_del(&qp->qps_list);
1902 if (send_cq)
1903 list_del(&qp->cq_send_list);
1904
1905 if (recv_cq)
1906 list_del(&qp->cq_recv_list);
e126ba97
EC		 1907
1908 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1909 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1910 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1911 if (send_cq != recv_cq)
19098df2 1912 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1913 NULL);
e126ba97 1914 }
89ea94a7
MG		 1915 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1916 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1917
0fb2ed66 1918 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1919 destroy_raw_packet_qp(dev, qp);
1920 } else {
1921 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1922 if (err)
1923 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1924 base->mqp.qpn);
1925 }
e126ba97 1926
0fb2ed66 1927 kfree(in);
e126ba97
EC		 1928
1929 if (qp->create_type == MLX5_QP_KERNEL)
1930 destroy_qp_kernel(dev, qp);
1931 else if (qp->create_type == MLX5_QP_USER)
19098df2 1932 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1933}
1934
1935static const char *ib_qp_type_str(enum ib_qp_type type)
1936{
1937 switch (type) {
1938 case IB_QPT_SMI:
1939 return "IB_QPT_SMI";
1940 case IB_QPT_GSI:
1941 return "IB_QPT_GSI";
1942 case IB_QPT_RC:
1943 return "IB_QPT_RC";
1944 case IB_QPT_UC:
1945 return "IB_QPT_UC";
1946 case IB_QPT_UD:
1947 return "IB_QPT_UD";
1948 case IB_QPT_RAW_IPV6:
1949 return "IB_QPT_RAW_IPV6";
1950 case IB_QPT_RAW_ETHERTYPE:
1951 return "IB_QPT_RAW_ETHERTYPE";
1952 case IB_QPT_XRC_INI:
1953 return "IB_QPT_XRC_INI";
1954 case IB_QPT_XRC_TGT:
1955 return "IB_QPT_XRC_TGT";
1956 case IB_QPT_RAW_PACKET:
1957 return "IB_QPT_RAW_PACKET";
1958 case MLX5_IB_QPT_REG_UMR:
1959 return "MLX5_IB_QPT_REG_UMR";
1960 case IB_QPT_MAX:
1961 default:
1962 return "Invalid QP type";
1963 }
1964}
1965
1966struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1967 struct ib_qp_init_attr *init_attr,
1968 struct ib_udata *udata)
1969{
1970 struct mlx5_ib_dev *dev;
1971 struct mlx5_ib_qp *qp;
1972 u16 xrcdn = 0;
1973 int err;
1974
1975 if (pd) {
1976 dev = to_mdev(pd->device);
0fb2ed66 1977
1978 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1979 if (!pd->uobject) {
1980 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1981 return ERR_PTR(-EINVAL);
1982 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1983 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1984 return ERR_PTR(-EINVAL);
1985 }
1986 }
09f16cf5
MD		 1987 } else {
1988 /* being cautious here */
1989 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1990 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1991 pr_warn("%s: no PD for transport %s\n", __func__,
1992 ib_qp_type_str(init_attr->qp_type));
1993 return ERR_PTR(-EINVAL);
1994 }
1995 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 1996 }
1997
1998 switch (init_attr->qp_type) {
1999 case IB_QPT_XRC_TGT:
2000 case IB_QPT_XRC_INI:
938fe83c 2001 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2002 mlx5_ib_dbg(dev, "XRC not supported\n");
2003 return ERR_PTR(-ENOSYS);
2004 }
2005 init_attr->recv_cq = NULL;
2006 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2007 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2008 init_attr->send_cq = NULL;
2009 }
2010
2011 /* fall through */
0fb2ed66 2012 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2013 case IB_QPT_RC:
2014 case IB_QPT_UC:
2015 case IB_QPT_UD:
2016 case IB_QPT_SMI:
d16e91da 2017 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2018 case MLX5_IB_QPT_REG_UMR:
2019 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2020 if (!qp)
2021 return ERR_PTR(-ENOMEM);
2022
2023 err = create_qp_common(dev, pd, init_attr, udata, qp);
2024 if (err) {
2025 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2026 kfree(qp);
2027 return ERR_PTR(err);
2028 }
2029
2030 if (is_qp0(init_attr->qp_type))
2031 qp->ibqp.qp_num = 0;
2032 else if (is_qp1(init_attr->qp_type))
2033 qp->ibqp.qp_num = 1;
2034 else
19098df2 2035 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2036
2037 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2038 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2039 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 2040 to_mcq(init_attr->send_cq)->mcq.cqn);
2041
19098df2 2042 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2043
2044 break;
2045
d16e91da
HE		 2046 case IB_QPT_GSI:
2047 return mlx5_ib_gsi_create_qp(pd, init_attr);
2048
e126ba97
EC		 2049 case IB_QPT_RAW_IPV6:
2050 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2051 case IB_QPT_MAX:
2052 default:
2053 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2054 init_attr->qp_type);
2055 /* Don't support raw QPs */
2056 return ERR_PTR(-EINVAL);
2057 }
2058
2059 return &qp->ibqp;
2060}
2061
2062int mlx5_ib_destroy_qp(struct ib_qp *qp)
2063{
2064 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2065 struct mlx5_ib_qp *mqp = to_mqp(qp);
2066
d16e91da
HE		 2067 if (unlikely(qp->qp_type == IB_QPT_GSI))
2068 return mlx5_ib_gsi_destroy_qp(qp);
2069
e126ba97
EC		 2070 destroy_qp_common(dev, mqp);
2071
2072 kfree(mqp);
2073
2074 return 0;
2075}
2076
2077static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2078 int attr_mask)
2079{
2080 u32 hw_access_flags = 0;
2081 u8 dest_rd_atomic;
2082 u32 access_flags;
2083
2084 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2085 dest_rd_atomic = attr->max_dest_rd_atomic;
2086 else
19098df2 2087 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2088
2089 if (attr_mask & IB_QP_ACCESS_FLAGS)
2090 access_flags = attr->qp_access_flags;
2091 else
19098df2 2092 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2093
2094 if (!dest_rd_atomic)
2095 access_flags &= IB_ACCESS_REMOTE_WRITE;
2096
2097 if (access_flags & IB_ACCESS_REMOTE_READ)
2098 hw_access_flags |= MLX5_QP_BIT_RRE;
2099 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2100 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2101 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2102 hw_access_flags |= MLX5_QP_BIT_RWE;
2103
2104 return cpu_to_be32(hw_access_flags);
2105}
2106
2107enum {
2108 MLX5_PATH_FLAG_FL = 1 << 0,
2109 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2110 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2111};
2112
2113static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2114{
2115 if (rate == IB_RATE_PORT_CURRENT) {
2116 return 0;
2117 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2118 return -EINVAL;
2119 } else {
2120 while (rate != IB_RATE_2_5_GBPS &&
2121 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2122 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2123 --rate;
2124 }
2125
2126 return rate + MLX5_STAT_RATE_OFFSET;
2127}
2128
75850d0b 2129static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2130 struct mlx5_ib_sq *sq, u8 sl)
2131{
2132 void *in;
2133 void *tisc;
2134 int inlen;
2135 int err;
2136
2137 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2138 in = mlx5_vzalloc(inlen);
2139 if (!in)
2140 return -ENOMEM;
2141
2142 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2143
2144 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2145 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2146
2147 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2148
2149 kvfree(in);
2150
2151 return err;
2152}
2153
2154static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2155 const struct ib_ah_attr *ah,
e126ba97 2156 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2157 u32 path_flags, const struct ib_qp_attr *attr,
2158 bool alt)
e126ba97 2159{
2811ba51 2160 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 2161 int err;
2162
e126ba97 2163 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2164 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2165 attr->pkey_index);
e126ba97 2166
e126ba97 2167 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2168 if (ah->grh.sgid_index >=
2169 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2170 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2171 ah->grh.sgid_index,
2172 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2173 return -EINVAL;
2174 }
2811ba51
AS		 2175 }
2176
2177 if (ll == IB_LINK_LAYER_ETHERNET) {
2178 if (!(ah->ah_flags & IB_AH_GRH))
2179 return -EINVAL;
2180 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2181 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2182 ah->grh.sgid_index);
2183 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2184 } else {
d3ae2bde
NO		 2185 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2186 path->fl_free_ar |=
2187 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2188 path->rlid = cpu_to_be16(ah->dlid);
2189 path->grh_mlid = ah->src_path_bits & 0x7f;
2190 if (ah->ah_flags & IB_AH_GRH)
2191 path->grh_mlid |= 1 << 7;
2192 path->dci_cfi_prio_sl = ah->sl & 0xf;
2193 }
2194
2195 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2196 path->mgid_index = ah->grh.sgid_index;
2197 path->hop_limit = ah->grh.hop_limit;
2198 path->tclass_flowlabel =
2199 cpu_to_be32((ah->grh.traffic_class << 20) |
2200 (ah->grh.flow_label));
2201 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2202 }
2203
2204 err = ib_rate_to_mlx5(dev, ah->static_rate);
2205 if (err < 0)
2206 return err;
2207 path->static_rate = err;
2208 path->port = port;
2209
e126ba97 2210 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2211 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2212
75850d0b 2213 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2214 return modify_raw_packet_eth_prio(dev->mdev,
2215 &qp->raw_packet_qp.sq,
2216 ah->sl & 0xf);
2217
e126ba97
EC		 2218 return 0;
2219}
2220
2221static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2222 [MLX5_QP_STATE_INIT] = {
2223 [MLX5_QP_STATE_INIT] = {
2224 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2225 MLX5_QP_OPTPAR_RAE |
2226 MLX5_QP_OPTPAR_RWE |
2227 MLX5_QP_OPTPAR_PKEY_INDEX |
2228 MLX5_QP_OPTPAR_PRI_PORT,
2229 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2230 MLX5_QP_OPTPAR_PKEY_INDEX |
2231 MLX5_QP_OPTPAR_PRI_PORT,
2232 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2233 MLX5_QP_OPTPAR_Q_KEY |
2234 MLX5_QP_OPTPAR_PRI_PORT,
2235 },
2236 [MLX5_QP_STATE_RTR] = {
2237 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2238 MLX5_QP_OPTPAR_RRE |
2239 MLX5_QP_OPTPAR_RAE |
2240 MLX5_QP_OPTPAR_RWE |
2241 MLX5_QP_OPTPAR_PKEY_INDEX,
2242 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2243 MLX5_QP_OPTPAR_RWE |
2244 MLX5_QP_OPTPAR_PKEY_INDEX,
2245 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2246 MLX5_QP_OPTPAR_Q_KEY,
2247 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2248 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2249 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2250 MLX5_QP_OPTPAR_RRE |
2251 MLX5_QP_OPTPAR_RAE |
2252 MLX5_QP_OPTPAR_RWE |
2253 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2254 },
2255 },
2256 [MLX5_QP_STATE_RTR] = {
2257 [MLX5_QP_STATE_RTS] = {
2258 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2259 MLX5_QP_OPTPAR_RRE |
2260 MLX5_QP_OPTPAR_RAE |
2261 MLX5_QP_OPTPAR_RWE |
2262 MLX5_QP_OPTPAR_PM_STATE |
2263 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2264 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2265 MLX5_QP_OPTPAR_RWE |
2266 MLX5_QP_OPTPAR_PM_STATE,
2267 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2268 },
2269 },
2270 [MLX5_QP_STATE_RTS] = {
2271 [MLX5_QP_STATE_RTS] = {
2272 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2273 MLX5_QP_OPTPAR_RAE |
2274 MLX5_QP_OPTPAR_RWE |
2275 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2276 MLX5_QP_OPTPAR_PM_STATE |
2277 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2278 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2279 MLX5_QP_OPTPAR_PM_STATE |
2280 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2281 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2282 MLX5_QP_OPTPAR_SRQN |
2283 MLX5_QP_OPTPAR_CQN_RCV,
2284 },
2285 },
2286 [MLX5_QP_STATE_SQER] = {
2287 [MLX5_QP_STATE_RTS] = {
2288 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2289 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2290 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2291 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2292 MLX5_QP_OPTPAR_RWE |
2293 MLX5_QP_OPTPAR_RAE |
2294 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2295 },
2296 },
2297};
2298
2299static int ib_nr_to_mlx5_nr(int ib_mask)
2300{
2301 switch (ib_mask) {
2302 case IB_QP_STATE:
2303 return 0;
2304 case IB_QP_CUR_STATE:
2305 return 0;
2306 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2307 return 0;
2308 case IB_QP_ACCESS_FLAGS:
2309 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2310 MLX5_QP_OPTPAR_RAE;
2311 case IB_QP_PKEY_INDEX:
2312 return MLX5_QP_OPTPAR_PKEY_INDEX;
2313 case IB_QP_PORT:
2314 return MLX5_QP_OPTPAR_PRI_PORT;
2315 case IB_QP_QKEY:
2316 return MLX5_QP_OPTPAR_Q_KEY;
2317 case IB_QP_AV:
2318 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2319 MLX5_QP_OPTPAR_PRI_PORT;
2320 case IB_QP_PATH_MTU:
2321 return 0;
2322 case IB_QP_TIMEOUT:
2323 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2324 case IB_QP_RETRY_CNT:
2325 return MLX5_QP_OPTPAR_RETRY_COUNT;
2326 case IB_QP_RNR_RETRY:
2327 return MLX5_QP_OPTPAR_RNR_RETRY;
2328 case IB_QP_RQ_PSN:
2329 return 0;
2330 case IB_QP_MAX_QP_RD_ATOMIC:
2331 return MLX5_QP_OPTPAR_SRA_MAX;
2332 case IB_QP_ALT_PATH:
2333 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2334 case IB_QP_MIN_RNR_TIMER:
2335 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2336 case IB_QP_SQ_PSN:
2337 return 0;
2338 case IB_QP_MAX_DEST_RD_ATOMIC:
2339 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2340 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2341 case IB_QP_PATH_MIG_STATE:
2342 return MLX5_QP_OPTPAR_PM_STATE;
2343 case IB_QP_CAP:
2344 return 0;
2345 case IB_QP_DEST_QPN:
2346 return 0;
2347 }
2348 return 0;
2349}
2350
2351static int ib_mask_to_mlx5_opt(int ib_mask)
2352{
2353 int result = 0;
2354 int i;
2355
2356 for (i = 0; i < 8 * sizeof(int); i++) {
2357 if ((1 << i) & ib_mask)
2358 result |= ib_nr_to_mlx5_nr(1 << i);
2359 }
2360
2361 return result;
2362}
2363
ad5f8e96 2364static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2365 struct mlx5_ib_rq *rq, int new_state)
2366{
2367 void *in;
2368 void *rqc;
2369 int inlen;
2370 int err;
2371
2372 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2373 in = mlx5_vzalloc(inlen);
2374 if (!in)
2375 return -ENOMEM;
2376
2377 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2378
2379 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2380 MLX5_SET(rqc, rqc, state, new_state);
2381
2382 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2383 if (err)
2384 goto out;
2385
2386 rq->state = new_state;
2387
2388out:
2389 kvfree(in);
2390 return err;
2391}
2392
2393static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2394 struct mlx5_ib_sq *sq, int new_state)
2395{
2396 void *in;
2397 void *sqc;
2398 int inlen;
2399 int err;
2400
2401 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2402 in = mlx5_vzalloc(inlen);
2403 if (!in)
2404 return -ENOMEM;
2405
2406 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2407
2408 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2409 MLX5_SET(sqc, sqc, state, new_state);
2410
2411 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2412 if (err)
2413 goto out;
2414
2415 sq->state = new_state;
2416
2417out:
2418 kvfree(in);
2419 return err;
2420}
2421
2422static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2423 u16 operation)
2424{
2425 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2426 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2427 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2428 int rq_state;
2429 int sq_state;
2430 int err;
2431
2432 switch (operation) {
2433 case MLX5_CMD_OP_RST2INIT_QP:
2434 rq_state = MLX5_RQC_STATE_RDY;
2435 sq_state = MLX5_SQC_STATE_RDY;
2436 break;
2437 case MLX5_CMD_OP_2ERR_QP:
2438 rq_state = MLX5_RQC_STATE_ERR;
2439 sq_state = MLX5_SQC_STATE_ERR;
2440 break;
2441 case MLX5_CMD_OP_2RST_QP:
2442 rq_state = MLX5_RQC_STATE_RST;
2443 sq_state = MLX5_SQC_STATE_RST;
2444 break;
2445 case MLX5_CMD_OP_INIT2INIT_QP:
2446 case MLX5_CMD_OP_INIT2RTR_QP:
2447 case MLX5_CMD_OP_RTR2RTS_QP:
2448 case MLX5_CMD_OP_RTS2RTS_QP:
2449 /* Nothing to do here... */
2450 return 0;
2451 default:
2452 WARN_ON(1);
2453 return -EINVAL;
2454 }
2455
2456 if (qp->rq.wqe_cnt) {
2457 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2458 if (err)
2459 return err;
2460 }
2461
2462 if (qp->sq.wqe_cnt)
2463 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2464
2465 return 0;
2466}
2467
e126ba97
EC		 2468static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2469 const struct ib_qp_attr *attr, int attr_mask,
2470 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2471{
427c1e7b 2472 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2473 [MLX5_QP_STATE_RST] = {
2474 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2475 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2476 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2477 },
2478 [MLX5_QP_STATE_INIT] = {
2479 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2480 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2481 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2482 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2483 },
2484 [MLX5_QP_STATE_RTR] = {
2485 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2486 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2487 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2488 },
2489 [MLX5_QP_STATE_RTS] = {
2490 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2491 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2492 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2493 },
2494 [MLX5_QP_STATE_SQD] = {
2495 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2496 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2497 },
2498 [MLX5_QP_STATE_SQER] = {
2499 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2500 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2501 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2502 },
2503 [MLX5_QP_STATE_ERR] = {
2504 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2505 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2506 }
2507 };
2508
e126ba97
EC		 2509 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2510 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2511 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2512 struct mlx5_ib_cq *send_cq, *recv_cq;
2513 struct mlx5_qp_context *context;
2514 struct mlx5_modify_qp_mbox_in *in;
2515 struct mlx5_ib_pd *pd;
2516 enum mlx5_qp_state mlx5_cur, mlx5_new;
2517 enum mlx5_qp_optpar optpar;
2518 int sqd_event;
2519 int mlx5_st;
2520 int err;
427c1e7b 2521 u16 op;
e126ba97
EC		 2522
2523 in = kzalloc(sizeof(*in), GFP_KERNEL);
2524 if (!in)
2525 return -ENOMEM;
2526
2527 context = &in->ctx;
2528 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2529 if (err < 0) {
2530 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2531 goto out;
158abf86 2532 }
e126ba97
EC		 2533
2534 context->flags = cpu_to_be32(err << 16);
2535
2536 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2537 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2538 } else {
2539 switch (attr->path_mig_state) {
2540 case IB_MIG_MIGRATED:
2541 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2542 break;
2543 case IB_MIG_REARM:
2544 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2545 break;
2546 case IB_MIG_ARMED:
2547 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2548 break;
2549 }
2550 }
2551
d16e91da 2552 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2553 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2554 } else if (ibqp->qp_type == IB_QPT_UD ||
2555 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2556 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2557 } else if (attr_mask & IB_QP_PATH_MTU) {
2558 if (attr->path_mtu < IB_MTU_256 ||
2559 attr->path_mtu > IB_MTU_4096) {
2560 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2561 err = -EINVAL;
2562 goto out;
2563 }
938fe83c
SM		 2564 context->mtu_msgmax = (attr->path_mtu << 5) |
2565 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2566 }
2567
2568 if (attr_mask & IB_QP_DEST_QPN)
2569 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2570
2571 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2572 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2573
2574 /* todo implement counter_index functionality */
2575
2576 if (is_sqp(ibqp->qp_type))
2577 context->pri_path.port = qp->port;
2578
2579 if (attr_mask & IB_QP_PORT)
2580 context->pri_path.port = attr->port_num;
2581
2582 if (attr_mask & IB_QP_AV) {
75850d0b 2583 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2584 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2585 attr_mask, 0, attr, false);
e126ba97
EC		 2586 if (err)
2587 goto out;
2588 }
2589
2590 if (attr_mask & IB_QP_TIMEOUT)
2591 context->pri_path.ackto_lt |= attr->timeout << 3;
2592
2593 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2594 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2595 &context->alt_path,
f879ee8d
AS		 2596 attr->alt_port_num,
2597 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2598 0, attr, true);
e126ba97
EC		 2599 if (err)
2600 goto out;
2601 }
2602
2603 pd = get_pd(qp);
89ea94a7
MG		 2604 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2605 &send_cq, &recv_cq);
e126ba97
EC		 2606
2607 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2608 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2609 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2610 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2611
2612 if (attr_mask & IB_QP_RNR_RETRY)
2613 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2614
2615 if (attr_mask & IB_QP_RETRY_CNT)
2616 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2617
2618 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2619 if (attr->max_rd_atomic)
2620 context->params1 |=
2621 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2622 }
2623
2624 if (attr_mask & IB_QP_SQ_PSN)
2625 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2626
2627 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2628 if (attr->max_dest_rd_atomic)
2629 context->params2 |=
2630 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2631 }
2632
2633 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2634 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2635
2636 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2637 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2638
2639 if (attr_mask & IB_QP_RQ_PSN)
2640 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2641
2642 if (attr_mask & IB_QP_QKEY)
2643 context->qkey = cpu_to_be32(attr->qkey);
2644
2645 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2646 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2647
2648 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2649 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2650 sqd_event = 1;
2651 else
2652 sqd_event = 0;
2653
2654 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2655 context->sq_crq_size |= cpu_to_be16(1 << 4);
2656
b11a4f9c
HE		 2657 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2658 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2659
2660 mlx5_cur = to_mlx5_state(cur_state);
2661 mlx5_new = to_mlx5_state(new_state);
2662 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2663 if (mlx5_st < 0)
e126ba97
EC		 2664 goto out;
2665
6aec21f6
HE		 2666 /* If moving to a reset or error state, we must disable page faults on
2667 * this QP and flush all current page faults. Otherwise a stale page
2668 * fault may attempt to work on this QP after it is reset and moved
2669 * again to RTS, and may cause the driver and the device to get out of
2670 * sync. */
2671 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2672 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2673 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2674 mlx5_ib_qp_disable_pagefaults(qp);
2675
427c1e7b 2676 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2677 !optab[mlx5_cur][mlx5_new])
2678 goto out;
2679
2680 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2681 optpar = ib_mask_to_mlx5_opt(attr_mask);
2682 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2683 in->optparam = cpu_to_be32(optpar);
ad5f8e96 2684
2685 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2686 err = modify_raw_packet_qp(dev, qp, op);
2687 else
2688 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2689 &base->mqp);
e126ba97
EC		 2690 if (err)
2691 goto out;
2692
ad5f8e96 2693 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2694 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2695 mlx5_ib_qp_enable_pagefaults(qp);
2696
e126ba97
EC		 2697 qp->state = new_state;
2698
2699 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2700 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2701 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2702 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2703 if (attr_mask & IB_QP_PORT)
2704 qp->port = attr->port_num;
2705 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2706 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2707
2708 /*
2709 * If we moved a kernel QP to RESET, clean up all old CQ
2710 * entries and reinitialize the QP.
2711 */
2712 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2713 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2714 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2715 if (send_cq != recv_cq)
19098df2 2716 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2717
2718 qp->rq.head = 0;
2719 qp->rq.tail = 0;
2720 qp->sq.head = 0;
2721 qp->sq.tail = 0;
2722 qp->sq.cur_post = 0;
2723 qp->sq.last_poll = 0;
2724 qp->db.db[MLX5_RCV_DBR] = 0;
2725 qp->db.db[MLX5_SND_DBR] = 0;
2726 }
2727
2728out:
2729 kfree(in);
2730 return err;
2731}
2732
2733int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2734 int attr_mask, struct ib_udata *udata)
2735{
2736 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2737 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2738 enum ib_qp_type qp_type;
e126ba97
EC		 2739 enum ib_qp_state cur_state, new_state;
2740 int err = -EINVAL;
2741 int port;
2811ba51 2742 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2743
28d61370
YH		 2744 if (ibqp->rwq_ind_tbl)
2745 return -ENOSYS;
2746
d16e91da
HE		 2747 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2748 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2749
2750 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2751 IB_QPT_GSI : ibqp->qp_type;
2752
e126ba97
EC		 2753 mutex_lock(&qp->mutex);
2754
2755 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2756 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2757
2811ba51
AS		 2758 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2759 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2760 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2761 }
2762
d16e91da
HE		 2763 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2764 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2765 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2766 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2767 goto out;
158abf86 2768 }
e126ba97
EC		 2769
2770 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2771 (attr->port_num == 0 ||
158abf86
HE		 2772 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2773 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2774 attr->port_num, dev->num_ports);
e126ba97 2775 goto out;
158abf86 2776 }
e126ba97
EC		 2777
2778 if (attr_mask & IB_QP_PKEY_INDEX) {
2779 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2780 if (attr->pkey_index >=
158abf86
HE		 2781 dev->mdev->port_caps[port - 1].pkey_table_len) {
2782 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2783 attr->pkey_index);
e126ba97 2784 goto out;
158abf86 2785 }
e126ba97
EC		 2786 }
2787
2788 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2789 attr->max_rd_atomic >
158abf86
HE		 2790 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2791 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2792 attr->max_rd_atomic);
e126ba97 2793 goto out;
158abf86 2794 }
e126ba97
EC		 2795
2796 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2797 attr->max_dest_rd_atomic >
158abf86
HE		 2798 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2799 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2800 attr->max_dest_rd_atomic);
e126ba97 2801 goto out;
158abf86 2802 }
e126ba97
EC		 2803
2804 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2805 err = 0;
2806 goto out;
2807 }
2808
2809 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2810
2811out:
2812 mutex_unlock(&qp->mutex);
2813 return err;
2814}
2815
2816static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2817{
2818 struct mlx5_ib_cq *cq;
2819 unsigned cur;
2820
2821 cur = wq->head - wq->tail;
2822 if (likely(cur + nreq < wq->max_post))
2823 return 0;
2824
2825 cq = to_mcq(ib_cq);
2826 spin_lock(&cq->lock);
2827 cur = wq->head - wq->tail;
2828 spin_unlock(&cq->lock);
2829
2830 return cur + nreq >= wq->max_post;
2831}
2832
2833static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2834 u64 remote_addr, u32 rkey)
2835{
2836 rseg->raddr = cpu_to_be64(remote_addr);
2837 rseg->rkey = cpu_to_be32(rkey);
2838 rseg->reserved = 0;
2839}
2840
f0313965
ES		 2841static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2842 struct ib_send_wr *wr, void *qend,
2843 struct mlx5_ib_qp *qp, int *size)
2844{
2845 void *seg = eseg;
2846
2847 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2848
2849 if (wr->send_flags & IB_SEND_IP_CSUM)
2850 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2851 MLX5_ETH_WQE_L4_CSUM;
2852
2853 seg += sizeof(struct mlx5_wqe_eth_seg);
2854 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2855
2856 if (wr->opcode == IB_WR_LSO) {
2857 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2858 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2859 u64 left, leftlen, copysz;
2860 void *pdata = ud_wr->header;
2861
2862 left = ud_wr->hlen;
2863 eseg->mss = cpu_to_be16(ud_wr->mss);
2864 eseg->inline_hdr_sz = cpu_to_be16(left);
2865
2866 /*
2867 * check if there is space till the end of queue, if yes,
2868 * copy all in one shot, otherwise copy till the end of queue,
2869 * rollback and than the copy the left
2870 */
2871 leftlen = qend - (void *)eseg->inline_hdr_start;
2872 copysz = min_t(u64, leftlen, left);
2873
2874 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2875
2876 if (likely(copysz > size_of_inl_hdr_start)) {
2877 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2878 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2879 }
2880
2881 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2882 seg = mlx5_get_send_wqe(qp, 0);
2883 left -= copysz;
2884 pdata += copysz;
2885 memcpy(seg, pdata, left);
2886 seg += ALIGN(left, 16);
2887 *size += ALIGN(left, 16) / 16;
2888 }
2889 }
2890
2891 return seg;
2892}
2893
e126ba97
EC		 2894static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2895 struct ib_send_wr *wr)
2896{
e622f2f4
CH		 2897 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2898 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2899 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2900}
2901
2902static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2903{
2904 dseg->byte_count = cpu_to_be32(sg->length);
2905 dseg->lkey = cpu_to_be32(sg->lkey);
2906 dseg->addr = cpu_to_be64(sg->addr);
2907}
2908
2909static __be16 get_klm_octo(int npages)
2910{
2911 return cpu_to_be16(ALIGN(npages, 8) / 2);
2912}
2913
2914static __be64 frwr_mkey_mask(void)
2915{
2916 u64 result;
2917
2918 result = MLX5_MKEY_MASK_LEN |
2919 MLX5_MKEY_MASK_PAGE_SIZE |
2920 MLX5_MKEY_MASK_START_ADDR |
2921 MLX5_MKEY_MASK_EN_RINVAL |
2922 MLX5_MKEY_MASK_KEY |
2923 MLX5_MKEY_MASK_LR |
2924 MLX5_MKEY_MASK_LW |
2925 MLX5_MKEY_MASK_RR |
2926 MLX5_MKEY_MASK_RW |
2927 MLX5_MKEY_MASK_A |
2928 MLX5_MKEY_MASK_SMALL_FENCE |
2929 MLX5_MKEY_MASK_FREE;
2930
2931 return cpu_to_be64(result);
2932}
2933
e6631814
SG		 2934static __be64 sig_mkey_mask(void)
2935{
2936 u64 result;
2937
2938 result = MLX5_MKEY_MASK_LEN |
2939 MLX5_MKEY_MASK_PAGE_SIZE |
2940 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2941 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2942 MLX5_MKEY_MASK_EN_RINVAL |
2943 MLX5_MKEY_MASK_KEY |
2944 MLX5_MKEY_MASK_LR |
2945 MLX5_MKEY_MASK_LW |
2946 MLX5_MKEY_MASK_RR |
2947 MLX5_MKEY_MASK_RW |
2948 MLX5_MKEY_MASK_SMALL_FENCE |
2949 MLX5_MKEY_MASK_FREE |
2950 MLX5_MKEY_MASK_BSF_EN;
2951
2952 return cpu_to_be64(result);
2953}
2954
8a187ee5
SG		 2955static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2956 struct mlx5_ib_mr *mr)
2957{
2958 int ndescs = mr->ndescs;
2959
2960 memset(umr, 0, sizeof(*umr));
b005d316
SG		 2961
2962 if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2963 /* KLMs take twice the size of MTTs */
2964 ndescs *= 2;
2965
8a187ee5
SG		 2966 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2967 umr->klm_octowords = get_klm_octo(ndescs);
2968 umr->mkey_mask = frwr_mkey_mask();
2969}
2970
dd01e66a 2971static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2972{
2973 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2974 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2975 umr->flags = 1 << 7;
e126ba97
EC		 2976}
2977
968e78dd
HE		 2978static __be64 get_umr_reg_mr_mask(void)
2979{
2980 u64 result;
2981
2982 result = MLX5_MKEY_MASK_LEN |
2983 MLX5_MKEY_MASK_PAGE_SIZE |
2984 MLX5_MKEY_MASK_START_ADDR |
2985 MLX5_MKEY_MASK_PD |
2986 MLX5_MKEY_MASK_LR |
2987 MLX5_MKEY_MASK_LW |
2988 MLX5_MKEY_MASK_KEY |
2989 MLX5_MKEY_MASK_RR |
2990 MLX5_MKEY_MASK_RW |
2991 MLX5_MKEY_MASK_A |
2992 MLX5_MKEY_MASK_FREE;
2993
2994 return cpu_to_be64(result);
2995}
2996
2997static __be64 get_umr_unreg_mr_mask(void)
2998{
2999 u64 result;
3000
3001 result = MLX5_MKEY_MASK_FREE;
3002
3003 return cpu_to_be64(result);
3004}
3005
3006static __be64 get_umr_update_mtt_mask(void)
3007{
3008 u64 result;
3009
3010 result = MLX5_MKEY_MASK_FREE;
3011
3012 return cpu_to_be64(result);
3013}
3014
56e11d62
NO		 3015static __be64 get_umr_update_translation_mask(void)
3016{
3017 u64 result;
3018
3019 result = MLX5_MKEY_MASK_LEN |
3020 MLX5_MKEY_MASK_PAGE_SIZE |
3021 MLX5_MKEY_MASK_START_ADDR |
3022 MLX5_MKEY_MASK_KEY |
3023 MLX5_MKEY_MASK_FREE;
3024
3025 return cpu_to_be64(result);
3026}
3027
3028static __be64 get_umr_update_access_mask(void)
3029{
3030 u64 result;
3031
3032 result = MLX5_MKEY_MASK_LW |
3033 MLX5_MKEY_MASK_RR |
3034 MLX5_MKEY_MASK_RW |
3035 MLX5_MKEY_MASK_A |
3036 MLX5_MKEY_MASK_KEY |
3037 MLX5_MKEY_MASK_FREE;
3038
3039 return cpu_to_be64(result);
3040}
3041
3042static __be64 get_umr_update_pd_mask(void)
3043{
3044 u64 result;
3045
3046 result = MLX5_MKEY_MASK_PD |
3047 MLX5_MKEY_MASK_KEY |
3048 MLX5_MKEY_MASK_FREE;
3049
3050 return cpu_to_be64(result);
3051}
3052
e126ba97
EC		 3053static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3054 struct ib_send_wr *wr)
3055{
e622f2f4 3056 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3057
3058 memset(umr, 0, sizeof(*umr));
3059
968e78dd
HE		 3060 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3061 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3062 else
3063 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3064
e126ba97 3065 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 3066 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 3067 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3068 umr->mkey_mask = get_umr_update_mtt_mask();
3069 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3070 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 3071 }
56e11d62
NO		 3072 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3073 umr->mkey_mask |= get_umr_update_translation_mask();
3074 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3075 umr->mkey_mask |= get_umr_update_access_mask();
3076 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3077 umr->mkey_mask |= get_umr_update_pd_mask();
3078 if (!umr->mkey_mask)
3079 umr->mkey_mask = get_umr_reg_mr_mask();
e126ba97 3080 } else {
968e78dd 3081 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 3082 }
3083
3084 if (!wr->num_sge)
968e78dd 3085 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3086}
3087
3088static u8 get_umr_flags(int acc)
3089{
3090 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3091 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3092 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3093 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3094 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3095}
3096
8a187ee5
SG		 3097static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3098 struct mlx5_ib_mr *mr,
3099 u32 key, int access)
3100{
3101 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3102
3103 memset(seg, 0, sizeof(*seg));
b005d316
SG		 3104
3105 if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3106 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3107 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3108 /* KLMs take twice the size of MTTs */
3109 ndescs *= 2;
3110
3111 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3112 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3113 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3114 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3115 seg->len = cpu_to_be64(mr->ibmr.length);
3116 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3117}
3118
dd01e66a 3119static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3120{
3121 memset(seg, 0, sizeof(*seg));
dd01e66a 3122 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3123}
3124
3125static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3126{
e622f2f4 3127 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3128
e126ba97
EC		 3129 memset(seg, 0, sizeof(*seg));
3130 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 3131 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3132 return;
3133 }
3134
968e78dd
HE		 3135 seg->flags = convert_access(umrwr->access_flags);
3136 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 3137 if (umrwr->pd)
3138 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 3139 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3140 }
3141 seg->len = cpu_to_be64(umrwr->length);
3142 seg->log2_page_size = umrwr->page_shift;
746b5583 3143 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3144 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3145}
3146
8a187ee5
SG		 3147static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3148 struct mlx5_ib_mr *mr,
3149 struct mlx5_ib_pd *pd)
3150{
3151 int bcount = mr->desc_size * mr->ndescs;
3152
3153 dseg->addr = cpu_to_be64(mr->desc_map);
3154 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3155 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3156}
3157
e126ba97
EC		 3158static __be32 send_ieth(struct ib_send_wr *wr)
3159{
3160 switch (wr->opcode) {
3161 case IB_WR_SEND_WITH_IMM:
3162 case IB_WR_RDMA_WRITE_WITH_IMM:
3163 return wr->ex.imm_data;
3164
3165 case IB_WR_SEND_WITH_INV:
3166 return cpu_to_be32(wr->ex.invalidate_rkey);
3167
3168 default:
3169 return 0;
3170 }
3171}
3172
3173static u8 calc_sig(void *wqe, int size)
3174{
3175 u8 *p = wqe;
3176 u8 res = 0;
3177 int i;
3178
3179 for (i = 0; i < size; i++)
3180 res ^= p[i];
3181
3182 return ~res;
3183}
3184
3185static u8 wq_sig(void *wqe)
3186{
3187 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3188}
3189
3190static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3191 void *wqe, int *sz)
3192{
3193 struct mlx5_wqe_inline_seg *seg;
3194 void *qend = qp->sq.qend;
3195 void *addr;
3196 int inl = 0;
3197 int copy;
3198 int len;
3199 int i;
3200
3201 seg = wqe;
3202 wqe += sizeof(*seg);
3203 for (i = 0; i < wr->num_sge; i++) {
3204 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3205 len = wr->sg_list[i].length;
3206 inl += len;
3207
3208 if (unlikely(inl > qp->max_inline_data))
3209 return -ENOMEM;
3210
3211 if (unlikely(wqe + len > qend)) {
3212 copy = qend - wqe;
3213 memcpy(wqe, addr, copy);
3214 addr += copy;
3215 len -= copy;
3216 wqe = mlx5_get_send_wqe(qp, 0);
3217 }
3218 memcpy(wqe, addr, len);
3219 wqe += len;
3220 }
3221
3222 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3223
3224 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3225
3226 return 0;
3227}
3228
e6631814
SG		 3229static u16 prot_field_size(enum ib_signature_type type)
3230{
3231 switch (type) {
3232 case IB_SIG_TYPE_T10_DIF:
3233 return MLX5_DIF_SIZE;
3234 default:
3235 return 0;
3236 }
3237}
3238
3239static u8 bs_selector(int block_size)
3240{
3241 switch (block_size) {
3242 case 512: return 0x1;
3243 case 520: return 0x2;
3244 case 4096: return 0x3;
3245 case 4160: return 0x4;
3246 case 1073741824: return 0x5;
3247 default: return 0;
3248 }
3249}
3250
78eda2bb
SG		 3251static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3252 struct mlx5_bsf_inl *inl)
e6631814 3253{
142537f4
SG		 3254 /* Valid inline section and allow BSF refresh */
3255 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3256 MLX5_BSF_REFRESH_DIF);
3257 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3258 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3259 /* repeating block */
3260 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3261 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3262 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3263
78eda2bb
SG		 3264 if (domain->sig.dif.ref_remap)
3265 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3266
78eda2bb
SG		 3267 if (domain->sig.dif.app_escape) {
3268 if (domain->sig.dif.ref_escape)
3269 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3270 else
3271 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3272 }
3273
78eda2bb
SG		 3274 inl->dif_app_bitmask_check =
3275 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3276}
3277
3278static int mlx5_set_bsf(struct ib_mr *sig_mr,
3279 struct ib_sig_attrs *sig_attrs,
3280 struct mlx5_bsf *bsf, u32 data_size)
3281{
3282 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3283 struct mlx5_bsf_basic *basic = &bsf->basic;
3284 struct ib_sig_domain *mem = &sig_attrs->mem;
3285 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3286
c7f44fbd 3287 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3288
3289 /* Basic + Extended + Inline */
3290 basic->bsf_size_sbs = 1 << 7;
3291 /* Input domain check byte mask */
3292 basic->check_byte_mask = sig_attrs->check_mask;
3293 basic->raw_data_size = cpu_to_be32(data_size);
3294
3295 /* Memory domain */
e6631814 3296 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3297 case IB_SIG_TYPE_NONE:
3298 break;
e6631814 3299 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3300 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3301 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3302 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3303 break;
3304 default:
3305 return -EINVAL;
3306 }
e6631814 3307
78eda2bb
SG		 3308 /* Wire domain */
3309 switch (sig_attrs->wire.sig_type) {
3310 case IB_SIG_TYPE_NONE:
3311 break;
3312 case IB_SIG_TYPE_T10_DIF:
e6631814 3313 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3314 mem->sig_type == wire->sig_type) {
e6631814 3315 /* Same block structure */
142537f4 3316 basic->bsf_size_sbs |= 1 << 4;
e6631814 3317 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3318 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3319 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3320 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3321 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3322 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3323 } else
3324 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3325
142537f4 3326 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3327 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3328 break;
e6631814
SG		 3329 default:
3330 return -EINVAL;
3331 }
3332
3333 return 0;
3334}
3335
e622f2f4
CH		 3336static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3337 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3338{
e622f2f4
CH		 3339 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3340 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3341 struct mlx5_bsf *bsf;
e622f2f4
CH		 3342 u32 data_len = wr->wr.sg_list->length;
3343 u32 data_key = wr->wr.sg_list->lkey;
3344 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3345 int ret;
3346 int wqe_size;
3347
e622f2f4
CH		 3348 if (!wr->prot ||
3349 (data_key == wr->prot->lkey &&
3350 data_va == wr->prot->addr &&
3351 data_len == wr->prot->length)) {
e6631814
SG		 3352 /**
3353 * Source domain doesn't contain signature information
5c273b16 3354 * or data and protection are interleaved in memory.
e6631814
SG		 3355 * So need construct:
3356 * ------------------
3357 * | data_klm |
3358 * ------------------
3359 * | BSF |
3360 * ------------------
3361 **/
3362 struct mlx5_klm *data_klm = *seg;
3363
3364 data_klm->bcount = cpu_to_be32(data_len);
3365 data_klm->key = cpu_to_be32(data_key);
3366 data_klm->va = cpu_to_be64(data_va);
3367 wqe_size = ALIGN(sizeof(*data_klm), 64);
3368 } else {
3369 /**
3370 * Source domain contains signature information
3371 * So need construct a strided block format:
3372 * ---------------------------
3373 * | stride_block_ctrl |
3374 * ---------------------------
3375 * | data_klm |
3376 * ---------------------------
3377 * | prot_klm |
3378 * ---------------------------
3379 * | BSF |
3380 * ---------------------------
3381 **/
3382 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3383 struct mlx5_stride_block_entry *data_sentry;
3384 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3385 u32 prot_key = wr->prot->lkey;
3386 u64 prot_va = wr->prot->addr;
e6631814
SG		 3387 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3388 int prot_size;
3389
3390 sblock_ctrl = *seg;
3391 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3392 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3393
3394 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3395 if (!prot_size) {
3396 pr_err("Bad block size given: %u\n", block_size);
3397 return -EINVAL;
3398 }
3399 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3400 prot_size);
3401 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3402 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3403 sblock_ctrl->num_entries = cpu_to_be16(2);
3404
3405 data_sentry->bcount = cpu_to_be16(block_size);
3406 data_sentry->key = cpu_to_be32(data_key);
3407 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3408 data_sentry->stride = cpu_to_be16(block_size);
3409
e6631814
SG		 3410 prot_sentry->bcount = cpu_to_be16(prot_size);
3411 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3412 prot_sentry->va = cpu_to_be64(prot_va);
3413 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3414
e6631814
SG		 3415 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3416 sizeof(*prot_sentry), 64);
3417 }
3418
3419 *seg += wqe_size;
3420 *size += wqe_size / 16;
3421 if (unlikely((*seg == qp->sq.qend)))
3422 *seg = mlx5_get_send_wqe(qp, 0);
3423
3424 bsf = *seg;
3425 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3426 if (ret)
3427 return -EINVAL;
3428
3429 *seg += sizeof(*bsf);
3430 *size += sizeof(*bsf) / 16;
3431 if (unlikely((*seg == qp->sq.qend)))
3432 *seg = mlx5_get_send_wqe(qp, 0);
3433
3434 return 0;
3435}
3436
3437static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3438 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3439 u32 length, u32 pdn)
3440{
e622f2f4 3441 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3442 u32 sig_key = sig_mr->rkey;
d5436ba0 3443 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3444
3445 memset(seg, 0, sizeof(*seg));
3446
e622f2f4 3447 seg->flags = get_umr_flags(wr->access_flags) |
e6631814
SG		 3448 MLX5_ACCESS_MODE_KLM;
3449 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3450 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3451 MLX5_MKEY_BSF_EN | pdn);
3452 seg->len = cpu_to_be64(length);
3453 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3454 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3455}
3456
3457static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3458 u32 nelements)
e6631814
SG		 3459{
3460 memset(umr, 0, sizeof(*umr));
3461
3462 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3463 umr->klm_octowords = get_klm_octo(nelements);
3464 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3465 umr->mkey_mask = sig_mkey_mask();
3466}
3467
3468
e622f2f4 3469static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3470 void **seg, int *size)
3471{
e622f2f4
CH		 3472 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3473 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3474 u32 pdn = get_pd(qp)->pdn;
3475 u32 klm_oct_size;
3476 int region_len, ret;
3477
e622f2f4
CH		 3478 if (unlikely(wr->wr.num_sge != 1) ||
3479 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3480 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3481 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3482 return -EINVAL;
3483
3484 /* length of the protected region, data + protection */
e622f2f4
CH		 3485 region_len = wr->wr.sg_list->length;
3486 if (wr->prot &&
3487 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3488 wr->prot->addr != wr->wr.sg_list->addr ||
3489 wr->prot->length != wr->wr.sg_list->length))
3490 region_len += wr->prot->length;
e6631814
SG		 3491
3492 /**
3493 * KLM octoword size - if protection was provided
3494 * then we use strided block format (3 octowords),
3495 * else we use single KLM (1 octoword)
3496 **/
e622f2f4 3497 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3498
e622f2f4 3499 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3500 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3501 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3502 if (unlikely((*seg == qp->sq.qend)))
3503 *seg = mlx5_get_send_wqe(qp, 0);
3504
3505 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3506 *seg += sizeof(struct mlx5_mkey_seg);
3507 *size += sizeof(struct mlx5_mkey_seg) / 16;
3508 if (unlikely((*seg == qp->sq.qend)))
3509 *seg = mlx5_get_send_wqe(qp, 0);
3510
3511 ret = set_sig_data_segment(wr, qp, seg, size);
3512 if (ret)
3513 return ret;
3514
d5436ba0 3515 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3516 return 0;
3517}
3518
3519static int set_psv_wr(struct ib_sig_domain *domain,
3520 u32 psv_idx, void **seg, int *size)
3521{
3522 struct mlx5_seg_set_psv *psv_seg = *seg;
3523
3524 memset(psv_seg, 0, sizeof(*psv_seg));
3525 psv_seg->psv_num = cpu_to_be32(psv_idx);
3526 switch (domain->sig_type) {
78eda2bb
SG		 3527 case IB_SIG_TYPE_NONE:
3528 break;
e6631814
SG		 3529 case IB_SIG_TYPE_T10_DIF:
3530 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3531 domain->sig.dif.app_tag);
3532 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3533 break;
e6631814
SG		 3534 default:
3535 pr_err("Bad signature type given.\n");
3536 return 1;
3537 }
3538
78eda2bb
SG		 3539 *seg += sizeof(*psv_seg);
3540 *size += sizeof(*psv_seg) / 16;
3541
e6631814
SG		 3542 return 0;
3543}
3544
8a187ee5
SG		 3545static int set_reg_wr(struct mlx5_ib_qp *qp,
3546 struct ib_reg_wr *wr,
3547 void **seg, int *size)
3548{
3549 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3550 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3551
3552 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3553 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3554 "Invalid IB_SEND_INLINE send flag\n");
3555 return -EINVAL;
3556 }
3557
3558 set_reg_umr_seg(*seg, mr);
3559 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3560 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3561 if (unlikely((*seg == qp->sq.qend)))
3562 *seg = mlx5_get_send_wqe(qp, 0);
3563
3564 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3565 *seg += sizeof(struct mlx5_mkey_seg);
3566 *size += sizeof(struct mlx5_mkey_seg) / 16;
3567 if (unlikely((*seg == qp->sq.qend)))
3568 *seg = mlx5_get_send_wqe(qp, 0);
3569
3570 set_reg_data_seg(*seg, mr, pd);
3571 *seg += sizeof(struct mlx5_wqe_data_seg);
3572 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3573
3574 return 0;
3575}
3576
dd01e66a 3577static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3578{
dd01e66a 3579 set_linv_umr_seg(*seg);
e126ba97
EC		 3580 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3581 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3582 if (unlikely((*seg == qp->sq.qend)))
3583 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3584 set_linv_mkey_seg(*seg);
e126ba97
EC		 3585 *seg += sizeof(struct mlx5_mkey_seg);
3586 *size += sizeof(struct mlx5_mkey_seg) / 16;
3587 if (unlikely((*seg == qp->sq.qend)))
3588 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3589}
3590
3591static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3592{
3593 __be32 *p = NULL;
3594 int tidx = idx;
3595 int i, j;
3596
3597 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3598 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3599 if ((i & 0xf) == 0) {
3600 void *buf = mlx5_get_send_wqe(qp, tidx);
3601 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3602 p = buf;
3603 j = 0;
3604 }
3605 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3606 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3607 be32_to_cpu(p[j + 3]));
3608 }
3609}
3610
3611static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3612 unsigned bytecnt, struct mlx5_ib_qp *qp)
3613{
3614 while (bytecnt > 0) {
3615 __iowrite64_copy(dst++, src++, 8);
3616 __iowrite64_copy(dst++, src++, 8);
3617 __iowrite64_copy(dst++, src++, 8);
3618 __iowrite64_copy(dst++, src++, 8);
3619 __iowrite64_copy(dst++, src++, 8);
3620 __iowrite64_copy(dst++, src++, 8);
3621 __iowrite64_copy(dst++, src++, 8);
3622 __iowrite64_copy(dst++, src++, 8);
3623 bytecnt -= 64;
3624 if (unlikely(src == qp->sq.qend))
3625 src = mlx5_get_send_wqe(qp, 0);
3626 }
3627}
3628
3629static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3630{
3631 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3632 wr->send_flags & IB_SEND_FENCE))
3633 return MLX5_FENCE_MODE_STRONG_ORDERING;
3634
3635 if (unlikely(fence)) {
3636 if (wr->send_flags & IB_SEND_FENCE)
3637 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3638 else
3639 return fence;
3640
3641 } else {
3642 return 0;
3643 }
3644}
3645
6e5eadac
SG		 3646static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3647 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3648 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3649 int *size, int nreq)
3650{
3651 int err = 0;
3652
3653 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3654 err = -ENOMEM;
3655 return err;
3656 }
3657
3658 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3659 *seg = mlx5_get_send_wqe(qp, *idx);
3660 *ctrl = *seg;
3661 *(uint32_t *)(*seg + 8) = 0;
3662 (*ctrl)->imm = send_ieth(wr);
3663 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3664 (wr->send_flags & IB_SEND_SIGNALED ?
3665 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3666 (wr->send_flags & IB_SEND_SOLICITED ?
3667 MLX5_WQE_CTRL_SOLICITED : 0);
3668
3669 *seg += sizeof(**ctrl);
3670 *size = sizeof(**ctrl) / 16;
3671
3672 return err;
3673}
3674
3675static void finish_wqe(struct mlx5_ib_qp *qp,
3676 struct mlx5_wqe_ctrl_seg *ctrl,
3677 u8 size, unsigned idx, u64 wr_id,
3678 int nreq, u8 fence, u8 next_fence,
3679 u32 mlx5_opcode)
3680{
3681 u8 opmod = 0;
3682
3683 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3684 mlx5_opcode | ((u32)opmod << 24));
19098df2 3685 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3686 ctrl->fm_ce_se |= fence;
3687 qp->fm_cache = next_fence;
3688 if (unlikely(qp->wq_sig))
3689 ctrl->signature = wq_sig(ctrl);
3690
3691 qp->sq.wrid[idx] = wr_id;
3692 qp->sq.w_list[idx].opcode = mlx5_opcode;
3693 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3694 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3695 qp->sq.w_list[idx].next = qp->sq.cur_post;
3696}
3697
3698
e126ba97
EC		 3699int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3700 struct ib_send_wr **bad_wr)
3701{
3702 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3703 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3704 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3705 struct mlx5_ib_qp *qp;
e6631814 3706 struct mlx5_ib_mr *mr;
e126ba97
EC		 3707 struct mlx5_wqe_data_seg *dpseg;
3708 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3709 struct mlx5_bf *bf;
e126ba97 3710 int uninitialized_var(size);
d16e91da 3711 void *qend;
e126ba97 3712 unsigned long flags;
e126ba97
EC		 3713 unsigned idx;
3714 int err = 0;
3715 int inl = 0;
3716 int num_sge;
3717 void *seg;
3718 int nreq;
3719 int i;
3720 u8 next_fence = 0;
e126ba97
EC		 3721 u8 fence;
3722
d16e91da
HE		 3723 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3724 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3725
3726 qp = to_mqp(ibqp);
3727 bf = qp->bf;
3728 qend = qp->sq.qend;
3729
e126ba97
EC		 3730 spin_lock_irqsave(&qp->sq.lock, flags);
3731
89ea94a7
MG		 3732 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3733 err = -EIO;
3734 *bad_wr = wr;
3735 nreq = 0;
3736 goto out;
3737 }
3738
e126ba97 3739 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3740 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3741 mlx5_ib_warn(dev, "\n");
3742 err = -EINVAL;
3743 *bad_wr = wr;
3744 goto out;
3745 }
3746
6e5eadac
SG		 3747 fence = qp->fm_cache;
3748 num_sge = wr->num_sge;
3749 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3750 mlx5_ib_warn(dev, "\n");
3751 err = -ENOMEM;
3752 *bad_wr = wr;
3753 goto out;
3754 }
3755
6e5eadac
SG		 3756 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3757 if (err) {
e126ba97
EC		 3758 mlx5_ib_warn(dev, "\n");
3759 err = -ENOMEM;
3760 *bad_wr = wr;
3761 goto out;
3762 }
3763
e126ba97
EC		 3764 switch (ibqp->qp_type) {
3765 case IB_QPT_XRC_INI:
3766 xrc = seg;
e126ba97
EC		 3767 seg += sizeof(*xrc);
3768 size += sizeof(*xrc) / 16;
3769 /* fall through */
3770 case IB_QPT_RC:
3771 switch (wr->opcode) {
3772 case IB_WR_RDMA_READ:
3773 case IB_WR_RDMA_WRITE:
3774 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3775 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3776 rdma_wr(wr)->rkey);
f241e749 3777 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3778 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3779 break;
3780
3781 case IB_WR_ATOMIC_CMP_AND_SWP:
3782 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3783 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3784 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3785 err = -ENOSYS;
3786 *bad_wr = wr;
3787 goto out;
e126ba97
EC		 3788
3789 case IB_WR_LOCAL_INV:
3790 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3791 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3792 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3793 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3794 num_sge = 0;
3795 break;
3796
8a187ee5
SG		 3797 case IB_WR_REG_MR:
3798 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3799 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3800 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3801 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3802 if (err) {
3803 *bad_wr = wr;
3804 goto out;
3805 }
3806 num_sge = 0;
3807 break;
3808
e6631814
SG		 3809 case IB_WR_REG_SIG_MR:
3810 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3811 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3812
3813 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3814 err = set_sig_umr_wr(wr, qp, &seg, &size);
3815 if (err) {
3816 mlx5_ib_warn(dev, "\n");
3817 *bad_wr = wr;
3818 goto out;
3819 }
3820
3821 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3822 nreq, get_fence(fence, wr),
3823 next_fence, MLX5_OPCODE_UMR);
3824 /*
3825 * SET_PSV WQEs are not signaled and solicited
3826 * on error
3827 */
3828 wr->send_flags &= ~IB_SEND_SIGNALED;
3829 wr->send_flags |= IB_SEND_SOLICITED;
3830 err = begin_wqe(qp, &seg, &ctrl, wr,
3831 &idx, &size, nreq);
3832 if (err) {
3833 mlx5_ib_warn(dev, "\n");
3834 err = -ENOMEM;
3835 *bad_wr = wr;
3836 goto out;
3837 }
3838
e622f2f4 3839 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3840 mr->sig->psv_memory.psv_idx, &seg,
3841 &size);
3842 if (err) {
3843 mlx5_ib_warn(dev, "\n");
3844 *bad_wr = wr;
3845 goto out;
3846 }
3847
3848 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3849 nreq, get_fence(fence, wr),
3850 next_fence, MLX5_OPCODE_SET_PSV);
3851 err = begin_wqe(qp, &seg, &ctrl, wr,
3852 &idx, &size, nreq);
3853 if (err) {
3854 mlx5_ib_warn(dev, "\n");
3855 err = -ENOMEM;
3856 *bad_wr = wr;
3857 goto out;
3858 }
3859
3860 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3861 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3862 mr->sig->psv_wire.psv_idx, &seg,
3863 &size);
3864 if (err) {
3865 mlx5_ib_warn(dev, "\n");
3866 *bad_wr = wr;
3867 goto out;
3868 }
3869
3870 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3871 nreq, get_fence(fence, wr),
3872 next_fence, MLX5_OPCODE_SET_PSV);
3873 num_sge = 0;
3874 goto skip_psv;
3875
e126ba97
EC		 3876 default:
3877 break;
3878 }
3879 break;
3880
3881 case IB_QPT_UC:
3882 switch (wr->opcode) {
3883 case IB_WR_RDMA_WRITE:
3884 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3885 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3886 rdma_wr(wr)->rkey);
e126ba97
EC		 3887 seg += sizeof(struct mlx5_wqe_raddr_seg);
3888 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3889 break;
3890
3891 default:
3892 break;
3893 }
3894 break;
3895
e126ba97 3896 case IB_QPT_SMI:
d16e91da 3897 case MLX5_IB_QPT_HW_GSI:
e126ba97 3898 set_datagram_seg(seg, wr);
f241e749 3899 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3900 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3901 if (unlikely((seg == qend)))
3902 seg = mlx5_get_send_wqe(qp, 0);
3903 break;
f0313965
ES		 3904 case IB_QPT_UD:
3905 set_datagram_seg(seg, wr);
3906 seg += sizeof(struct mlx5_wqe_datagram_seg);
3907 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3908
3909 if (unlikely((seg == qend)))
3910 seg = mlx5_get_send_wqe(qp, 0);
3911
3912 /* handle qp that supports ud offload */
3913 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3914 struct mlx5_wqe_eth_pad *pad;
e126ba97 3915
f0313965
ES		 3916 pad = seg;
3917 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3918 seg += sizeof(struct mlx5_wqe_eth_pad);
3919 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3920
3921 seg = set_eth_seg(seg, wr, qend, qp, &size);
3922
3923 if (unlikely((seg == qend)))
3924 seg = mlx5_get_send_wqe(qp, 0);
3925 }
3926 break;
e126ba97
EC		 3927 case MLX5_IB_QPT_REG_UMR:
3928 if (wr->opcode != MLX5_IB_WR_UMR) {
3929 err = -EINVAL;
3930 mlx5_ib_warn(dev, "bad opcode\n");
3931 goto out;
3932 }
3933 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3934 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3935 set_reg_umr_segment(seg, wr);
3936 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3937 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3938 if (unlikely((seg == qend)))
3939 seg = mlx5_get_send_wqe(qp, 0);
3940 set_reg_mkey_segment(seg, wr);
3941 seg += sizeof(struct mlx5_mkey_seg);
3942 size += sizeof(struct mlx5_mkey_seg) / 16;
3943 if (unlikely((seg == qend)))
3944 seg = mlx5_get_send_wqe(qp, 0);
3945 break;
3946
3947 default:
3948 break;
3949 }
3950
3951 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3952 int uninitialized_var(sz);
3953
3954 err = set_data_inl_seg(qp, wr, seg, &sz);
3955 if (unlikely(err)) {
3956 mlx5_ib_warn(dev, "\n");
3957 *bad_wr = wr;
3958 goto out;
3959 }
3960 inl = 1;
3961 size += sz;
3962 } else {
3963 dpseg = seg;
3964 for (i = 0; i < num_sge; i++) {
3965 if (unlikely(dpseg == qend)) {
3966 seg = mlx5_get_send_wqe(qp, 0);
3967 dpseg = seg;
3968 }
3969 if (likely(wr->sg_list[i].length)) {
3970 set_data_ptr_seg(dpseg, wr->sg_list + i);
3971 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3972 dpseg++;
3973 }
3974 }
3975 }
3976
6e5eadac
SG		 3977 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3978 get_fence(fence, wr), next_fence,
3979 mlx5_ib_opcode[wr->opcode]);
e6631814 3980skip_psv:
e126ba97
EC		 3981 if (0)
3982 dump_wqe(qp, idx, size);
3983 }
3984
3985out:
3986 if (likely(nreq)) {
3987 qp->sq.head += nreq;
3988
3989 /* Make sure that descriptors are written before
3990 * updating doorbell record and ringing the doorbell
3991 */
3992 wmb();
3993
3994 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3995
ada388f7
EC		 3996 /* Make sure doorbell record is visible to the HCA before
3997 * we hit doorbell */
3998 wmb();
3999
e126ba97
EC		 4000 if (bf->need_lock)
4001 spin_lock(&bf->lock);
6a4f139a
EC		 4002 else
4003 __acquire(&bf->lock);
e126ba97
EC		 4004
4005 /* TBD enable WC */
4006 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4007 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4008 /* wc_wmb(); */
4009 } else {
4010 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4011 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4012 /* Make sure doorbells don't leak out of SQ spinlock
4013 * and reach the HCA out of order.
4014 */
4015 mmiowb();
4016 }
4017 bf->offset ^= bf->buf_size;
4018 if (bf->need_lock)
4019 spin_unlock(&bf->lock);
6a4f139a
EC		 4020 else
4021 __release(&bf->lock);
e126ba97
EC		 4022 }
4023
4024 spin_unlock_irqrestore(&qp->sq.lock, flags);
4025
4026 return err;
4027}
4028
4029static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4030{
4031 sig->signature = calc_sig(sig, size);
4032}
4033
4034int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4035 struct ib_recv_wr **bad_wr)
4036{
4037 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4038 struct mlx5_wqe_data_seg *scat;
4039 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4040 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4041 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4042 unsigned long flags;
4043 int err = 0;
4044 int nreq;
4045 int ind;
4046 int i;
4047
d16e91da
HE		 4048 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4049 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4050
e126ba97
EC		 4051 spin_lock_irqsave(&qp->rq.lock, flags);
4052
89ea94a7
MG		 4053 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4054 err = -EIO;
4055 *bad_wr = wr;
4056 nreq = 0;
4057 goto out;
4058 }
4059
e126ba97
EC		 4060 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4061
4062 for (nreq = 0; wr; nreq++, wr = wr->next) {
4063 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4064 err = -ENOMEM;
4065 *bad_wr = wr;
4066 goto out;
4067 }
4068
4069 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4070 err = -EINVAL;
4071 *bad_wr = wr;
4072 goto out;
4073 }
4074
4075 scat = get_recv_wqe(qp, ind);
4076 if (qp->wq_sig)
4077 scat++;
4078
4079 for (i = 0; i < wr->num_sge; i++)
4080 set_data_ptr_seg(scat + i, wr->sg_list + i);
4081
4082 if (i < qp->rq.max_gs) {
4083 scat[i].byte_count = 0;
4084 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4085 scat[i].addr = 0;
4086 }
4087
4088 if (qp->wq_sig) {
4089 sig = (struct mlx5_rwqe_sig *)scat;
4090 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4091 }
4092
4093 qp->rq.wrid[ind] = wr->wr_id;
4094
4095 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4096 }
4097
4098out:
4099 if (likely(nreq)) {
4100 qp->rq.head += nreq;
4101
4102 /* Make sure that descriptors are written before
4103 * doorbell record.
4104 */
4105 wmb();
4106
4107 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4108 }
4109
4110 spin_unlock_irqrestore(&qp->rq.lock, flags);
4111
4112 return err;
4113}
4114
4115static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4116{
4117 switch (mlx5_state) {
4118 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4119 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4120 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4121 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4122 case MLX5_QP_STATE_SQ_DRAINING:
4123 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4124 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4125 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4126 default: return -1;
4127 }
4128}
4129
4130static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4131{
4132 switch (mlx5_mig_state) {
4133 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4134 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4135 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4136 default: return -1;
4137 }
4138}
4139
4140static int to_ib_qp_access_flags(int mlx5_flags)
4141{
4142 int ib_flags = 0;
4143
4144 if (mlx5_flags & MLX5_QP_BIT_RRE)
4145 ib_flags |= IB_ACCESS_REMOTE_READ;
4146 if (mlx5_flags & MLX5_QP_BIT_RWE)
4147 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4148 if (mlx5_flags & MLX5_QP_BIT_RAE)
4149 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4150
4151 return ib_flags;
4152}
4153
4154static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4155 struct mlx5_qp_path *path)
4156{
9603b61d 4157 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4158
4159 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4160 ib_ah_attr->port_num = path->port;
4161
c7a08ac7 4162 if (ib_ah_attr->port_num == 0 ||
938fe83c 4163 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4164 return;
4165
2811ba51 4166 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4167
4168 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4169 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4170 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4171 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4172 if (ib_ah_attr->ah_flags) {
4173 ib_ah_attr->grh.sgid_index = path->mgid_index;
4174 ib_ah_attr->grh.hop_limit = path->hop_limit;
4175 ib_ah_attr->grh.traffic_class =
4176 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4177 ib_ah_attr->grh.flow_label =
4178 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4179 memcpy(ib_ah_attr->grh.dgid.raw,
4180 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4181 }
4182}
4183
6d2f89df 4184static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4185 struct mlx5_ib_sq *sq,
4186 u8 *sq_state)
4187{
4188 void *out;
4189 void *sqc;
4190 int inlen;
4191 int err;
4192
4193 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4194 out = mlx5_vzalloc(inlen);
4195 if (!out)
4196 return -ENOMEM;
4197
4198 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4199 if (err)
4200 goto out;
4201
4202 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4203 *sq_state = MLX5_GET(sqc, sqc, state);
4204 sq->state = *sq_state;
4205
4206out:
4207 kvfree(out);
4208 return err;
4209}
4210
4211static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4212 struct mlx5_ib_rq *rq,
4213 u8 *rq_state)
4214{
4215 void *out;
4216 void *rqc;
4217 int inlen;
4218 int err;
4219
4220 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4221 out = mlx5_vzalloc(inlen);
4222 if (!out)
4223 return -ENOMEM;
4224
4225 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4226 if (err)
4227 goto out;
4228
4229 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4230 *rq_state = MLX5_GET(rqc, rqc, state);
4231 rq->state = *rq_state;
4232
4233out:
4234 kvfree(out);
4235 return err;
4236}
4237
4238static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4239 struct mlx5_ib_qp *qp, u8 *qp_state)
4240{
4241 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4242 [MLX5_RQC_STATE_RST] = {
4243 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4244 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4245 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4246 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4247 },
4248 [MLX5_RQC_STATE_RDY] = {
4249 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4250 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4251 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4252 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4253 },
4254 [MLX5_RQC_STATE_ERR] = {
4255 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4256 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4257 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4258 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4259 },
4260 [MLX5_RQ_STATE_NA] = {
4261 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4262 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4263 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4264 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4265 },
4266 };
4267
4268 *qp_state = sqrq_trans[rq_state][sq_state];
4269
4270 if (*qp_state == MLX5_QP_STATE_BAD) {
4271 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4272 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4273 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4274 return -EINVAL;
4275 }
4276
4277 if (*qp_state == MLX5_QP_STATE)
4278 *qp_state = qp->state;
4279
4280 return 0;
4281}
4282
4283static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4284 struct mlx5_ib_qp *qp,
4285 u8 *raw_packet_qp_state)
4286{
4287 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4288 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4289 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4290 int err;
4291 u8 sq_state = MLX5_SQ_STATE_NA;
4292 u8 rq_state = MLX5_RQ_STATE_NA;
4293
4294 if (qp->sq.wqe_cnt) {
4295 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4296 if (err)
4297 return err;
4298 }
4299
4300 if (qp->rq.wqe_cnt) {
4301 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4302 if (err)
4303 return err;
4304 }
4305
4306 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4307 raw_packet_qp_state);
4308}
4309
4310static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4311 struct ib_qp_attr *qp_attr)
e126ba97 4312{
e126ba97
EC		 4313 struct mlx5_query_qp_mbox_out *outb;
4314 struct mlx5_qp_context *context;
4315 int mlx5_state;
4316 int err = 0;
4317
e126ba97 4318 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
6d2f89df 4319 if (!outb)
4320 return -ENOMEM;
4321
e126ba97 4322 context = &outb->ctx;
19098df2 4323 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4324 sizeof(*outb));
e126ba97 4325 if (err)
6d2f89df 4326 goto out;
e126ba97
EC		 4327
4328 mlx5_state = be32_to_cpu(context->flags) >> 28;
4329
4330 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4331 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4332 qp_attr->path_mig_state =
4333 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4334 qp_attr->qkey = be32_to_cpu(context->qkey);
4335 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4336 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4337 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4338 qp_attr->qp_access_flags =
4339 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4340
4341 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4342 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4343 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4344 qp_attr->alt_pkey_index =
4345 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4346 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4347 }
4348
d3ae2bde 4349 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4350 qp_attr->port_num = context->pri_path.port;
4351
4352 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4353 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4354
4355 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4356
4357 qp_attr->max_dest_rd_atomic =
4358 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4359 qp_attr->min_rnr_timer =
4360 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4361 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4362 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4363 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4364 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4365
4366out:
4367 kfree(outb);
4368 return err;
4369}
4370
4371int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4372 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4373{
4374 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4375 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4376 int err = 0;
4377 u8 raw_packet_qp_state;
4378
28d61370
YH		 4379 if (ibqp->rwq_ind_tbl)
4380 return -ENOSYS;
4381
d16e91da
HE		 4382 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4383 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4384 qp_init_attr);
4385
6d2f89df 4386#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4387 /*
4388 * Wait for any outstanding page faults, in case the user frees memory
4389 * based upon this query's result.
4390 */
4391 flush_workqueue(mlx5_ib_page_fault_wq);
4392#endif
4393
4394 mutex_lock(&qp->mutex);
4395
4396 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4397 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4398 if (err)
4399 goto out;
4400 qp->state = raw_packet_qp_state;
4401 qp_attr->port_num = 1;
4402 } else {
4403 err = query_qp_attr(dev, qp, qp_attr);
4404 if (err)
4405 goto out;
4406 }
4407
4408 qp_attr->qp_state = qp->state;
e126ba97
EC		 4409 qp_attr->cur_qp_state = qp_attr->qp_state;
4410 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4411 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4412
4413 if (!ibqp->uobject) {
0540d814 4414 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4415 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4416 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4417 } else {
4418 qp_attr->cap.max_send_wr = 0;
4419 qp_attr->cap.max_send_sge = 0;
4420 }
4421
0540d814
NO		 4422 qp_init_attr->qp_type = ibqp->qp_type;
4423 qp_init_attr->recv_cq = ibqp->recv_cq;
4424 qp_init_attr->send_cq = ibqp->send_cq;
4425 qp_init_attr->srq = ibqp->srq;
4426 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4427
4428 qp_init_attr->cap = qp_attr->cap;
4429
4430 qp_init_attr->create_flags = 0;
4431 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4432 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4433
051f2630
LR		 4434 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4435 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4436 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4437 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4438 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4439 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4440 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4441 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4442
e126ba97
EC		 4443 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4444 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4445
e126ba97
EC		 4446out:
4447 mutex_unlock(&qp->mutex);
4448 return err;
4449}
4450
4451struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4452 struct ib_ucontext *context,
4453 struct ib_udata *udata)
4454{
4455 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4456 struct mlx5_ib_xrcd *xrcd;
4457 int err;
4458
938fe83c 4459 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4460 return ERR_PTR(-ENOSYS);
4461
4462 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4463 if (!xrcd)
4464 return ERR_PTR(-ENOMEM);
4465
9603b61d 4466 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4467 if (err) {
4468 kfree(xrcd);
4469 return ERR_PTR(-ENOMEM);
4470 }
4471
4472 return &xrcd->ibxrcd;
4473}
4474
4475int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4476{
4477 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4478 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4479 int err;
4480
9603b61d 4481 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4482 if (err) {
4483 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4484 return err;
4485 }
4486
4487 kfree(xrcd);
4488
4489 return 0;
4490}
79b20a6c
YH		 4491
4492static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4493 struct ib_wq_init_attr *init_attr)
4494{
4495 struct mlx5_ib_dev *dev;
4496 __be64 *rq_pas0;
4497 void *in;
4498 void *rqc;
4499 void *wq;
4500 int inlen;
4501 int err;
4502
4503 dev = to_mdev(pd->device);
4504
4505 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4506 in = mlx5_vzalloc(inlen);
4507 if (!in)
4508 return -ENOMEM;
4509
4510 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4511 MLX5_SET(rqc, rqc, mem_rq_type,
4512 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4513 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4514 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4515 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4516 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4517 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4518 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4519 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4520 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4521 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4522 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4523 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4524 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4525 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4526 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4527 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4528 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4529 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4530 kvfree(in);
4531 return err;
4532}
4533
4534static int set_user_rq_size(struct mlx5_ib_dev *dev,
4535 struct ib_wq_init_attr *wq_init_attr,
4536 struct mlx5_ib_create_wq *ucmd,
4537 struct mlx5_ib_rwq *rwq)
4538{
4539 /* Sanity check RQ size before proceeding */
4540 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4541 return -EINVAL;
4542
4543 if (!ucmd->rq_wqe_count)
4544 return -EINVAL;
4545
4546 rwq->wqe_count = ucmd->rq_wqe_count;
4547 rwq->wqe_shift = ucmd->rq_wqe_shift;
4548 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4549 rwq->log_rq_stride = rwq->wqe_shift;
4550 rwq->log_rq_size = ilog2(rwq->wqe_count);
4551 return 0;
4552}
4553
4554static int prepare_user_rq(struct ib_pd *pd,
4555 struct ib_wq_init_attr *init_attr,
4556 struct ib_udata *udata,
4557 struct mlx5_ib_rwq *rwq)
4558{
4559 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4560 struct mlx5_ib_create_wq ucmd = {};
4561 int err;
4562 size_t required_cmd_sz;
4563
4564 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4565 if (udata->inlen < required_cmd_sz) {
4566 mlx5_ib_dbg(dev, "invalid inlen\n");
4567 return -EINVAL;
4568 }
4569
4570 if (udata->inlen > sizeof(ucmd) &&
4571 !ib_is_udata_cleared(udata, sizeof(ucmd),
4572 udata->inlen - sizeof(ucmd))) {
4573 mlx5_ib_dbg(dev, "inlen is not supported\n");
4574 return -EOPNOTSUPP;
4575 }
4576
4577 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4578 mlx5_ib_dbg(dev, "copy failed\n");
4579 return -EFAULT;
4580 }
4581
4582 if (ucmd.comp_mask) {
4583 mlx5_ib_dbg(dev, "invalid comp mask\n");
4584 return -EOPNOTSUPP;
4585 }
4586
4587 if (ucmd.reserved) {
4588 mlx5_ib_dbg(dev, "invalid reserved\n");
4589 return -EOPNOTSUPP;
4590 }
4591
4592 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4593 if (err) {
4594 mlx5_ib_dbg(dev, "err %d\n", err);
4595 return err;
4596 }
4597
4598 err = create_user_rq(dev, pd, rwq, &ucmd);
4599 if (err) {
4600 mlx5_ib_dbg(dev, "err %d\n", err);
4601 if (err)
4602 return err;
4603 }
4604
4605 rwq->user_index = ucmd.user_index;
4606 return 0;
4607}
4608
4609struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4610 struct ib_wq_init_attr *init_attr,
4611 struct ib_udata *udata)
4612{
4613 struct mlx5_ib_dev *dev;
4614 struct mlx5_ib_rwq *rwq;
4615 struct mlx5_ib_create_wq_resp resp = {};
4616 size_t min_resp_len;
4617 int err;
4618
4619 if (!udata)
4620 return ERR_PTR(-ENOSYS);
4621
4622 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4623 if (udata->outlen && udata->outlen < min_resp_len)
4624 return ERR_PTR(-EINVAL);
4625
4626 dev = to_mdev(pd->device);
4627 switch (init_attr->wq_type) {
4628 case IB_WQT_RQ:
4629 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4630 if (!rwq)
4631 return ERR_PTR(-ENOMEM);
4632 err = prepare_user_rq(pd, init_attr, udata, rwq);
4633 if (err)
4634 goto err;
4635 err = create_rq(rwq, pd, init_attr);
4636 if (err)
4637 goto err_user_rq;
4638 break;
4639 default:
4640 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4641 init_attr->wq_type);
4642 return ERR_PTR(-EINVAL);
4643 }
4644
4645 rwq->ibwq.wq_num = rwq->rqn;
4646 rwq->ibwq.state = IB_WQS_RESET;
4647 if (udata->outlen) {
4648 resp.response_length = offsetof(typeof(resp), response_length) +
4649 sizeof(resp.response_length);
4650 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4651 if (err)
4652 goto err_copy;
4653 }
4654
4655 return &rwq->ibwq;
4656
4657err_copy:
4658 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4659err_user_rq:
4660 destroy_user_rq(pd, rwq);
4661err:
4662 kfree(rwq);
4663 return ERR_PTR(err);
4664}
4665
4666int mlx5_ib_destroy_wq(struct ib_wq *wq)
4667{
4668 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4669 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4670
4671 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4672 destroy_user_rq(wq->pd, rwq);
4673 kfree(rwq);
4674
4675 return 0;
4676}
4677
c5f90929
YH		 4678struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4679 struct ib_rwq_ind_table_init_attr *init_attr,
4680 struct ib_udata *udata)
4681{
4682 struct mlx5_ib_dev *dev = to_mdev(device);
4683 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4684 int sz = 1 << init_attr->log_ind_tbl_size;
4685 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4686 size_t min_resp_len;
4687 int inlen;
4688 int err;
4689 int i;
4690 u32 *in;
4691 void *rqtc;
4692
4693 if (udata->inlen > 0 &&
4694 !ib_is_udata_cleared(udata, 0,
4695 udata->inlen))
4696 return ERR_PTR(-EOPNOTSUPP);
4697
4698 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4699 if (udata->outlen && udata->outlen < min_resp_len)
4700 return ERR_PTR(-EINVAL);
4701
4702 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4703 if (!rwq_ind_tbl)
4704 return ERR_PTR(-ENOMEM);
4705
4706 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4707 in = mlx5_vzalloc(inlen);
4708 if (!in) {
4709 err = -ENOMEM;
4710 goto err;
4711 }
4712
4713 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4714
4715 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4716 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4717
4718 for (i = 0; i < sz; i++)
4719 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4720
4721 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4722 kvfree(in);
4723
4724 if (err)
4725 goto err;
4726
4727 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4728 if (udata->outlen) {
4729 resp.response_length = offsetof(typeof(resp), response_length) +
4730 sizeof(resp.response_length);
4731 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4732 if (err)
4733 goto err_copy;
4734 }
4735
4736 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4737
4738err_copy:
4739 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4740err:
4741 kfree(rwq_ind_tbl);
4742 return ERR_PTR(err);
4743}
4744
4745int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4746{
4747 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4748 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4749
4750 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4751
4752 kfree(rwq_ind_tbl);
4753 return 0;
4754}
4755
79b20a6c
YH		 4756int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4757 u32 wq_attr_mask, struct ib_udata *udata)
4758{
4759 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4760 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4761 struct mlx5_ib_modify_wq ucmd = {};
4762 size_t required_cmd_sz;
4763 int curr_wq_state;
4764 int wq_state;
4765 int inlen;
4766 int err;
4767 void *rqc;
4768 void *in;
4769
4770 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4771 if (udata->inlen < required_cmd_sz)
4772 return -EINVAL;
4773
4774 if (udata->inlen > sizeof(ucmd) &&
4775 !ib_is_udata_cleared(udata, sizeof(ucmd),
4776 udata->inlen - sizeof(ucmd)))
4777 return -EOPNOTSUPP;
4778
4779 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4780 return -EFAULT;
4781
4782 if (ucmd.comp_mask || ucmd.reserved)
4783 return -EOPNOTSUPP;
4784
4785 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4786 in = mlx5_vzalloc(inlen);
4787 if (!in)
4788 return -ENOMEM;
4789
4790 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4791
4792 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4793 wq_attr->curr_wq_state : wq->state;
4794 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4795 wq_attr->wq_state : curr_wq_state;
4796 if (curr_wq_state == IB_WQS_ERR)
4797 curr_wq_state = MLX5_RQC_STATE_ERR;
4798 if (wq_state == IB_WQS_ERR)
4799 wq_state = MLX5_RQC_STATE_ERR;
4800 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4801 MLX5_SET(rqc, rqc, state, wq_state);
4802
4803 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4804 kvfree(in);
4805 if (!err)
4806 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4807
4808 return err;
4809}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git